1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1991 Regents of the University of California. 5 * All rights reserved. 6 * Copyright (c) 1994 John S. Dyson 7 * All rights reserved. 8 * Copyright (c) 1994 David Greenman 9 * All rights reserved. 10 * Copyright (c) 2003 Peter Wemm 11 * All rights reserved. 12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to Berkeley by 16 * the Systems Programming Group of the University of Utah Computer 17 * Science Department and William Jolitz of UUNET Technologies Inc. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the University of 30 * California, Berkeley and its contributors. 31 * 4. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 */ 47 /*- 48 * Copyright (c) 2003 Networks Associates Technology, Inc. 49 * Copyright (c) 2014-2020 The FreeBSD Foundation 50 * All rights reserved. 51 * 52 * This software was developed for the FreeBSD Project by Jake Burkholder, 53 * Safeport Network Services, and Network Associates Laboratories, the 54 * Security Research Division of Network Associates, Inc. under 55 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 56 * CHATS research program. 57 * 58 * Portions of this software were developed by 59 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from 60 * the FreeBSD Foundation. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions 64 * are met: 65 * 1. Redistributions of source code must retain the above copyright 66 * notice, this list of conditions and the following disclaimer. 67 * 2. Redistributions in binary form must reproduce the above copyright 68 * notice, this list of conditions and the following disclaimer in the 69 * documentation and/or other materials provided with the distribution. 70 * 71 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 72 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 74 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 77 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 78 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 79 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 80 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 81 * SUCH DAMAGE. 82 */ 83 84 #define AMD64_NPT_AWARE 85 86 #include <sys/cdefs.h> 87 /* 88 * Manages physical address maps. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106 #include "opt_ddb.h" 107 #include "opt_kstack_pages.h" 108 #include "opt_pmap.h" 109 #include "opt_vm.h" 110 111 #include <sys/param.h> 112 #include <sys/asan.h> 113 #include <sys/bitstring.h> 114 #include <sys/bus.h> 115 #include <sys/systm.h> 116 #include <sys/counter.h> 117 #include <sys/kernel.h> 118 #include <sys/ktr.h> 119 #include <sys/lock.h> 120 #include <sys/malloc.h> 121 #include <sys/mman.h> 122 #include <sys/msan.h> 123 #include <sys/mutex.h> 124 #include <sys/proc.h> 125 #include <sys/rangeset.h> 126 #include <sys/rwlock.h> 127 #include <sys/sbuf.h> 128 #include <sys/smr.h> 129 #include <sys/sx.h> 130 #include <sys/turnstile.h> 131 #include <sys/vmem.h> 132 #include <sys/vmmeter.h> 133 #include <sys/sched.h> 134 #include <sys/sysctl.h> 135 #include <sys/smp.h> 136 #ifdef DDB 137 #include <sys/kdb.h> 138 #include <ddb/ddb.h> 139 #endif 140 141 #include <vm/vm.h> 142 #include <vm/vm_param.h> 143 #include <vm/vm_kern.h> 144 #include <vm/vm_page.h> 145 #include <vm/vm_map.h> 146 #include <vm/vm_object.h> 147 #include <vm/vm_extern.h> 148 #include <vm/vm_pageout.h> 149 #include <vm/vm_pager.h> 150 #include <vm/vm_phys.h> 151 #include <vm/vm_radix.h> 152 #include <vm/vm_reserv.h> 153 #include <vm/vm_dumpset.h> 154 #include <vm/uma.h> 155 156 #include <machine/asan.h> 157 #include <machine/intr_machdep.h> 158 #include <x86/apicvar.h> 159 #include <x86/ifunc.h> 160 #include <machine/cpu.h> 161 #include <machine/cputypes.h> 162 #include <machine/md_var.h> 163 #include <machine/msan.h> 164 #include <machine/pcb.h> 165 #include <machine/specialreg.h> 166 #include <machine/smp.h> 167 #include <machine/sysarch.h> 168 #include <machine/tss.h> 169 170 #ifdef NUMA 171 #define PMAP_MEMDOM MAXMEMDOM 172 #else 173 #define PMAP_MEMDOM 1 174 #endif 175 176 static __inline bool 177 pmap_type_guest(pmap_t pmap) 178 { 179 180 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI)); 181 } 182 183 static __inline bool 184 pmap_emulate_ad_bits(pmap_t pmap) 185 { 186 187 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0); 188 } 189 190 static __inline pt_entry_t 191 pmap_valid_bit(pmap_t pmap) 192 { 193 pt_entry_t mask; 194 195 switch (pmap->pm_type) { 196 case PT_X86: 197 case PT_RVI: 198 mask = X86_PG_V; 199 break; 200 case PT_EPT: 201 if (pmap_emulate_ad_bits(pmap)) 202 mask = EPT_PG_EMUL_V; 203 else 204 mask = EPT_PG_READ; 205 break; 206 default: 207 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type); 208 } 209 210 return (mask); 211 } 212 213 static __inline pt_entry_t 214 pmap_rw_bit(pmap_t pmap) 215 { 216 pt_entry_t mask; 217 218 switch (pmap->pm_type) { 219 case PT_X86: 220 case PT_RVI: 221 mask = X86_PG_RW; 222 break; 223 case PT_EPT: 224 if (pmap_emulate_ad_bits(pmap)) 225 mask = EPT_PG_EMUL_RW; 226 else 227 mask = EPT_PG_WRITE; 228 break; 229 default: 230 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type); 231 } 232 233 return (mask); 234 } 235 236 static pt_entry_t pg_g; 237 238 static __inline pt_entry_t 239 pmap_global_bit(pmap_t pmap) 240 { 241 pt_entry_t mask; 242 243 switch (pmap->pm_type) { 244 case PT_X86: 245 mask = pg_g; 246 break; 247 case PT_RVI: 248 case PT_EPT: 249 mask = 0; 250 break; 251 default: 252 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type); 253 } 254 255 return (mask); 256 } 257 258 static __inline pt_entry_t 259 pmap_accessed_bit(pmap_t pmap) 260 { 261 pt_entry_t mask; 262 263 switch (pmap->pm_type) { 264 case PT_X86: 265 case PT_RVI: 266 mask = X86_PG_A; 267 break; 268 case PT_EPT: 269 if (pmap_emulate_ad_bits(pmap)) 270 mask = EPT_PG_READ; 271 else 272 mask = EPT_PG_A; 273 break; 274 default: 275 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type); 276 } 277 278 return (mask); 279 } 280 281 static __inline pt_entry_t 282 pmap_modified_bit(pmap_t pmap) 283 { 284 pt_entry_t mask; 285 286 switch (pmap->pm_type) { 287 case PT_X86: 288 case PT_RVI: 289 mask = X86_PG_M; 290 break; 291 case PT_EPT: 292 if (pmap_emulate_ad_bits(pmap)) 293 mask = EPT_PG_WRITE; 294 else 295 mask = EPT_PG_M; 296 break; 297 default: 298 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type); 299 } 300 301 return (mask); 302 } 303 304 static __inline pt_entry_t 305 pmap_pku_mask_bit(pmap_t pmap) 306 { 307 308 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0); 309 } 310 311 static __inline bool 312 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte) 313 { 314 315 if (!pmap_emulate_ad_bits(pmap)) 316 return (true); 317 318 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type)); 319 320 /* 321 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration 322 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared 323 * if the EPT_PG_WRITE bit is set. 324 */ 325 if ((pte & EPT_PG_WRITE) != 0) 326 return (false); 327 328 /* 329 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set. 330 */ 331 if ((pte & EPT_PG_EXECUTE) == 0 || 332 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0)) 333 return (true); 334 else 335 return (false); 336 } 337 338 #ifdef PV_STATS 339 #define PV_STAT(x) do { x ; } while (0) 340 #else 341 #define PV_STAT(x) do { } while (0) 342 #endif 343 344 #ifdef NUMA 345 #define pa_index(pa) ({ \ 346 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \ 347 ("address %lx beyond the last segment", (pa))); \ 348 (pa) >> PDRSHIFT; \ 349 }) 350 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)]) 351 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page)) 352 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \ 353 struct rwlock *_lock; \ 354 if (__predict_false((pa) > pmap_last_pa)) \ 355 _lock = &pv_dummy_large.pv_lock; \ 356 else \ 357 _lock = &(pa_to_pmdp(pa)->pv_lock); \ 358 _lock; \ 359 }) 360 #else 361 #define pa_index(pa) ((pa) >> PDRSHIFT) 362 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 363 364 #define NPV_LIST_LOCKS MAXCPU 365 366 #define PHYS_TO_PV_LIST_LOCK(pa) \ 367 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS]) 368 #endif 369 370 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \ 371 struct rwlock **_lockp = (lockp); \ 372 struct rwlock *_new_lock; \ 373 \ 374 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \ 375 if (_new_lock != *_lockp) { \ 376 if (*_lockp != NULL) \ 377 rw_wunlock(*_lockp); \ 378 *_lockp = _new_lock; \ 379 rw_wlock(*_lockp); \ 380 } \ 381 } while (0) 382 383 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \ 384 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m)) 385 386 #define RELEASE_PV_LIST_LOCK(lockp) do { \ 387 struct rwlock **_lockp = (lockp); \ 388 \ 389 if (*_lockp != NULL) { \ 390 rw_wunlock(*_lockp); \ 391 *_lockp = NULL; \ 392 } \ 393 } while (0) 394 395 #define VM_PAGE_TO_PV_LIST_LOCK(m) \ 396 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m)) 397 398 /* 399 * Statically allocate kernel pmap memory. However, memory for 400 * pm_pcids is obtained after the dynamic allocator is operational. 401 * Initialize it with a non-canonical pointer to catch early accesses 402 * regardless of the active mapping. 403 */ 404 struct pmap kernel_pmap_store = { 405 .pm_pcidp = (void *)0xdeadbeefdeadbeef, 406 }; 407 408 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 409 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 410 411 int nkpt; 412 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0, 413 "Number of kernel page table pages allocated on bootup"); 414 415 static int ndmpdp; 416 vm_paddr_t dmaplimit; 417 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS_LA48; 418 pt_entry_t pg_nx; 419 420 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 421 "VM/pmap parameters"); 422 423 static int __read_frequently pg_ps_enabled = 1; 424 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 425 &pg_ps_enabled, 0, "Are large page mappings enabled?"); 426 427 int __read_frequently la57 = 0; 428 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 429 &la57, 0, 430 "5-level paging for host is enabled"); 431 432 /* 433 * The default value is needed in order to preserve compatibility with 434 * some userspace programs that put tags into sign-extended bits. 435 */ 436 int prefer_uva_la48 = 1; 437 SYSCTL_INT(_vm_pmap, OID_AUTO, prefer_uva_la48, CTLFLAG_RDTUN, 438 &prefer_uva_la48, 0, 439 "Userspace maps are limited to LA48 unless otherwise configured"); 440 441 static bool 442 pmap_is_la57(pmap_t pmap) 443 { 444 if (pmap->pm_type == PT_X86) 445 return (la57); 446 return (false); /* XXXKIB handle EPT */ 447 } 448 449 #define PAT_INDEX_SIZE 8 450 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 451 452 static u_int64_t KPTphys; /* phys addr of kernel level 1 */ 453 static u_int64_t KPDphys; /* phys addr of kernel level 2 */ 454 static u_int64_t KPDPphys; /* phys addr of kernel level 3 */ 455 u_int64_t KPML4phys; /* phys addr of kernel level 4 */ 456 u_int64_t KPML5phys; /* phys addr of kernel level 5, 457 if supported */ 458 459 #ifdef KASAN 460 static uint64_t KASANPDPphys; 461 #endif 462 #ifdef KMSAN 463 static uint64_t KMSANSHADPDPphys; 464 static uint64_t KMSANORIGPDPphys; 465 466 /* 467 * To support systems with large amounts of memory, it is necessary to extend 468 * the maximum size of the direct map. This could eat into the space reserved 469 * for the shadow map. 470 */ 471 _Static_assert(DMPML4I + NDMPML4E <= KMSANSHADPML4I, "direct map overflow"); 472 #endif 473 474 static pml4_entry_t *kernel_pml4; 475 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */ 476 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */ 477 static u_int64_t DMPML4phys; /* ... level 4, for la57 */ 478 static int ndmpdpphys; /* number of DMPDPphys pages */ 479 480 vm_paddr_t kernphys; /* phys addr of start of bootstrap data */ 481 vm_paddr_t KERNend; /* and the end */ 482 483 struct kva_layout_s kva_layout = { 484 .kva_min = KV4ADDR(PML4PML4I, 0, 0, 0), 485 .kva_max = KV4ADDR(NPML4EPG - 1, NPDPEPG - 1, 486 NPDEPG - 1, NPTEPG - 1), 487 .dmap_low = KV4ADDR(DMPML4I, 0, 0, 0), 488 .dmap_high = KV4ADDR(DMPML4I + NDMPML4E, 0, 0, 0), 489 .lm_low = KV4ADDR(LMSPML4I, 0, 0, 0), 490 .lm_high = KV4ADDR(LMEPML4I + 1, 0, 0, 0), 491 .km_low = KV4ADDR(KPML4BASE, 0, 0, 0), 492 .km_high = KV4ADDR(KPML4BASE + NKPML4E - 1, NPDPEPG - 1, 493 NPDEPG - 1, NPTEPG - 1), 494 .rec_pt = KV4ADDR(PML4PML4I, 0, 0, 0), 495 .kasan_shadow_low = KV4ADDR(KASANPML4I, 0, 0, 0), 496 .kasan_shadow_high = KV4ADDR(KASANPML4I + NKASANPML4E, 0, 0, 0), 497 .kmsan_shadow_low = KV4ADDR(KMSANSHADPML4I, 0, 0, 0), 498 .kmsan_shadow_high = KV4ADDR(KMSANSHADPML4I + NKMSANSHADPML4E, 499 0, 0, 0), 500 .kmsan_origin_low = KV4ADDR(KMSANORIGPML4I, 0, 0, 0), 501 .kmsan_origin_high = KV4ADDR(KMSANORIGPML4I + NKMSANORIGPML4E, 502 0, 0, 0), 503 }; 504 505 struct kva_layout_s kva_layout_la57 = { 506 .kva_min = KV5ADDR(NPML5EPG / 2, 0, 0, 0, 0), /* == rec_pt */ 507 .kva_max = KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1, 508 NPDEPG - 1, NPTEPG - 1), 509 .dmap_low = KV5ADDR(DMPML5I, 0, 0, 0, 0), 510 .dmap_high = KV5ADDR(DMPML5I + NDMPML5E, 0, 0, 0, 0), 511 .lm_low = KV5ADDR(LMSPML5I, 0, 0, 0, 0), 512 .lm_high = KV5ADDR(LMEPML5I + 1, 0, 0, 0, 0), 513 .km_low = KV4ADDR(KPML4BASE, 0, 0, 0), 514 .km_high = KV4ADDR(KPML4BASE + NKPML4E - 1, NPDPEPG - 1, 515 NPDEPG - 1, NPTEPG - 1), 516 .rec_pt = KV5ADDR(PML5PML5I, 0, 0, 0, 0), 517 .kasan_shadow_low = KV4ADDR(KASANPML4I, 0, 0, 0), 518 .kasan_shadow_high = KV4ADDR(KASANPML4I + NKASANPML4E, 0, 0, 0), 519 .kmsan_shadow_low = KV4ADDR(KMSANSHADPML4I, 0, 0, 0), 520 .kmsan_shadow_high = KV4ADDR(KMSANSHADPML4I + NKMSANSHADPML4E, 521 0, 0, 0), 522 .kmsan_origin_low = KV4ADDR(KMSANORIGPML4I, 0, 0, 0), 523 .kmsan_origin_high = KV4ADDR(KMSANORIGPML4I + NKMSANORIGPML4E, 524 0, 0, 0), 525 }; 526 527 /* 528 * pmap_mapdev support pre initialization (i.e. console) 529 */ 530 #define PMAP_PREINIT_MAPPING_COUNT 8 531 static struct pmap_preinit_mapping { 532 vm_paddr_t pa; 533 vm_offset_t va; 534 vm_size_t sz; 535 int mode; 536 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT]; 537 static int pmap_initialized; 538 539 /* 540 * Data for the pv entry allocation mechanism. 541 * Updates to pv_invl_gen are protected by the pv list lock but reads are not. 542 */ 543 #ifdef NUMA 544 static __inline int 545 pc_to_domain(struct pv_chunk *pc) 546 { 547 548 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc))); 549 } 550 #else 551 static __inline int 552 pc_to_domain(struct pv_chunk *pc __unused) 553 { 554 555 return (0); 556 } 557 #endif 558 559 struct pv_chunks_list { 560 struct mtx pvc_lock; 561 TAILQ_HEAD(pch, pv_chunk) pvc_list; 562 int active_reclaims; 563 } __aligned(CACHE_LINE_SIZE); 564 565 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM]; 566 567 #ifdef NUMA 568 struct pmap_large_md_page { 569 struct rwlock pv_lock; 570 struct md_page pv_page; 571 u_long pv_invl_gen; 572 }; 573 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large; 574 #define pv_dummy pv_dummy_large.pv_page 575 __read_mostly static struct pmap_large_md_page *pv_table; 576 __read_mostly vm_paddr_t pmap_last_pa; 577 #else 578 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS]; 579 static u_long pv_invl_gen[NPV_LIST_LOCKS]; 580 static struct md_page *pv_table; 581 static struct md_page pv_dummy; 582 #endif 583 584 /* 585 * All those kernel PT submaps that BSD is so fond of 586 */ 587 pt_entry_t *CMAP1 = NULL; 588 caddr_t CADDR1 = 0; 589 static vm_offset_t qframe = 0; 590 static struct mtx qframe_mtx; 591 592 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */ 593 594 static vmem_t *large_vmem; 595 static u_int lm_ents; 596 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= kva_layout.lm_low && \ 597 (va) < kva_layout.lm_high) 598 599 int pmap_pcid_enabled = 1; 600 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 601 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?"); 602 int invpcid_works = 0; 603 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0, 604 "Is the invpcid instruction available ?"); 605 int invlpgb_works; 606 SYSCTL_INT(_vm_pmap, OID_AUTO, invlpgb_works, CTLFLAG_RD, &invlpgb_works, 0, 607 "Is the invlpgb instruction available?"); 608 int invlpgb_maxcnt; 609 int pmap_pcid_invlpg_workaround = 0; 610 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_invlpg_workaround, 611 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 612 &pmap_pcid_invlpg_workaround, 0, 613 "Enable small core PCID/INVLPG workaround"); 614 int pmap_pcid_invlpg_workaround_uena = 1; 615 616 int __read_frequently pti = 0; 617 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 618 &pti, 0, 619 "Page Table Isolation enabled"); 620 static vm_object_t pti_obj; 621 static pml4_entry_t *pti_pml4; 622 static vm_pindex_t pti_pg_idx; 623 static bool pti_finalized; 624 625 static int pmap_growkernel_panic = 0; 626 SYSCTL_INT(_vm_pmap, OID_AUTO, growkernel_panic, CTLFLAG_RDTUN, 627 &pmap_growkernel_panic, 0, 628 "panic on failure to allocate kernel page table page"); 629 630 struct pmap_pkru_range { 631 struct rs_el pkru_rs_el; 632 u_int pkru_keyidx; 633 int pkru_flags; 634 }; 635 636 static uma_zone_t pmap_pkru_ranges_zone; 637 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 638 pt_entry_t *pte); 639 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va); 640 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva); 641 static void *pkru_dup_range(void *ctx, void *data); 642 static void pkru_free_range(void *ctx, void *node); 643 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap); 644 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva); 645 static void pmap_pkru_deassign_all(pmap_t pmap); 646 647 static COUNTER_U64_DEFINE_EARLY(pcid_save_cnt); 648 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLFLAG_RD, 649 &pcid_save_cnt, "Count of saved TLB context on switch"); 650 651 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker = 652 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker); 653 static struct mtx invl_gen_mtx; 654 /* Fake lock object to satisfy turnstiles interface. */ 655 static struct lock_object invl_gen_ts = { 656 .lo_name = "invlts", 657 }; 658 static struct pmap_invl_gen pmap_invl_gen_head = { 659 .gen = 1, 660 .next = NULL, 661 }; 662 static u_long pmap_invl_gen = 1; 663 static int pmap_invl_waiters; 664 static struct callout pmap_invl_callout; 665 static bool pmap_invl_callout_inited; 666 667 #define PMAP_ASSERT_NOT_IN_DI() \ 668 KASSERT(pmap_not_in_di(), ("DI already started")) 669 670 static bool 671 pmap_di_locked(void) 672 { 673 int tun; 674 675 if ((cpu_feature2 & CPUID2_CX16) == 0) 676 return (true); 677 tun = 0; 678 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun); 679 return (tun != 0); 680 } 681 682 static int 683 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS) 684 { 685 int locked; 686 687 locked = pmap_di_locked(); 688 return (sysctl_handle_int(oidp, &locked, 0, req)); 689 } 690 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN | 691 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "", 692 "Locked delayed invalidation"); 693 694 static bool pmap_not_in_di_l(void); 695 static bool pmap_not_in_di_u(void); 696 DEFINE_IFUNC(, bool, pmap_not_in_di, (void)) 697 { 698 699 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u); 700 } 701 702 static bool 703 pmap_not_in_di_l(void) 704 { 705 struct pmap_invl_gen *invl_gen; 706 707 invl_gen = &curthread->td_md.md_invl_gen; 708 return (invl_gen->gen == 0); 709 } 710 711 static void 712 pmap_thread_init_invl_gen_l(struct thread *td) 713 { 714 struct pmap_invl_gen *invl_gen; 715 716 invl_gen = &td->td_md.md_invl_gen; 717 invl_gen->gen = 0; 718 } 719 720 static void 721 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen) 722 { 723 struct turnstile *ts; 724 725 ts = turnstile_trywait(&invl_gen_ts); 726 if (*m_gen > atomic_load_long(invl_gen)) 727 turnstile_wait(ts, NULL, TS_SHARED_QUEUE); 728 else 729 turnstile_cancel(ts); 730 } 731 732 static void 733 pmap_delayed_invl_finish_unblock(u_long new_gen) 734 { 735 struct turnstile *ts; 736 737 turnstile_chain_lock(&invl_gen_ts); 738 ts = turnstile_lookup(&invl_gen_ts); 739 if (new_gen != 0) 740 pmap_invl_gen = new_gen; 741 if (ts != NULL) { 742 turnstile_broadcast(ts, TS_SHARED_QUEUE); 743 turnstile_unpend(ts); 744 } 745 turnstile_chain_unlock(&invl_gen_ts); 746 } 747 748 /* 749 * Start a new Delayed Invalidation (DI) block of code, executed by 750 * the current thread. Within a DI block, the current thread may 751 * destroy both the page table and PV list entries for a mapping and 752 * then release the corresponding PV list lock before ensuring that 753 * the mapping is flushed from the TLBs of any processors with the 754 * pmap active. 755 */ 756 static void 757 pmap_delayed_invl_start_l(void) 758 { 759 struct pmap_invl_gen *invl_gen; 760 u_long currgen; 761 762 invl_gen = &curthread->td_md.md_invl_gen; 763 PMAP_ASSERT_NOT_IN_DI(); 764 mtx_lock(&invl_gen_mtx); 765 if (LIST_EMPTY(&pmap_invl_gen_tracker)) 766 currgen = pmap_invl_gen; 767 else 768 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen; 769 invl_gen->gen = currgen + 1; 770 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link); 771 mtx_unlock(&invl_gen_mtx); 772 } 773 774 /* 775 * Finish the DI block, previously started by the current thread. All 776 * required TLB flushes for the pages marked by 777 * pmap_delayed_invl_page() must be finished before this function is 778 * called. 779 * 780 * This function works by bumping the global DI generation number to 781 * the generation number of the current thread's DI, unless there is a 782 * pending DI that started earlier. In the latter case, bumping the 783 * global DI generation number would incorrectly signal that the 784 * earlier DI had finished. Instead, this function bumps the earlier 785 * DI's generation number to match the generation number of the 786 * current thread's DI. 787 */ 788 static void 789 pmap_delayed_invl_finish_l(void) 790 { 791 struct pmap_invl_gen *invl_gen, *next; 792 793 invl_gen = &curthread->td_md.md_invl_gen; 794 KASSERT(invl_gen->gen != 0, ("missed invl_start")); 795 mtx_lock(&invl_gen_mtx); 796 next = LIST_NEXT(invl_gen, link); 797 if (next == NULL) 798 pmap_delayed_invl_finish_unblock(invl_gen->gen); 799 else 800 next->gen = invl_gen->gen; 801 LIST_REMOVE(invl_gen, link); 802 mtx_unlock(&invl_gen_mtx); 803 invl_gen->gen = 0; 804 } 805 806 static bool 807 pmap_not_in_di_u(void) 808 { 809 struct pmap_invl_gen *invl_gen; 810 811 invl_gen = &curthread->td_md.md_invl_gen; 812 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0); 813 } 814 815 static void 816 pmap_thread_init_invl_gen_u(struct thread *td) 817 { 818 struct pmap_invl_gen *invl_gen; 819 820 invl_gen = &td->td_md.md_invl_gen; 821 invl_gen->gen = 0; 822 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID; 823 } 824 825 static bool 826 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out) 827 { 828 uint64_t new_high, new_low, old_high, old_low; 829 char res; 830 831 old_low = new_low = 0; 832 old_high = new_high = (uintptr_t)0; 833 834 __asm volatile("lock;cmpxchg16b\t%1" 835 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high) 836 : "b"(new_low), "c" (new_high) 837 : "memory", "cc"); 838 if (res == 0) { 839 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0) 840 return (false); 841 out->gen = old_low; 842 out->next = (void *)old_high; 843 } else { 844 out->gen = new_low; 845 out->next = (void *)new_high; 846 } 847 return (true); 848 } 849 850 static bool 851 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val, 852 struct pmap_invl_gen *new_val) 853 { 854 uint64_t new_high, new_low, old_high, old_low; 855 char res; 856 857 new_low = new_val->gen; 858 new_high = (uintptr_t)new_val->next; 859 old_low = old_val->gen; 860 old_high = (uintptr_t)old_val->next; 861 862 __asm volatile("lock;cmpxchg16b\t%1" 863 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high) 864 : "b"(new_low), "c" (new_high) 865 : "memory", "cc"); 866 return (res); 867 } 868 869 static COUNTER_U64_DEFINE_EARLY(pv_page_count); 870 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_page_count, CTLFLAG_RD, 871 &pv_page_count, "Current number of allocated pv pages"); 872 873 static COUNTER_U64_DEFINE_EARLY(user_pt_page_count); 874 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, user_pt_page_count, CTLFLAG_RD, 875 &user_pt_page_count, 876 "Current number of allocated page table pages for userspace"); 877 878 static COUNTER_U64_DEFINE_EARLY(kernel_pt_page_count); 879 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, kernel_pt_page_count, CTLFLAG_RD, 880 &kernel_pt_page_count, 881 "Current number of allocated page table pages for the kernel"); 882 883 #ifdef PV_STATS 884 885 static COUNTER_U64_DEFINE_EARLY(invl_start_restart); 886 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_start_restart, 887 CTLFLAG_RD, &invl_start_restart, 888 "Number of delayed TLB invalidation request restarts"); 889 890 static COUNTER_U64_DEFINE_EARLY(invl_finish_restart); 891 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD, 892 &invl_finish_restart, 893 "Number of delayed TLB invalidation completion restarts"); 894 895 static int invl_max_qlen; 896 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD, 897 &invl_max_qlen, 0, 898 "Maximum delayed TLB invalidation request queue length"); 899 #endif 900 901 #define di_delay locks_delay 902 903 static void 904 pmap_delayed_invl_start_u(void) 905 { 906 struct pmap_invl_gen *invl_gen, *p, prev, new_prev; 907 struct thread *td; 908 struct lock_delay_arg lda; 909 uintptr_t prevl; 910 u_char pri; 911 #ifdef PV_STATS 912 int i, ii; 913 #endif 914 915 td = curthread; 916 invl_gen = &td->td_md.md_invl_gen; 917 PMAP_ASSERT_NOT_IN_DI(); 918 lock_delay_arg_init(&lda, &di_delay); 919 invl_gen->saved_pri = 0; 920 pri = td->td_base_pri; 921 if (pri > PVM) { 922 thread_lock(td); 923 pri = td->td_base_pri; 924 if (pri > PVM) { 925 invl_gen->saved_pri = pri; 926 sched_prio(td, PVM); 927 } 928 thread_unlock(td); 929 } 930 again: 931 PV_STAT(i = 0); 932 for (p = &pmap_invl_gen_head;; p = prev.next) { 933 PV_STAT(i++); 934 prevl = (uintptr_t)atomic_load_ptr(&p->next); 935 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) { 936 PV_STAT(counter_u64_add(invl_start_restart, 1)); 937 lock_delay(&lda); 938 goto again; 939 } 940 if (prevl == 0) 941 break; 942 prev.next = (void *)prevl; 943 } 944 #ifdef PV_STATS 945 if ((ii = invl_max_qlen) < i) 946 atomic_cmpset_int(&invl_max_qlen, ii, i); 947 #endif 948 949 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) { 950 PV_STAT(counter_u64_add(invl_start_restart, 1)); 951 lock_delay(&lda); 952 goto again; 953 } 954 955 new_prev.gen = prev.gen; 956 new_prev.next = invl_gen; 957 invl_gen->gen = prev.gen + 1; 958 959 /* Formal fence between store to invl->gen and updating *p. */ 960 atomic_thread_fence_rel(); 961 962 /* 963 * After inserting an invl_gen element with invalid bit set, 964 * this thread blocks any other thread trying to enter the 965 * delayed invalidation block. Do not allow to remove us from 966 * the CPU, because it causes starvation for other threads. 967 */ 968 critical_enter(); 969 970 /* 971 * ABA for *p is not possible there, since p->gen can only 972 * increase. So if the *p thread finished its di, then 973 * started a new one and got inserted into the list at the 974 * same place, its gen will appear greater than the previously 975 * read gen. 976 */ 977 if (!pmap_di_store_invl(p, &prev, &new_prev)) { 978 critical_exit(); 979 PV_STAT(counter_u64_add(invl_start_restart, 1)); 980 lock_delay(&lda); 981 goto again; 982 } 983 984 /* 985 * There we clear PMAP_INVL_GEN_NEXT_INVALID in 986 * invl_gen->next, allowing other threads to iterate past us. 987 * pmap_di_store_invl() provides fence between the generation 988 * write and the update of next. 989 */ 990 invl_gen->next = NULL; 991 critical_exit(); 992 } 993 994 static bool 995 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen, 996 struct pmap_invl_gen *p) 997 { 998 struct pmap_invl_gen prev, new_prev; 999 u_long mygen; 1000 1001 /* 1002 * Load invl_gen->gen after setting invl_gen->next 1003 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger 1004 * generations to propagate to our invl_gen->gen. Lock prefix 1005 * in atomic_set_ptr() worked as seq_cst fence. 1006 */ 1007 mygen = atomic_load_long(&invl_gen->gen); 1008 1009 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen) 1010 return (false); 1011 1012 KASSERT(prev.gen < mygen, 1013 ("invalid di gen sequence %lu %lu", prev.gen, mygen)); 1014 new_prev.gen = mygen; 1015 new_prev.next = (void *)((uintptr_t)invl_gen->next & 1016 ~PMAP_INVL_GEN_NEXT_INVALID); 1017 1018 /* Formal fence between load of prev and storing update to it. */ 1019 atomic_thread_fence_rel(); 1020 1021 return (pmap_di_store_invl(p, &prev, &new_prev)); 1022 } 1023 1024 static void 1025 pmap_delayed_invl_finish_u(void) 1026 { 1027 struct pmap_invl_gen *invl_gen, *p; 1028 struct thread *td; 1029 struct lock_delay_arg lda; 1030 uintptr_t prevl; 1031 1032 td = curthread; 1033 invl_gen = &td->td_md.md_invl_gen; 1034 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0")); 1035 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0, 1036 ("missed invl_start: INVALID")); 1037 lock_delay_arg_init(&lda, &di_delay); 1038 1039 again: 1040 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) { 1041 prevl = (uintptr_t)atomic_load_ptr(&p->next); 1042 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) { 1043 PV_STAT(counter_u64_add(invl_finish_restart, 1)); 1044 lock_delay(&lda); 1045 goto again; 1046 } 1047 if ((void *)prevl == invl_gen) 1048 break; 1049 } 1050 1051 /* 1052 * It is legitimate to not find ourself on the list if a 1053 * thread before us finished its DI and started it again. 1054 */ 1055 if (__predict_false(p == NULL)) { 1056 PV_STAT(counter_u64_add(invl_finish_restart, 1)); 1057 lock_delay(&lda); 1058 goto again; 1059 } 1060 1061 critical_enter(); 1062 atomic_set_ptr((uintptr_t *)&invl_gen->next, 1063 PMAP_INVL_GEN_NEXT_INVALID); 1064 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) { 1065 atomic_clear_ptr((uintptr_t *)&invl_gen->next, 1066 PMAP_INVL_GEN_NEXT_INVALID); 1067 critical_exit(); 1068 PV_STAT(counter_u64_add(invl_finish_restart, 1)); 1069 lock_delay(&lda); 1070 goto again; 1071 } 1072 critical_exit(); 1073 if (atomic_load_int(&pmap_invl_waiters) > 0) 1074 pmap_delayed_invl_finish_unblock(0); 1075 if (invl_gen->saved_pri != 0) { 1076 thread_lock(td); 1077 sched_prio(td, invl_gen->saved_pri); 1078 thread_unlock(td); 1079 } 1080 } 1081 1082 #ifdef DDB 1083 DB_SHOW_COMMAND(di_queue, pmap_di_queue) 1084 { 1085 struct pmap_invl_gen *p, *pn; 1086 struct thread *td; 1087 uintptr_t nextl; 1088 bool first; 1089 1090 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn, 1091 first = false) { 1092 nextl = (uintptr_t)atomic_load_ptr(&p->next); 1093 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID); 1094 td = first ? NULL : __containerof(p, struct thread, 1095 td_md.md_invl_gen); 1096 db_printf("gen %lu inv %d td %p tid %d\n", p->gen, 1097 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td, 1098 td != NULL ? td->td_tid : -1); 1099 } 1100 } 1101 #endif 1102 1103 #ifdef PV_STATS 1104 static COUNTER_U64_DEFINE_EARLY(invl_wait); 1105 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait, 1106 CTLFLAG_RD, &invl_wait, 1107 "Number of times DI invalidation blocked pmap_remove_all/write"); 1108 1109 static COUNTER_U64_DEFINE_EARLY(invl_wait_slow); 1110 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, 1111 &invl_wait_slow, "Number of slow invalidation waits for lockless DI"); 1112 1113 #endif 1114 1115 #ifdef NUMA 1116 static u_long * 1117 pmap_delayed_invl_genp(vm_page_t m) 1118 { 1119 vm_paddr_t pa; 1120 u_long *gen; 1121 1122 pa = VM_PAGE_TO_PHYS(m); 1123 if (__predict_false((pa) > pmap_last_pa)) 1124 gen = &pv_dummy_large.pv_invl_gen; 1125 else 1126 gen = &(pa_to_pmdp(pa)->pv_invl_gen); 1127 1128 return (gen); 1129 } 1130 #else 1131 static u_long * 1132 pmap_delayed_invl_genp(vm_page_t m) 1133 { 1134 1135 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]); 1136 } 1137 #endif 1138 1139 static void 1140 pmap_delayed_invl_callout_func(void *arg __unused) 1141 { 1142 1143 if (atomic_load_int(&pmap_invl_waiters) == 0) 1144 return; 1145 pmap_delayed_invl_finish_unblock(0); 1146 } 1147 1148 static void 1149 pmap_delayed_invl_callout_init(void *arg __unused) 1150 { 1151 1152 if (pmap_di_locked()) 1153 return; 1154 callout_init(&pmap_invl_callout, 1); 1155 pmap_invl_callout_inited = true; 1156 } 1157 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY, 1158 pmap_delayed_invl_callout_init, NULL); 1159 1160 /* 1161 * Ensure that all currently executing DI blocks, that need to flush 1162 * TLB for the given page m, actually flushed the TLB at the time the 1163 * function returned. If the page m has an empty PV list and we call 1164 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a 1165 * valid mapping for the page m in either its page table or TLB. 1166 * 1167 * This function works by blocking until the global DI generation 1168 * number catches up with the generation number associated with the 1169 * given page m and its PV list. Since this function's callers 1170 * typically own an object lock and sometimes own a page lock, it 1171 * cannot sleep. Instead, it blocks on a turnstile to relinquish the 1172 * processor. 1173 */ 1174 static void 1175 pmap_delayed_invl_wait_l(vm_page_t m) 1176 { 1177 u_long *m_gen; 1178 #ifdef PV_STATS 1179 bool accounted = false; 1180 #endif 1181 1182 m_gen = pmap_delayed_invl_genp(m); 1183 while (*m_gen > pmap_invl_gen) { 1184 #ifdef PV_STATS 1185 if (!accounted) { 1186 counter_u64_add(invl_wait, 1); 1187 accounted = true; 1188 } 1189 #endif 1190 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen); 1191 } 1192 } 1193 1194 static void 1195 pmap_delayed_invl_wait_u(vm_page_t m) 1196 { 1197 u_long *m_gen; 1198 struct lock_delay_arg lda; 1199 bool fast; 1200 1201 fast = true; 1202 m_gen = pmap_delayed_invl_genp(m); 1203 lock_delay_arg_init(&lda, &di_delay); 1204 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) { 1205 if (fast || !pmap_invl_callout_inited) { 1206 PV_STAT(counter_u64_add(invl_wait, 1)); 1207 lock_delay(&lda); 1208 fast = false; 1209 } else { 1210 /* 1211 * The page's invalidation generation number 1212 * is still below the current thread's number. 1213 * Prepare to block so that we do not waste 1214 * CPU cycles or worse, suffer livelock. 1215 * 1216 * Since it is impossible to block without 1217 * racing with pmap_delayed_invl_finish_u(), 1218 * prepare for the race by incrementing 1219 * pmap_invl_waiters and arming a 1-tick 1220 * callout which will unblock us if we lose 1221 * the race. 1222 */ 1223 atomic_add_int(&pmap_invl_waiters, 1); 1224 1225 /* 1226 * Re-check the current thread's invalidation 1227 * generation after incrementing 1228 * pmap_invl_waiters, so that there is no race 1229 * with pmap_delayed_invl_finish_u() setting 1230 * the page generation and checking 1231 * pmap_invl_waiters. The only race allowed 1232 * is for a missed unblock, which is handled 1233 * by the callout. 1234 */ 1235 if (*m_gen > 1236 atomic_load_long(&pmap_invl_gen_head.gen)) { 1237 callout_reset(&pmap_invl_callout, 1, 1238 pmap_delayed_invl_callout_func, NULL); 1239 PV_STAT(counter_u64_add(invl_wait_slow, 1)); 1240 pmap_delayed_invl_wait_block(m_gen, 1241 &pmap_invl_gen_head.gen); 1242 } 1243 atomic_add_int(&pmap_invl_waiters, -1); 1244 } 1245 } 1246 } 1247 1248 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *)) 1249 { 1250 1251 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l : 1252 pmap_thread_init_invl_gen_u); 1253 } 1254 1255 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void)) 1256 { 1257 1258 return (pmap_di_locked() ? pmap_delayed_invl_start_l : 1259 pmap_delayed_invl_start_u); 1260 } 1261 1262 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void)) 1263 { 1264 1265 return (pmap_di_locked() ? pmap_delayed_invl_finish_l : 1266 pmap_delayed_invl_finish_u); 1267 } 1268 1269 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t)) 1270 { 1271 1272 return (pmap_di_locked() ? pmap_delayed_invl_wait_l : 1273 pmap_delayed_invl_wait_u); 1274 } 1275 1276 /* 1277 * Mark the page m's PV list as participating in the current thread's 1278 * DI block. Any threads concurrently using m's PV list to remove or 1279 * restrict all mappings to m will wait for the current thread's DI 1280 * block to complete before proceeding. 1281 * 1282 * The function works by setting the DI generation number for m's PV 1283 * list to at least the DI generation number of the current thread. 1284 * This forces a caller of pmap_delayed_invl_wait() to block until 1285 * current thread calls pmap_delayed_invl_finish(). 1286 */ 1287 static void 1288 pmap_delayed_invl_page(vm_page_t m) 1289 { 1290 u_long gen, *m_gen; 1291 1292 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED); 1293 gen = curthread->td_md.md_invl_gen.gen; 1294 if (gen == 0) 1295 return; 1296 m_gen = pmap_delayed_invl_genp(m); 1297 if (*m_gen < gen) 1298 *m_gen = gen; 1299 } 1300 1301 /* 1302 * Crashdump maps. 1303 */ 1304 static caddr_t crashdumpmap; 1305 1306 /* 1307 * Internal flags for pmap_enter()'s helper functions. 1308 */ 1309 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */ 1310 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */ 1311 1312 /* 1313 * Internal flags for pmap_mapdev_internal() and 1314 * pmap_change_props_locked(). 1315 */ 1316 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */ 1317 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */ 1318 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */ 1319 1320 TAILQ_HEAD(pv_chunklist, pv_chunk); 1321 1322 static void free_pv_chunk(struct pv_chunk *pc); 1323 static void free_pv_chunk_batch(struct pv_chunklist *batch); 1324 static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 1325 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp); 1326 static int popcnt_pc_map_pq(uint64_t *map); 1327 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp); 1328 static void reserve_pv_entries(pmap_t pmap, int needed, 1329 struct rwlock **lockp); 1330 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1331 struct rwlock **lockp); 1332 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, 1333 u_int flags, struct rwlock **lockp); 1334 #if VM_NRESERVLEVEL > 0 1335 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1336 struct rwlock **lockp); 1337 #endif 1338 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 1339 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 1340 vm_offset_t va); 1341 1342 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte); 1343 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size, 1344 vm_prot_t prot, int mode, int flags); 1345 static bool pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 1346 static bool pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, 1347 vm_offset_t va, struct rwlock **lockp); 1348 static bool pmap_demote_pde_mpte(pmap_t pmap, pd_entry_t *pde, 1349 vm_offset_t va, struct rwlock **lockp, vm_page_t mpte); 1350 static bool pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, 1351 vm_offset_t va, vm_page_t m); 1352 static int pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, 1353 vm_prot_t prot, struct rwlock **lockp); 1354 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, 1355 u_int flags, vm_page_t m, struct rwlock **lockp); 1356 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 1357 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp); 1358 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 1359 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted, 1360 bool allpte_PG_A_set); 1361 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, 1362 vm_offset_t eva); 1363 static void pmap_invalidate_cache_range_all(vm_offset_t sva, 1364 vm_offset_t eva); 1365 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, 1366 pd_entry_t pde); 1367 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 1368 static vm_page_t pmap_large_map_getptp_unlocked(void); 1369 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va); 1370 #if VM_NRESERVLEVEL > 0 1371 static bool pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, 1372 vm_page_t mpte, struct rwlock **lockp); 1373 #endif 1374 static bool pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 1375 vm_prot_t prot); 1376 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask); 1377 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, 1378 bool exec); 1379 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va); 1380 static pd_entry_t *pmap_pti_pde(vm_offset_t va); 1381 static void pmap_pti_wire_pte(void *pte); 1382 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 1383 bool demote_kpde, struct spglist *free, struct rwlock **lockp); 1384 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 1385 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp); 1386 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va); 1387 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 1388 struct spglist *free); 1389 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1390 pd_entry_t *pde, struct spglist *free, 1391 struct rwlock **lockp); 1392 static bool pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 1393 vm_page_t m, struct rwlock **lockp); 1394 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 1395 pd_entry_t newpde); 1396 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde); 1397 1398 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp, 1399 struct rwlock **lockp); 1400 static vm_page_t pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, 1401 struct rwlock **lockp, vm_offset_t va); 1402 static vm_page_t pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, 1403 struct rwlock **lockp, vm_offset_t va); 1404 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, 1405 struct rwlock **lockp); 1406 1407 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, 1408 struct spglist *free); 1409 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *); 1410 1411 static vm_page_t pmap_alloc_pt_page(pmap_t, vm_pindex_t, int); 1412 static void pmap_free_pt_page(pmap_t, vm_page_t, bool); 1413 1414 /********************/ 1415 /* Inline functions */ 1416 /********************/ 1417 1418 /* 1419 * Return a non-clipped indexes for a given VA, which are page table 1420 * pages indexes at the corresponding level. 1421 */ 1422 static __inline vm_pindex_t 1423 pmap_pde_pindex(vm_offset_t va) 1424 { 1425 return (va >> PDRSHIFT); 1426 } 1427 1428 static __inline vm_pindex_t 1429 pmap_pdpe_pindex(vm_offset_t va) 1430 { 1431 return (NUPDE + (va >> PDPSHIFT)); 1432 } 1433 1434 static __inline vm_pindex_t 1435 pmap_pml4e_pindex(vm_offset_t va) 1436 { 1437 return (NUPDE + NUPDPE + (va >> PML4SHIFT)); 1438 } 1439 1440 static __inline vm_pindex_t 1441 pmap_pml5e_pindex(vm_offset_t va) 1442 { 1443 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT)); 1444 } 1445 1446 static __inline pml4_entry_t * 1447 pmap_pml5e(pmap_t pmap, vm_offset_t va) 1448 { 1449 1450 MPASS(pmap_is_la57(pmap)); 1451 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]); 1452 } 1453 1454 static __inline pml4_entry_t * 1455 pmap_pml5e_u(pmap_t pmap, vm_offset_t va) 1456 { 1457 1458 MPASS(pmap_is_la57(pmap)); 1459 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]); 1460 } 1461 1462 static __inline pml4_entry_t * 1463 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va) 1464 { 1465 pml4_entry_t *pml4e; 1466 1467 /* XXX MPASS(pmap_is_la57(pmap); */ 1468 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME); 1469 return (&pml4e[pmap_pml4e_index(va)]); 1470 } 1471 1472 /* Return a pointer to the PML4 slot that corresponds to a VA */ 1473 static __inline pml4_entry_t * 1474 pmap_pml4e(pmap_t pmap, vm_offset_t va) 1475 { 1476 pml5_entry_t *pml5e; 1477 pml4_entry_t *pml4e; 1478 pt_entry_t PG_V; 1479 1480 if (pmap_is_la57(pmap)) { 1481 pml5e = pmap_pml5e(pmap, va); 1482 PG_V = pmap_valid_bit(pmap); 1483 if ((*pml5e & PG_V) == 0) 1484 return (NULL); 1485 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME); 1486 } else { 1487 pml4e = pmap->pm_pmltop; 1488 } 1489 return (&pml4e[pmap_pml4e_index(va)]); 1490 } 1491 1492 static __inline pml4_entry_t * 1493 pmap_pml4e_u(pmap_t pmap, vm_offset_t va) 1494 { 1495 MPASS(!pmap_is_la57(pmap)); 1496 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]); 1497 } 1498 1499 /* Return a pointer to the PDP slot that corresponds to a VA */ 1500 static __inline pdp_entry_t * 1501 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va) 1502 { 1503 pdp_entry_t *pdpe; 1504 1505 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME); 1506 return (&pdpe[pmap_pdpe_index(va)]); 1507 } 1508 1509 /* Return a pointer to the PDP slot that corresponds to a VA */ 1510 static __inline pdp_entry_t * 1511 pmap_pdpe(pmap_t pmap, vm_offset_t va) 1512 { 1513 pml4_entry_t *pml4e; 1514 pt_entry_t PG_V; 1515 1516 PG_V = pmap_valid_bit(pmap); 1517 pml4e = pmap_pml4e(pmap, va); 1518 if (pml4e == NULL || (*pml4e & PG_V) == 0) 1519 return (NULL); 1520 return (pmap_pml4e_to_pdpe(pml4e, va)); 1521 } 1522 1523 /* Return a pointer to the PD slot that corresponds to a VA */ 1524 static __inline pd_entry_t * 1525 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va) 1526 { 1527 pd_entry_t *pde; 1528 1529 KASSERT((*pdpe & PG_PS) == 0, 1530 ("%s: pdpe %#lx is a leaf", __func__, *pdpe)); 1531 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME); 1532 return (&pde[pmap_pde_index(va)]); 1533 } 1534 1535 /* Return a pointer to the PD slot that corresponds to a VA */ 1536 static __inline pd_entry_t * 1537 pmap_pde(pmap_t pmap, vm_offset_t va) 1538 { 1539 pdp_entry_t *pdpe; 1540 pt_entry_t PG_V; 1541 1542 PG_V = pmap_valid_bit(pmap); 1543 pdpe = pmap_pdpe(pmap, va); 1544 if (pdpe == NULL || (*pdpe & PG_V) == 0) 1545 return (NULL); 1546 KASSERT((*pdpe & PG_PS) == 0, 1547 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va)); 1548 return (pmap_pdpe_to_pde(pdpe, va)); 1549 } 1550 1551 /* Return a pointer to the PT slot that corresponds to a VA */ 1552 static __inline pt_entry_t * 1553 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va) 1554 { 1555 pt_entry_t *pte; 1556 1557 KASSERT((*pde & PG_PS) == 0, 1558 ("%s: pde %#lx is a leaf", __func__, *pde)); 1559 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME); 1560 return (&pte[pmap_pte_index(va)]); 1561 } 1562 1563 /* Return a pointer to the PT slot that corresponds to a VA */ 1564 static __inline pt_entry_t * 1565 pmap_pte(pmap_t pmap, vm_offset_t va) 1566 { 1567 pd_entry_t *pde; 1568 pt_entry_t PG_V; 1569 1570 PG_V = pmap_valid_bit(pmap); 1571 pde = pmap_pde(pmap, va); 1572 if (pde == NULL || (*pde & PG_V) == 0) 1573 return (NULL); 1574 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */ 1575 return ((pt_entry_t *)pde); 1576 return (pmap_pde_to_pte(pde, va)); 1577 } 1578 1579 static __inline void 1580 pmap_resident_count_adj(pmap_t pmap, int count) 1581 { 1582 1583 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1584 KASSERT(pmap->pm_stats.resident_count + count >= 0, 1585 ("pmap %p resident count underflow %ld %d", pmap, 1586 pmap->pm_stats.resident_count, count)); 1587 pmap->pm_stats.resident_count += count; 1588 } 1589 1590 static __inline void 1591 pmap_pt_page_count_pinit(pmap_t pmap, int count) 1592 { 1593 KASSERT(pmap->pm_stats.resident_count + count >= 0, 1594 ("pmap %p resident count underflow %ld %d", pmap, 1595 pmap->pm_stats.resident_count, count)); 1596 pmap->pm_stats.resident_count += count; 1597 } 1598 1599 static __inline void 1600 pmap_pt_page_count_adj(pmap_t pmap, int count) 1601 { 1602 if (pmap == kernel_pmap) 1603 counter_u64_add(kernel_pt_page_count, count); 1604 else { 1605 if (pmap != NULL) 1606 pmap_resident_count_adj(pmap, count); 1607 counter_u64_add(user_pt_page_count, count); 1608 } 1609 } 1610 1611 pt_entry_t vtoptem __read_mostly = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + 1612 NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1) << 3; 1613 vm_offset_t PTmap __read_mostly = (vm_offset_t)P4Tmap; 1614 1615 pt_entry_t * 1616 vtopte(vm_offset_t va) 1617 { 1618 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va)); 1619 1620 return ((pt_entry_t *)(PTmap + ((va >> (PAGE_SHIFT - 3)) & vtoptem))); 1621 } 1622 1623 pd_entry_t vtopdem __read_mostly = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + 1624 NPML4EPGSHIFT)) - 1) << 3; 1625 vm_offset_t PDmap __read_mostly = (vm_offset_t)P4Dmap; 1626 1627 static __inline pd_entry_t * 1628 vtopde(vm_offset_t va) 1629 { 1630 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va)); 1631 1632 return ((pt_entry_t *)(PDmap + ((va >> (PDRSHIFT - 3)) & vtopdem))); 1633 } 1634 1635 static u_int64_t 1636 allocpages(vm_paddr_t *firstaddr, int n) 1637 { 1638 u_int64_t ret; 1639 1640 ret = *firstaddr; 1641 bzero((void *)ret, n * PAGE_SIZE); 1642 *firstaddr += n * PAGE_SIZE; 1643 return (ret); 1644 } 1645 1646 CTASSERT(powerof2(NDMPML4E)); 1647 1648 /* number of kernel PDP slots */ 1649 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG) 1650 1651 static void 1652 nkpt_init(vm_paddr_t addr) 1653 { 1654 int pt_pages; 1655 1656 #ifdef NKPT 1657 pt_pages = NKPT; 1658 #else 1659 pt_pages = howmany(addr - kernphys, NBPDR) + 1; /* +1 for 2M hole @0 */ 1660 pt_pages += NKPDPE(pt_pages); 1661 1662 /* 1663 * Add some slop beyond the bare minimum required for bootstrapping 1664 * the kernel. 1665 * 1666 * This is quite important when allocating KVA for kernel modules. 1667 * The modules are required to be linked in the negative 2GB of 1668 * the address space. If we run out of KVA in this region then 1669 * pmap_growkernel() will need to allocate page table pages to map 1670 * the entire 512GB of KVA space which is an unnecessary tax on 1671 * physical memory. 1672 * 1673 * Secondly, device memory mapped as part of setting up the low- 1674 * level console(s) is taken from KVA, starting at virtual_avail. 1675 * This is because cninit() is called after pmap_bootstrap() but 1676 * before vm_mem_init() and pmap_init(). 20MB for a frame buffer 1677 * is not uncommon. 1678 */ 1679 pt_pages += 32; /* 64MB additional slop. */ 1680 #endif 1681 nkpt = pt_pages; 1682 } 1683 1684 /* 1685 * Returns the proper write/execute permission for a physical page that is 1686 * part of the initial boot allocations. 1687 * 1688 * If the page has kernel text, it is marked as read-only. If the page has 1689 * kernel read-only data, it is marked as read-only/not-executable. If the 1690 * page has only read-write data, it is marked as read-write/not-executable. 1691 * If the page is below/above the kernel range, it is marked as read-write. 1692 * 1693 * This function operates on 2M pages, since we map the kernel space that 1694 * way. 1695 */ 1696 static inline pt_entry_t 1697 bootaddr_rwx(vm_paddr_t pa) 1698 { 1699 /* 1700 * The kernel is loaded at a 2MB-aligned address, and memory below that 1701 * need not be executable. The .bss section is padded to a 2MB 1702 * boundary, so memory following the kernel need not be executable 1703 * either. Preloaded kernel modules have their mapping permissions 1704 * fixed up by the linker. 1705 */ 1706 if (pa < trunc_2mpage(kernphys + btext - KERNSTART) || 1707 pa >= trunc_2mpage(kernphys + _end - KERNSTART)) 1708 return (X86_PG_RW | pg_nx); 1709 1710 /* 1711 * The linker should ensure that the read-only and read-write 1712 * portions don't share the same 2M page, so this shouldn't 1713 * impact read-only data. However, in any case, any page with 1714 * read-write data needs to be read-write. 1715 */ 1716 if (pa >= trunc_2mpage(kernphys + brwsection - KERNSTART)) 1717 return (X86_PG_RW | pg_nx); 1718 1719 /* 1720 * Mark any 2M page containing kernel text as read-only. Mark 1721 * other pages with read-only data as read-only and not executable. 1722 * (It is likely a small portion of the read-only data section will 1723 * be marked as read-only, but executable. This should be acceptable 1724 * since the read-only protection will keep the data from changing.) 1725 * Note that fixups to the .text section will still work until we 1726 * set CR0.WP. 1727 */ 1728 if (pa < round_2mpage(kernphys + etext - KERNSTART)) 1729 return (0); 1730 return (pg_nx); 1731 } 1732 1733 extern const char la57_trampoline[]; 1734 1735 static void 1736 pmap_bootstrap_la57(vm_paddr_t *firstaddr) 1737 { 1738 void (*la57_tramp)(uint64_t pml5); 1739 pml5_entry_t *pt; 1740 uint64_t cr4; 1741 1742 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0) 1743 return; 1744 la57 = 1; 1745 TUNABLE_INT_FETCH("vm.pmap.la57", &la57); 1746 if (!la57) 1747 return; 1748 1749 KPML5phys = allocpages(firstaddr, 1); 1750 KPML4phys = rcr3() & 0xfffff000; /* pml4 from loader must be < 4G */ 1751 1752 pt = (pml5_entry_t *)KPML5phys; 1753 pt[0] = KPML4phys | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M; 1754 pt[NPML4EPG - 1] = KPML4phys | X86_PG_V | X86_PG_RW | X86_PG_A | 1755 X86_PG_M; 1756 1757 la57_tramp = (void (*)(uint64_t))((uintptr_t)la57_trampoline - 1758 KERNSTART + amd64_loadaddr()); 1759 printf("Calling la57 trampoline at %p, KPML5phys %#lx ...", 1760 la57_tramp, KPML5phys); 1761 if (lass_enabled) { 1762 cr4 = rcr4(); 1763 load_cr4(cr4 & ~CR4_LASS); 1764 } 1765 la57_tramp(KPML5phys); 1766 printf(" alive in la57 mode\n"); 1767 if (lass_enabled) { 1768 cr4 = rcr4(); 1769 load_cr4(cr4 | CR4_LASS); 1770 } 1771 } 1772 1773 static void 1774 create_pagetables(vm_paddr_t *firstaddr) 1775 { 1776 pd_entry_t *pd_p; 1777 pdp_entry_t *pdp_p; 1778 pml4_entry_t *p4_p, *p4d_p; 1779 pml5_entry_t *p5_p; 1780 uint64_t DMPDkernphys; 1781 vm_paddr_t pax; 1782 #ifdef KASAN 1783 pt_entry_t *pt_p; 1784 uint64_t KASANPDphys, KASANPTphys, KASANphys; 1785 vm_offset_t kasankernbase; 1786 int kasankpdpi, kasankpdi, nkasanpte; 1787 #endif 1788 int i, j, ndm1g, nkpdpe, nkdmpde, ndmpml4phys; 1789 1790 TSENTER(); 1791 /* Allocate page table pages for the direct map */ 1792 ndmpdp = howmany(ptoa(Maxmem), NBPDP); 1793 if (ndmpdp < 4) /* Minimum 4GB of dirmap */ 1794 ndmpdp = 4; 1795 ndmpdpphys = howmany(ndmpdp, NPDPEPG); 1796 if (la57) { 1797 ndmpml4phys = howmany(ndmpdpphys, NPML4EPG); 1798 if (ndmpml4phys > NDMPML5E) { 1799 printf("NDMPML5E limits system to %ld GB\n", 1800 (u_long)NDMPML5E * NBPML5 / 1024 / 1024 / 1024); 1801 Maxmem = atop(NDMPML5E * NBPML5); 1802 ndmpml4phys = NDMPML5E; 1803 ndmpdpphys = ndmpml4phys * NPML4EPG; 1804 ndmpdp = ndmpdpphys * NPDEPG; 1805 } 1806 DMPML4phys = allocpages(firstaddr, ndmpml4phys); 1807 } else { 1808 if (ndmpdpphys > NDMPML4E) { 1809 /* 1810 * Each NDMPML4E allows 512 GB, so limit to 1811 * that, and then readjust ndmpdp and 1812 * ndmpdpphys. 1813 */ 1814 printf("NDMPML4E limits system to %d GB\n", 1815 NDMPML4E * 512); 1816 Maxmem = atop(NDMPML4E * NBPML4); 1817 ndmpdpphys = NDMPML4E; 1818 ndmpdp = NDMPML4E * NPDEPG; 1819 } 1820 } 1821 DMPDPphys = allocpages(firstaddr, ndmpdpphys); 1822 ndm1g = 0; 1823 if ((amd_feature & AMDID_PAGE1GB) != 0) { 1824 /* 1825 * Calculate the number of 1G pages that will fully fit in 1826 * Maxmem. 1827 */ 1828 ndm1g = ptoa(Maxmem) >> PDPSHIFT; 1829 1830 /* 1831 * Allocate 2M pages for the kernel. These will be used in 1832 * place of the one or more 1G pages from ndm1g that maps 1833 * kernel memory into DMAP. 1834 */ 1835 nkdmpde = howmany((vm_offset_t)brwsection - KERNSTART + 1836 kernphys - rounddown2(kernphys, NBPDP), NBPDP); 1837 DMPDkernphys = allocpages(firstaddr, nkdmpde); 1838 } 1839 if (ndm1g < ndmpdp) 1840 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g); 1841 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT; 1842 1843 /* Allocate pages. */ 1844 if (la57) { 1845 KPML5phys = allocpages(firstaddr, 1); 1846 p5_p = (pml5_entry_t *)KPML5phys; 1847 } 1848 KPML4phys = allocpages(firstaddr, 1); 1849 p4_p = (pml4_entry_t *)KPML4phys; 1850 1851 KPDPphys = allocpages(firstaddr, NKPML4E); 1852 #ifdef KASAN 1853 KASANPDPphys = allocpages(firstaddr, NKASANPML4E); 1854 KASANPDphys = allocpages(firstaddr, 1); 1855 #endif 1856 #ifdef KMSAN 1857 /* 1858 * The KMSAN shadow maps are initially left unpopulated, since there is 1859 * no need to shadow memory above KERNBASE. 1860 */ 1861 KMSANSHADPDPphys = allocpages(firstaddr, NKMSANSHADPML4E); 1862 KMSANORIGPDPphys = allocpages(firstaddr, NKMSANORIGPML4E); 1863 #endif 1864 1865 /* 1866 * Allocate the initial number of kernel page table pages required to 1867 * bootstrap. We defer this until after all memory-size dependent 1868 * allocations are done (e.g. direct map), so that we don't have to 1869 * build in too much slop in our estimate. 1870 * 1871 * Note that when NKPML4E > 1, we have an empty page underneath 1872 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed) 1873 * pages. (pmap_enter requires a PD page to exist for each KPML4E.) 1874 */ 1875 nkpt_init(*firstaddr); 1876 nkpdpe = NKPDPE(nkpt); 1877 1878 KPTphys = allocpages(firstaddr, nkpt); 1879 KPDphys = allocpages(firstaddr, nkpdpe); 1880 1881 #ifdef KASAN 1882 nkasanpte = howmany(nkpt, KASAN_SHADOW_SCALE); 1883 KASANPTphys = allocpages(firstaddr, nkasanpte); 1884 KASANphys = allocpages(firstaddr, nkasanpte * NPTEPG); 1885 #endif 1886 1887 /* 1888 * Connect the zero-filled PT pages to their PD entries. This 1889 * implicitly maps the PT pages at their correct locations within 1890 * the PTmap. 1891 */ 1892 pd_p = (pd_entry_t *)KPDphys; 1893 for (i = 0; i < nkpt; i++) 1894 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V; 1895 1896 /* 1897 * Map from start of the kernel in physical memory (staging 1898 * area) to the end of loader preallocated memory using 2MB 1899 * pages. This replaces some of the PD entries created above. 1900 * For compatibility, identity map 2M at the start. 1901 */ 1902 pd_p[0] = X86_PG_V | PG_PS | pg_g | X86_PG_M | X86_PG_A | 1903 X86_PG_RW | pg_nx; 1904 for (i = 1, pax = kernphys; pax < KERNend; i++, pax += NBPDR) { 1905 /* Preset PG_M and PG_A because demotion expects it. */ 1906 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M | 1907 X86_PG_A | bootaddr_rwx(pax); 1908 } 1909 1910 /* 1911 * Because we map the physical blocks in 2M pages, adjust firstaddr 1912 * to record the physical blocks we've actually mapped into kernel 1913 * virtual address space. 1914 */ 1915 if (*firstaddr < round_2mpage(KERNend)) 1916 *firstaddr = round_2mpage(KERNend); 1917 1918 /* And connect up the PD to the PDP (leaving room for L4 pages) */ 1919 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE)); 1920 for (i = 0; i < nkpdpe; i++) 1921 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V; 1922 1923 #ifdef KASAN 1924 kasankernbase = kasan_md_addr_to_shad(KERNBASE); 1925 kasankpdpi = pmap_pdpe_index(kasankernbase); 1926 kasankpdi = pmap_pde_index(kasankernbase); 1927 1928 pdp_p = (pdp_entry_t *)KASANPDPphys; 1929 pdp_p[kasankpdpi] = (KASANPDphys | X86_PG_RW | X86_PG_V | pg_nx); 1930 1931 pd_p = (pd_entry_t *)KASANPDphys; 1932 for (i = 0; i < nkasanpte; i++) 1933 pd_p[i + kasankpdi] = (KASANPTphys + ptoa(i)) | X86_PG_RW | 1934 X86_PG_V | pg_nx; 1935 1936 pt_p = (pt_entry_t *)KASANPTphys; 1937 for (i = 0; i < nkasanpte * NPTEPG; i++) 1938 pt_p[i] = (KASANphys + ptoa(i)) | X86_PG_RW | X86_PG_V | 1939 X86_PG_M | X86_PG_A | pg_nx; 1940 #endif 1941 1942 /* 1943 * Now, set up the direct map region using 2MB and/or 1GB pages. If 1944 * the end of physical memory is not aligned to a 1GB page boundary, 1945 * then the residual physical memory is mapped with 2MB pages. Later, 1946 * if pmap_mapdev{_attr}() uses the direct map for non-write-back 1947 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings 1948 * that are partially used. 1949 */ 1950 pd_p = (pd_entry_t *)DMPDphys; 1951 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) { 1952 pd_p[j] = (vm_paddr_t)i << PDRSHIFT; 1953 /* Preset PG_M and PG_A because demotion expects it. */ 1954 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g | 1955 X86_PG_M | X86_PG_A | pg_nx; 1956 } 1957 pdp_p = (pdp_entry_t *)DMPDPphys; 1958 for (i = 0; i < ndm1g; i++) { 1959 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT; 1960 /* Preset PG_M and PG_A because demotion expects it. */ 1961 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g | 1962 X86_PG_M | X86_PG_A | pg_nx; 1963 } 1964 for (j = 0; i < ndmpdp; i++, j++) { 1965 pdp_p[i] = DMPDphys + ptoa(j); 1966 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx; 1967 } 1968 1969 /* 1970 * Connect the Direct Map slots up to the PML4. 1971 * pml5 entries for DMAP are handled below in global pml5 loop. 1972 */ 1973 p4d_p = la57 ? (pml4_entry_t *)DMPML4phys : &p4_p[DMPML4I]; 1974 for (i = 0; i < ndmpdpphys; i++) { 1975 p4d_p[i] = (DMPDPphys + ptoa(i)) | X86_PG_RW | X86_PG_V | 1976 pg_nx; 1977 } 1978 1979 /* 1980 * Instead of using a 1G page for the memory containing the kernel, 1981 * use 2M pages with read-only and no-execute permissions. (If using 1G 1982 * pages, this will partially overwrite the PDPEs above.) 1983 */ 1984 if (ndm1g > 0) { 1985 pd_p = (pd_entry_t *)DMPDkernphys; 1986 for (i = 0, pax = rounddown2(kernphys, NBPDP); 1987 i < NPDEPG * nkdmpde; i++, pax += NBPDR) { 1988 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M | 1989 X86_PG_A | pg_nx | bootaddr_rwx(pax); 1990 } 1991 j = rounddown2(kernphys, NBPDP) >> PDPSHIFT; 1992 for (i = 0; i < nkdmpde; i++) { 1993 pdp_p[i + j] = (DMPDkernphys + ptoa(i)) | 1994 X86_PG_RW | X86_PG_V | pg_nx; 1995 } 1996 } 1997 1998 #ifdef KASAN 1999 /* Connect the KASAN shadow map slots up to the PML4. */ 2000 for (i = 0; i < NKASANPML4E; i++) { 2001 p4_p[KASANPML4I + i] = KASANPDPphys + ptoa(i); 2002 p4_p[KASANPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx; 2003 } 2004 #endif 2005 2006 #ifdef KMSAN 2007 /* Connect the KMSAN shadow map slots up to the PML4. */ 2008 for (i = 0; i < NKMSANSHADPML4E; i++) { 2009 p4_p[KMSANSHADPML4I + i] = KMSANSHADPDPphys + ptoa(i); 2010 p4_p[KMSANSHADPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx; 2011 } 2012 2013 /* Connect the KMSAN origin map slots up to the PML4. */ 2014 for (i = 0; i < NKMSANORIGPML4E; i++) { 2015 p4_p[KMSANORIGPML4I + i] = KMSANORIGPDPphys + ptoa(i); 2016 p4_p[KMSANORIGPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx; 2017 } 2018 #endif 2019 2020 /* Connect the KVA slots up to the PML4 */ 2021 for (i = 0; i < NKPML4E; i++) { 2022 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i); 2023 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V; 2024 } 2025 2026 if (la57) { 2027 /* XXXKIB bootstrap KPML5phys page is lost */ 2028 for (i = 0; i < NPML5EPG; i++) { 2029 if (i == PML5PML5I) { 2030 /* 2031 * Recursively map PML5 to itself in 2032 * order to get PTmap and PDmap. 2033 */ 2034 p5_p[i] = KPML5phys | X86_PG_RW | X86_PG_A | 2035 X86_PG_M | X86_PG_V | pg_nx; 2036 } else if (i >= DMPML5I && i < DMPML5I + ndmpml4phys) { 2037 /* Connect DMAP pml4 pages to PML5. */ 2038 p5_p[i] = (DMPML4phys + ptoa(i - DMPML5I)) | 2039 X86_PG_RW | X86_PG_V | pg_nx; 2040 } else if (i == pmap_pml5e_index(UPT_MAX_ADDRESS)) { 2041 p5_p[i] = KPML4phys | X86_PG_RW | X86_PG_A | 2042 X86_PG_M | X86_PG_V; 2043 } else { 2044 p5_p[i] = 0; 2045 } 2046 } 2047 } else { 2048 /* Recursively map PML4 to itself in order to get PTmap */ 2049 p4_p[PML4PML4I] = KPML4phys; 2050 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx; 2051 } 2052 TSEXIT(); 2053 } 2054 2055 /* 2056 * Bootstrap the system enough to run with virtual memory. 2057 * 2058 * On amd64 this is called after mapping has already been enabled 2059 * and just syncs the pmap module with what has already been done. 2060 * [We can't call it easily with mapping off since the kernel is not 2061 * mapped with PA == VA, hence we would have to relocate every address 2062 * from the linked base (virtual) address "KERNBASE" to the actual 2063 * (physical) address starting relative to 0] 2064 */ 2065 void 2066 pmap_bootstrap(vm_paddr_t *firstaddr) 2067 { 2068 vm_offset_t va; 2069 pt_entry_t *pte, *pcpu_pte; 2070 struct region_descriptor r_gdt; 2071 uint64_t cr4, pcpu0_phys; 2072 u_long res; 2073 int i; 2074 2075 TSENTER(); 2076 KERNend = *firstaddr; 2077 res = atop(KERNend - (vm_paddr_t)kernphys); 2078 2079 if (!pti) 2080 pg_g = X86_PG_G; 2081 2082 /* 2083 * Create an initial set of page tables to run the kernel in. 2084 */ 2085 pmap_bootstrap_la57(firstaddr); 2086 create_pagetables(firstaddr); 2087 2088 pcpu0_phys = allocpages(firstaddr, 1); 2089 2090 /* 2091 * Add a physical memory segment (vm_phys_seg) corresponding to the 2092 * preallocated kernel page table pages so that vm_page structures 2093 * representing these pages will be created. The vm_page structures 2094 * are required for promotion of the corresponding kernel virtual 2095 * addresses to superpage mappings. 2096 */ 2097 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt)); 2098 2099 /* 2100 * Account for the virtual addresses mapped by create_pagetables(). 2101 */ 2102 virtual_avail = (vm_offset_t)KERNSTART + round_2mpage(KERNend - 2103 (vm_paddr_t)kernphys); 2104 virtual_end = kva_layout.km_high; 2105 2106 /* 2107 * Enable PG_G global pages, then switch to the kernel page 2108 * table from the bootstrap page table. After the switch, it 2109 * is possible to enable SMEP and SMAP since PG_U bits are 2110 * correct now. 2111 */ 2112 cr4 = rcr4(); 2113 cr4 |= CR4_PGE; 2114 load_cr4(cr4); 2115 load_cr3(la57 ? KPML5phys : KPML4phys); 2116 if (cpu_stdext_feature & CPUID_STDEXT_SMEP) 2117 cr4 |= CR4_SMEP; 2118 if (cpu_stdext_feature & CPUID_STDEXT_SMAP) 2119 cr4 |= CR4_SMAP; 2120 load_cr4(cr4); 2121 2122 /* 2123 * Initialize the kernel pmap (which is statically allocated). 2124 * Count bootstrap data as being resident in case any of this data is 2125 * later unmapped (using pmap_remove()) and freed. 2126 * 2127 * DMAP_TO_PHYS()/PHYS_TO_DMAP() are functional only after 2128 * kva_layout is fixed. 2129 */ 2130 PMAP_LOCK_INIT(kernel_pmap); 2131 if (la57) { 2132 kva_layout = kva_layout_la57; 2133 vtoptem = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + 2134 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1) << 3; 2135 PTmap = (vm_offset_t)P5Tmap; 2136 vtopdem = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + 2137 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1) << 3; 2138 PDmap = (vm_offset_t)P5Dmap; 2139 kernel_pmap->pm_pmltop = (void *)PHYS_TO_DMAP(KPML5phys); 2140 kernel_pmap->pm_cr3 = KPML5phys; 2141 pmap_pt_page_count_adj(kernel_pmap, 1); /* top-level page */ 2142 } else { 2143 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys); 2144 kernel_pmap->pm_pmltop = kernel_pml4; 2145 kernel_pmap->pm_cr3 = KPML4phys; 2146 } 2147 kernel_pmap->pm_ucr3 = PMAP_NO_CR3; 2148 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 2149 kernel_pmap->pm_stats.resident_count = res; 2150 vm_radix_init(&kernel_pmap->pm_root); 2151 kernel_pmap->pm_flags = pmap_flags; 2152 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) { 2153 rangeset_init(&kernel_pmap->pm_pkru, pkru_dup_range, 2154 pkru_free_range, kernel_pmap, M_NOWAIT); 2155 } 2156 2157 /* 2158 * The kernel pmap is always active on all CPUs. Once CPUs are 2159 * enumerated, the mask will be set equal to all_cpus. 2160 */ 2161 CPU_FILL(&kernel_pmap->pm_active); 2162 2163 /* 2164 * Initialize the TLB invalidations generation number lock. 2165 */ 2166 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF); 2167 2168 /* 2169 * Reserve some special page table entries/VA space for temporary 2170 * mapping of pages. 2171 */ 2172 #define SYSMAP(c, p, v, n) \ 2173 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2174 2175 va = virtual_avail; 2176 pte = vtopte(va); 2177 2178 /* 2179 * Crashdump maps. The first page is reused as CMAP1 for the 2180 * memory test. 2181 */ 2182 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS) 2183 CADDR1 = crashdumpmap; 2184 2185 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU); 2186 virtual_avail = va; 2187 2188 /* 2189 * Map the BSP PCPU now, the rest of the PCPUs are mapped by 2190 * amd64_mp_alloc_pcpu()/start_all_aps() when we know the 2191 * number of CPUs and NUMA affinity. 2192 */ 2193 pcpu_pte[0] = pcpu0_phys | X86_PG_V | X86_PG_RW | pg_g | pg_nx | 2194 X86_PG_M | X86_PG_A; 2195 for (i = 1; i < MAXCPU; i++) 2196 pcpu_pte[i] = 0; 2197 2198 /* 2199 * Re-initialize PCPU area for BSP after switching. 2200 * Make hardware use gdt and common_tss from the new PCPU. 2201 * Also clears the usage of temporary gdt during switch to 2202 * LA57 paging. 2203 */ 2204 STAILQ_INIT(&cpuhead); 2205 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]); 2206 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu)); 2207 amd64_bsp_pcpu_init1(&__pcpu[0]); 2208 amd64_bsp_ist_init(&__pcpu[0]); 2209 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) + 2210 IOPERM_BITMAP_SIZE; 2211 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT * 2212 sizeof(struct user_segment_descriptor)); 2213 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss; 2214 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2215 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]); 2216 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1; 2217 r_gdt.rd_base = (long)__pcpu[0].pc_gdt; 2218 lgdt(&r_gdt); 2219 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]); 2220 ltr(GSEL(GPROC0_SEL, SEL_KPL)); 2221 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic; 2222 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id; 2223 2224 /* 2225 * Initialize the PAT MSR. 2226 * pmap_init_pat() clears and sets CR4_PGE, which, as a 2227 * side-effect, invalidates stale PG_G TLB entries that might 2228 * have been created in our pre-boot environment. 2229 */ 2230 pmap_init_pat(); 2231 2232 /* Initialize TLB Context Id. */ 2233 if (pmap_pcid_enabled) { 2234 kernel_pmap->pm_pcidp = (void *)(uintptr_t) 2235 offsetof(struct pcpu, pc_kpmap_store); 2236 2237 PCPU_SET(kpmap_store.pm_pcid, PMAP_PCID_KERN); 2238 PCPU_SET(kpmap_store.pm_gen, 1); 2239 2240 /* 2241 * PMAP_PCID_KERN + 1 is used for initialization of 2242 * proc0 pmap. The pmap' pcid state might be used by 2243 * EFIRT entry before first context switch, so it 2244 * needs to be valid. 2245 */ 2246 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2); 2247 PCPU_SET(pcid_gen, 1); 2248 2249 /* 2250 * pcpu area for APs is zeroed during AP startup. 2251 * pc_pcid_next and pc_pcid_gen are initialized by AP 2252 * during pcpu setup. 2253 */ 2254 load_cr4(rcr4() | CR4_PCIDE); 2255 } 2256 TSEXIT(); 2257 } 2258 2259 /* 2260 * Setup the PAT MSR. 2261 */ 2262 void 2263 pmap_init_pat(void) 2264 { 2265 uint64_t pat_msr; 2266 u_long cr0, cr4; 2267 int i; 2268 2269 /* Bail if this CPU doesn't implement PAT. */ 2270 if ((cpu_feature & CPUID_PAT) == 0) 2271 panic("no PAT??"); 2272 2273 /* Set default PAT index table. */ 2274 for (i = 0; i < PAT_INDEX_SIZE; i++) 2275 pat_index[i] = -1; 2276 pat_index[PAT_WRITE_BACK] = 0; 2277 pat_index[PAT_WRITE_THROUGH] = 1; 2278 pat_index[PAT_UNCACHEABLE] = 3; 2279 pat_index[PAT_WRITE_COMBINING] = 6; 2280 pat_index[PAT_WRITE_PROTECTED] = 5; 2281 pat_index[PAT_UNCACHED] = 2; 2282 2283 /* 2284 * Initialize default PAT entries. 2285 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 2286 * Program 5 and 6 as WP and WC. 2287 * 2288 * Leave 4 and 7 as WB and UC. Note that a recursive page table 2289 * mapping for a 2M page uses a PAT value with the bit 3 set due 2290 * to its overload with PG_PS. 2291 */ 2292 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 2293 PAT_VALUE(1, PAT_WRITE_THROUGH) | 2294 PAT_VALUE(2, PAT_UNCACHED) | 2295 PAT_VALUE(3, PAT_UNCACHEABLE) | 2296 PAT_VALUE(4, PAT_WRITE_BACK) | 2297 PAT_VALUE(5, PAT_WRITE_PROTECTED) | 2298 PAT_VALUE(6, PAT_WRITE_COMBINING) | 2299 PAT_VALUE(7, PAT_UNCACHEABLE); 2300 2301 /* Disable PGE. */ 2302 cr4 = rcr4(); 2303 load_cr4(cr4 & ~CR4_PGE); 2304 2305 /* Disable caches (CD = 1, NW = 0). */ 2306 cr0 = rcr0(); 2307 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 2308 2309 /* Flushes caches and TLBs. */ 2310 wbinvd(); 2311 invltlb(); 2312 2313 /* Update PAT and index table. */ 2314 wrmsr(MSR_PAT, pat_msr); 2315 2316 /* Flush caches and TLBs again. */ 2317 wbinvd(); 2318 invltlb(); 2319 2320 /* Restore caches and PGE. */ 2321 load_cr0(cr0); 2322 load_cr4(cr4); 2323 } 2324 2325 vm_page_t 2326 pmap_page_alloc_below_4g(bool zeroed) 2327 { 2328 return (vm_page_alloc_noobj_contig((zeroed ? VM_ALLOC_ZERO : 0), 2329 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT)); 2330 } 2331 2332 /* 2333 * Initialize a vm_page's machine-dependent fields. 2334 */ 2335 void 2336 pmap_page_init(vm_page_t m) 2337 { 2338 2339 TAILQ_INIT(&m->md.pv_list); 2340 m->md.pat_mode = PAT_WRITE_BACK; 2341 } 2342 2343 static int pmap_allow_2m_x_ept; 2344 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 2345 &pmap_allow_2m_x_ept, 0, 2346 "Allow executable superpage mappings in EPT"); 2347 2348 void 2349 pmap_allow_2m_x_ept_recalculate(void) 2350 { 2351 /* 2352 * SKL002, SKL012S. Since the EPT format is only used by 2353 * Intel CPUs, the vendor check is merely a formality. 2354 */ 2355 if (!(cpu_vendor_id != CPU_VENDOR_INTEL || 2356 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 || 2357 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 2358 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */ 2359 CPUID_TO_MODEL(cpu_id) == 0x27 || 2360 CPUID_TO_MODEL(cpu_id) == 0x35 || 2361 CPUID_TO_MODEL(cpu_id) == 0x36 || 2362 CPUID_TO_MODEL(cpu_id) == 0x37 || 2363 CPUID_TO_MODEL(cpu_id) == 0x86 || 2364 CPUID_TO_MODEL(cpu_id) == 0x1c || 2365 CPUID_TO_MODEL(cpu_id) == 0x4a || 2366 CPUID_TO_MODEL(cpu_id) == 0x4c || 2367 CPUID_TO_MODEL(cpu_id) == 0x4d || 2368 CPUID_TO_MODEL(cpu_id) == 0x5a || 2369 CPUID_TO_MODEL(cpu_id) == 0x5c || 2370 CPUID_TO_MODEL(cpu_id) == 0x5d || 2371 CPUID_TO_MODEL(cpu_id) == 0x5f || 2372 CPUID_TO_MODEL(cpu_id) == 0x6e || 2373 CPUID_TO_MODEL(cpu_id) == 0x7a || 2374 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */ 2375 CPUID_TO_MODEL(cpu_id) == 0x85)))) 2376 pmap_allow_2m_x_ept = 1; 2377 #ifndef BURN_BRIDGES 2378 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept); 2379 #endif 2380 TUNABLE_INT_FETCH("vm.pmap.allow_2m_x_ept", &pmap_allow_2m_x_ept); 2381 } 2382 2383 static bool 2384 pmap_allow_2m_x_page(pmap_t pmap, bool executable) 2385 { 2386 2387 return (pmap->pm_type != PT_EPT || !executable || 2388 !pmap_allow_2m_x_ept); 2389 } 2390 2391 #ifdef NUMA 2392 static void 2393 pmap_init_pv_table(void) 2394 { 2395 struct pmap_large_md_page *pvd; 2396 vm_size_t s; 2397 long start, end, highest, pv_npg; 2398 int domain, i, j, pages; 2399 2400 /* 2401 * For correctness we depend on the size being evenly divisible into a 2402 * page. As a tradeoff between performance and total memory use, the 2403 * entry is 64 bytes (aka one cacheline) in size. Not being smaller 2404 * avoids false-sharing, but not being 128 bytes potentially allows for 2405 * avoidable traffic due to adjacent cacheline prefetcher. 2406 * 2407 * Assert the size so that accidental changes fail to compile. 2408 */ 2409 CTASSERT((sizeof(*pvd) == 64)); 2410 2411 /* 2412 * Calculate the size of the array. 2413 */ 2414 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end; 2415 pv_npg = howmany(pmap_last_pa, NBPDR); 2416 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page); 2417 s = round_page(s); 2418 pv_table = (struct pmap_large_md_page *)kva_alloc(s); 2419 if (pv_table == NULL) 2420 panic("%s: kva_alloc failed\n", __func__); 2421 2422 /* 2423 * Iterate physical segments to allocate space for respective pages. 2424 */ 2425 highest = -1; 2426 s = 0; 2427 for (i = 0; i < vm_phys_nsegs; i++) { 2428 end = vm_phys_segs[i].end / NBPDR; 2429 domain = vm_phys_segs[i].domain; 2430 2431 if (highest >= end) 2432 continue; 2433 2434 start = highest + 1; 2435 pvd = &pv_table[start]; 2436 2437 pages = end - start + 1; 2438 s = round_page(pages * sizeof(*pvd)); 2439 highest = start + (s / sizeof(*pvd)) - 1; 2440 2441 for (j = 0; j < s; j += PAGE_SIZE) { 2442 vm_page_t m = vm_page_alloc_noobj_domain(domain, 0); 2443 if (m == NULL) 2444 panic("failed to allocate PV table page"); 2445 pmap_qenter((vm_offset_t)pvd + j, &m, 1); 2446 } 2447 2448 for (j = 0; j < s / sizeof(*pvd); j++) { 2449 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW); 2450 TAILQ_INIT(&pvd->pv_page.pv_list); 2451 pvd->pv_page.pv_gen = 0; 2452 pvd->pv_page.pat_mode = 0; 2453 pvd->pv_invl_gen = 0; 2454 pvd++; 2455 } 2456 } 2457 pvd = &pv_dummy_large; 2458 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW); 2459 TAILQ_INIT(&pvd->pv_page.pv_list); 2460 pvd->pv_page.pv_gen = 0; 2461 pvd->pv_page.pat_mode = 0; 2462 pvd->pv_invl_gen = 0; 2463 } 2464 #else 2465 static void 2466 pmap_init_pv_table(void) 2467 { 2468 vm_size_t s; 2469 long i, pv_npg; 2470 2471 /* 2472 * Initialize the pool of pv list locks. 2473 */ 2474 for (i = 0; i < NPV_LIST_LOCKS; i++) 2475 rw_init(&pv_list_locks[i], "pmap pv list"); 2476 2477 /* 2478 * Calculate the size of the pv head table for superpages. 2479 */ 2480 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR); 2481 2482 /* 2483 * Allocate memory for the pv head table for superpages. 2484 */ 2485 s = (vm_size_t)pv_npg * sizeof(struct md_page); 2486 s = round_page(s); 2487 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO); 2488 for (i = 0; i < pv_npg; i++) 2489 TAILQ_INIT(&pv_table[i].pv_list); 2490 TAILQ_INIT(&pv_dummy.pv_list); 2491 } 2492 #endif 2493 2494 /* 2495 * Initialize the pmap module. 2496 * 2497 * Called by vm_mem_init(), to initialize any structures that the pmap 2498 * system needs to map virtual memory. 2499 */ 2500 void 2501 pmap_init(void) 2502 { 2503 struct pmap_preinit_mapping *ppim; 2504 vm_page_t m, mpte; 2505 pml4_entry_t *pml4e; 2506 unsigned long lm_max; 2507 int error, i, ret, skz63; 2508 2509 /* L1TF, reserve page @0 unconditionally */ 2510 vm_page_blacklist_add(0, bootverbose); 2511 2512 /* Detect bare-metal Skylake Server and Skylake-X. */ 2513 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL && 2514 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) { 2515 /* 2516 * Skylake-X errata SKZ63. Processor May Hang When 2517 * Executing Code In an HLE Transaction Region between 2518 * 40000000H and 403FFFFFH. 2519 * 2520 * Mark the pages in the range as preallocated. It 2521 * seems to be impossible to distinguish between 2522 * Skylake Server and Skylake X. 2523 */ 2524 skz63 = 1; 2525 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63); 2526 if (skz63 != 0) { 2527 if (bootverbose) 2528 printf("SKZ63: skipping 4M RAM starting " 2529 "at physical 1G\n"); 2530 for (i = 0; i < atop(0x400000); i++) { 2531 ret = vm_page_blacklist_add(0x40000000 + 2532 ptoa(i), false); 2533 if (!ret && bootverbose) 2534 printf("page at %#x already used\n", 2535 0x40000000 + ptoa(i)); 2536 } 2537 } 2538 } 2539 2540 /* IFU */ 2541 pmap_allow_2m_x_ept_recalculate(); 2542 2543 /* 2544 * Initialize the vm page array entries for the kernel pmap's 2545 * page table pages. 2546 */ 2547 PMAP_LOCK(kernel_pmap); 2548 for (i = 0; i < nkpt; i++) { 2549 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 2550 KASSERT(mpte >= vm_page_array && 2551 mpte < &vm_page_array[vm_page_array_size], 2552 ("pmap_init: page table page is out of range")); 2553 mpte->pindex = pmap_pde_pindex(KERNBASE) + i; 2554 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 2555 mpte->ref_count = 1; 2556 2557 /* 2558 * Collect the page table pages that were replaced by a 2MB 2559 * page in create_pagetables(). They are zero filled. 2560 */ 2561 if ((i == 0 || 2562 kernphys + ((vm_paddr_t)(i - 1) << PDRSHIFT) < KERNend) && 2563 pmap_insert_pt_page(kernel_pmap, mpte, false, false)) 2564 panic("pmap_init: pmap_insert_pt_page failed"); 2565 } 2566 PMAP_UNLOCK(kernel_pmap); 2567 vm_wire_add(nkpt); 2568 2569 /* 2570 * If the kernel is running on a virtual machine, then it must assume 2571 * that MCA is enabled by the hypervisor. Moreover, the kernel must 2572 * be prepared for the hypervisor changing the vendor and family that 2573 * are reported by CPUID. Consequently, the workaround for AMD Family 2574 * 10h Erratum 383 is enabled if the processor's feature set does not 2575 * include at least one feature that is only supported by older Intel 2576 * or newer AMD processors. 2577 */ 2578 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 && 2579 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 2580 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 2581 AMDID2_FMA4)) == 0) 2582 workaround_erratum383 = 1; 2583 2584 /* 2585 * Are large page mappings enabled? 2586 */ 2587 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 2588 if (pg_ps_enabled) { 2589 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 2590 ("pmap_init: can't assign to pagesizes[1]")); 2591 pagesizes[1] = NBPDR; 2592 if ((amd_feature & AMDID_PAGE1GB) != 0) { 2593 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0, 2594 ("pmap_init: can't assign to pagesizes[2]")); 2595 pagesizes[2] = NBPDP; 2596 } 2597 } 2598 2599 /* 2600 * Initialize pv chunk lists. 2601 */ 2602 for (i = 0; i < PMAP_MEMDOM; i++) { 2603 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF); 2604 TAILQ_INIT(&pv_chunks[i].pvc_list); 2605 } 2606 pmap_init_pv_table(); 2607 2608 pmap_initialized = 1; 2609 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 2610 ppim = pmap_preinit_mapping + i; 2611 if (ppim->va == 0) 2612 continue; 2613 /* Make the direct map consistent */ 2614 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) { 2615 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa), 2616 ppim->sz, ppim->mode); 2617 } 2618 if (!bootverbose) 2619 continue; 2620 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i, 2621 ppim->pa, ppim->va, ppim->sz, ppim->mode); 2622 } 2623 2624 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN); 2625 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK, 2626 (vmem_addr_t *)&qframe); 2627 if (error != 0) 2628 panic("qframe allocation failed"); 2629 2630 lm_ents = 8; 2631 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents); 2632 lm_max = (kva_layout.lm_high - kva_layout.lm_low) / NBPML4; 2633 if (lm_ents > lm_max) { 2634 printf( 2635 "pmap: shrinking large map from requested %d slots to %ld slots\n", 2636 lm_ents, lm_max); 2637 lm_ents = lm_max; 2638 } 2639 #ifdef KMSAN 2640 if (!la57 && lm_ents > KMSANORIGPML4I - LMSPML4I) { 2641 printf( 2642 "pmap: shrinking large map for KMSAN (%d slots to %ld slots)\n", 2643 lm_ents, KMSANORIGPML4I - LMSPML4I); 2644 lm_ents = KMSANORIGPML4I - LMSPML4I; 2645 } 2646 #endif 2647 if (bootverbose) 2648 printf("pmap: large map %u PML4 slots (%lu GB)\n", 2649 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024)); 2650 if (lm_ents != 0) { 2651 large_vmem = vmem_create("large", kva_layout.lm_low, 2652 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK); 2653 if (large_vmem == NULL) { 2654 printf("pmap: cannot create large map\n"); 2655 lm_ents = 0; 2656 } 2657 if (la57) { 2658 for (i = 0; i < howmany((vm_offset_t)NBPML4 * 2659 lm_ents, NBPML5); i++) { 2660 m = pmap_large_map_getptp_unlocked(); 2661 kernel_pmap->pm_pmltop[LMSPML5I + i] = X86_PG_V | 2662 X86_PG_RW | X86_PG_A | X86_PG_M | 2663 pg_nx | VM_PAGE_TO_PHYS(m); 2664 } 2665 } 2666 for (i = 0; i < lm_ents; i++) { 2667 m = pmap_large_map_getptp_unlocked(); 2668 pml4e = pmap_pml4e(kernel_pmap, kva_layout.lm_low + 2669 (u_long)i * NBPML4); 2670 *pml4e = X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | 2671 pg_nx | VM_PAGE_TO_PHYS(m); 2672 } 2673 } 2674 } 2675 2676 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries, 2677 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0, 2678 "Maximum number of PML4 entries for use by large map (tunable). " 2679 "Each entry corresponds to 512GB of address space."); 2680 2681 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 2682 "2MB page mapping counters"); 2683 2684 static COUNTER_U64_DEFINE_EARLY(pmap_pde_demotions); 2685 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, demotions, 2686 CTLFLAG_RD, &pmap_pde_demotions, "2MB page demotions"); 2687 2688 static COUNTER_U64_DEFINE_EARLY(pmap_pde_mappings); 2689 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 2690 &pmap_pde_mappings, "2MB page mappings"); 2691 2692 static COUNTER_U64_DEFINE_EARLY(pmap_pde_p_failures); 2693 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 2694 &pmap_pde_p_failures, "2MB page promotion failures"); 2695 2696 static COUNTER_U64_DEFINE_EARLY(pmap_pde_promotions); 2697 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 2698 &pmap_pde_promotions, "2MB page promotions"); 2699 2700 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 2701 "1GB page mapping counters"); 2702 2703 static COUNTER_U64_DEFINE_EARLY(pmap_pdpe_demotions); 2704 SYSCTL_COUNTER_U64(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD, 2705 &pmap_pdpe_demotions, "1GB page demotions"); 2706 2707 /*************************************************** 2708 * Low level helper routines..... 2709 ***************************************************/ 2710 2711 static pt_entry_t 2712 pmap_swap_pat(pmap_t pmap, pt_entry_t entry) 2713 { 2714 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT; 2715 2716 switch (pmap->pm_type) { 2717 case PT_X86: 2718 case PT_RVI: 2719 /* Verify that both PAT bits are not set at the same time */ 2720 KASSERT((entry & x86_pat_bits) != x86_pat_bits, 2721 ("Invalid PAT bits in entry %#lx", entry)); 2722 2723 /* Swap the PAT bits if one of them is set */ 2724 if ((entry & x86_pat_bits) != 0) 2725 entry ^= x86_pat_bits; 2726 break; 2727 case PT_EPT: 2728 /* 2729 * Nothing to do - the memory attributes are represented 2730 * the same way for regular pages and superpages. 2731 */ 2732 break; 2733 default: 2734 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type); 2735 } 2736 2737 return (entry); 2738 } 2739 2740 bool 2741 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode) 2742 { 2743 2744 return (mode >= 0 && mode < PAT_INDEX_SIZE && 2745 pat_index[(int)mode] >= 0); 2746 } 2747 2748 /* 2749 * Determine the appropriate bits to set in a PTE or PDE for a specified 2750 * caching mode. 2751 */ 2752 int 2753 pmap_cache_bits(pmap_t pmap, int mode, bool is_pde) 2754 { 2755 int cache_bits, pat_flag, pat_idx; 2756 2757 if (!pmap_is_valid_memattr(pmap, mode)) 2758 panic("Unknown caching mode %d\n", mode); 2759 2760 switch (pmap->pm_type) { 2761 case PT_X86: 2762 case PT_RVI: 2763 /* The PAT bit is different for PTE's and PDE's. */ 2764 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT; 2765 2766 /* Map the caching mode to a PAT index. */ 2767 pat_idx = pat_index[mode]; 2768 2769 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 2770 cache_bits = 0; 2771 if (pat_idx & 0x4) 2772 cache_bits |= pat_flag; 2773 if (pat_idx & 0x2) 2774 cache_bits |= PG_NC_PCD; 2775 if (pat_idx & 0x1) 2776 cache_bits |= PG_NC_PWT; 2777 break; 2778 2779 case PT_EPT: 2780 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode); 2781 break; 2782 2783 default: 2784 panic("unsupported pmap type %d", pmap->pm_type); 2785 } 2786 2787 return (cache_bits); 2788 } 2789 2790 static int 2791 pmap_cache_mask(pmap_t pmap, bool is_pde) 2792 { 2793 int mask; 2794 2795 switch (pmap->pm_type) { 2796 case PT_X86: 2797 case PT_RVI: 2798 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE; 2799 break; 2800 case PT_EPT: 2801 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7); 2802 break; 2803 default: 2804 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type); 2805 } 2806 2807 return (mask); 2808 } 2809 2810 static int 2811 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde) 2812 { 2813 int pat_flag, pat_idx; 2814 2815 pat_idx = 0; 2816 switch (pmap->pm_type) { 2817 case PT_X86: 2818 case PT_RVI: 2819 /* The PAT bit is different for PTE's and PDE's. */ 2820 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT; 2821 2822 if ((pte & pat_flag) != 0) 2823 pat_idx |= 0x4; 2824 if ((pte & PG_NC_PCD) != 0) 2825 pat_idx |= 0x2; 2826 if ((pte & PG_NC_PWT) != 0) 2827 pat_idx |= 0x1; 2828 break; 2829 case PT_EPT: 2830 if ((pte & EPT_PG_IGNORE_PAT) != 0) 2831 panic("EPT PTE %#lx has no PAT memory type", pte); 2832 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3; 2833 break; 2834 } 2835 2836 /* See pmap_init_pat(). */ 2837 if (pat_idx == 4) 2838 pat_idx = 0; 2839 if (pat_idx == 7) 2840 pat_idx = 3; 2841 2842 return (pat_idx); 2843 } 2844 2845 bool 2846 pmap_ps_enabled(pmap_t pmap) 2847 { 2848 2849 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0); 2850 } 2851 2852 static void 2853 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde) 2854 { 2855 2856 switch (pmap->pm_type) { 2857 case PT_X86: 2858 break; 2859 case PT_RVI: 2860 case PT_EPT: 2861 /* 2862 * XXX 2863 * This is a little bogus since the generation number is 2864 * supposed to be bumped up when a region of the address 2865 * space is invalidated in the page tables. 2866 * 2867 * In this case the old PDE entry is valid but yet we want 2868 * to make sure that any mappings using the old entry are 2869 * invalidated in the TLB. 2870 * 2871 * The reason this works as expected is because we rendezvous 2872 * "all" host cpus and force any vcpu context to exit as a 2873 * side-effect. 2874 */ 2875 atomic_add_long(&pmap->pm_eptgen, 1); 2876 break; 2877 default: 2878 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type); 2879 } 2880 pde_store(pde, newpde); 2881 } 2882 2883 /* 2884 * After changing the page size for the specified virtual address in the page 2885 * table, flush the corresponding entries from the processor's TLB. Only the 2886 * calling processor's TLB is affected. 2887 * 2888 * The calling thread must be pinned to a processor. 2889 */ 2890 static void 2891 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde) 2892 { 2893 pt_entry_t PG_G; 2894 2895 if (pmap_type_guest(pmap)) 2896 return; 2897 2898 KASSERT(pmap->pm_type == PT_X86, 2899 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type)); 2900 2901 PG_G = pmap_global_bit(pmap); 2902 2903 if ((newpde & PG_PS) == 0) 2904 /* Demotion: flush a specific 2MB page mapping. */ 2905 pmap_invlpg(pmap, va); 2906 else if ((newpde & PG_G) == 0) 2907 /* 2908 * Promotion: flush every 4KB page mapping from the TLB 2909 * because there are too many to flush individually. 2910 */ 2911 invltlb(); 2912 else { 2913 /* 2914 * Promotion: flush every 4KB page mapping from the TLB, 2915 * including any global (PG_G) mappings. 2916 * 2917 * This function is only used on older processors that 2918 * do not support the invpcid instruction. 2919 */ 2920 invltlb_glob(); 2921 } 2922 } 2923 2924 /* 2925 * The amd64 pmap uses different approaches to TLB invalidation 2926 * depending on the kernel configuration, available hardware features, 2927 * and known hardware errata. The kernel configuration option that 2928 * has the greatest operational impact on TLB invalidation is PTI, 2929 * which is enabled automatically on affected Intel CPUs. The most 2930 * impactful hardware features are first PCID, and then INVPCID 2931 * instruction presence. PCID usage is quite different for PTI 2932 * vs. non-PTI. 2933 * 2934 * * Kernel Page Table Isolation (PTI or KPTI) is used to mitigate 2935 * the Meltdown bug in some Intel CPUs. Under PTI, each user address 2936 * space is served by two page tables, user and kernel. The user 2937 * page table only maps user space and a kernel trampoline. The 2938 * kernel trampoline includes the entirety of the kernel text but 2939 * only the kernel data that is needed to switch from user to kernel 2940 * mode. The kernel page table maps the user and kernel address 2941 * spaces in their entirety. It is identical to the per-process 2942 * page table used in non-PTI mode. 2943 * 2944 * User page tables are only used when the CPU is in user mode. 2945 * Consequently, some TLB invalidations can be postponed until the 2946 * switch from kernel to user mode. In contrast, the user 2947 * space part of the kernel page table is used for copyout(9), so 2948 * TLB invalidations on this page table cannot be similarly postponed. 2949 * 2950 * The existence of a user mode page table for the given pmap is 2951 * indicated by a pm_ucr3 value that differs from PMAP_NO_CR3, in 2952 * which case pm_ucr3 contains the %cr3 register value for the user 2953 * mode page table's root. 2954 * 2955 * * The pm_active bitmask indicates which CPUs currently have the 2956 * pmap active. A CPU's bit is set on context switch to the pmap, and 2957 * cleared on switching off this CPU. For the kernel page table, 2958 * the pm_active field is immutable and contains all CPUs. The 2959 * kernel page table is always logically active on every processor, 2960 * but not necessarily in use by the hardware, e.g., in PTI mode. 2961 * 2962 * When requesting invalidation of virtual addresses with 2963 * pmap_invalidate_XXX() functions, the pmap sends shootdown IPIs to 2964 * all CPUs recorded as active in pm_active. Updates to and reads 2965 * from pm_active are not synchronized, and so they may race with 2966 * each other. Shootdown handlers are prepared to handle the race. 2967 * 2968 * * PCID is an optional feature of the long mode x86 MMU where TLB 2969 * entries are tagged with the 'Process ID' of the address space 2970 * they belong to. This feature provides a limited namespace for 2971 * process identifiers, 12 bits, supporting 4095 simultaneous IDs 2972 * total. 2973 * 2974 * Allocation of a PCID to a pmap is done by an algorithm described 2975 * in section 15.12, "Other TLB Consistency Algorithms", of 2976 * Vahalia's book "Unix Internals". A PCID cannot be allocated for 2977 * the whole lifetime of a pmap in pmap_pinit() due to the limited 2978 * namespace. Instead, a per-CPU, per-pmap PCID is assigned when 2979 * the CPU is about to start caching TLB entries from a pmap, 2980 * i.e., on the context switch that activates the pmap on the CPU. 2981 * 2982 * The PCID allocator maintains a per-CPU, per-pmap generation 2983 * count, pm_gen, which is incremented each time a new PCID is 2984 * allocated. On TLB invalidation, the generation counters for the 2985 * pmap are zeroed, which signals the context switch code that the 2986 * previously allocated PCID is no longer valid. Effectively, 2987 * zeroing any of these counters triggers a TLB shootdown for the 2988 * given CPU/address space, due to the allocation of a new PCID. 2989 * 2990 * Zeroing can be performed remotely. Consequently, if a pmap is 2991 * inactive on a CPU, then a TLB shootdown for that pmap and CPU can 2992 * be initiated by an ordinary memory access to reset the target 2993 * CPU's generation count within the pmap. The CPU initiating the 2994 * TLB shootdown does not need to send an IPI to the target CPU. 2995 * 2996 * * PTI + PCID. The available PCIDs are divided into two sets: PCIDs 2997 * for complete (kernel) page tables, and PCIDs for user mode page 2998 * tables. A user PCID value is obtained from the kernel PCID value 2999 * by setting the highest bit, 11, to 1 (0x800 == PMAP_PCID_USER_PT). 3000 * 3001 * User space page tables are activated on return to user mode, by 3002 * loading pm_ucr3 into %cr3. If the PCPU(ucr3_load_mask) requests 3003 * clearing bit 63 of the loaded ucr3, this effectively causes 3004 * complete invalidation of the user mode TLB entries for the 3005 * current pmap. In which case, local invalidations of individual 3006 * pages in the user page table are skipped. 3007 * 3008 * * Local invalidation, all modes. If the requested invalidation is 3009 * for a specific address or the total invalidation of a currently 3010 * active pmap, then the TLB is flushed using INVLPG for a kernel 3011 * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a 3012 * user space page table(s). 3013 * 3014 * If the INVPCID instruction is available, it is used to flush user 3015 * entries from the kernel page table. 3016 * 3017 * When PCID is enabled, the INVLPG instruction invalidates all TLB 3018 * entries for the given page that either match the current PCID or 3019 * are global. Since TLB entries for the same page under different 3020 * PCIDs are unaffected, kernel pages which reside in all address 3021 * spaces could be problematic. We avoid the problem by creating 3022 * all kernel PTEs with the global flag (PG_G) set, when PTI is 3023 * disabled. 3024 * 3025 * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its 3026 * address space, all other 4095 PCIDs are used for user mode spaces 3027 * as described above. A context switch allocates a new PCID if 3028 * the recorded PCID is zero or the recorded generation does not match 3029 * the CPU's generation, effectively flushing the TLB for this address space. 3030 * Total remote invalidation is performed by zeroing pm_gen for all CPUs. 3031 * local user page: INVLPG 3032 * local kernel page: INVLPG 3033 * local user total: INVPCID(CTX) 3034 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob() 3035 * remote user page, inactive pmap: zero pm_gen 3036 * remote user page, active pmap: zero pm_gen + IPI:INVLPG 3037 * (Both actions are required to handle the aforementioned pm_active races.) 3038 * remote kernel page: IPI:INVLPG 3039 * remote user total, inactive pmap: zero pm_gen 3040 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) or 3041 * reload %cr3) 3042 * (See note above about pm_active races.) 3043 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob()) 3044 * 3045 * PTI enabled, PCID present. 3046 * local user page: INVLPG for kpt, INVPCID(ADDR) or (INVLPG for ucr3) 3047 * for upt 3048 * local kernel page: INVLPG 3049 * local user total: INVPCID(CTX) or reload %cr3 for kpt, clear PCID_SAVE 3050 * on loading UCR3 into %cr3 for upt 3051 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob() 3052 * remote user page, inactive pmap: zero pm_gen 3053 * remote user page, active pmap: zero pm_gen + IPI:(INVLPG for kpt, 3054 * INVPCID(ADDR) for upt) 3055 * remote kernel page: IPI:INVLPG 3056 * remote user total, inactive pmap: zero pm_gen 3057 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) for kpt, 3058 * clear PCID_SAVE on loading UCR3 into $cr3 for upt) 3059 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob()) 3060 * 3061 * No PCID. 3062 * local user page: INVLPG 3063 * local kernel page: INVLPG 3064 * local user total: reload %cr3 3065 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob() 3066 * remote user page, inactive pmap: - 3067 * remote user page, active pmap: IPI:INVLPG 3068 * remote kernel page: IPI:INVLPG 3069 * remote user total, inactive pmap: - 3070 * remote user total, active pmap: IPI:(reload %cr3) 3071 * remote kernel total: IPI:INVPCID(CTXGLOB) or invltlb_glob() 3072 * Since on return to user mode, the reload of %cr3 with ucr3 causes 3073 * TLB invalidation, no specific action is required for user page table. 3074 * 3075 * EPT. EPT pmaps do not map KVA, all mappings are userspace. 3076 * XXX TODO 3077 */ 3078 3079 /* 3080 * Interrupt the cpus that are executing in the guest context. 3081 * This will force the vcpu to exit and the cached EPT mappings 3082 * will be invalidated by the host before the next vmresume. 3083 */ 3084 static __inline void 3085 pmap_invalidate_ept(pmap_t pmap) 3086 { 3087 smr_seq_t goal; 3088 int ipinum; 3089 3090 sched_pin(); 3091 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active), 3092 ("pmap_invalidate_ept: absurd pm_active")); 3093 3094 /* 3095 * The TLB mappings associated with a vcpu context are not 3096 * flushed each time a different vcpu is chosen to execute. 3097 * 3098 * This is in contrast with a process's vtop mappings that 3099 * are flushed from the TLB on each context switch. 3100 * 3101 * Therefore we need to do more than just a TLB shootdown on 3102 * the active cpus in 'pmap->pm_active'. To do this we keep 3103 * track of the number of invalidations performed on this pmap. 3104 * 3105 * Each vcpu keeps a cache of this counter and compares it 3106 * just before a vmresume. If the counter is out-of-date an 3107 * invept will be done to flush stale mappings from the TLB. 3108 * 3109 * To ensure that all vCPU threads have observed the new counter 3110 * value before returning, we use SMR. Ordering is important here: 3111 * the VMM enters an SMR read section before loading the counter 3112 * and after updating the pm_active bit set. Thus, pm_active is 3113 * a superset of active readers, and any reader that has observed 3114 * the goal has observed the new counter value. 3115 */ 3116 atomic_add_long(&pmap->pm_eptgen, 1); 3117 3118 goal = smr_advance(pmap->pm_eptsmr); 3119 3120 /* 3121 * Force the vcpu to exit and trap back into the hypervisor. 3122 */ 3123 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK; 3124 ipi_selected(pmap->pm_active, ipinum); 3125 sched_unpin(); 3126 3127 /* 3128 * Ensure that all active vCPUs will observe the new generation counter 3129 * value before executing any more guest instructions. 3130 */ 3131 smr_wait(pmap->pm_eptsmr, goal); 3132 } 3133 3134 static inline void 3135 pmap_invalidate_preipi_pcid(pmap_t pmap) 3136 { 3137 struct pmap_pcid *pcidp; 3138 u_int cpuid, i; 3139 3140 sched_pin(); 3141 3142 cpuid = PCPU_GET(cpuid); 3143 if (pmap != PCPU_GET(curpmap)) 3144 cpuid = 0xffffffff; /* An impossible value */ 3145 3146 CPU_FOREACH(i) { 3147 if (cpuid != i) { 3148 pcidp = zpcpu_get_cpu(pmap->pm_pcidp, i); 3149 pcidp->pm_gen = 0; 3150 } 3151 } 3152 3153 /* 3154 * The fence is between stores to pm_gen and the read of the 3155 * pm_active mask. We need to ensure that it is impossible 3156 * for us to miss the bit update in pm_active and 3157 * simultaneously observe a non-zero pm_gen in 3158 * pmap_activate_sw(), otherwise TLB update is missed. 3159 * Without the fence, IA32 allows such an outcome. Note that 3160 * pm_active is updated by a locked operation, which provides 3161 * the reciprocal fence. 3162 */ 3163 atomic_thread_fence_seq_cst(); 3164 } 3165 3166 static void 3167 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused) 3168 { 3169 sched_pin(); 3170 } 3171 3172 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t)) 3173 { 3174 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid : 3175 pmap_invalidate_preipi_nopcid); 3176 } 3177 3178 static inline void 3179 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va, 3180 const bool invpcid_works1) 3181 { 3182 struct invpcid_descr d; 3183 uint64_t kcr3, ucr3; 3184 uint32_t pcid; 3185 3186 /* 3187 * Because pm_pcid is recalculated on a context switch, we 3188 * must ensure there is no preemption, not just pinning. 3189 * Otherwise, we might use a stale value below. 3190 */ 3191 CRITICAL_ASSERT(curthread); 3192 3193 /* 3194 * No need to do anything with user page tables invalidation 3195 * if there is no user page table, or invalidation is deferred 3196 * until the return to userspace. ucr3_load_mask is stable 3197 * because we have preemption disabled. 3198 */ 3199 if (pmap->pm_ucr3 == PMAP_NO_CR3 || 3200 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) 3201 return; 3202 3203 pcid = pmap_get_pcid(pmap); 3204 if (invpcid_works1) { 3205 d.pcid = pcid | PMAP_PCID_USER_PT; 3206 d.pad = 0; 3207 d.addr = va; 3208 invpcid(&d, INVPCID_ADDR); 3209 } else { 3210 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE; 3211 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE; 3212 pmap_pti_pcid_invlpg(ucr3, kcr3, va); 3213 } 3214 } 3215 3216 static void 3217 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va) 3218 { 3219 pmap_invalidate_page_pcid_cb(pmap, va, true); 3220 } 3221 3222 static void 3223 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va) 3224 { 3225 pmap_invalidate_page_pcid_cb(pmap, va, false); 3226 } 3227 3228 static void 3229 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused) 3230 { 3231 } 3232 3233 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t)) 3234 { 3235 if (pmap_pcid_enabled) 3236 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb : 3237 pmap_invalidate_page_pcid_noinvpcid_cb); 3238 return (pmap_invalidate_page_nopcid_cb); 3239 } 3240 3241 static void 3242 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va, 3243 vm_offset_t addr2 __unused) 3244 { 3245 if (pmap == kernel_pmap) { 3246 pmap_invlpg(kernel_pmap, va); 3247 } else if (pmap == PCPU_GET(curpmap)) { 3248 invlpg(va); 3249 pmap_invalidate_page_cb(pmap, va); 3250 } 3251 } 3252 3253 void 3254 pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 3255 { 3256 if (pmap_type_guest(pmap)) { 3257 pmap_invalidate_ept(pmap); 3258 return; 3259 } 3260 3261 KASSERT(pmap->pm_type == PT_X86, 3262 ("pmap_invalidate_page: invalid type %d", pmap->pm_type)); 3263 3264 pmap_invalidate_preipi(pmap); 3265 smp_masked_invlpg(va, pmap, pmap_invalidate_page_curcpu_cb); 3266 } 3267 3268 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */ 3269 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE) 3270 3271 static void 3272 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 3273 const bool invpcid_works1) 3274 { 3275 struct invpcid_descr d; 3276 uint64_t kcr3, ucr3; 3277 uint32_t pcid; 3278 3279 CRITICAL_ASSERT(curthread); 3280 3281 if (pmap != PCPU_GET(curpmap) || 3282 pmap->pm_ucr3 == PMAP_NO_CR3 || 3283 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) 3284 return; 3285 3286 pcid = pmap_get_pcid(pmap); 3287 if (invpcid_works1) { 3288 d.pcid = pcid | PMAP_PCID_USER_PT; 3289 d.pad = 0; 3290 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE) 3291 invpcid(&d, INVPCID_ADDR); 3292 } else { 3293 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE; 3294 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE; 3295 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva); 3296 } 3297 } 3298 3299 static void 3300 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva, 3301 vm_offset_t eva) 3302 { 3303 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true); 3304 } 3305 3306 static void 3307 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva, 3308 vm_offset_t eva) 3309 { 3310 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false); 3311 } 3312 3313 static void 3314 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused, 3315 vm_offset_t eva __unused) 3316 { 3317 } 3318 3319 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t, 3320 vm_offset_t)) 3321 { 3322 if (pmap_pcid_enabled) 3323 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb : 3324 pmap_invalidate_range_pcid_noinvpcid_cb); 3325 return (pmap_invalidate_range_nopcid_cb); 3326 } 3327 3328 static void 3329 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3330 { 3331 vm_offset_t addr; 3332 3333 if (pmap == kernel_pmap) { 3334 if (PCPU_GET(pcid_invlpg_workaround)) { 3335 struct invpcid_descr d = { 0 }; 3336 3337 invpcid(&d, INVPCID_CTXGLOB); 3338 } else { 3339 for (addr = sva; addr < eva; addr += PAGE_SIZE) 3340 invlpg(addr); 3341 } 3342 } else if (pmap == PCPU_GET(curpmap)) { 3343 for (addr = sva; addr < eva; addr += PAGE_SIZE) 3344 invlpg(addr); 3345 pmap_invalidate_range_cb(pmap, sva, eva); 3346 } 3347 } 3348 3349 void 3350 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3351 { 3352 if (eva - sva >= PMAP_INVLPG_THRESHOLD) { 3353 pmap_invalidate_all(pmap); 3354 return; 3355 } 3356 3357 if (pmap_type_guest(pmap)) { 3358 pmap_invalidate_ept(pmap); 3359 return; 3360 } 3361 3362 KASSERT(pmap->pm_type == PT_X86, 3363 ("pmap_invalidate_range: invalid type %d", pmap->pm_type)); 3364 3365 pmap_invalidate_preipi(pmap); 3366 smp_masked_invlpg_range(sva, eva, pmap, 3367 pmap_invalidate_range_curcpu_cb); 3368 } 3369 3370 static inline void 3371 pmap_invalidate_all_cb_template(pmap_t pmap, bool pmap_pcid_enabled1, 3372 bool invpcid_works1) 3373 { 3374 struct invpcid_descr d; 3375 uint64_t kcr3; 3376 uint32_t pcid; 3377 3378 if (pmap == kernel_pmap) { 3379 if (invpcid_works1) { 3380 bzero(&d, sizeof(d)); 3381 invpcid(&d, INVPCID_CTXGLOB); 3382 } else { 3383 invltlb_glob(); 3384 } 3385 } else if (pmap == PCPU_GET(curpmap)) { 3386 if (pmap_pcid_enabled1) { 3387 CRITICAL_ASSERT(curthread); 3388 3389 pcid = pmap_get_pcid(pmap); 3390 if (invpcid_works1) { 3391 d.pcid = pcid; 3392 d.pad = 0; 3393 d.addr = 0; 3394 invpcid(&d, INVPCID_CTX); 3395 } else { 3396 kcr3 = pmap->pm_cr3 | pcid; 3397 load_cr3(kcr3); 3398 } 3399 if (pmap->pm_ucr3 != PMAP_NO_CR3) 3400 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE); 3401 } else { 3402 invltlb(); 3403 } 3404 } 3405 } 3406 3407 static void 3408 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap, vm_offset_t addr1 __unused, 3409 vm_offset_t addr2 __unused) 3410 { 3411 pmap_invalidate_all_cb_template(pmap, true, true); 3412 } 3413 3414 static void 3415 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t addr1 __unused, 3416 vm_offset_t addr2 __unused) 3417 { 3418 pmap_invalidate_all_cb_template(pmap, true, false); 3419 } 3420 3421 static void 3422 pmap_invalidate_all_nopcid_invpcid_cb(pmap_t pmap, vm_offset_t addr1 __unused, 3423 vm_offset_t addr2 __unused) 3424 { 3425 pmap_invalidate_all_cb_template(pmap, false, true); 3426 } 3427 3428 static void 3429 pmap_invalidate_all_nopcid_noinvpcid_cb(pmap_t pmap, vm_offset_t addr1 __unused, 3430 vm_offset_t addr2 __unused) 3431 { 3432 pmap_invalidate_all_cb_template(pmap, false, false); 3433 } 3434 3435 DEFINE_IFUNC(static, void, pmap_invalidate_all_curcpu_cb, (pmap_t, vm_offset_t, 3436 vm_offset_t)) 3437 { 3438 if (pmap_pcid_enabled) 3439 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb : 3440 pmap_invalidate_all_pcid_noinvpcid_cb); 3441 return (invpcid_works ? pmap_invalidate_all_nopcid_invpcid_cb : 3442 pmap_invalidate_all_nopcid_noinvpcid_cb); 3443 } 3444 3445 void 3446 pmap_invalidate_all(pmap_t pmap) 3447 { 3448 if (pmap_type_guest(pmap)) { 3449 pmap_invalidate_ept(pmap); 3450 return; 3451 } 3452 3453 KASSERT(pmap->pm_type == PT_X86, 3454 ("pmap_invalidate_all: invalid type %d", pmap->pm_type)); 3455 3456 pmap_invalidate_preipi(pmap); 3457 smp_masked_invltlb(pmap, pmap_invalidate_all_curcpu_cb); 3458 } 3459 3460 static void 3461 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused, 3462 vm_offset_t addr2 __unused) 3463 { 3464 wbinvd(); 3465 } 3466 3467 void 3468 pmap_invalidate_cache(void) 3469 { 3470 sched_pin(); 3471 smp_cache_flush(pmap_invalidate_cache_curcpu_cb); 3472 } 3473 3474 struct pde_action { 3475 cpuset_t invalidate; /* processors that invalidate their TLB */ 3476 pmap_t pmap; 3477 vm_offset_t va; 3478 pd_entry_t *pde; 3479 pd_entry_t newpde; 3480 u_int store; /* processor that updates the PDE */ 3481 }; 3482 3483 static void 3484 pmap_update_pde_action(void *arg) 3485 { 3486 struct pde_action *act = arg; 3487 3488 if (act->store == PCPU_GET(cpuid)) 3489 pmap_update_pde_store(act->pmap, act->pde, act->newpde); 3490 } 3491 3492 static void 3493 pmap_update_pde_teardown(void *arg) 3494 { 3495 struct pde_action *act = arg; 3496 3497 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 3498 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde); 3499 } 3500 3501 /* 3502 * Change the page size for the specified virtual address in a way that 3503 * prevents any possibility of the TLB ever having two entries that map the 3504 * same virtual address using different page sizes. This is the recommended 3505 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 3506 * machine check exception for a TLB state that is improperly diagnosed as a 3507 * hardware error. 3508 */ 3509 static void 3510 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 3511 { 3512 struct pde_action act; 3513 cpuset_t active, other_cpus; 3514 u_int cpuid; 3515 3516 sched_pin(); 3517 cpuid = PCPU_GET(cpuid); 3518 other_cpus = all_cpus; 3519 CPU_CLR(cpuid, &other_cpus); 3520 if (pmap == kernel_pmap || pmap_type_guest(pmap)) 3521 active = all_cpus; 3522 else { 3523 active = pmap->pm_active; 3524 } 3525 if (CPU_OVERLAP(&active, &other_cpus)) { 3526 act.store = cpuid; 3527 act.invalidate = active; 3528 act.va = va; 3529 act.pmap = pmap; 3530 act.pde = pde; 3531 act.newpde = newpde; 3532 CPU_SET(cpuid, &active); 3533 smp_rendezvous_cpus(active, 3534 smp_no_rendezvous_barrier, pmap_update_pde_action, 3535 pmap_update_pde_teardown, &act); 3536 } else { 3537 pmap_update_pde_store(pmap, pde, newpde); 3538 if (CPU_ISSET(cpuid, &active)) 3539 pmap_update_pde_invalidate(pmap, va, newpde); 3540 } 3541 sched_unpin(); 3542 } 3543 3544 static void 3545 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 3546 { 3547 3548 /* 3549 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created 3550 * by a promotion that did not invalidate the 512 4KB page mappings 3551 * that might exist in the TLB. Consequently, at this point, the TLB 3552 * may hold both 4KB and 2MB page mappings for the address range [va, 3553 * va + NBPDR). Therefore, the entire range must be invalidated here. 3554 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any 3555 * 4KB page mappings for the address range [va, va + NBPDR), and so a 3556 * single INVLPG suffices to invalidate the 2MB page mapping from the 3557 * TLB. 3558 */ 3559 if ((pde & PG_PROMOTED) != 0) 3560 pmap_invalidate_range(pmap, va, va + NBPDR - 1); 3561 else 3562 pmap_invalidate_page(pmap, va); 3563 } 3564 3565 DEFINE_IFUNC(, void, pmap_invalidate_cache_range, 3566 (vm_offset_t sva, vm_offset_t eva)) 3567 { 3568 3569 if ((cpu_feature & CPUID_SS) != 0) 3570 return (pmap_invalidate_cache_range_selfsnoop); 3571 if ((cpu_feature & CPUID_CLFSH) != 0) 3572 return (pmap_force_invalidate_cache_range); 3573 return (pmap_invalidate_cache_range_all); 3574 } 3575 3576 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 3577 3578 static void 3579 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva) 3580 { 3581 3582 KASSERT((sva & PAGE_MASK) == 0, 3583 ("pmap_invalidate_cache_range: sva not page-aligned")); 3584 KASSERT((eva & PAGE_MASK) == 0, 3585 ("pmap_invalidate_cache_range: eva not page-aligned")); 3586 } 3587 3588 static void 3589 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva) 3590 { 3591 3592 pmap_invalidate_cache_range_check_align(sva, eva); 3593 } 3594 3595 void 3596 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 3597 { 3598 3599 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1); 3600 3601 /* 3602 * XXX: Some CPUs fault, hang, or trash the local APIC 3603 * registers if we use CLFLUSH on the local APIC range. The 3604 * local APIC is always uncached, so we don't need to flush 3605 * for that range anyway. 3606 */ 3607 if (pmap_kextract(sva) == lapic_paddr) 3608 return; 3609 3610 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) { 3611 /* 3612 * Do per-cache line flush. Use a locked 3613 * instruction to insure that previous stores are 3614 * included in the write-back. The processor 3615 * propagates flush to other processors in the cache 3616 * coherence domain. 3617 */ 3618 atomic_thread_fence_seq_cst(); 3619 for (; sva < eva; sva += cpu_clflush_line_size) 3620 clflushopt(sva); 3621 atomic_thread_fence_seq_cst(); 3622 } else { 3623 /* 3624 * Writes are ordered by CLFLUSH on Intel CPUs. 3625 */ 3626 if (cpu_vendor_id != CPU_VENDOR_INTEL) 3627 mfence(); 3628 for (; sva < eva; sva += cpu_clflush_line_size) 3629 clflush(sva); 3630 if (cpu_vendor_id != CPU_VENDOR_INTEL) 3631 mfence(); 3632 } 3633 } 3634 3635 static void 3636 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva) 3637 { 3638 3639 pmap_invalidate_cache_range_check_align(sva, eva); 3640 pmap_invalidate_cache(); 3641 } 3642 3643 /* 3644 * Remove the specified set of pages from the data and instruction caches. 3645 * 3646 * In contrast to pmap_invalidate_cache_range(), this function does not 3647 * rely on the CPU's self-snoop feature, because it is intended for use 3648 * when moving pages into a different cache domain. 3649 */ 3650 void 3651 pmap_invalidate_cache_pages(vm_page_t *pages, int count) 3652 { 3653 vm_offset_t daddr, eva; 3654 int i; 3655 bool useclflushopt; 3656 3657 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0; 3658 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 3659 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt)) 3660 pmap_invalidate_cache(); 3661 else { 3662 if (useclflushopt) 3663 atomic_thread_fence_seq_cst(); 3664 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 3665 mfence(); 3666 for (i = 0; i < count; i++) { 3667 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i])); 3668 eva = daddr + PAGE_SIZE; 3669 for (; daddr < eva; daddr += cpu_clflush_line_size) { 3670 if (useclflushopt) 3671 clflushopt(daddr); 3672 else 3673 clflush(daddr); 3674 } 3675 } 3676 if (useclflushopt) 3677 atomic_thread_fence_seq_cst(); 3678 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 3679 mfence(); 3680 } 3681 } 3682 3683 void 3684 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva) 3685 { 3686 3687 pmap_invalidate_cache_range_check_align(sva, eva); 3688 3689 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) { 3690 pmap_force_invalidate_cache_range(sva, eva); 3691 return; 3692 } 3693 3694 /* See comment in pmap_force_invalidate_cache_range(). */ 3695 if (pmap_kextract(sva) == lapic_paddr) 3696 return; 3697 3698 atomic_thread_fence_seq_cst(); 3699 for (; sva < eva; sva += cpu_clflush_line_size) 3700 clwb(sva); 3701 atomic_thread_fence_seq_cst(); 3702 } 3703 3704 void 3705 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr) 3706 { 3707 pt_entry_t *pte; 3708 vm_offset_t vaddr; 3709 int error __diagused; 3710 int pte_bits; 3711 3712 KASSERT((spa & PAGE_MASK) == 0, 3713 ("pmap_flush_cache_phys_range: spa not page-aligned")); 3714 KASSERT((epa & PAGE_MASK) == 0, 3715 ("pmap_flush_cache_phys_range: epa not page-aligned")); 3716 3717 if (spa < dmaplimit) { 3718 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN( 3719 dmaplimit, epa))); 3720 if (dmaplimit >= epa) 3721 return; 3722 spa = dmaplimit; 3723 } 3724 3725 pte_bits = pmap_cache_bits(kernel_pmap, mattr, false) | X86_PG_RW | 3726 X86_PG_V; 3727 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK, 3728 &vaddr); 3729 KASSERT(error == 0, ("vmem_alloc failed: %d", error)); 3730 pte = vtopte(vaddr); 3731 for (; spa < epa; spa += PAGE_SIZE) { 3732 sched_pin(); 3733 pte_store(pte, spa | pte_bits); 3734 pmap_invlpg(kernel_pmap, vaddr); 3735 /* XXXKIB atomic inside flush_cache_range are excessive */ 3736 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE); 3737 sched_unpin(); 3738 } 3739 vmem_free(kernel_arena, vaddr, PAGE_SIZE); 3740 } 3741 3742 /* 3743 * Routine: pmap_extract 3744 * Function: 3745 * Extract the physical page address associated 3746 * with the given map/virtual_address pair. 3747 */ 3748 vm_paddr_t 3749 pmap_extract(pmap_t pmap, vm_offset_t va) 3750 { 3751 pdp_entry_t *pdpe; 3752 pd_entry_t *pde; 3753 pt_entry_t *pte, PG_V; 3754 vm_paddr_t pa; 3755 3756 pa = 0; 3757 PG_V = pmap_valid_bit(pmap); 3758 PMAP_LOCK(pmap); 3759 pdpe = pmap_pdpe(pmap, va); 3760 if (pdpe != NULL && (*pdpe & PG_V) != 0) { 3761 if ((*pdpe & PG_PS) != 0) 3762 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK); 3763 else { 3764 pde = pmap_pdpe_to_pde(pdpe, va); 3765 if ((*pde & PG_V) != 0) { 3766 if ((*pde & PG_PS) != 0) { 3767 pa = (*pde & PG_PS_FRAME) | 3768 (va & PDRMASK); 3769 } else { 3770 pte = pmap_pde_to_pte(pde, va); 3771 pa = (*pte & PG_FRAME) | 3772 (va & PAGE_MASK); 3773 } 3774 } 3775 } 3776 } 3777 PMAP_UNLOCK(pmap); 3778 return (pa); 3779 } 3780 3781 /* 3782 * Routine: pmap_extract_and_hold 3783 * Function: 3784 * Atomically extract and hold the physical page 3785 * with the given pmap and virtual address pair 3786 * if that mapping permits the given protection. 3787 */ 3788 vm_page_t 3789 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3790 { 3791 pdp_entry_t pdpe, *pdpep; 3792 pd_entry_t pde, *pdep; 3793 pt_entry_t pte, PG_RW, PG_V; 3794 vm_page_t m; 3795 3796 m = NULL; 3797 PG_RW = pmap_rw_bit(pmap); 3798 PG_V = pmap_valid_bit(pmap); 3799 PMAP_LOCK(pmap); 3800 3801 pdpep = pmap_pdpe(pmap, va); 3802 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0) 3803 goto out; 3804 if ((pdpe & PG_PS) != 0) { 3805 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0) 3806 goto out; 3807 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK)); 3808 goto check_page; 3809 } 3810 3811 pdep = pmap_pdpe_to_pde(pdpep, va); 3812 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0) 3813 goto out; 3814 if ((pde & PG_PS) != 0) { 3815 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0) 3816 goto out; 3817 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK)); 3818 goto check_page; 3819 } 3820 3821 pte = *pmap_pde_to_pte(pdep, va); 3822 if ((pte & PG_V) == 0 || 3823 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)) 3824 goto out; 3825 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 3826 3827 check_page: 3828 if (m != NULL && !vm_page_wire_mapped(m)) 3829 m = NULL; 3830 out: 3831 PMAP_UNLOCK(pmap); 3832 return (m); 3833 } 3834 3835 /* 3836 * Routine: pmap_kextract 3837 * Function: 3838 * Extract the physical page address associated with the given kernel 3839 * virtual address. 3840 */ 3841 vm_paddr_t 3842 pmap_kextract(vm_offset_t va) 3843 { 3844 pd_entry_t pde; 3845 vm_paddr_t pa; 3846 3847 if (va >= kva_layout.dmap_low && va < kva_layout.dmap_high) { 3848 pa = DMAP_TO_PHYS(va); 3849 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) { 3850 pa = pmap_large_map_kextract(va); 3851 } else { 3852 pde = *vtopde(va); 3853 if (pde & PG_PS) { 3854 pa = (pde & PG_PS_FRAME) | (va & PDRMASK); 3855 } else { 3856 /* 3857 * Beware of a concurrent promotion that changes the 3858 * PDE at this point! For example, vtopte() must not 3859 * be used to access the PTE because it would use the 3860 * new PDE. It is, however, safe to use the old PDE 3861 * because the page table page is preserved by the 3862 * promotion. 3863 */ 3864 pa = *pmap_pde_to_pte(&pde, va); 3865 pa = (pa & PG_FRAME) | (va & PAGE_MASK); 3866 } 3867 } 3868 return (pa); 3869 } 3870 3871 /*************************************************** 3872 * Low level mapping routines..... 3873 ***************************************************/ 3874 3875 /* 3876 * Add a wired page to the kva. 3877 * Note: not SMP coherent. 3878 */ 3879 void 3880 pmap_kenter(vm_offset_t va, vm_paddr_t pa) 3881 { 3882 pt_entry_t *pte; 3883 3884 pte = vtopte(va); 3885 pte_store(pte, pa | pg_g | pg_nx | X86_PG_A | X86_PG_M | 3886 X86_PG_RW | X86_PG_V); 3887 } 3888 3889 static __inline void 3890 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 3891 { 3892 pt_entry_t *pte; 3893 int cache_bits; 3894 3895 pte = vtopte(va); 3896 cache_bits = pmap_cache_bits(kernel_pmap, mode, false); 3897 pte_store(pte, pa | pg_g | pg_nx | X86_PG_A | X86_PG_M | 3898 X86_PG_RW | X86_PG_V | cache_bits); 3899 } 3900 3901 /* 3902 * Remove a page from the kernel pagetables. 3903 * Note: not SMP coherent. 3904 */ 3905 void 3906 pmap_kremove(vm_offset_t va) 3907 { 3908 pt_entry_t *pte; 3909 3910 pte = vtopte(va); 3911 pte_clear(pte); 3912 } 3913 3914 /* 3915 * Used to map a range of physical addresses into kernel 3916 * virtual address space. 3917 * 3918 * The value passed in '*virt' is a suggested virtual address for 3919 * the mapping. Architectures which can support a direct-mapped 3920 * physical to virtual region can return the appropriate address 3921 * within that region, leaving '*virt' unchanged. Other 3922 * architectures should map the pages starting at '*virt' and 3923 * update '*virt' with the first usable address after the mapped 3924 * region. 3925 */ 3926 vm_offset_t 3927 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 3928 { 3929 return PHYS_TO_DMAP(start); 3930 } 3931 3932 /* 3933 * Add a list of wired pages to the kva 3934 * this routine is only used for temporary 3935 * kernel mappings that do not need to have 3936 * page modification or references recorded. 3937 * Note that old mappings are simply written 3938 * over. The page *must* be wired. 3939 * Note: SMP coherent. Uses a ranged shootdown IPI. 3940 */ 3941 void 3942 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 3943 { 3944 pt_entry_t *endpte, oldpte, pa, *pte; 3945 vm_page_t m; 3946 int cache_bits; 3947 3948 oldpte = 0; 3949 pte = vtopte(sva); 3950 endpte = pte + count; 3951 while (pte < endpte) { 3952 m = *ma++; 3953 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, false); 3954 pa = VM_PAGE_TO_PHYS(m) | cache_bits; 3955 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) { 3956 oldpte |= *pte; 3957 pte_store(pte, pa | pg_g | pg_nx | X86_PG_A | 3958 X86_PG_M | X86_PG_RW | X86_PG_V); 3959 } 3960 pte++; 3961 } 3962 if (__predict_false((oldpte & X86_PG_V) != 0)) 3963 pmap_invalidate_range(kernel_pmap, sva, sva + count * 3964 PAGE_SIZE); 3965 } 3966 3967 /* 3968 * This routine tears out page mappings from the 3969 * kernel -- it is meant only for temporary mappings. 3970 * Note: SMP coherent. Uses a ranged shootdown IPI. 3971 */ 3972 void 3973 pmap_qremove(vm_offset_t sva, int count) 3974 { 3975 vm_offset_t va; 3976 3977 va = sva; 3978 while (count-- > 0) { 3979 /* 3980 * pmap_enter() calls within the kernel virtual 3981 * address space happen on virtual addresses from 3982 * subarenas that import superpage-sized and -aligned 3983 * address ranges. So, the virtual address that we 3984 * allocate to use with pmap_qenter() can't be close 3985 * enough to one of those pmap_enter() calls for it to 3986 * be caught up in a promotion. 3987 */ 3988 KASSERT(va >= kva_layout.km_low, ("usermode va %lx", va)); 3989 KASSERT((*vtopde(va) & X86_PG_PS) == 0, 3990 ("pmap_qremove on promoted va %#lx", va)); 3991 3992 pmap_kremove(va); 3993 va += PAGE_SIZE; 3994 } 3995 pmap_invalidate_range(kernel_pmap, sva, va); 3996 } 3997 3998 /*************************************************** 3999 * Page table page management routines..... 4000 ***************************************************/ 4001 /* 4002 * Schedule the specified unused page table page to be freed. Specifically, 4003 * add the page to the specified list of pages that will be released to the 4004 * physical memory manager after the TLB has been updated. 4005 */ 4006 static __inline void 4007 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, bool set_PG_ZERO) 4008 { 4009 4010 if (set_PG_ZERO) 4011 m->flags |= PG_ZERO; 4012 else 4013 m->flags &= ~PG_ZERO; 4014 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 4015 } 4016 4017 /* 4018 * Inserts the specified page table page into the specified pmap's collection 4019 * of idle page table pages. Each of a pmap's page table pages is responsible 4020 * for mapping a distinct range of virtual addresses. The pmap's collection is 4021 * ordered by this virtual address range. 4022 * 4023 * If "promoted" is false, then the page table page "mpte" must be zero filled; 4024 * "mpte"'s valid field will be set to 0. 4025 * 4026 * If "promoted" is true and "allpte_PG_A_set" is false, then "mpte" must 4027 * contain valid mappings with identical attributes except for PG_A; "mpte"'s 4028 * valid field will be set to 1. 4029 * 4030 * If "promoted" and "allpte_PG_A_set" are both true, then "mpte" must contain 4031 * valid mappings with identical attributes including PG_A; "mpte"'s valid 4032 * field will be set to VM_PAGE_BITS_ALL. 4033 */ 4034 static __inline int 4035 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted, 4036 bool allpte_PG_A_set) 4037 { 4038 4039 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4040 KASSERT(promoted || !allpte_PG_A_set, 4041 ("a zero-filled PTP can't have PG_A set in every PTE")); 4042 mpte->valid = promoted ? (allpte_PG_A_set ? VM_PAGE_BITS_ALL : 1) : 0; 4043 return (vm_radix_insert(&pmap->pm_root, mpte)); 4044 } 4045 4046 /* 4047 * Removes the page table page mapping the specified virtual address from the 4048 * specified pmap's collection of idle page table pages, and returns it. 4049 * Otherwise, returns NULL if there is no page table page corresponding to the 4050 * specified virtual address. 4051 */ 4052 static __inline vm_page_t 4053 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 4054 { 4055 4056 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4057 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va))); 4058 } 4059 4060 /* 4061 * Decrements a page table page's reference count, which is used to record the 4062 * number of valid page table entries within the page. If the reference count 4063 * drops to zero, then the page table page is unmapped. Returns true if the 4064 * page table page was unmapped and false otherwise. 4065 */ 4066 static inline bool 4067 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 4068 { 4069 4070 --m->ref_count; 4071 if (m->ref_count == 0) { 4072 _pmap_unwire_ptp(pmap, va, m, free); 4073 return (true); 4074 } else 4075 return (false); 4076 } 4077 4078 static void 4079 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 4080 { 4081 pml5_entry_t *pml5; 4082 pml4_entry_t *pml4; 4083 pdp_entry_t *pdp; 4084 pd_entry_t *pd; 4085 vm_page_t pdpg, pdppg, pml4pg; 4086 4087 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4088 4089 /* 4090 * unmap the page table page 4091 */ 4092 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) { 4093 /* PML4 page */ 4094 MPASS(pmap_is_la57(pmap)); 4095 pml5 = pmap_pml5e(pmap, va); 4096 *pml5 = 0; 4097 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) { 4098 pml5 = pmap_pml5e_u(pmap, va); 4099 *pml5 = 0; 4100 } 4101 } else if (m->pindex >= NUPDE + NUPDPE) { 4102 /* PDP page */ 4103 pml4 = pmap_pml4e(pmap, va); 4104 *pml4 = 0; 4105 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL && 4106 va <= VM_MAXUSER_ADDRESS) { 4107 pml4 = pmap_pml4e_u(pmap, va); 4108 *pml4 = 0; 4109 } 4110 } else if (m->pindex >= NUPDE) { 4111 /* PD page */ 4112 pdp = pmap_pdpe(pmap, va); 4113 *pdp = 0; 4114 } else { 4115 /* PTE page */ 4116 pd = pmap_pde(pmap, va); 4117 *pd = 0; 4118 } 4119 if (m->pindex < NUPDE) { 4120 /* We just released a PT, unhold the matching PD */ 4121 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME); 4122 pmap_unwire_ptp(pmap, va, pdpg, free); 4123 } else if (m->pindex < NUPDE + NUPDPE) { 4124 /* We just released a PD, unhold the matching PDP */ 4125 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME); 4126 pmap_unwire_ptp(pmap, va, pdppg, free); 4127 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) { 4128 /* We just released a PDP, unhold the matching PML4 */ 4129 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME); 4130 pmap_unwire_ptp(pmap, va, pml4pg, free); 4131 } 4132 4133 pmap_pt_page_count_adj(pmap, -1); 4134 4135 /* 4136 * Put page on a list so that it is released after 4137 * *ALL* TLB shootdown is done 4138 */ 4139 pmap_add_delayed_free_list(m, free, true); 4140 } 4141 4142 /* 4143 * After removing a page table entry, this routine is used to 4144 * conditionally free the page, and manage the reference count. 4145 */ 4146 static int 4147 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, 4148 struct spglist *free) 4149 { 4150 vm_page_t mpte; 4151 4152 if (va >= VM_MAXUSER_ADDRESS) 4153 return (0); 4154 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0")); 4155 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 4156 return (pmap_unwire_ptp(pmap, va, mpte, free)); 4157 } 4158 4159 /* 4160 * Release a page table page reference after a failed attempt to create a 4161 * mapping. 4162 */ 4163 static void 4164 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 4165 { 4166 struct spglist free; 4167 4168 SLIST_INIT(&free); 4169 if (pmap_unwire_ptp(pmap, va, mpte, &free)) { 4170 /* 4171 * Although "va" was never mapped, paging-structure caches 4172 * could nonetheless have entries that refer to the freed 4173 * page table pages. Invalidate those entries. 4174 */ 4175 pmap_invalidate_page(pmap, va); 4176 vm_page_free_pages_toq(&free, true); 4177 } 4178 } 4179 4180 static void 4181 pmap_pinit_pcids(pmap_t pmap, uint32_t pcid, int gen) 4182 { 4183 struct pmap_pcid *pcidp; 4184 int i; 4185 4186 CPU_FOREACH(i) { 4187 pcidp = zpcpu_get_cpu(pmap->pm_pcidp, i); 4188 pcidp->pm_pcid = pcid; 4189 pcidp->pm_gen = gen; 4190 } 4191 } 4192 4193 void 4194 pmap_pinit0(pmap_t pmap) 4195 { 4196 struct proc *p; 4197 struct thread *td; 4198 4199 PMAP_LOCK_INIT(pmap); 4200 pmap->pm_pmltop = kernel_pmap->pm_pmltop; 4201 pmap->pm_pmltopu = NULL; 4202 pmap->pm_cr3 = kernel_pmap->pm_cr3; 4203 /* hack to keep pmap_pti_pcid_invalidate() alive */ 4204 pmap->pm_ucr3 = PMAP_NO_CR3; 4205 vm_radix_init(&pmap->pm_root); 4206 CPU_ZERO(&pmap->pm_active); 4207 TAILQ_INIT(&pmap->pm_pvchunk); 4208 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 4209 pmap->pm_flags = pmap_flags; 4210 pmap->pm_pcidp = uma_zalloc_pcpu(pcpu_zone_8, M_WAITOK); 4211 pmap_pinit_pcids(pmap, PMAP_PCID_KERN + 1, 1); 4212 pmap_activate_boot(pmap); 4213 td = curthread; 4214 if (pti) { 4215 p = td->td_proc; 4216 PROC_LOCK(p); 4217 p->p_md.md_flags |= P_MD_KPTI; 4218 PROC_UNLOCK(p); 4219 } 4220 pmap_thread_init_invl_gen(td); 4221 4222 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) { 4223 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges", 4224 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL, 4225 UMA_ALIGN_PTR, 0); 4226 } 4227 } 4228 4229 void 4230 pmap_pinit_pml4(vm_page_t pml4pg) 4231 { 4232 pml4_entry_t *pm_pml4; 4233 int i; 4234 4235 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg)); 4236 4237 /* Wire in kernel global address entries. */ 4238 for (i = 0; i < NKPML4E; i++) { 4239 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW | 4240 X86_PG_V; 4241 } 4242 #ifdef KASAN 4243 for (i = 0; i < NKASANPML4E; i++) { 4244 pm_pml4[KASANPML4I + i] = (KASANPDPphys + ptoa(i)) | X86_PG_RW | 4245 X86_PG_V | pg_nx; 4246 } 4247 #endif 4248 #ifdef KMSAN 4249 for (i = 0; i < NKMSANSHADPML4E; i++) { 4250 pm_pml4[KMSANSHADPML4I + i] = (KMSANSHADPDPphys + ptoa(i)) | 4251 X86_PG_RW | X86_PG_V | pg_nx; 4252 } 4253 for (i = 0; i < NKMSANORIGPML4E; i++) { 4254 pm_pml4[KMSANORIGPML4I + i] = (KMSANORIGPDPphys + ptoa(i)) | 4255 X86_PG_RW | X86_PG_V | pg_nx; 4256 } 4257 #endif 4258 for (i = 0; i < ndmpdpphys; i++) { 4259 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW | 4260 X86_PG_V; 4261 } 4262 4263 /* install self-referential address mapping entry(s) */ 4264 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW | 4265 X86_PG_A | X86_PG_M; 4266 4267 /* install large map entries if configured */ 4268 for (i = 0; i < lm_ents; i++) 4269 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i]; 4270 } 4271 4272 void 4273 pmap_pinit_pml5(vm_page_t pml5pg) 4274 { 4275 pml5_entry_t *pm_pml5; 4276 int i; 4277 4278 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg)); 4279 for (i = 0; i < NPML5EPG / 2; i++) 4280 pm_pml5[i] = 0; 4281 for (; i < NPML5EPG; i++) 4282 pm_pml5[i] = kernel_pmap->pm_pmltop[i]; 4283 } 4284 4285 static void 4286 pmap_pinit_pml4_pti(vm_page_t pml4pgu) 4287 { 4288 pml4_entry_t *pm_pml4u; 4289 int i; 4290 4291 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu)); 4292 for (i = 0; i < NPML4EPG; i++) 4293 pm_pml4u[i] = pti_pml4[i]; 4294 } 4295 4296 static void 4297 pmap_pinit_pml5_pti(vm_page_t pml5pgu) 4298 { 4299 pml5_entry_t *pm_pml5u; 4300 4301 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu)); 4302 pagezero(pm_pml5u); 4303 4304 /* 4305 * Add pml5 entry at top of KVA pointing to existing pml4 pti 4306 * table, entering all kernel mappings needed for usermode 4307 * into level 5 table. 4308 */ 4309 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 4310 pmap_kextract((vm_offset_t)pti_pml4) | 4311 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M; 4312 } 4313 4314 /* Allocate a page table page and do related bookkeeping */ 4315 static vm_page_t 4316 pmap_alloc_pt_page(pmap_t pmap, vm_pindex_t pindex, int flags) 4317 { 4318 vm_page_t m; 4319 4320 m = vm_page_alloc_noobj(flags); 4321 if (__predict_false(m == NULL)) 4322 return (NULL); 4323 m->pindex = pindex; 4324 pmap_pt_page_count_adj(pmap, 1); 4325 return (m); 4326 } 4327 4328 static void 4329 pmap_free_pt_page(pmap_t pmap, vm_page_t m, bool zerofilled) 4330 { 4331 /* 4332 * This function assumes the page will need to be unwired, 4333 * even though the counterpart allocation in pmap_alloc_pt_page() 4334 * doesn't enforce VM_ALLOC_WIRED. However, all current uses 4335 * of pmap_free_pt_page() require unwiring. The case in which 4336 * a PT page doesn't require unwiring because its ref_count has 4337 * naturally reached 0 is handled through _pmap_unwire_ptp(). 4338 */ 4339 vm_page_unwire_noq(m); 4340 if (zerofilled) 4341 vm_page_free_zero(m); 4342 else 4343 vm_page_free(m); 4344 4345 pmap_pt_page_count_adj(pmap, -1); 4346 } 4347 4348 _Static_assert(sizeof(struct pmap_pcid) == 8, "Fix pcpu zone for pm_pcidp"); 4349 4350 /* 4351 * Initialize a preallocated and zeroed pmap structure, 4352 * such as one in a vmspace structure. 4353 */ 4354 int 4355 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags) 4356 { 4357 vm_page_t pmltop_pg, pmltop_pgu; 4358 vm_paddr_t pmltop_phys; 4359 4360 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 4361 4362 /* 4363 * Allocate the page directory page. Pass NULL instead of a 4364 * pointer to the pmap here to avoid calling 4365 * pmap_resident_count_adj() through pmap_pt_page_count_adj(), 4366 * since that requires pmap lock. Instead do the accounting 4367 * manually. 4368 * 4369 * Note that final call to pmap_remove() optimization that 4370 * checks for zero resident_count is basically disabled by 4371 * accounting for top-level page. But the optimization was 4372 * not effective since we started using non-managed mapping of 4373 * the shared page. 4374 */ 4375 pmltop_pg = pmap_alloc_pt_page(NULL, 0, VM_ALLOC_WIRED | VM_ALLOC_ZERO | 4376 VM_ALLOC_WAITOK); 4377 pmap_pt_page_count_pinit(pmap, 1); 4378 4379 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg); 4380 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys); 4381 4382 if (pmap_pcid_enabled) { 4383 if (pmap->pm_pcidp == NULL) 4384 pmap->pm_pcidp = uma_zalloc_pcpu(pcpu_zone_8, 4385 M_WAITOK); 4386 pmap_pinit_pcids(pmap, PMAP_PCID_NONE, 0); 4387 } 4388 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */ 4389 pmap->pm_ucr3 = PMAP_NO_CR3; 4390 pmap->pm_pmltopu = NULL; 4391 4392 pmap->pm_type = pm_type; 4393 4394 /* 4395 * Do not install the host kernel mappings in the nested page 4396 * tables. These mappings are meaningless in the guest physical 4397 * address space. 4398 * Install minimal kernel mappings in PTI case. 4399 */ 4400 switch (pm_type) { 4401 case PT_X86: 4402 pmap->pm_cr3 = pmltop_phys; 4403 if (pmap_is_la57(pmap)) 4404 pmap_pinit_pml5(pmltop_pg); 4405 else 4406 pmap_pinit_pml4(pmltop_pg); 4407 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) { 4408 /* 4409 * As with pmltop_pg, pass NULL instead of a 4410 * pointer to the pmap to ensure that the PTI 4411 * page counted explicitly. 4412 */ 4413 pmltop_pgu = pmap_alloc_pt_page(NULL, 0, 4414 VM_ALLOC_WIRED | VM_ALLOC_WAITOK); 4415 pmap_pt_page_count_pinit(pmap, 1); 4416 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP( 4417 VM_PAGE_TO_PHYS(pmltop_pgu)); 4418 if (pmap_is_la57(pmap)) 4419 pmap_pinit_pml5_pti(pmltop_pgu); 4420 else 4421 pmap_pinit_pml4_pti(pmltop_pgu); 4422 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu); 4423 } 4424 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) { 4425 rangeset_init(&pmap->pm_pkru, pkru_dup_range, 4426 pkru_free_range, pmap, M_NOWAIT); 4427 } 4428 break; 4429 case PT_EPT: 4430 case PT_RVI: 4431 pmap->pm_eptsmr = smr_create("pmap", 0, 0); 4432 break; 4433 } 4434 4435 vm_radix_init(&pmap->pm_root); 4436 CPU_ZERO(&pmap->pm_active); 4437 TAILQ_INIT(&pmap->pm_pvchunk); 4438 pmap->pm_flags = flags; 4439 pmap->pm_eptgen = 0; 4440 4441 return (1); 4442 } 4443 4444 int 4445 pmap_pinit(pmap_t pmap) 4446 { 4447 4448 return (pmap_pinit_type(pmap, PT_X86, pmap_flags)); 4449 } 4450 4451 static void 4452 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte) 4453 { 4454 vm_page_t mpg; 4455 struct spglist free; 4456 4457 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 4458 if (mpg->ref_count != 0) 4459 return; 4460 SLIST_INIT(&free); 4461 _pmap_unwire_ptp(pmap, va, mpg, &free); 4462 pmap_invalidate_page(pmap, va); 4463 vm_page_free_pages_toq(&free, true); 4464 } 4465 4466 static pml4_entry_t * 4467 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va, 4468 bool addref) 4469 { 4470 vm_pindex_t pml5index; 4471 pml5_entry_t *pml5; 4472 pml4_entry_t *pml4; 4473 vm_page_t pml4pg; 4474 pt_entry_t PG_V; 4475 bool allocated; 4476 4477 if (!pmap_is_la57(pmap)) 4478 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]); 4479 4480 PG_V = pmap_valid_bit(pmap); 4481 pml5index = pmap_pml5e_index(va); 4482 pml5 = &pmap->pm_pmltop[pml5index]; 4483 if ((*pml5 & PG_V) == 0) { 4484 if (pmap_allocpte_nosleep(pmap, pmap_pml5e_pindex(va), lockp, 4485 va) == NULL) 4486 return (NULL); 4487 allocated = true; 4488 } else { 4489 allocated = false; 4490 } 4491 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME); 4492 pml4 = &pml4[pmap_pml4e_index(va)]; 4493 if ((*pml4 & PG_V) == 0) { 4494 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME); 4495 if (allocated && !addref) 4496 pml4pg->ref_count--; 4497 else if (!allocated && addref) 4498 pml4pg->ref_count++; 4499 } 4500 return (pml4); 4501 } 4502 4503 static pdp_entry_t * 4504 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va, 4505 bool addref) 4506 { 4507 vm_page_t pdppg; 4508 pml4_entry_t *pml4; 4509 pdp_entry_t *pdp; 4510 pt_entry_t PG_V; 4511 bool allocated; 4512 4513 PG_V = pmap_valid_bit(pmap); 4514 4515 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false); 4516 if (pml4 == NULL) 4517 return (NULL); 4518 4519 if ((*pml4 & PG_V) == 0) { 4520 /* Have to allocate a new pdp, recurse */ 4521 if (pmap_allocpte_nosleep(pmap, pmap_pml4e_pindex(va), lockp, 4522 va) == NULL) { 4523 if (pmap_is_la57(pmap)) 4524 pmap_allocpte_free_unref(pmap, va, 4525 pmap_pml5e(pmap, va)); 4526 return (NULL); 4527 } 4528 allocated = true; 4529 } else { 4530 allocated = false; 4531 } 4532 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME); 4533 pdp = &pdp[pmap_pdpe_index(va)]; 4534 if ((*pdp & PG_V) == 0) { 4535 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME); 4536 if (allocated && !addref) 4537 pdppg->ref_count--; 4538 else if (!allocated && addref) 4539 pdppg->ref_count++; 4540 } 4541 return (pdp); 4542 } 4543 4544 /* 4545 * The ptepindexes, i.e. page indices, of the page table pages encountered 4546 * while translating virtual address va are defined as follows: 4547 * - for the page table page (last level), 4548 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT, 4549 * in other words, it is just the index of the PDE that maps the page 4550 * table page. 4551 * - for the page directory page, 4552 * ptepindex = NUPDE (number of userland PD entries) + 4553 * (pmap_pde_index(va) >> NPDEPGSHIFT) 4554 * i.e. index of PDPE is put after the last index of PDE, 4555 * - for the page directory pointer page, 4556 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT + 4557 * NPML4EPGSHIFT), 4558 * i.e. index of pml4e is put after the last index of PDPE, 4559 * - for the PML4 page (if LA57 mode is enabled), 4560 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >> 4561 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT), 4562 * i.e. index of pml5e is put after the last index of PML4E. 4563 * 4564 * Define an order on the paging entries, where all entries of the 4565 * same height are put together, then heights are put from deepest to 4566 * root. Then ptexpindex is the sequential number of the 4567 * corresponding paging entry in this order. 4568 * 4569 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of 4570 * LA57 paging structures even in LA48 paging mode. Moreover, the 4571 * ptepindexes are calculated as if the paging structures were 5-level 4572 * regardless of the actual mode of operation. 4573 * 4574 * The root page at PML4/PML5 does not participate in this indexing scheme, 4575 * since it is statically allocated by pmap_pinit() and not by pmap_allocpte(). 4576 */ 4577 static vm_page_t 4578 pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp, 4579 vm_offset_t va) 4580 { 4581 vm_pindex_t pml5index, pml4index; 4582 pml5_entry_t *pml5, *pml5u; 4583 pml4_entry_t *pml4, *pml4u; 4584 pdp_entry_t *pdp; 4585 pd_entry_t *pd; 4586 vm_page_t m, pdpg; 4587 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 4588 4589 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4590 4591 PG_A = pmap_accessed_bit(pmap); 4592 PG_M = pmap_modified_bit(pmap); 4593 PG_V = pmap_valid_bit(pmap); 4594 PG_RW = pmap_rw_bit(pmap); 4595 4596 /* 4597 * Allocate a page table page. 4598 */ 4599 m = pmap_alloc_pt_page(pmap, ptepindex, 4600 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 4601 if (m == NULL) 4602 return (NULL); 4603 4604 /* 4605 * Map the pagetable page into the process address space, if 4606 * it isn't already there. 4607 */ 4608 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) { 4609 MPASS(pmap_is_la57(pmap)); 4610 4611 pml5index = pmap_pml5e_index(va); 4612 pml5 = &pmap->pm_pmltop[pml5index]; 4613 KASSERT((*pml5 & PG_V) == 0, 4614 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5)); 4615 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 4616 4617 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) { 4618 MPASS(pmap->pm_ucr3 != PMAP_NO_CR3); 4619 *pml5 |= pg_nx; 4620 4621 pml5u = &pmap->pm_pmltopu[pml5index]; 4622 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | 4623 PG_A | PG_M; 4624 } 4625 } else if (ptepindex >= NUPDE + NUPDPE) { 4626 pml4index = pmap_pml4e_index(va); 4627 /* Wire up a new PDPE page */ 4628 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true); 4629 if (pml4 == NULL) { 4630 pmap_free_pt_page(pmap, m, true); 4631 return (NULL); 4632 } 4633 KASSERT((*pml4 & PG_V) == 0, 4634 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4)); 4635 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 4636 4637 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL && 4638 pml4index < NUPML4E) { 4639 MPASS(pmap->pm_ucr3 != PMAP_NO_CR3); 4640 4641 /* 4642 * PTI: Make all user-space mappings in the 4643 * kernel-mode page table no-execute so that 4644 * we detect any programming errors that leave 4645 * the kernel-mode page table active on return 4646 * to user space. 4647 */ 4648 *pml4 |= pg_nx; 4649 4650 pml4u = &pmap->pm_pmltopu[pml4index]; 4651 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | 4652 PG_A | PG_M; 4653 } 4654 } else if (ptepindex >= NUPDE) { 4655 /* Wire up a new PDE page */ 4656 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true); 4657 if (pdp == NULL) { 4658 pmap_free_pt_page(pmap, m, true); 4659 return (NULL); 4660 } 4661 KASSERT((*pdp & PG_V) == 0, 4662 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp)); 4663 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 4664 } else { 4665 /* Wire up a new PTE page */ 4666 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false); 4667 if (pdp == NULL) { 4668 pmap_free_pt_page(pmap, m, true); 4669 return (NULL); 4670 } 4671 if ((*pdp & PG_V) == 0) { 4672 /* Have to allocate a new pd, recurse */ 4673 if (pmap_allocpte_nosleep(pmap, pmap_pdpe_pindex(va), 4674 lockp, va) == NULL) { 4675 pmap_allocpte_free_unref(pmap, va, 4676 pmap_pml4e(pmap, va)); 4677 pmap_free_pt_page(pmap, m, true); 4678 return (NULL); 4679 } 4680 } else { 4681 /* Add reference to the pd page */ 4682 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME); 4683 pdpg->ref_count++; 4684 } 4685 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME); 4686 4687 /* Now we know where the page directory page is */ 4688 pd = &pd[pmap_pde_index(va)]; 4689 KASSERT((*pd & PG_V) == 0, 4690 ("pmap %p va %#lx pd %#lx", pmap, va, *pd)); 4691 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 4692 } 4693 4694 return (m); 4695 } 4696 4697 /* 4698 * This routine is called if the desired page table page does not exist. 4699 * 4700 * If page table page allocation fails, this routine may sleep before 4701 * returning NULL. It sleeps only if a lock pointer was given. Sleep 4702 * occurs right before returning to the caller. This way, we never 4703 * drop pmap lock to sleep while a page table page has ref_count == 0, 4704 * which prevents the page from being freed under us. 4705 */ 4706 static vm_page_t 4707 pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp, 4708 vm_offset_t va) 4709 { 4710 vm_page_t m; 4711 4712 m = pmap_allocpte_nosleep(pmap, ptepindex, lockp, va); 4713 if (m == NULL && lockp != NULL) { 4714 RELEASE_PV_LIST_LOCK(lockp); 4715 PMAP_UNLOCK(pmap); 4716 PMAP_ASSERT_NOT_IN_DI(); 4717 vm_wait(NULL); 4718 PMAP_LOCK(pmap); 4719 } 4720 return (m); 4721 } 4722 4723 static pd_entry_t * 4724 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp, 4725 struct rwlock **lockp) 4726 { 4727 pdp_entry_t *pdpe, PG_V; 4728 pd_entry_t *pde; 4729 vm_page_t pdpg; 4730 vm_pindex_t pdpindex; 4731 4732 PG_V = pmap_valid_bit(pmap); 4733 4734 retry: 4735 pdpe = pmap_pdpe(pmap, va); 4736 if (pdpe != NULL && (*pdpe & PG_V) != 0) { 4737 pde = pmap_pdpe_to_pde(pdpe, va); 4738 if (va < VM_MAXUSER_ADDRESS) { 4739 /* Add a reference to the pd page. */ 4740 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME); 4741 pdpg->ref_count++; 4742 } else 4743 pdpg = NULL; 4744 } else if (va < VM_MAXUSER_ADDRESS) { 4745 /* Allocate a pd page. */ 4746 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT; 4747 pdpg = pmap_allocpte_alloc(pmap, NUPDE + pdpindex, lockp, va); 4748 if (pdpg == NULL) { 4749 if (lockp != NULL) 4750 goto retry; 4751 else 4752 return (NULL); 4753 } 4754 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg)); 4755 pde = &pde[pmap_pde_index(va)]; 4756 } else 4757 panic("pmap_alloc_pde: missing page table page for va %#lx", 4758 va); 4759 *pdpgp = pdpg; 4760 return (pde); 4761 } 4762 4763 static vm_page_t 4764 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 4765 { 4766 vm_pindex_t ptepindex; 4767 pd_entry_t *pd, PG_V; 4768 vm_page_t m; 4769 4770 PG_V = pmap_valid_bit(pmap); 4771 4772 /* 4773 * Calculate pagetable page index 4774 */ 4775 ptepindex = pmap_pde_pindex(va); 4776 retry: 4777 /* 4778 * Get the page directory entry 4779 */ 4780 pd = pmap_pde(pmap, va); 4781 4782 /* 4783 * This supports switching from a 2MB page to a 4784 * normal 4K page. 4785 */ 4786 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) { 4787 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) { 4788 /* 4789 * Invalidation of the 2MB page mapping may have caused 4790 * the deallocation of the underlying PD page. 4791 */ 4792 pd = NULL; 4793 } 4794 } 4795 4796 /* 4797 * If the page table page is mapped, we just increment the 4798 * hold count, and activate it. 4799 */ 4800 if (pd != NULL && (*pd & PG_V) != 0) { 4801 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME); 4802 m->ref_count++; 4803 } else { 4804 /* 4805 * Here if the pte page isn't mapped, or if it has been 4806 * deallocated. 4807 */ 4808 m = pmap_allocpte_alloc(pmap, ptepindex, lockp, va); 4809 if (m == NULL && lockp != NULL) 4810 goto retry; 4811 } 4812 return (m); 4813 } 4814 4815 /*************************************************** 4816 * Pmap allocation/deallocation routines. 4817 ***************************************************/ 4818 4819 /* 4820 * Release any resources held by the given physical map. 4821 * Called when a pmap initialized by pmap_pinit is being released. 4822 * Should only be called if the map contains no valid mappings. 4823 */ 4824 void 4825 pmap_release(pmap_t pmap) 4826 { 4827 vm_page_t m; 4828 int i; 4829 4830 KASSERT(vm_radix_is_empty(&pmap->pm_root), 4831 ("pmap_release: pmap %p has reserved page table page(s)", 4832 pmap)); 4833 KASSERT(CPU_EMPTY(&pmap->pm_active), 4834 ("releasing active pmap %p", pmap)); 4835 4836 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop)); 4837 4838 if (pmap_is_la57(pmap)) { 4839 for (i = NPML5EPG / 2; i < NPML5EPG; i++) 4840 pmap->pm_pmltop[i] = 0; 4841 } else { 4842 for (i = 0; i < NKPML4E; i++) /* KVA */ 4843 pmap->pm_pmltop[KPML4BASE + i] = 0; 4844 #ifdef KASAN 4845 for (i = 0; i < NKASANPML4E; i++) /* KASAN shadow map */ 4846 pmap->pm_pmltop[KASANPML4I + i] = 0; 4847 #endif 4848 #ifdef KMSAN 4849 for (i = 0; i < NKMSANSHADPML4E; i++) /* KMSAN shadow map */ 4850 pmap->pm_pmltop[KMSANSHADPML4I + i] = 0; 4851 for (i = 0; i < NKMSANORIGPML4E; i++) /* KMSAN shadow map */ 4852 pmap->pm_pmltop[KMSANORIGPML4I + i] = 0; 4853 #endif 4854 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */ 4855 pmap->pm_pmltop[DMPML4I + i] = 0; 4856 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */ 4857 for (i = 0; i < lm_ents; i++) /* Large Map */ 4858 pmap->pm_pmltop[LMSPML4I + i] = 0; 4859 } 4860 4861 pmap_free_pt_page(NULL, m, true); 4862 pmap_pt_page_count_pinit(pmap, -1); 4863 4864 if (pmap->pm_pmltopu != NULL) { 4865 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap-> 4866 pm_pmltopu)); 4867 pmap_free_pt_page(NULL, m, false); 4868 pmap_pt_page_count_pinit(pmap, -1); 4869 } 4870 if (pmap->pm_type == PT_X86 && 4871 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) 4872 rangeset_fini(&pmap->pm_pkru); 4873 4874 KASSERT(pmap->pm_stats.resident_count == 0, 4875 ("pmap_release: pmap %p resident count %ld != 0", 4876 pmap, pmap->pm_stats.resident_count)); 4877 } 4878 4879 static int 4880 kvm_size(SYSCTL_HANDLER_ARGS) 4881 { 4882 unsigned long ksize = kva_layout.km_high - kva_layout.km_low; 4883 4884 return sysctl_handle_long(oidp, &ksize, 0, req); 4885 } 4886 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE, 4887 0, 0, kvm_size, "LU", 4888 "Size of KVM"); 4889 4890 static int 4891 kvm_free(SYSCTL_HANDLER_ARGS) 4892 { 4893 unsigned long kfree = kva_layout.km_high - kernel_vm_end; 4894 4895 return sysctl_handle_long(oidp, &kfree, 0, req); 4896 } 4897 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE, 4898 0, 0, kvm_free, "LU", 4899 "Amount of KVM free"); 4900 4901 #ifdef KMSAN 4902 static void 4903 pmap_kmsan_shadow_map_page_array(vm_paddr_t pdppa, vm_size_t size) 4904 { 4905 pdp_entry_t *pdpe; 4906 pd_entry_t *pde; 4907 pt_entry_t *pte; 4908 vm_paddr_t dummypa, dummypd, dummypt; 4909 int i, npde, npdpg; 4910 4911 npdpg = howmany(size, NBPDP); 4912 npde = size / NBPDR; 4913 4914 dummypa = vm_phys_early_alloc(-1, PAGE_SIZE); 4915 pagezero((void *)PHYS_TO_DMAP(dummypa)); 4916 4917 dummypt = vm_phys_early_alloc(-1, PAGE_SIZE); 4918 pagezero((void *)PHYS_TO_DMAP(dummypt)); 4919 dummypd = vm_phys_early_alloc(-1, PAGE_SIZE * npdpg); 4920 for (i = 0; i < npdpg; i++) 4921 pagezero((void *)PHYS_TO_DMAP(dummypd + ptoa(i))); 4922 4923 pte = (pt_entry_t *)PHYS_TO_DMAP(dummypt); 4924 for (i = 0; i < NPTEPG; i++) 4925 pte[i] = (pt_entry_t)(dummypa | X86_PG_V | X86_PG_RW | 4926 X86_PG_A | X86_PG_M | pg_nx); 4927 4928 pde = (pd_entry_t *)PHYS_TO_DMAP(dummypd); 4929 for (i = 0; i < npde; i++) 4930 pde[i] = (pd_entry_t)(dummypt | X86_PG_V | X86_PG_RW | pg_nx); 4931 4932 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(pdppa); 4933 for (i = 0; i < npdpg; i++) 4934 pdpe[i] = (pdp_entry_t)(dummypd + ptoa(i) | X86_PG_V | 4935 X86_PG_RW | pg_nx); 4936 } 4937 4938 static void 4939 pmap_kmsan_page_array_startup(vm_offset_t start, vm_offset_t end) 4940 { 4941 vm_size_t size; 4942 4943 KASSERT(start % NBPDP == 0, ("unaligned page array start address")); 4944 4945 /* 4946 * The end of the page array's KVA region is 2MB aligned, see 4947 * kmem_init(). 4948 */ 4949 size = round_2mpage(end) - start; 4950 pmap_kmsan_shadow_map_page_array(KMSANSHADPDPphys, size); 4951 pmap_kmsan_shadow_map_page_array(KMSANORIGPDPphys, size); 4952 } 4953 #endif 4954 4955 /* 4956 * Allocate physical memory for the vm_page array and map it into KVA, 4957 * attempting to back the vm_pages with domain-local memory. 4958 */ 4959 void 4960 pmap_page_array_startup(long pages) 4961 { 4962 pdp_entry_t *pdpe; 4963 pd_entry_t *pde, newpdir; 4964 vm_offset_t va, start, end; 4965 vm_paddr_t pa; 4966 long pfn; 4967 int domain, i; 4968 4969 vm_page_array_size = pages; 4970 4971 start = kva_layout.km_low; 4972 end = start + pages * sizeof(struct vm_page); 4973 for (va = start; va < end; va += NBPDR) { 4974 pfn = first_page + (va - start) / sizeof(struct vm_page); 4975 domain = vm_phys_domain(ptoa(pfn)); 4976 pdpe = pmap_pdpe(kernel_pmap, va); 4977 if ((*pdpe & X86_PG_V) == 0) { 4978 pa = vm_phys_early_alloc(domain, PAGE_SIZE); 4979 dump_add_page(pa); 4980 pagezero((void *)PHYS_TO_DMAP(pa)); 4981 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW | 4982 X86_PG_A | X86_PG_M); 4983 } 4984 pde = pmap_pdpe_to_pde(pdpe, va); 4985 if ((*pde & X86_PG_V) != 0) 4986 panic("Unexpected pde"); 4987 pa = vm_phys_early_alloc(domain, NBPDR); 4988 for (i = 0; i < NPDEPG; i++) 4989 dump_add_page(pa + i * PAGE_SIZE); 4990 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A | 4991 X86_PG_M | PG_PS | pg_g | pg_nx); 4992 pde_store(pde, newpdir); 4993 } 4994 vm_page_array = (vm_page_t)start; 4995 4996 #ifdef KMSAN 4997 pmap_kmsan_page_array_startup(start, end); 4998 #endif 4999 } 5000 5001 /* 5002 * grow the number of kernel page table entries, if needed 5003 */ 5004 static int 5005 pmap_growkernel_nopanic(vm_offset_t addr) 5006 { 5007 vm_paddr_t paddr; 5008 vm_page_t nkpg; 5009 pd_entry_t *pde, newpdir; 5010 pdp_entry_t *pdpe; 5011 vm_offset_t end; 5012 int rv; 5013 5014 TSENTER(); 5015 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 5016 rv = KERN_SUCCESS; 5017 5018 /* 5019 * The kernel map covers two distinct regions of KVA: that used 5020 * for dynamic kernel memory allocations, and the uppermost 2GB 5021 * of the virtual address space. The latter is used to map the 5022 * kernel and loadable kernel modules. This scheme enables the 5023 * use of a special code generation model for kernel code which 5024 * takes advantage of compact addressing modes in machine code. 5025 * 5026 * Both regions grow upwards; to avoid wasting memory, the gap 5027 * in between is unmapped. If "addr" is above "KERNBASE", the 5028 * kernel's region is grown, otherwise the kmem region is grown. 5029 * 5030 * The correctness of this action is based on the following 5031 * argument: vm_map_insert() allocates contiguous ranges of the 5032 * kernel virtual address space. It calls this function if a range 5033 * ends after "kernel_vm_end". If the kernel is mapped between 5034 * "kernel_vm_end" and "addr", then the range cannot begin at 5035 * "kernel_vm_end". In fact, its beginning address cannot be less 5036 * than the kernel. Thus, there is no immediate need to allocate 5037 * any new kernel page table pages between "kernel_vm_end" and 5038 * "KERNBASE". 5039 */ 5040 if (KERNBASE < addr) { 5041 end = KERNBASE + nkpt * NBPDR; 5042 if (end == 0) { 5043 TSEXIT(); 5044 return (rv); 5045 } 5046 } else { 5047 end = kernel_vm_end; 5048 } 5049 5050 addr = roundup2(addr, NBPDR); 5051 if (addr - 1 >= vm_map_max(kernel_map)) 5052 addr = vm_map_max(kernel_map); 5053 if (addr <= end) { 5054 /* 5055 * The grown region is already mapped, so there is 5056 * nothing to do. 5057 */ 5058 TSEXIT(); 5059 return (rv); 5060 } 5061 5062 kasan_shadow_map(end, addr - end); 5063 kmsan_shadow_map(end, addr - end); 5064 while (end < addr) { 5065 pdpe = pmap_pdpe(kernel_pmap, end); 5066 if ((*pdpe & X86_PG_V) == 0) { 5067 nkpg = pmap_alloc_pt_page(kernel_pmap, 5068 pmap_pdpe_pindex(end), VM_ALLOC_INTERRUPT | 5069 VM_ALLOC_NOFREE | VM_ALLOC_WIRED | VM_ALLOC_ZERO); 5070 if (nkpg == NULL) { 5071 rv = KERN_RESOURCE_SHORTAGE; 5072 break; 5073 } 5074 paddr = VM_PAGE_TO_PHYS(nkpg); 5075 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW | 5076 X86_PG_A | X86_PG_M); 5077 continue; /* try again */ 5078 } 5079 pde = pmap_pdpe_to_pde(pdpe, end); 5080 if ((*pde & X86_PG_V) != 0) { 5081 end = (end + NBPDR) & ~PDRMASK; 5082 if (end - 1 >= vm_map_max(kernel_map)) { 5083 end = vm_map_max(kernel_map); 5084 break; 5085 } 5086 continue; 5087 } 5088 5089 nkpg = pmap_alloc_pt_page(kernel_pmap, pmap_pde_pindex(end), 5090 VM_ALLOC_INTERRUPT | VM_ALLOC_NOFREE | VM_ALLOC_WIRED | 5091 VM_ALLOC_ZERO); 5092 if (nkpg == NULL) { 5093 rv = KERN_RESOURCE_SHORTAGE; 5094 break; 5095 } 5096 5097 paddr = VM_PAGE_TO_PHYS(nkpg); 5098 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M; 5099 pde_store(pde, newpdir); 5100 5101 end = (end + NBPDR) & ~PDRMASK; 5102 if (end - 1 >= vm_map_max(kernel_map)) { 5103 end = vm_map_max(kernel_map); 5104 break; 5105 } 5106 } 5107 5108 if (end <= KERNBASE) 5109 kernel_vm_end = end; 5110 else 5111 nkpt = howmany(end - KERNBASE, NBPDR); 5112 TSEXIT(); 5113 return (rv); 5114 } 5115 5116 int 5117 pmap_growkernel(vm_offset_t addr) 5118 { 5119 int rv; 5120 5121 rv = pmap_growkernel_nopanic(addr); 5122 if (rv != KERN_SUCCESS && pmap_growkernel_panic) 5123 panic("pmap_growkernel: no memory to grow kernel"); 5124 return (rv); 5125 } 5126 5127 /*************************************************** 5128 * page management routines. 5129 ***************************************************/ 5130 5131 static const uint64_t pc_freemask[_NPCM] = { 5132 [0 ... _NPCM - 2] = PC_FREEN, 5133 [_NPCM - 1] = PC_FREEL 5134 }; 5135 5136 #ifdef PV_STATS 5137 5138 static COUNTER_U64_DEFINE_EARLY(pc_chunk_count); 5139 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, 5140 &pc_chunk_count, "Current number of pv entry cnunks"); 5141 5142 static COUNTER_U64_DEFINE_EARLY(pc_chunk_allocs); 5143 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, 5144 &pc_chunk_allocs, "Total number of pv entry chunks allocated"); 5145 5146 static COUNTER_U64_DEFINE_EARLY(pc_chunk_frees); 5147 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, 5148 &pc_chunk_frees, "Total number of pv entry chunks freed"); 5149 5150 static COUNTER_U64_DEFINE_EARLY(pc_chunk_tryfail); 5151 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, 5152 &pc_chunk_tryfail, 5153 "Number of failed attempts to get a pv entry chunk page"); 5154 5155 static COUNTER_U64_DEFINE_EARLY(pv_entry_frees); 5156 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, 5157 &pv_entry_frees, "Total number of pv entries freed"); 5158 5159 static COUNTER_U64_DEFINE_EARLY(pv_entry_allocs); 5160 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, 5161 &pv_entry_allocs, "Total number of pv entries allocated"); 5162 5163 static COUNTER_U64_DEFINE_EARLY(pv_entry_count); 5164 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, 5165 &pv_entry_count, "Current number of pv entries"); 5166 5167 static COUNTER_U64_DEFINE_EARLY(pv_entry_spare); 5168 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, 5169 &pv_entry_spare, "Current number of spare pv entries"); 5170 #endif 5171 5172 static void 5173 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di) 5174 { 5175 5176 if (pmap == NULL) 5177 return; 5178 pmap_invalidate_all(pmap); 5179 if (pmap != locked_pmap) 5180 PMAP_UNLOCK(pmap); 5181 if (start_di) 5182 pmap_delayed_invl_finish(); 5183 } 5184 5185 /* 5186 * We are in a serious low memory condition. Resort to 5187 * drastic measures to free some pages so we can allocate 5188 * another pv entry chunk. 5189 * 5190 * Returns NULL if PV entries were reclaimed from the specified pmap. 5191 * 5192 * We do not, however, unmap 2mpages because subsequent accesses will 5193 * allocate per-page pv entries until repromotion occurs, thereby 5194 * exacerbating the shortage of free pv entries. 5195 */ 5196 static vm_page_t 5197 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain) 5198 { 5199 struct pv_chunks_list *pvc; 5200 struct pv_chunk *pc, *pc_marker, *pc_marker_end; 5201 struct pv_chunk_header pc_marker_b, pc_marker_end_b; 5202 struct md_page *pvh; 5203 pd_entry_t *pde; 5204 pmap_t next_pmap, pmap; 5205 pt_entry_t *pte, tpte; 5206 pt_entry_t PG_G, PG_A, PG_M, PG_RW; 5207 pv_entry_t pv; 5208 vm_offset_t va; 5209 vm_page_t m, m_pc; 5210 struct spglist free; 5211 uint64_t inuse; 5212 int bit, field, freed; 5213 bool start_di, restart; 5214 5215 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 5216 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL")); 5217 pmap = NULL; 5218 m_pc = NULL; 5219 PG_G = PG_A = PG_M = PG_RW = 0; 5220 SLIST_INIT(&free); 5221 bzero(&pc_marker_b, sizeof(pc_marker_b)); 5222 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b)); 5223 pc_marker = (struct pv_chunk *)&pc_marker_b; 5224 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b; 5225 5226 /* 5227 * A delayed invalidation block should already be active if 5228 * pmap_advise() or pmap_remove() called this function by way 5229 * of pmap_demote_pde_locked(). 5230 */ 5231 start_di = pmap_not_in_di(); 5232 5233 pvc = &pv_chunks[domain]; 5234 mtx_lock(&pvc->pvc_lock); 5235 pvc->active_reclaims++; 5236 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru); 5237 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru); 5238 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end && 5239 SLIST_EMPTY(&free)) { 5240 next_pmap = pc->pc_pmap; 5241 if (next_pmap == NULL) { 5242 /* 5243 * The next chunk is a marker. However, it is 5244 * not our marker, so active_reclaims must be 5245 * > 1. Consequently, the next_chunk code 5246 * will not rotate the pv_chunks list. 5247 */ 5248 goto next_chunk; 5249 } 5250 mtx_unlock(&pvc->pvc_lock); 5251 5252 /* 5253 * A pv_chunk can only be removed from the pc_lru list 5254 * when both pc_chunks_mutex is owned and the 5255 * corresponding pmap is locked. 5256 */ 5257 if (pmap != next_pmap) { 5258 restart = false; 5259 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, 5260 start_di); 5261 pmap = next_pmap; 5262 /* Avoid deadlock and lock recursion. */ 5263 if (pmap > locked_pmap) { 5264 RELEASE_PV_LIST_LOCK(lockp); 5265 PMAP_LOCK(pmap); 5266 if (start_di) 5267 pmap_delayed_invl_start(); 5268 mtx_lock(&pvc->pvc_lock); 5269 restart = true; 5270 } else if (pmap != locked_pmap) { 5271 if (PMAP_TRYLOCK(pmap)) { 5272 if (start_di) 5273 pmap_delayed_invl_start(); 5274 mtx_lock(&pvc->pvc_lock); 5275 restart = true; 5276 } else { 5277 pmap = NULL; /* pmap is not locked */ 5278 mtx_lock(&pvc->pvc_lock); 5279 pc = TAILQ_NEXT(pc_marker, pc_lru); 5280 if (pc == NULL || 5281 pc->pc_pmap != next_pmap) 5282 continue; 5283 goto next_chunk; 5284 } 5285 } else if (start_di) 5286 pmap_delayed_invl_start(); 5287 PG_G = pmap_global_bit(pmap); 5288 PG_A = pmap_accessed_bit(pmap); 5289 PG_M = pmap_modified_bit(pmap); 5290 PG_RW = pmap_rw_bit(pmap); 5291 if (restart) 5292 continue; 5293 } 5294 5295 /* 5296 * Destroy every non-wired, 4 KB page mapping in the chunk. 5297 */ 5298 freed = 0; 5299 for (field = 0; field < _NPCM; field++) { 5300 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 5301 inuse != 0; inuse &= ~(1UL << bit)) { 5302 bit = bsfq(inuse); 5303 pv = &pc->pc_pventry[field * 64 + bit]; 5304 va = pv->pv_va; 5305 pde = pmap_pde(pmap, va); 5306 if ((*pde & PG_PS) != 0) 5307 continue; 5308 pte = pmap_pde_to_pte(pde, va); 5309 if ((*pte & PG_W) != 0) 5310 continue; 5311 tpte = pte_load_clear(pte); 5312 if ((tpte & PG_G) != 0) 5313 pmap_invalidate_page(pmap, va); 5314 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 5315 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5316 vm_page_dirty(m); 5317 if ((tpte & PG_A) != 0) 5318 vm_page_aflag_set(m, PGA_REFERENCED); 5319 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 5320 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 5321 m->md.pv_gen++; 5322 if (TAILQ_EMPTY(&m->md.pv_list) && 5323 (m->flags & PG_FICTITIOUS) == 0) { 5324 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5325 if (TAILQ_EMPTY(&pvh->pv_list)) { 5326 vm_page_aflag_clear(m, 5327 PGA_WRITEABLE); 5328 } 5329 } 5330 pmap_delayed_invl_page(m); 5331 pc->pc_map[field] |= 1UL << bit; 5332 pmap_unuse_pt(pmap, va, *pde, &free); 5333 freed++; 5334 } 5335 } 5336 if (freed == 0) { 5337 mtx_lock(&pvc->pvc_lock); 5338 goto next_chunk; 5339 } 5340 /* Every freed mapping is for a 4 KB page. */ 5341 pmap_resident_count_adj(pmap, -freed); 5342 PV_STAT(counter_u64_add(pv_entry_frees, freed)); 5343 PV_STAT(counter_u64_add(pv_entry_spare, freed)); 5344 PV_STAT(counter_u64_add(pv_entry_count, -freed)); 5345 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5346 if (pc_is_free(pc)) { 5347 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV)); 5348 PV_STAT(counter_u64_add(pc_chunk_count, -1)); 5349 PV_STAT(counter_u64_add(pc_chunk_frees, 1)); 5350 /* Entire chunk is free; return it. */ 5351 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 5352 dump_drop_page(m_pc->phys_addr); 5353 mtx_lock(&pvc->pvc_lock); 5354 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 5355 break; 5356 } 5357 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 5358 mtx_lock(&pvc->pvc_lock); 5359 /* One freed pv entry in locked_pmap is sufficient. */ 5360 if (pmap == locked_pmap) 5361 break; 5362 next_chunk: 5363 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru); 5364 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru); 5365 if (pvc->active_reclaims == 1 && pmap != NULL) { 5366 /* 5367 * Rotate the pv chunks list so that we do not 5368 * scan the same pv chunks that could not be 5369 * freed (because they contained a wired 5370 * and/or superpage mapping) on every 5371 * invocation of reclaim_pv_chunk(). 5372 */ 5373 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) { 5374 MPASS(pc->pc_pmap != NULL); 5375 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 5376 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru); 5377 } 5378 } 5379 } 5380 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru); 5381 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru); 5382 pvc->active_reclaims--; 5383 mtx_unlock(&pvc->pvc_lock); 5384 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di); 5385 if (m_pc == NULL && !SLIST_EMPTY(&free)) { 5386 m_pc = SLIST_FIRST(&free); 5387 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 5388 /* Recycle a freed page table page. */ 5389 m_pc->ref_count = 1; 5390 } 5391 vm_page_free_pages_toq(&free, true); 5392 return (m_pc); 5393 } 5394 5395 static vm_page_t 5396 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp) 5397 { 5398 vm_page_t m; 5399 int i, domain; 5400 5401 domain = PCPU_GET(domain); 5402 for (i = 0; i < vm_ndomains; i++) { 5403 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain); 5404 if (m != NULL) 5405 break; 5406 domain = (domain + 1) % vm_ndomains; 5407 } 5408 5409 return (m); 5410 } 5411 5412 /* 5413 * free the pv_entry back to the free list 5414 */ 5415 static void 5416 free_pv_entry(pmap_t pmap, pv_entry_t pv) 5417 { 5418 struct pv_chunk *pc; 5419 int idx, field, bit; 5420 5421 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5422 PV_STAT(counter_u64_add(pv_entry_frees, 1)); 5423 PV_STAT(counter_u64_add(pv_entry_spare, 1)); 5424 PV_STAT(counter_u64_add(pv_entry_count, -1)); 5425 pc = pv_to_chunk(pv); 5426 idx = pv - &pc->pc_pventry[0]; 5427 field = idx / 64; 5428 bit = idx % 64; 5429 pc->pc_map[field] |= 1ul << bit; 5430 if (!pc_is_free(pc)) { 5431 /* 98% of the time, pc is already at the head of the list. */ 5432 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) { 5433 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5434 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 5435 } 5436 return; 5437 } 5438 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5439 free_pv_chunk(pc); 5440 } 5441 5442 static void 5443 free_pv_chunk_dequeued(struct pv_chunk *pc) 5444 { 5445 vm_page_t m; 5446 5447 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV)); 5448 PV_STAT(counter_u64_add(pc_chunk_count, -1)); 5449 PV_STAT(counter_u64_add(pc_chunk_frees, 1)); 5450 counter_u64_add(pv_page_count, -1); 5451 /* entire chunk is free, return it */ 5452 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 5453 dump_drop_page(m->phys_addr); 5454 vm_page_unwire_noq(m); 5455 vm_page_free(m); 5456 } 5457 5458 static void 5459 free_pv_chunk(struct pv_chunk *pc) 5460 { 5461 struct pv_chunks_list *pvc; 5462 5463 pvc = &pv_chunks[pc_to_domain(pc)]; 5464 mtx_lock(&pvc->pvc_lock); 5465 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 5466 mtx_unlock(&pvc->pvc_lock); 5467 free_pv_chunk_dequeued(pc); 5468 } 5469 5470 static void 5471 free_pv_chunk_batch(struct pv_chunklist *batch) 5472 { 5473 struct pv_chunks_list *pvc; 5474 struct pv_chunk *pc, *npc; 5475 int i; 5476 5477 for (i = 0; i < vm_ndomains; i++) { 5478 if (TAILQ_EMPTY(&batch[i])) 5479 continue; 5480 pvc = &pv_chunks[i]; 5481 mtx_lock(&pvc->pvc_lock); 5482 TAILQ_FOREACH(pc, &batch[i], pc_list) { 5483 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 5484 } 5485 mtx_unlock(&pvc->pvc_lock); 5486 } 5487 5488 for (i = 0; i < vm_ndomains; i++) { 5489 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) { 5490 free_pv_chunk_dequeued(pc); 5491 } 5492 } 5493 } 5494 5495 /* 5496 * Returns a new PV entry, allocating a new PV chunk from the system when 5497 * needed. If this PV chunk allocation fails and a PV list lock pointer was 5498 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is 5499 * returned. 5500 * 5501 * The given PV list lock may be released. 5502 */ 5503 static pv_entry_t 5504 get_pv_entry(pmap_t pmap, struct rwlock **lockp) 5505 { 5506 struct pv_chunks_list *pvc; 5507 int bit, field; 5508 pv_entry_t pv; 5509 struct pv_chunk *pc; 5510 vm_page_t m; 5511 5512 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5513 PV_STAT(counter_u64_add(pv_entry_allocs, 1)); 5514 retry: 5515 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 5516 if (pc != NULL) { 5517 for (field = 0; field < _NPCM; field++) { 5518 if (pc->pc_map[field]) { 5519 bit = bsfq(pc->pc_map[field]); 5520 break; 5521 } 5522 } 5523 if (field < _NPCM) { 5524 pv = &pc->pc_pventry[field * 64 + bit]; 5525 pc->pc_map[field] &= ~(1ul << bit); 5526 /* If this was the last item, move it to tail */ 5527 if (pc_is_full(pc)) { 5528 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5529 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, 5530 pc_list); 5531 } 5532 PV_STAT(counter_u64_add(pv_entry_count, 1)); 5533 PV_STAT(counter_u64_add(pv_entry_spare, -1)); 5534 return (pv); 5535 } 5536 } 5537 /* No free items, allocate another chunk */ 5538 m = vm_page_alloc_noobj(VM_ALLOC_WIRED); 5539 if (m == NULL) { 5540 if (lockp == NULL) { 5541 PV_STAT(counter_u64_add(pc_chunk_tryfail, 1)); 5542 return (NULL); 5543 } 5544 m = reclaim_pv_chunk(pmap, lockp); 5545 if (m == NULL) 5546 goto retry; 5547 } else 5548 counter_u64_add(pv_page_count, 1); 5549 PV_STAT(counter_u64_add(pc_chunk_count, 1)); 5550 PV_STAT(counter_u64_add(pc_chunk_allocs, 1)); 5551 dump_add_page(m->phys_addr); 5552 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 5553 pc->pc_pmap = pmap; 5554 pc->pc_map[0] = PC_FREEN & ~1ul; /* preallocated bit 0 */ 5555 pc->pc_map[1] = PC_FREEN; 5556 pc->pc_map[2] = PC_FREEL; 5557 pvc = &pv_chunks[vm_page_domain(m)]; 5558 mtx_lock(&pvc->pvc_lock); 5559 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru); 5560 mtx_unlock(&pvc->pvc_lock); 5561 pv = &pc->pc_pventry[0]; 5562 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 5563 PV_STAT(counter_u64_add(pv_entry_count, 1)); 5564 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV - 1)); 5565 return (pv); 5566 } 5567 5568 /* 5569 * Returns the number of one bits within the given PV chunk map. 5570 * 5571 * The erratas for Intel processors state that "POPCNT Instruction May 5572 * Take Longer to Execute Than Expected". It is believed that the 5573 * issue is the spurious dependency on the destination register. 5574 * Provide a hint to the register rename logic that the destination 5575 * value is overwritten, by clearing it, as suggested in the 5576 * optimization manual. It should be cheap for unaffected processors 5577 * as well. 5578 * 5579 * Reference numbers for erratas are 5580 * 4th Gen Core: HSD146 5581 * 5th Gen Core: BDM85 5582 * 6th Gen Core: SKL029 5583 */ 5584 static int 5585 popcnt_pc_map_pq(uint64_t *map) 5586 { 5587 u_long result, tmp; 5588 5589 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;" 5590 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;" 5591 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0" 5592 : "=&r" (result), "=&r" (tmp) 5593 : "m" (map[0]), "m" (map[1]), "m" (map[2])); 5594 return (result); 5595 } 5596 5597 /* 5598 * Ensure that the number of spare PV entries in the specified pmap meets or 5599 * exceeds the given count, "needed". 5600 * 5601 * The given PV list lock may be released. 5602 */ 5603 static void 5604 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp) 5605 { 5606 struct pv_chunks_list *pvc; 5607 struct pch new_tail[PMAP_MEMDOM]; 5608 struct pv_chunk *pc; 5609 vm_page_t m; 5610 int avail, free, i; 5611 bool reclaimed; 5612 5613 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5614 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL")); 5615 5616 /* 5617 * Newly allocated PV chunks must be stored in a private list until 5618 * the required number of PV chunks have been allocated. Otherwise, 5619 * reclaim_pv_chunk() could recycle one of these chunks. In 5620 * contrast, these chunks must be added to the pmap upon allocation. 5621 */ 5622 for (i = 0; i < PMAP_MEMDOM; i++) 5623 TAILQ_INIT(&new_tail[i]); 5624 retry: 5625 avail = 0; 5626 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) { 5627 #ifndef __POPCNT__ 5628 if ((cpu_feature2 & CPUID2_POPCNT) == 0) 5629 bit_count((bitstr_t *)pc->pc_map, 0, 5630 sizeof(pc->pc_map) * NBBY, &free); 5631 else 5632 #endif 5633 free = popcnt_pc_map_pq(pc->pc_map); 5634 if (free == 0) 5635 break; 5636 avail += free; 5637 if (avail >= needed) 5638 break; 5639 } 5640 for (reclaimed = false; avail < needed; avail += _NPCPV) { 5641 m = vm_page_alloc_noobj(VM_ALLOC_WIRED); 5642 if (m == NULL) { 5643 m = reclaim_pv_chunk(pmap, lockp); 5644 if (m == NULL) 5645 goto retry; 5646 reclaimed = true; 5647 } else 5648 counter_u64_add(pv_page_count, 1); 5649 PV_STAT(counter_u64_add(pc_chunk_count, 1)); 5650 PV_STAT(counter_u64_add(pc_chunk_allocs, 1)); 5651 dump_add_page(m->phys_addr); 5652 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 5653 pc->pc_pmap = pmap; 5654 pc->pc_map[0] = PC_FREEN; 5655 pc->pc_map[1] = PC_FREEN; 5656 pc->pc_map[2] = PC_FREEL; 5657 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 5658 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru); 5659 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV)); 5660 5661 /* 5662 * The reclaim might have freed a chunk from the current pmap. 5663 * If that chunk contained available entries, we need to 5664 * re-count the number of available entries. 5665 */ 5666 if (reclaimed) 5667 goto retry; 5668 } 5669 for (i = 0; i < vm_ndomains; i++) { 5670 if (TAILQ_EMPTY(&new_tail[i])) 5671 continue; 5672 pvc = &pv_chunks[i]; 5673 mtx_lock(&pvc->pvc_lock); 5674 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru); 5675 mtx_unlock(&pvc->pvc_lock); 5676 } 5677 } 5678 5679 /* 5680 * First find and then remove the pv entry for the specified pmap and virtual 5681 * address from the specified pv list. Returns the pv entry if found and NULL 5682 * otherwise. This operation can be performed on pv lists for either 4KB or 5683 * 2MB page mappings. 5684 */ 5685 static __inline pv_entry_t 5686 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 5687 { 5688 pv_entry_t pv; 5689 5690 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5691 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 5692 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 5693 pvh->pv_gen++; 5694 break; 5695 } 5696 } 5697 return (pv); 5698 } 5699 5700 /* 5701 * After demotion from a 2MB page mapping to 512 4KB page mappings, 5702 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv 5703 * entries for each of the 4KB page mappings. 5704 */ 5705 static void 5706 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 5707 struct rwlock **lockp) 5708 { 5709 struct md_page *pvh; 5710 struct pv_chunk *pc; 5711 pv_entry_t pv; 5712 vm_offset_t va_last; 5713 vm_page_t m; 5714 int bit, field; 5715 5716 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5717 KASSERT((pa & PDRMASK) == 0, 5718 ("pmap_pv_demote_pde: pa is not 2mpage aligned")); 5719 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 5720 5721 /* 5722 * Transfer the 2mpage's pv entry for this mapping to the first 5723 * page's pv list. Once this transfer begins, the pv list lock 5724 * must not be released until the last pv entry is reinstantiated. 5725 */ 5726 pvh = pa_to_pvh(pa); 5727 va = trunc_2mpage(va); 5728 pv = pmap_pvh_remove(pvh, pmap, va); 5729 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 5730 m = PHYS_TO_VM_PAGE(pa); 5731 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 5732 m->md.pv_gen++; 5733 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 5734 PV_STAT(counter_u64_add(pv_entry_allocs, NPTEPG - 1)); 5735 va_last = va + NBPDR - PAGE_SIZE; 5736 for (;;) { 5737 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 5738 KASSERT(!pc_is_full(pc), ("pmap_pv_demote_pde: missing spare")); 5739 for (field = 0; field < _NPCM; field++) { 5740 while (pc->pc_map[field]) { 5741 bit = bsfq(pc->pc_map[field]); 5742 pc->pc_map[field] &= ~(1ul << bit); 5743 pv = &pc->pc_pventry[field * 64 + bit]; 5744 va += PAGE_SIZE; 5745 pv->pv_va = va; 5746 m++; 5747 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5748 ("pmap_pv_demote_pde: page %p is not managed", m)); 5749 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 5750 m->md.pv_gen++; 5751 if (va == va_last) 5752 goto out; 5753 } 5754 } 5755 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5756 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 5757 } 5758 out: 5759 if (pc_is_full(pc)) { 5760 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5761 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 5762 } 5763 PV_STAT(counter_u64_add(pv_entry_count, NPTEPG - 1)); 5764 PV_STAT(counter_u64_add(pv_entry_spare, -(NPTEPG - 1))); 5765 } 5766 5767 #if VM_NRESERVLEVEL > 0 5768 /* 5769 * After promotion from 512 4KB page mappings to a single 2MB page mapping, 5770 * replace the many pv entries for the 4KB page mappings by a single pv entry 5771 * for the 2MB page mapping. 5772 */ 5773 static void 5774 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 5775 struct rwlock **lockp) 5776 { 5777 struct md_page *pvh; 5778 pv_entry_t pv; 5779 vm_offset_t va_last; 5780 vm_page_t m; 5781 5782 KASSERT((pa & PDRMASK) == 0, 5783 ("pmap_pv_promote_pde: pa is not 2mpage aligned")); 5784 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 5785 5786 /* 5787 * Transfer the first page's pv entry for this mapping to the 2mpage's 5788 * pv list. Aside from avoiding the cost of a call to get_pv_entry(), 5789 * a transfer avoids the possibility that get_pv_entry() calls 5790 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the 5791 * mappings that is being promoted. 5792 */ 5793 m = PHYS_TO_VM_PAGE(pa); 5794 va = trunc_2mpage(va); 5795 pv = pmap_pvh_remove(&m->md, pmap, va); 5796 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 5797 pvh = pa_to_pvh(pa); 5798 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 5799 pvh->pv_gen++; 5800 /* Free the remaining NPTEPG - 1 pv entries. */ 5801 va_last = va + NBPDR - PAGE_SIZE; 5802 do { 5803 m++; 5804 va += PAGE_SIZE; 5805 pmap_pvh_free(&m->md, pmap, va); 5806 } while (va < va_last); 5807 } 5808 #endif /* VM_NRESERVLEVEL > 0 */ 5809 5810 /* 5811 * First find and then destroy the pv entry for the specified pmap and virtual 5812 * address. This operation can be performed on pv lists for either 4KB or 2MB 5813 * page mappings. 5814 */ 5815 static void 5816 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 5817 { 5818 pv_entry_t pv; 5819 5820 pv = pmap_pvh_remove(pvh, pmap, va); 5821 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 5822 free_pv_entry(pmap, pv); 5823 } 5824 5825 /* 5826 * Conditionally create the PV entry for a 4KB page mapping if the required 5827 * memory can be allocated without resorting to reclamation. 5828 */ 5829 static bool 5830 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m, 5831 struct rwlock **lockp) 5832 { 5833 pv_entry_t pv; 5834 5835 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5836 /* Pass NULL instead of the lock pointer to disable reclamation. */ 5837 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 5838 pv->pv_va = va; 5839 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 5840 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 5841 m->md.pv_gen++; 5842 return (true); 5843 } else 5844 return (false); 5845 } 5846 5847 /* 5848 * Create the PV entry for a 2MB page mapping. Always returns true unless the 5849 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns 5850 * false if the PV entry cannot be allocated without resorting to reclamation. 5851 */ 5852 static bool 5853 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags, 5854 struct rwlock **lockp) 5855 { 5856 struct md_page *pvh; 5857 pv_entry_t pv; 5858 vm_paddr_t pa; 5859 5860 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5861 /* Pass NULL instead of the lock pointer to disable reclamation. */ 5862 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ? 5863 NULL : lockp)) == NULL) 5864 return (false); 5865 pv->pv_va = va; 5866 pa = pde & PG_PS_FRAME; 5867 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 5868 pvh = pa_to_pvh(pa); 5869 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 5870 pvh->pv_gen++; 5871 return (true); 5872 } 5873 5874 /* 5875 * Fills a page table page with mappings to consecutive physical pages. 5876 */ 5877 static void 5878 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 5879 { 5880 pt_entry_t *pte; 5881 5882 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 5883 *pte = newpte; 5884 newpte += PAGE_SIZE; 5885 } 5886 } 5887 5888 /* 5889 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page 5890 * mapping is invalidated. 5891 */ 5892 static bool 5893 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 5894 { 5895 struct rwlock *lock; 5896 bool rv; 5897 5898 lock = NULL; 5899 rv = pmap_demote_pde_locked(pmap, pde, va, &lock); 5900 if (lock != NULL) 5901 rw_wunlock(lock); 5902 return (rv); 5903 } 5904 5905 static void 5906 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused) 5907 { 5908 #ifdef INVARIANTS 5909 #ifdef DIAGNOSTIC 5910 pt_entry_t *xpte, *ypte; 5911 5912 for (xpte = firstpte; xpte < firstpte + NPTEPG; 5913 xpte++, newpte += PAGE_SIZE) { 5914 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) { 5915 printf("pmap_demote_pde: xpte %zd and newpte map " 5916 "different pages: found %#lx, expected %#lx\n", 5917 xpte - firstpte, *xpte, newpte); 5918 printf("page table dump\n"); 5919 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++) 5920 printf("%zd %#lx\n", ypte - firstpte, *ypte); 5921 panic("firstpte"); 5922 } 5923 } 5924 #else 5925 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 5926 ("pmap_demote_pde: firstpte and newpte map different physical" 5927 " addresses")); 5928 #endif 5929 #endif 5930 } 5931 5932 static void 5933 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 5934 pd_entry_t oldpde, struct rwlock **lockp) 5935 { 5936 struct spglist free; 5937 vm_offset_t sva; 5938 5939 SLIST_INIT(&free); 5940 sva = trunc_2mpage(va); 5941 pmap_remove_pde(pmap, pde, sva, true, &free, lockp); 5942 if ((oldpde & pmap_global_bit(pmap)) == 0) 5943 pmap_invalidate_pde_page(pmap, sva, oldpde); 5944 vm_page_free_pages_toq(&free, true); 5945 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p", 5946 va, pmap); 5947 } 5948 5949 static bool 5950 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, 5951 struct rwlock **lockp) 5952 { 5953 return (pmap_demote_pde_mpte(pmap, pde, va, lockp, NULL)); 5954 } 5955 5956 static bool 5957 pmap_demote_pde_mpte(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, 5958 struct rwlock **lockp, vm_page_t mpte) 5959 { 5960 pd_entry_t newpde, oldpde; 5961 pt_entry_t *firstpte, newpte; 5962 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V; 5963 vm_paddr_t mptepa; 5964 int PG_PTE_CACHE; 5965 bool in_kernel; 5966 5967 PG_A = pmap_accessed_bit(pmap); 5968 PG_G = pmap_global_bit(pmap); 5969 PG_M = pmap_modified_bit(pmap); 5970 PG_RW = pmap_rw_bit(pmap); 5971 PG_V = pmap_valid_bit(pmap); 5972 PG_PTE_CACHE = pmap_cache_mask(pmap, false); 5973 PG_PKU_MASK = pmap_pku_mask_bit(pmap); 5974 5975 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 5976 oldpde = *pde; 5977 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 5978 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 5979 KASSERT((oldpde & PG_MANAGED) == 0 || lockp != NULL, 5980 ("pmap_demote_pde: lockp for a managed mapping is NULL")); 5981 in_kernel = va >= VM_MAXUSER_ADDRESS; 5982 if (mpte == NULL) { 5983 /* 5984 * Invalidate the 2MB page mapping and return "failure" if the 5985 * mapping was never accessed and not wired. 5986 */ 5987 if ((oldpde & PG_A) == 0) { 5988 if ((oldpde & PG_W) == 0) { 5989 pmap_demote_pde_abort(pmap, va, pde, oldpde, 5990 lockp); 5991 return (false); 5992 } 5993 mpte = pmap_remove_pt_page(pmap, va); 5994 /* Fill the PTP with PTEs that have PG_A cleared. */ 5995 mpte->valid = 0; 5996 } else if ((mpte = pmap_remove_pt_page(pmap, va)) == NULL) { 5997 KASSERT((oldpde & PG_W) == 0, 5998 ("pmap_demote_pde: page table page for a wired mapping is missing")); 5999 6000 /* 6001 * If the page table page is missing and the mapping 6002 * is for a kernel address, the mapping must belong to 6003 * the direct map. Page table pages are preallocated 6004 * for every other part of the kernel address space, 6005 * so the direct map region is the only part of the 6006 * kernel address space that must be handled here. 6007 */ 6008 KASSERT(!in_kernel || (va >= kva_layout.dmap_low && 6009 va < kva_layout.dmap_high), 6010 ("pmap_demote_pde: No saved mpte for va %#lx", va)); 6011 6012 /* 6013 * If the 2MB page mapping belongs to the direct map 6014 * region of the kernel's address space, then the page 6015 * allocation request specifies the highest possible 6016 * priority (VM_ALLOC_INTERRUPT). Otherwise, the 6017 * priority is normal. 6018 */ 6019 mpte = pmap_alloc_pt_page(pmap, pmap_pde_pindex(va), 6020 (in_kernel ? VM_ALLOC_INTERRUPT : 0) | 6021 VM_ALLOC_WIRED); 6022 6023 /* 6024 * If the allocation of the new page table page fails, 6025 * invalidate the 2MB page mapping and return "failure". 6026 */ 6027 if (mpte == NULL) { 6028 pmap_demote_pde_abort(pmap, va, pde, oldpde, 6029 lockp); 6030 return (false); 6031 } 6032 6033 if (!in_kernel) 6034 mpte->ref_count = NPTEPG; 6035 } 6036 } 6037 mptepa = VM_PAGE_TO_PHYS(mpte); 6038 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa); 6039 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 6040 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 6041 ("pmap_demote_pde: oldpde is missing PG_M")); 6042 newpte = oldpde & ~PG_PS; 6043 newpte = pmap_swap_pat(pmap, newpte); 6044 6045 /* 6046 * If the PTP is not leftover from an earlier promotion or it does not 6047 * have PG_A set in every PTE, then fill it. The new PTEs will all 6048 * have PG_A set, unless this is a wired mapping with PG_A clear. 6049 */ 6050 if (!vm_page_all_valid(mpte)) 6051 pmap_fill_ptp(firstpte, newpte); 6052 6053 pmap_demote_pde_check(firstpte, newpte); 6054 6055 /* 6056 * If the mapping has changed attributes, update the PTEs. 6057 */ 6058 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 6059 pmap_fill_ptp(firstpte, newpte); 6060 6061 /* 6062 * The spare PV entries must be reserved prior to demoting the 6063 * mapping, that is, prior to changing the PDE. Otherwise, the state 6064 * of the PDE and the PV lists will be inconsistent, which can result 6065 * in reclaim_pv_chunk() attempting to remove a PV entry from the 6066 * wrong PV list and pmap_pv_demote_pde() failing to find the expected 6067 * PV entry for the 2MB page mapping that is being demoted. 6068 */ 6069 if ((oldpde & PG_MANAGED) != 0) 6070 reserve_pv_entries(pmap, NPTEPG - 1, lockp); 6071 6072 /* 6073 * Demote the mapping. This pmap is locked. The old PDE has 6074 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 6075 * set. Thus, there is no danger of a race with another 6076 * processor changing the setting of PG_A and/or PG_M between 6077 * the read above and the store below. 6078 */ 6079 if (workaround_erratum383) 6080 pmap_update_pde(pmap, va, pde, newpde); 6081 else 6082 pde_store(pde, newpde); 6083 6084 /* 6085 * Invalidate a stale recursive mapping of the page table page. 6086 */ 6087 if (in_kernel) 6088 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 6089 6090 /* 6091 * Demote the PV entry. 6092 */ 6093 if ((oldpde & PG_MANAGED) != 0) 6094 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp); 6095 6096 counter_u64_add(pmap_pde_demotions, 1); 6097 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p", 6098 va, pmap); 6099 return (true); 6100 } 6101 6102 /* 6103 * pmap_remove_kernel_pde: Remove a kernel superpage mapping. 6104 */ 6105 static void 6106 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 6107 { 6108 pd_entry_t newpde; 6109 vm_paddr_t mptepa; 6110 vm_page_t mpte; 6111 6112 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap)); 6113 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6114 mpte = pmap_remove_pt_page(pmap, va); 6115 KASSERT(mpte != NULL, ("pmap_remove_kernel_pde: missing pt page")); 6116 6117 mptepa = VM_PAGE_TO_PHYS(mpte); 6118 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V; 6119 6120 /* 6121 * If this page table page was unmapped by a promotion, then it 6122 * contains valid mappings. Zero it to invalidate those mappings. 6123 */ 6124 if (vm_page_any_valid(mpte)) 6125 pagezero((void *)PHYS_TO_DMAP(mptepa)); 6126 6127 /* 6128 * Demote the mapping. 6129 */ 6130 if (workaround_erratum383) 6131 pmap_update_pde(pmap, va, pde, newpde); 6132 else 6133 pde_store(pde, newpde); 6134 6135 /* 6136 * Invalidate a stale recursive mapping of the page table page. 6137 */ 6138 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 6139 } 6140 6141 /* 6142 * pmap_remove_pde: do the things to unmap a superpage in a process 6143 */ 6144 static int 6145 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, bool demote_kpde, 6146 struct spglist *free, struct rwlock **lockp) 6147 { 6148 struct md_page *pvh; 6149 pd_entry_t oldpde; 6150 vm_offset_t eva, va; 6151 vm_page_t m, mpte; 6152 pt_entry_t PG_G, PG_A, PG_M, PG_RW; 6153 6154 PG_G = pmap_global_bit(pmap); 6155 PG_A = pmap_accessed_bit(pmap); 6156 PG_M = pmap_modified_bit(pmap); 6157 PG_RW = pmap_rw_bit(pmap); 6158 6159 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6160 KASSERT((sva & PDRMASK) == 0, 6161 ("pmap_remove_pde: sva is not 2mpage aligned")); 6162 oldpde = pte_load_clear(pdq); 6163 if (oldpde & PG_W) 6164 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 6165 if ((oldpde & PG_G) != 0) 6166 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde); 6167 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE); 6168 if (oldpde & PG_MANAGED) { 6169 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME); 6170 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 6171 pmap_pvh_free(pvh, pmap, sva); 6172 eva = sva + NBPDR; 6173 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 6174 va < eva; va += PAGE_SIZE, m++) { 6175 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 6176 vm_page_dirty(m); 6177 if (oldpde & PG_A) 6178 vm_page_aflag_set(m, PGA_REFERENCED); 6179 if (TAILQ_EMPTY(&m->md.pv_list) && 6180 TAILQ_EMPTY(&pvh->pv_list)) 6181 vm_page_aflag_clear(m, PGA_WRITEABLE); 6182 pmap_delayed_invl_page(m); 6183 } 6184 } 6185 if (pmap != kernel_pmap) { 6186 mpte = pmap_remove_pt_page(pmap, sva); 6187 if (mpte != NULL) { 6188 KASSERT(vm_page_any_valid(mpte), 6189 ("pmap_remove_pde: pte page not promoted")); 6190 pmap_pt_page_count_adj(pmap, -1); 6191 KASSERT(mpte->ref_count == NPTEPG, 6192 ("pmap_remove_pde: pte page ref count error")); 6193 mpte->ref_count = 0; 6194 pmap_add_delayed_free_list(mpte, free, false); 6195 } 6196 } else if (demote_kpde) { 6197 pmap_remove_kernel_pde(pmap, pdq, sva); 6198 } else { 6199 mpte = vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(sva)); 6200 if (vm_page_any_valid(mpte)) { 6201 mpte->valid = 0; 6202 pmap_zero_page(mpte); 6203 } 6204 } 6205 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free)); 6206 } 6207 6208 /* 6209 * pmap_remove_pte: do the things to unmap a page in a process 6210 */ 6211 static int 6212 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 6213 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp) 6214 { 6215 struct md_page *pvh; 6216 pt_entry_t oldpte, PG_A, PG_M, PG_RW; 6217 vm_page_t m; 6218 6219 PG_A = pmap_accessed_bit(pmap); 6220 PG_M = pmap_modified_bit(pmap); 6221 PG_RW = pmap_rw_bit(pmap); 6222 6223 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6224 oldpte = pte_load_clear(ptq); 6225 if (oldpte & PG_W) 6226 pmap->pm_stats.wired_count -= 1; 6227 pmap_resident_count_adj(pmap, -1); 6228 if (oldpte & PG_MANAGED) { 6229 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 6230 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 6231 vm_page_dirty(m); 6232 if (oldpte & PG_A) 6233 vm_page_aflag_set(m, PGA_REFERENCED); 6234 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 6235 pmap_pvh_free(&m->md, pmap, va); 6236 if (TAILQ_EMPTY(&m->md.pv_list) && 6237 (m->flags & PG_FICTITIOUS) == 0) { 6238 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 6239 if (TAILQ_EMPTY(&pvh->pv_list)) 6240 vm_page_aflag_clear(m, PGA_WRITEABLE); 6241 } 6242 pmap_delayed_invl_page(m); 6243 } 6244 return (pmap_unuse_pt(pmap, va, ptepde, free)); 6245 } 6246 6247 /* 6248 * Remove a single page from a process address space 6249 */ 6250 static void 6251 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 6252 struct spglist *free) 6253 { 6254 struct rwlock *lock; 6255 pt_entry_t *pte, PG_V; 6256 6257 PG_V = pmap_valid_bit(pmap); 6258 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6259 if ((*pde & PG_V) == 0) 6260 return; 6261 pte = pmap_pde_to_pte(pde, va); 6262 if ((*pte & PG_V) == 0) 6263 return; 6264 lock = NULL; 6265 pmap_remove_pte(pmap, pte, va, *pde, free, &lock); 6266 if (lock != NULL) 6267 rw_wunlock(lock); 6268 pmap_invalidate_page(pmap, va); 6269 } 6270 6271 /* 6272 * Removes the specified range of addresses from the page table page. 6273 */ 6274 static bool 6275 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 6276 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp) 6277 { 6278 pt_entry_t PG_G, *pte; 6279 vm_offset_t va; 6280 bool anyvalid; 6281 6282 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6283 PG_G = pmap_global_bit(pmap); 6284 anyvalid = false; 6285 va = eva; 6286 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++, 6287 sva += PAGE_SIZE) { 6288 if (*pte == 0) { 6289 if (va != eva) { 6290 pmap_invalidate_range(pmap, va, sva); 6291 va = eva; 6292 } 6293 continue; 6294 } 6295 if ((*pte & PG_G) == 0) 6296 anyvalid = true; 6297 else if (va == eva) 6298 va = sva; 6299 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) { 6300 sva += PAGE_SIZE; 6301 break; 6302 } 6303 } 6304 if (va != eva) 6305 pmap_invalidate_range(pmap, va, sva); 6306 return (anyvalid); 6307 } 6308 6309 static void 6310 pmap_remove1(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, bool map_delete) 6311 { 6312 struct rwlock *lock; 6313 vm_page_t mt; 6314 vm_offset_t va_next; 6315 pml5_entry_t *pml5e; 6316 pml4_entry_t *pml4e; 6317 pdp_entry_t *pdpe; 6318 pd_entry_t ptpaddr, *pde; 6319 pt_entry_t PG_G, PG_V; 6320 struct spglist free; 6321 int anyvalid; 6322 6323 PG_G = pmap_global_bit(pmap); 6324 PG_V = pmap_valid_bit(pmap); 6325 6326 /* 6327 * If there are no resident pages besides the top level page 6328 * table page(s), there is nothing to do. Kernel pmap always 6329 * accounts whole preloaded area as resident, which makes its 6330 * resident count > 2. 6331 * Perform an unsynchronized read. This is, however, safe. 6332 */ 6333 if (pmap->pm_stats.resident_count <= 1 + (pmap->pm_pmltopu != NULL ? 6334 1 : 0)) 6335 return; 6336 6337 anyvalid = 0; 6338 SLIST_INIT(&free); 6339 6340 pmap_delayed_invl_start(); 6341 PMAP_LOCK(pmap); 6342 if (map_delete) 6343 pmap_pkru_on_remove(pmap, sva, eva); 6344 6345 /* 6346 * special handling of removing one page. a very 6347 * common operation and easy to short circuit some 6348 * code. 6349 */ 6350 if (sva + PAGE_SIZE == eva) { 6351 pde = pmap_pde(pmap, sva); 6352 if (pde && (*pde & PG_PS) == 0) { 6353 pmap_remove_page(pmap, sva, pde, &free); 6354 goto out; 6355 } 6356 } 6357 6358 lock = NULL; 6359 for (; sva < eva; sva = va_next) { 6360 if (pmap->pm_stats.resident_count == 0) 6361 break; 6362 6363 if (pmap_is_la57(pmap)) { 6364 pml5e = pmap_pml5e(pmap, sva); 6365 if ((*pml5e & PG_V) == 0) { 6366 va_next = (sva + NBPML5) & ~PML5MASK; 6367 if (va_next < sva) 6368 va_next = eva; 6369 continue; 6370 } 6371 pml4e = pmap_pml5e_to_pml4e(pml5e, sva); 6372 } else { 6373 pml4e = pmap_pml4e(pmap, sva); 6374 } 6375 if ((*pml4e & PG_V) == 0) { 6376 va_next = (sva + NBPML4) & ~PML4MASK; 6377 if (va_next < sva) 6378 va_next = eva; 6379 continue; 6380 } 6381 6382 va_next = (sva + NBPDP) & ~PDPMASK; 6383 if (va_next < sva) 6384 va_next = eva; 6385 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 6386 if ((*pdpe & PG_V) == 0) 6387 continue; 6388 if ((*pdpe & PG_PS) != 0) { 6389 KASSERT(va_next <= eva, 6390 ("partial update of non-transparent 1G mapping " 6391 "pdpe %#lx sva %#lx eva %#lx va_next %#lx", 6392 *pdpe, sva, eva, va_next)); 6393 MPASS(pmap != kernel_pmap); /* XXXKIB */ 6394 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0); 6395 anyvalid = 1; 6396 *pdpe = 0; 6397 pmap_resident_count_adj(pmap, -NBPDP / PAGE_SIZE); 6398 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME); 6399 pmap_unwire_ptp(pmap, sva, mt, &free); 6400 continue; 6401 } 6402 6403 /* 6404 * Calculate index for next page table. 6405 */ 6406 va_next = (sva + NBPDR) & ~PDRMASK; 6407 if (va_next < sva) 6408 va_next = eva; 6409 6410 pde = pmap_pdpe_to_pde(pdpe, sva); 6411 ptpaddr = *pde; 6412 6413 /* 6414 * Weed out invalid mappings. 6415 */ 6416 if (ptpaddr == 0) 6417 continue; 6418 6419 /* 6420 * Check for large page. 6421 */ 6422 if ((ptpaddr & PG_PS) != 0) { 6423 /* 6424 * Are we removing the entire large page? If not, 6425 * demote the mapping and fall through. 6426 */ 6427 if (sva + NBPDR == va_next && eva >= va_next) { 6428 /* 6429 * The TLB entry for a PG_G mapping is 6430 * invalidated by pmap_remove_pde(). 6431 */ 6432 if ((ptpaddr & PG_G) == 0) 6433 anyvalid = 1; 6434 pmap_remove_pde(pmap, pde, sva, true, &free, 6435 &lock); 6436 continue; 6437 } else if (!pmap_demote_pde_locked(pmap, pde, sva, 6438 &lock)) { 6439 /* The large page mapping was destroyed. */ 6440 continue; 6441 } else 6442 ptpaddr = *pde; 6443 } 6444 6445 /* 6446 * Limit our scan to either the end of the va represented 6447 * by the current page table page, or to the end of the 6448 * range being removed. 6449 */ 6450 if (va_next > eva) 6451 va_next = eva; 6452 6453 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock)) 6454 anyvalid = 1; 6455 } 6456 if (lock != NULL) 6457 rw_wunlock(lock); 6458 out: 6459 if (anyvalid) 6460 pmap_invalidate_all(pmap); 6461 PMAP_UNLOCK(pmap); 6462 pmap_delayed_invl_finish(); 6463 vm_page_free_pages_toq(&free, true); 6464 } 6465 6466 /* 6467 * Remove the given range of addresses from the specified map. 6468 * 6469 * It is assumed that the start and end are properly 6470 * rounded to the page size. 6471 */ 6472 void 6473 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 6474 { 6475 pmap_remove1(pmap, sva, eva, false); 6476 } 6477 6478 /* 6479 * Remove the given range of addresses as part of a logical unmap 6480 * operation. This has the effect of calling pmap_remove(), but 6481 * also clears any metadata that should persist for the lifetime 6482 * of a logical mapping. 6483 */ 6484 void 6485 pmap_map_delete(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 6486 { 6487 pmap_remove1(pmap, sva, eva, true); 6488 } 6489 6490 /* 6491 * Routine: pmap_remove_all 6492 * Function: 6493 * Removes this physical page from 6494 * all physical maps in which it resides. 6495 * Reflects back modify bits to the pager. 6496 * 6497 * Notes: 6498 * Original versions of this routine were very 6499 * inefficient because they iteratively called 6500 * pmap_remove (slow...) 6501 */ 6502 6503 void 6504 pmap_remove_all(vm_page_t m) 6505 { 6506 struct md_page *pvh; 6507 pv_entry_t pv; 6508 pmap_t pmap; 6509 struct rwlock *lock; 6510 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW; 6511 pd_entry_t *pde; 6512 vm_offset_t va; 6513 struct spglist free; 6514 int pvh_gen, md_gen; 6515 6516 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6517 ("pmap_remove_all: page %p is not managed", m)); 6518 SLIST_INIT(&free); 6519 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 6520 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 6521 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 6522 rw_wlock(lock); 6523 retry: 6524 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 6525 pmap = PV_PMAP(pv); 6526 if (!PMAP_TRYLOCK(pmap)) { 6527 pvh_gen = pvh->pv_gen; 6528 rw_wunlock(lock); 6529 PMAP_LOCK(pmap); 6530 rw_wlock(lock); 6531 if (pvh_gen != pvh->pv_gen) { 6532 PMAP_UNLOCK(pmap); 6533 goto retry; 6534 } 6535 } 6536 va = pv->pv_va; 6537 pde = pmap_pde(pmap, va); 6538 (void)pmap_demote_pde_locked(pmap, pde, va, &lock); 6539 PMAP_UNLOCK(pmap); 6540 } 6541 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 6542 pmap = PV_PMAP(pv); 6543 if (!PMAP_TRYLOCK(pmap)) { 6544 pvh_gen = pvh->pv_gen; 6545 md_gen = m->md.pv_gen; 6546 rw_wunlock(lock); 6547 PMAP_LOCK(pmap); 6548 rw_wlock(lock); 6549 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 6550 PMAP_UNLOCK(pmap); 6551 goto retry; 6552 } 6553 } 6554 PG_A = pmap_accessed_bit(pmap); 6555 PG_M = pmap_modified_bit(pmap); 6556 PG_RW = pmap_rw_bit(pmap); 6557 pmap_resident_count_adj(pmap, -1); 6558 pde = pmap_pde(pmap, pv->pv_va); 6559 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 6560 " a 2mpage in page %p's pv list", m)); 6561 pte = pmap_pde_to_pte(pde, pv->pv_va); 6562 tpte = pte_load_clear(pte); 6563 if (tpte & PG_W) 6564 pmap->pm_stats.wired_count--; 6565 if (tpte & PG_A) 6566 vm_page_aflag_set(m, PGA_REFERENCED); 6567 6568 /* 6569 * Update the vm_page_t clean and reference bits. 6570 */ 6571 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 6572 vm_page_dirty(m); 6573 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free); 6574 pmap_invalidate_page(pmap, pv->pv_va); 6575 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 6576 m->md.pv_gen++; 6577 free_pv_entry(pmap, pv); 6578 PMAP_UNLOCK(pmap); 6579 } 6580 vm_page_aflag_clear(m, PGA_WRITEABLE); 6581 rw_wunlock(lock); 6582 pmap_delayed_invl_wait(m); 6583 vm_page_free_pages_toq(&free, true); 6584 } 6585 6586 /* 6587 * pmap_protect_pde: do the things to protect a 2mpage in a process 6588 */ 6589 static bool 6590 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 6591 { 6592 pd_entry_t newpde, oldpde; 6593 vm_page_t m, mt; 6594 bool anychanged; 6595 pt_entry_t PG_G, PG_M, PG_RW; 6596 6597 PG_G = pmap_global_bit(pmap); 6598 PG_M = pmap_modified_bit(pmap); 6599 PG_RW = pmap_rw_bit(pmap); 6600 6601 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6602 KASSERT((sva & PDRMASK) == 0, 6603 ("pmap_protect_pde: sva is not 2mpage aligned")); 6604 anychanged = false; 6605 retry: 6606 oldpde = newpde = *pde; 6607 if ((prot & VM_PROT_WRITE) == 0) { 6608 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) == 6609 (PG_MANAGED | PG_M | PG_RW)) { 6610 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 6611 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 6612 vm_page_dirty(mt); 6613 } 6614 newpde &= ~(PG_RW | PG_M); 6615 } 6616 if ((prot & VM_PROT_EXECUTE) == 0) 6617 newpde |= pg_nx; 6618 if (newpde != oldpde) { 6619 /* 6620 * As an optimization to future operations on this PDE, clear 6621 * PG_PROMOTED. The impending invalidation will remove any 6622 * lingering 4KB page mappings from the TLB. 6623 */ 6624 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED)) 6625 goto retry; 6626 if ((oldpde & PG_G) != 0) 6627 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde); 6628 else 6629 anychanged = true; 6630 } 6631 return (anychanged); 6632 } 6633 6634 /* 6635 * Set the physical protection on the 6636 * specified range of this map as requested. 6637 */ 6638 void 6639 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 6640 { 6641 vm_page_t m; 6642 vm_offset_t va_next; 6643 pml4_entry_t *pml4e; 6644 pdp_entry_t *pdpe; 6645 pd_entry_t ptpaddr, *pde; 6646 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V; 6647 pt_entry_t obits, pbits; 6648 bool anychanged; 6649 6650 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 6651 if (prot == VM_PROT_NONE) { 6652 pmap_remove(pmap, sva, eva); 6653 return; 6654 } 6655 6656 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 6657 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 6658 return; 6659 6660 PG_G = pmap_global_bit(pmap); 6661 PG_M = pmap_modified_bit(pmap); 6662 PG_V = pmap_valid_bit(pmap); 6663 PG_RW = pmap_rw_bit(pmap); 6664 anychanged = false; 6665 6666 /* 6667 * Although this function delays and batches the invalidation 6668 * of stale TLB entries, it does not need to call 6669 * pmap_delayed_invl_start() and 6670 * pmap_delayed_invl_finish(), because it does not 6671 * ordinarily destroy mappings. Stale TLB entries from 6672 * protection-only changes need only be invalidated before the 6673 * pmap lock is released, because protection-only changes do 6674 * not destroy PV entries. Even operations that iterate over 6675 * a physical page's PV list of mappings, like 6676 * pmap_remove_write(), acquire the pmap lock for each 6677 * mapping. Consequently, for protection-only changes, the 6678 * pmap lock suffices to synchronize both page table and TLB 6679 * updates. 6680 * 6681 * This function only destroys a mapping if pmap_demote_pde() 6682 * fails. In that case, stale TLB entries are immediately 6683 * invalidated. 6684 */ 6685 6686 PMAP_LOCK(pmap); 6687 for (; sva < eva; sva = va_next) { 6688 pml4e = pmap_pml4e(pmap, sva); 6689 if (pml4e == NULL || (*pml4e & PG_V) == 0) { 6690 va_next = (sva + NBPML4) & ~PML4MASK; 6691 if (va_next < sva) 6692 va_next = eva; 6693 continue; 6694 } 6695 6696 va_next = (sva + NBPDP) & ~PDPMASK; 6697 if (va_next < sva) 6698 va_next = eva; 6699 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 6700 if ((*pdpe & PG_V) == 0) 6701 continue; 6702 if ((*pdpe & PG_PS) != 0) { 6703 KASSERT(va_next <= eva, 6704 ("partial update of non-transparent 1G mapping " 6705 "pdpe %#lx sva %#lx eva %#lx va_next %#lx", 6706 *pdpe, sva, eva, va_next)); 6707 retry_pdpe: 6708 obits = pbits = *pdpe; 6709 MPASS((pbits & (PG_MANAGED | PG_G)) == 0); 6710 MPASS(pmap != kernel_pmap); /* XXXKIB */ 6711 if ((prot & VM_PROT_WRITE) == 0) 6712 pbits &= ~(PG_RW | PG_M); 6713 if ((prot & VM_PROT_EXECUTE) == 0) 6714 pbits |= pg_nx; 6715 6716 if (pbits != obits) { 6717 if (!atomic_cmpset_long(pdpe, obits, pbits)) 6718 /* PG_PS cannot be cleared under us, */ 6719 goto retry_pdpe; 6720 anychanged = true; 6721 } 6722 continue; 6723 } 6724 6725 va_next = (sva + NBPDR) & ~PDRMASK; 6726 if (va_next < sva) 6727 va_next = eva; 6728 6729 pde = pmap_pdpe_to_pde(pdpe, sva); 6730 ptpaddr = *pde; 6731 6732 /* 6733 * Weed out invalid mappings. 6734 */ 6735 if (ptpaddr == 0) 6736 continue; 6737 6738 /* 6739 * Check for large page. 6740 */ 6741 if ((ptpaddr & PG_PS) != 0) { 6742 /* 6743 * Are we protecting the entire large page? 6744 */ 6745 if (sva + NBPDR == va_next && eva >= va_next) { 6746 /* 6747 * The TLB entry for a PG_G mapping is 6748 * invalidated by pmap_protect_pde(). 6749 */ 6750 if (pmap_protect_pde(pmap, pde, sva, prot)) 6751 anychanged = true; 6752 continue; 6753 } 6754 6755 /* 6756 * Does the large page mapping need to change? If so, 6757 * demote it and fall through. 6758 */ 6759 pbits = ptpaddr; 6760 if ((prot & VM_PROT_WRITE) == 0) 6761 pbits &= ~(PG_RW | PG_M); 6762 if ((prot & VM_PROT_EXECUTE) == 0) 6763 pbits |= pg_nx; 6764 if (ptpaddr == pbits || !pmap_demote_pde(pmap, pde, 6765 sva)) { 6766 /* 6767 * Either the large page mapping doesn't need 6768 * to change, or it was destroyed during 6769 * demotion. 6770 */ 6771 continue; 6772 } 6773 } 6774 6775 if (va_next > eva) 6776 va_next = eva; 6777 6778 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 6779 sva += PAGE_SIZE) { 6780 retry: 6781 obits = pbits = *pte; 6782 if ((pbits & PG_V) == 0) 6783 continue; 6784 6785 if ((prot & VM_PROT_WRITE) == 0) { 6786 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 6787 (PG_MANAGED | PG_M | PG_RW)) { 6788 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 6789 vm_page_dirty(m); 6790 } 6791 pbits &= ~(PG_RW | PG_M); 6792 } 6793 if ((prot & VM_PROT_EXECUTE) == 0) 6794 pbits |= pg_nx; 6795 6796 if (pbits != obits) { 6797 if (!atomic_cmpset_long(pte, obits, pbits)) 6798 goto retry; 6799 if (obits & PG_G) 6800 pmap_invalidate_page(pmap, sva); 6801 else 6802 anychanged = true; 6803 } 6804 } 6805 } 6806 if (anychanged) 6807 pmap_invalidate_all(pmap); 6808 PMAP_UNLOCK(pmap); 6809 } 6810 6811 static bool 6812 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde) 6813 { 6814 6815 if (pmap->pm_type != PT_EPT) 6816 return (false); 6817 return ((pde & EPT_PG_EXECUTE) != 0); 6818 } 6819 6820 #if VM_NRESERVLEVEL > 0 6821 /* 6822 * Tries to promote the 512, contiguous 4KB page mappings that are within a 6823 * single page table page (PTP) to a single 2MB page mapping. For promotion 6824 * to occur, two conditions must be met: (1) the 4KB page mappings must map 6825 * aligned, contiguous physical memory and (2) the 4KB page mappings must have 6826 * identical characteristics. 6827 */ 6828 static bool 6829 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, vm_page_t mpte, 6830 struct rwlock **lockp) 6831 { 6832 pd_entry_t newpde; 6833 pt_entry_t *firstpte, oldpte, pa, *pte; 6834 pt_entry_t allpte_PG_A, PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V; 6835 int PG_PTE_CACHE; 6836 6837 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6838 if (!pmap_ps_enabled(pmap)) 6839 return (false); 6840 6841 PG_A = pmap_accessed_bit(pmap); 6842 PG_G = pmap_global_bit(pmap); 6843 PG_M = pmap_modified_bit(pmap); 6844 PG_V = pmap_valid_bit(pmap); 6845 PG_RW = pmap_rw_bit(pmap); 6846 PG_PKU_MASK = pmap_pku_mask_bit(pmap); 6847 PG_PTE_CACHE = pmap_cache_mask(pmap, false); 6848 6849 /* 6850 * Examine the first PTE in the specified PTP. Abort if this PTE is 6851 * ineligible for promotion due to hardware errata, invalid, or does 6852 * not map the first 4KB physical page within a 2MB page. 6853 */ 6854 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME); 6855 newpde = *firstpte; 6856 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap, newpde))) 6857 return (false); 6858 if ((newpde & ((PG_FRAME & PDRMASK) | PG_V)) != PG_V) { 6859 counter_u64_add(pmap_pde_p_failures, 1); 6860 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx" 6861 " in pmap %p", va, pmap); 6862 return (false); 6863 } 6864 6865 /* 6866 * Both here and in the below "for" loop, to allow for repromotion 6867 * after MADV_FREE, conditionally write protect a clean PTE before 6868 * possibly aborting the promotion due to other PTE attributes. Why? 6869 * Suppose that MADV_FREE is applied to a part of a superpage, the 6870 * address range [S, E). pmap_advise() will demote the superpage 6871 * mapping, destroy the 4KB page mapping at the end of [S, E), and 6872 * clear PG_M and PG_A in the PTEs for the rest of [S, E). Later, 6873 * imagine that the memory in [S, E) is recycled, but the last 4KB 6874 * page in [S, E) is not the last to be rewritten, or simply accessed. 6875 * In other words, there is still a 4KB page in [S, E), call it P, 6876 * that is writeable but PG_M and PG_A are clear in P's PTE. Unless 6877 * we write protect P before aborting the promotion, if and when P is 6878 * finally rewritten, there won't be a page fault to trigger 6879 * repromotion. 6880 */ 6881 setpde: 6882 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 6883 /* 6884 * When PG_M is already clear, PG_RW can be cleared without 6885 * a TLB invalidation. 6886 */ 6887 if (!atomic_fcmpset_long(firstpte, &newpde, newpde & ~PG_RW)) 6888 goto setpde; 6889 newpde &= ~PG_RW; 6890 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx" 6891 " in pmap %p", va & ~PDRMASK, pmap); 6892 } 6893 6894 /* 6895 * Examine each of the other PTEs in the specified PTP. Abort if this 6896 * PTE maps an unexpected 4KB physical page or does not have identical 6897 * characteristics to the first PTE. 6898 */ 6899 allpte_PG_A = newpde & PG_A; 6900 pa = (newpde & (PG_PS_FRAME | PG_V)) + NBPDR - PAGE_SIZE; 6901 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 6902 oldpte = *pte; 6903 if ((oldpte & (PG_FRAME | PG_V)) != pa) { 6904 counter_u64_add(pmap_pde_p_failures, 1); 6905 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx" 6906 " in pmap %p", va, pmap); 6907 return (false); 6908 } 6909 setpte: 6910 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 6911 /* 6912 * When PG_M is already clear, PG_RW can be cleared 6913 * without a TLB invalidation. 6914 */ 6915 if (!atomic_fcmpset_long(pte, &oldpte, oldpte & ~PG_RW)) 6916 goto setpte; 6917 oldpte &= ~PG_RW; 6918 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx" 6919 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) | 6920 (va & ~PDRMASK), pmap); 6921 } 6922 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 6923 counter_u64_add(pmap_pde_p_failures, 1); 6924 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx" 6925 " in pmap %p", va, pmap); 6926 return (false); 6927 } 6928 allpte_PG_A &= oldpte; 6929 pa -= PAGE_SIZE; 6930 } 6931 6932 /* 6933 * Unless all PTEs have PG_A set, clear it from the superpage mapping, 6934 * so that promotions triggered by speculative mappings, such as 6935 * pmap_enter_quick(), don't automatically mark the underlying pages 6936 * as referenced. 6937 */ 6938 newpde &= ~PG_A | allpte_PG_A; 6939 6940 /* 6941 * EPT PTEs with PG_M set and PG_A clear are not supported by early 6942 * MMUs supporting EPT. 6943 */ 6944 KASSERT((newpde & PG_A) != 0 || safe_to_clear_referenced(pmap, newpde), 6945 ("unsupported EPT PTE")); 6946 6947 /* 6948 * Save the PTP in its current state until the PDE mapping the 6949 * superpage is demoted by pmap_demote_pde() or destroyed by 6950 * pmap_remove_pde(). If PG_A is not set in every PTE, then request 6951 * that the PTP be refilled on demotion. 6952 */ 6953 if (mpte == NULL) 6954 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 6955 KASSERT(mpte >= vm_page_array && 6956 mpte < &vm_page_array[vm_page_array_size], 6957 ("pmap_promote_pde: page table page is out of range")); 6958 KASSERT(mpte->pindex == pmap_pde_pindex(va), 6959 ("pmap_promote_pde: page table page's pindex is wrong " 6960 "mpte %p pidx %#lx va %#lx va pde pidx %#lx", 6961 mpte, mpte->pindex, va, pmap_pde_pindex(va))); 6962 if (pmap_insert_pt_page(pmap, mpte, true, allpte_PG_A != 0)) { 6963 counter_u64_add(pmap_pde_p_failures, 1); 6964 CTR2(KTR_PMAP, 6965 "pmap_promote_pde: failure for va %#lx in pmap %p", va, 6966 pmap); 6967 return (false); 6968 } 6969 6970 /* 6971 * Promote the pv entries. 6972 */ 6973 if ((newpde & PG_MANAGED) != 0) 6974 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp); 6975 6976 /* 6977 * Propagate the PAT index to its proper position. 6978 */ 6979 newpde = pmap_swap_pat(pmap, newpde); 6980 6981 /* 6982 * Map the superpage. 6983 */ 6984 if (workaround_erratum383) 6985 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 6986 else 6987 pde_store(pde, PG_PROMOTED | PG_PS | newpde); 6988 6989 counter_u64_add(pmap_pde_promotions, 1); 6990 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx" 6991 " in pmap %p", va, pmap); 6992 return (true); 6993 } 6994 #endif /* VM_NRESERVLEVEL > 0 */ 6995 6996 static int 6997 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags, 6998 int psind) 6999 { 7000 vm_page_t mp; 7001 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V; 7002 7003 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 7004 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0, 7005 ("psind %d unexpected", psind)); 7006 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0, 7007 ("unaligned phys address %#lx newpte %#lx psind %d", 7008 newpte & PG_FRAME, newpte, psind)); 7009 KASSERT((va & (pagesizes[psind] - 1)) == 0, 7010 ("unaligned va %#lx psind %d", va, psind)); 7011 KASSERT(va < VM_MAXUSER_ADDRESS, 7012 ("kernel mode non-transparent superpage")); /* XXXKIB */ 7013 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS, 7014 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */ 7015 7016 PG_V = pmap_valid_bit(pmap); 7017 7018 restart: 7019 pten = newpte; 7020 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind], &pten)) 7021 return (KERN_PROTECTION_FAILURE); 7022 7023 if (psind == 2) { /* 1G */ 7024 pml4e = pmap_pml4e(pmap, va); 7025 if (pml4e == NULL || (*pml4e & PG_V) == 0) { 7026 mp = pmap_allocpte_alloc(pmap, pmap_pml4e_pindex(va), 7027 NULL, va); 7028 if (mp == NULL) 7029 goto allocf; 7030 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp)); 7031 pdpe = &pdpe[pmap_pdpe_index(va)]; 7032 origpte = *pdpe; 7033 MPASS(origpte == 0); 7034 } else { 7035 pdpe = pmap_pml4e_to_pdpe(pml4e, va); 7036 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va)); 7037 origpte = *pdpe; 7038 if ((origpte & PG_V) == 0) { 7039 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME); 7040 mp->ref_count++; 7041 } 7042 } 7043 *pdpe = pten; 7044 } else /* (psind == 1) */ { /* 2M */ 7045 pde = pmap_pde(pmap, va); 7046 if (pde == NULL) { 7047 mp = pmap_allocpte_alloc(pmap, pmap_pdpe_pindex(va), 7048 NULL, va); 7049 if (mp == NULL) 7050 goto allocf; 7051 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp)); 7052 pde = &pde[pmap_pde_index(va)]; 7053 origpte = *pde; 7054 MPASS(origpte == 0); 7055 } else { 7056 origpte = *pde; 7057 if ((origpte & PG_V) == 0) { 7058 pdpe = pmap_pdpe(pmap, va); 7059 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0); 7060 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME); 7061 mp->ref_count++; 7062 } 7063 } 7064 *pde = pten; 7065 } 7066 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 && 7067 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)), 7068 ("va %#lx changing %s phys page origpte %#lx pten %#lx", 7069 va, psind == 2 ? "1G" : "2M", origpte, pten)); 7070 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0) 7071 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE; 7072 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0) 7073 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE; 7074 if ((origpte & PG_V) == 0) 7075 pmap_resident_count_adj(pmap, pagesizes[psind] / PAGE_SIZE); 7076 7077 return (KERN_SUCCESS); 7078 7079 allocf: 7080 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 7081 return (KERN_RESOURCE_SHORTAGE); 7082 PMAP_UNLOCK(pmap); 7083 vm_wait(NULL); 7084 PMAP_LOCK(pmap); 7085 goto restart; 7086 } 7087 7088 /* 7089 * Insert the given physical page (p) at 7090 * the specified virtual address (v) in the 7091 * target physical map with the protection requested. 7092 * 7093 * If specified, the page will be wired down, meaning 7094 * that the related pte can not be reclaimed. 7095 * 7096 * NB: This is the only routine which MAY NOT lazy-evaluate 7097 * or lose information. That is, this routine must actually 7098 * insert this page into the given map NOW. 7099 * 7100 * When destroying both a page table and PV entry, this function 7101 * performs the TLB invalidation before releasing the PV list 7102 * lock, so we do not need pmap_delayed_invl_page() calls here. 7103 */ 7104 int 7105 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 7106 u_int flags, int8_t psind) 7107 { 7108 struct rwlock *lock; 7109 pd_entry_t *pde; 7110 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V; 7111 pt_entry_t newpte, origpte; 7112 pv_entry_t pv; 7113 vm_paddr_t opa, pa; 7114 vm_page_t mpte, om; 7115 int rv; 7116 bool nosleep; 7117 7118 PG_A = pmap_accessed_bit(pmap); 7119 PG_G = pmap_global_bit(pmap); 7120 PG_M = pmap_modified_bit(pmap); 7121 PG_V = pmap_valid_bit(pmap); 7122 PG_RW = pmap_rw_bit(pmap); 7123 7124 va = trunc_page(va); 7125 KASSERT(va <= kva_layout.km_high, ("pmap_enter: toobig")); 7126 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 7127 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)", 7128 va)); 7129 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va), 7130 ("pmap_enter: managed mapping within the clean submap")); 7131 if ((m->oflags & VPO_UNMANAGED) == 0) 7132 VM_PAGE_OBJECT_BUSY_ASSERT(m); 7133 KASSERT((flags & PMAP_ENTER_RESERVED) == 0, 7134 ("pmap_enter: flags %u has reserved bits set", flags)); 7135 pa = VM_PAGE_TO_PHYS(m); 7136 newpte = (pt_entry_t)(pa | PG_A | PG_V); 7137 if ((flags & VM_PROT_WRITE) != 0) 7138 newpte |= PG_M; 7139 if ((prot & VM_PROT_WRITE) != 0) 7140 newpte |= PG_RW; 7141 KASSERT((newpte & (PG_M | PG_RW)) != PG_M, 7142 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't")); 7143 if ((prot & VM_PROT_EXECUTE) == 0) 7144 newpte |= pg_nx; 7145 if ((flags & PMAP_ENTER_WIRED) != 0) 7146 newpte |= PG_W; 7147 if (va < VM_MAXUSER_ADDRESS) 7148 newpte |= PG_U; 7149 if (pmap == kernel_pmap) 7150 newpte |= PG_G; 7151 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0); 7152 7153 /* 7154 * Set modified bit gratuitously for writeable mappings if 7155 * the page is unmanaged. We do not want to take a fault 7156 * to do the dirty bit accounting for these mappings. 7157 */ 7158 if ((m->oflags & VPO_UNMANAGED) != 0) { 7159 if ((newpte & PG_RW) != 0) 7160 newpte |= PG_M; 7161 } else 7162 newpte |= PG_MANAGED; 7163 7164 lock = NULL; 7165 PMAP_LOCK(pmap); 7166 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) { 7167 KASSERT((m->oflags & VPO_UNMANAGED) != 0, 7168 ("managed largepage va %#lx flags %#x", va, flags)); 7169 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags, 7170 psind); 7171 goto out; 7172 } 7173 if (psind == 1) { 7174 /* Assert the required virtual and physical alignment. */ 7175 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned")); 7176 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind")); 7177 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock); 7178 goto out; 7179 } 7180 mpte = NULL; 7181 7182 /* 7183 * In the case that a page table page is not 7184 * resident, we are creating it here. 7185 */ 7186 retry: 7187 pde = pmap_pde(pmap, va); 7188 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 || 7189 pmap_demote_pde_locked(pmap, pde, va, &lock))) { 7190 pte = pmap_pde_to_pte(pde, va); 7191 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) { 7192 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 7193 mpte->ref_count++; 7194 } 7195 } else if (va < VM_MAXUSER_ADDRESS) { 7196 /* 7197 * Here if the pte page isn't mapped, or if it has been 7198 * deallocated. 7199 */ 7200 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0; 7201 mpte = pmap_allocpte_alloc(pmap, pmap_pde_pindex(va), 7202 nosleep ? NULL : &lock, va); 7203 if (mpte == NULL && nosleep) { 7204 rv = KERN_RESOURCE_SHORTAGE; 7205 goto out; 7206 } 7207 goto retry; 7208 } else 7209 panic("pmap_enter: invalid page directory va=%#lx", va); 7210 7211 origpte = *pte; 7212 pv = NULL; 7213 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) 7214 newpte |= pmap_pkru_get(pmap, va); 7215 7216 /* 7217 * Is the specified virtual address already mapped? 7218 */ 7219 if ((origpte & PG_V) != 0) { 7220 /* 7221 * Wiring change, just update stats. We don't worry about 7222 * wiring PT pages as they remain resident as long as there 7223 * are valid mappings in them. Hence, if a user page is wired, 7224 * the PT page will be also. 7225 */ 7226 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0) 7227 pmap->pm_stats.wired_count++; 7228 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0) 7229 pmap->pm_stats.wired_count--; 7230 7231 /* 7232 * Remove the extra PT page reference. 7233 */ 7234 if (mpte != NULL) { 7235 mpte->ref_count--; 7236 KASSERT(mpte->ref_count > 0, 7237 ("pmap_enter: missing reference to page table page," 7238 " va: 0x%lx", va)); 7239 } 7240 7241 /* 7242 * Has the physical page changed? 7243 */ 7244 opa = origpte & PG_FRAME; 7245 if (opa == pa) { 7246 /* 7247 * No, might be a protection or wiring change. 7248 */ 7249 if ((origpte & PG_MANAGED) != 0 && 7250 (newpte & PG_RW) != 0) 7251 vm_page_aflag_set(m, PGA_WRITEABLE); 7252 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0) 7253 goto unchanged; 7254 goto validate; 7255 } 7256 7257 /* 7258 * The physical page has changed. Temporarily invalidate 7259 * the mapping. This ensures that all threads sharing the 7260 * pmap keep a consistent view of the mapping, which is 7261 * necessary for the correct handling of COW faults. It 7262 * also permits reuse of the old mapping's PV entry, 7263 * avoiding an allocation. 7264 * 7265 * For consistency, handle unmanaged mappings the same way. 7266 */ 7267 origpte = pte_load_clear(pte); 7268 KASSERT((origpte & PG_FRAME) == opa, 7269 ("pmap_enter: unexpected pa update for %#lx", va)); 7270 if ((origpte & PG_MANAGED) != 0) { 7271 om = PHYS_TO_VM_PAGE(opa); 7272 7273 /* 7274 * The pmap lock is sufficient to synchronize with 7275 * concurrent calls to pmap_page_test_mappings() and 7276 * pmap_ts_referenced(). 7277 */ 7278 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 7279 vm_page_dirty(om); 7280 if ((origpte & PG_A) != 0) { 7281 pmap_invalidate_page(pmap, va); 7282 vm_page_aflag_set(om, PGA_REFERENCED); 7283 } 7284 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa); 7285 pv = pmap_pvh_remove(&om->md, pmap, va); 7286 KASSERT(pv != NULL, 7287 ("pmap_enter: no PV entry for %#lx", va)); 7288 if ((newpte & PG_MANAGED) == 0) 7289 free_pv_entry(pmap, pv); 7290 if ((om->a.flags & PGA_WRITEABLE) != 0 && 7291 TAILQ_EMPTY(&om->md.pv_list) && 7292 ((om->flags & PG_FICTITIOUS) != 0 || 7293 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 7294 vm_page_aflag_clear(om, PGA_WRITEABLE); 7295 } else { 7296 /* 7297 * Since this mapping is unmanaged, assume that PG_A 7298 * is set. 7299 */ 7300 pmap_invalidate_page(pmap, va); 7301 } 7302 origpte = 0; 7303 } else { 7304 /* 7305 * Increment the counters. 7306 */ 7307 if ((newpte & PG_W) != 0) 7308 pmap->pm_stats.wired_count++; 7309 pmap_resident_count_adj(pmap, 1); 7310 } 7311 7312 /* 7313 * Enter on the PV list if part of our managed memory. 7314 */ 7315 if ((newpte & PG_MANAGED) != 0) { 7316 if (pv == NULL) { 7317 pv = get_pv_entry(pmap, &lock); 7318 pv->pv_va = va; 7319 } 7320 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa); 7321 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 7322 m->md.pv_gen++; 7323 if ((newpte & PG_RW) != 0) 7324 vm_page_aflag_set(m, PGA_WRITEABLE); 7325 } 7326 7327 /* 7328 * Update the PTE. 7329 */ 7330 if ((origpte & PG_V) != 0) { 7331 validate: 7332 origpte = pte_load_store(pte, newpte); 7333 KASSERT((origpte & PG_FRAME) == pa, 7334 ("pmap_enter: unexpected pa update for %#lx", va)); 7335 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) == 7336 (PG_M | PG_RW)) { 7337 if ((origpte & PG_MANAGED) != 0) 7338 vm_page_dirty(m); 7339 7340 /* 7341 * Although the PTE may still have PG_RW set, TLB 7342 * invalidation may nonetheless be required because 7343 * the PTE no longer has PG_M set. 7344 */ 7345 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) { 7346 /* 7347 * This PTE change does not require TLB invalidation. 7348 */ 7349 goto unchanged; 7350 } 7351 if ((origpte & PG_A) != 0) 7352 pmap_invalidate_page(pmap, va); 7353 } else 7354 pte_store(pte, newpte); 7355 7356 unchanged: 7357 7358 #if VM_NRESERVLEVEL > 0 7359 /* 7360 * If both the page table page and the reservation are fully 7361 * populated, then attempt promotion. 7362 */ 7363 if ((mpte == NULL || mpte->ref_count == NPTEPG) && 7364 (m->flags & PG_FICTITIOUS) == 0 && 7365 vm_reserv_level_iffullpop(m) == 0) 7366 (void)pmap_promote_pde(pmap, pde, va, mpte, &lock); 7367 #endif 7368 7369 rv = KERN_SUCCESS; 7370 out: 7371 if (lock != NULL) 7372 rw_wunlock(lock); 7373 PMAP_UNLOCK(pmap); 7374 return (rv); 7375 } 7376 7377 /* 7378 * Tries to create a read- and/or execute-only 2MB page mapping. Returns 7379 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error 7380 * value. See pmap_enter_pde() for the possible error values when "no sleep", 7381 * "no replace", and "no reclaim" are specified. 7382 */ 7383 static int 7384 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 7385 struct rwlock **lockp) 7386 { 7387 pd_entry_t newpde; 7388 pt_entry_t PG_V; 7389 7390 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 7391 PG_V = pmap_valid_bit(pmap); 7392 newpde = VM_PAGE_TO_PHYS(m) | 7393 pmap_cache_bits(pmap, m->md.pat_mode, true) | PG_PS | PG_V; 7394 if ((m->oflags & VPO_UNMANAGED) == 0) 7395 newpde |= PG_MANAGED; 7396 if ((prot & VM_PROT_EXECUTE) == 0) 7397 newpde |= pg_nx; 7398 if (va < VM_MAXUSER_ADDRESS) 7399 newpde |= PG_U; 7400 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP | 7401 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp)); 7402 } 7403 7404 /* 7405 * Returns true if every page table entry in the specified page table page is 7406 * zero. 7407 */ 7408 static bool 7409 pmap_every_pte_zero(vm_paddr_t pa) 7410 { 7411 pt_entry_t *pt_end, *pte; 7412 7413 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned")); 7414 pte = (pt_entry_t *)PHYS_TO_DMAP(pa); 7415 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) { 7416 if (*pte != 0) 7417 return (false); 7418 } 7419 return (true); 7420 } 7421 7422 /* 7423 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if 7424 * the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE, 7425 * KERN_PROTECTION_FAILURE, or KERN_RESOURCE_SHORTAGE otherwise. Returns 7426 * KERN_FAILURE if either (1) PMAP_ENTER_NOREPLACE was specified and a 4KB 7427 * page mapping already exists within the 2MB virtual address range starting 7428 * at the specified virtual address or (2) the requested 2MB page mapping is 7429 * not supported due to hardware errata. Returns KERN_NO_SPACE if 7430 * PMAP_ENTER_NOREPLACE was specified and a 2MB page mapping already exists at 7431 * the specified virtual address. Returns KERN_PROTECTION_FAILURE if the PKRU 7432 * settings are not the same across the 2MB virtual address range starting at 7433 * the specified virtual address. Returns KERN_RESOURCE_SHORTAGE if either 7434 * (1) PMAP_ENTER_NOSLEEP was specified and a page table page allocation 7435 * failed or (2) PMAP_ENTER_NORECLAIM was specified and a PV entry allocation 7436 * failed. 7437 * 7438 * The parameter "m" is only used when creating a managed, writeable mapping. 7439 */ 7440 static int 7441 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags, 7442 vm_page_t m, struct rwlock **lockp) 7443 { 7444 struct spglist free; 7445 pd_entry_t oldpde, *pde; 7446 pt_entry_t PG_G, PG_RW, PG_V; 7447 vm_page_t mt, pdpg; 7448 vm_page_t uwptpg; 7449 7450 PG_G = pmap_global_bit(pmap); 7451 PG_RW = pmap_rw_bit(pmap); 7452 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW, 7453 ("pmap_enter_pde: newpde is missing PG_M")); 7454 KASSERT((flags & (PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM)) != 7455 PMAP_ENTER_NORECLAIM, 7456 ("pmap_enter_pde: flags is missing PMAP_ENTER_NOREPLACE")); 7457 PG_V = pmap_valid_bit(pmap); 7458 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 7459 7460 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap, 7461 newpde))) { 7462 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx" 7463 " in pmap %p", va, pmap); 7464 return (KERN_FAILURE); 7465 } 7466 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags & 7467 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) { 7468 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 7469 " in pmap %p", va, pmap); 7470 return (KERN_RESOURCE_SHORTAGE); 7471 } 7472 7473 /* 7474 * If pkru is not same for the whole pde range, return failure 7475 * and let vm_fault() cope. Check after pde allocation, since 7476 * it could sleep. 7477 */ 7478 if (!pmap_pkru_same(pmap, va, va + NBPDR, &newpde)) { 7479 pmap_abort_ptp(pmap, va, pdpg); 7480 return (KERN_PROTECTION_FAILURE); 7481 } 7482 7483 /* 7484 * If there are existing mappings, either abort or remove them. 7485 */ 7486 oldpde = *pde; 7487 if ((oldpde & PG_V) != 0) { 7488 KASSERT(pdpg == NULL || pdpg->ref_count > 1, 7489 ("pmap_enter_pde: pdpg's reference count is too low")); 7490 if ((flags & PMAP_ENTER_NOREPLACE) != 0) { 7491 if ((oldpde & PG_PS) != 0) { 7492 if (pdpg != NULL) 7493 pdpg->ref_count--; 7494 CTR2(KTR_PMAP, 7495 "pmap_enter_pde: no space for va %#lx" 7496 " in pmap %p", va, pmap); 7497 return (KERN_NO_SPACE); 7498 } else if (va < VM_MAXUSER_ADDRESS || 7499 !pmap_every_pte_zero(oldpde & PG_FRAME)) { 7500 if (pdpg != NULL) 7501 pdpg->ref_count--; 7502 CTR2(KTR_PMAP, 7503 "pmap_enter_pde: failure for va %#lx" 7504 " in pmap %p", va, pmap); 7505 return (KERN_FAILURE); 7506 } 7507 } 7508 /* Break the existing mapping(s). */ 7509 SLIST_INIT(&free); 7510 if ((oldpde & PG_PS) != 0) { 7511 /* 7512 * The reference to the PD page that was acquired by 7513 * pmap_alloc_pde() ensures that it won't be freed. 7514 * However, if the PDE resulted from a promotion, and 7515 * the mapping is not from kernel_pmap, then 7516 * a reserved PT page could be freed. 7517 */ 7518 (void)pmap_remove_pde(pmap, pde, va, false, &free, 7519 lockp); 7520 if ((oldpde & PG_G) == 0) 7521 pmap_invalidate_pde_page(pmap, va, oldpde); 7522 } else { 7523 if (va >= VM_MAXUSER_ADDRESS) { 7524 /* 7525 * Try to save the ptp in the trie 7526 * before any changes to mappings are 7527 * made. Abort on failure. 7528 */ 7529 mt = PHYS_TO_VM_PAGE(oldpde & PG_FRAME); 7530 if (pmap_insert_pt_page(pmap, mt, false, 7531 false)) { 7532 CTR1(KTR_PMAP, 7533 "pmap_enter_pde: cannot ins kern ptp va %#lx", 7534 va); 7535 return (KERN_RESOURCE_SHORTAGE); 7536 } 7537 /* 7538 * Both pmap_remove_pde() and 7539 * pmap_remove_ptes() will zero-fill 7540 * the kernel page table page. 7541 */ 7542 } 7543 pmap_delayed_invl_start(); 7544 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free, 7545 lockp)) 7546 pmap_invalidate_all(pmap); 7547 pmap_delayed_invl_finish(); 7548 } 7549 if (va < VM_MAXUSER_ADDRESS) { 7550 vm_page_free_pages_toq(&free, true); 7551 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p", 7552 pde)); 7553 } else { 7554 KASSERT(SLIST_EMPTY(&free), 7555 ("pmap_enter_pde: freed kernel page table page")); 7556 } 7557 } 7558 7559 /* 7560 * Allocate leaf ptpage for wired userspace pages. 7561 */ 7562 uwptpg = NULL; 7563 if ((newpde & PG_W) != 0 && pmap != kernel_pmap) { 7564 uwptpg = pmap_alloc_pt_page(pmap, pmap_pde_pindex(va), 7565 VM_ALLOC_WIRED); 7566 if (uwptpg == NULL) { 7567 pmap_abort_ptp(pmap, va, pdpg); 7568 return (KERN_RESOURCE_SHORTAGE); 7569 } 7570 if (pmap_insert_pt_page(pmap, uwptpg, true, false)) { 7571 pmap_free_pt_page(pmap, uwptpg, false); 7572 pmap_abort_ptp(pmap, va, pdpg); 7573 return (KERN_RESOURCE_SHORTAGE); 7574 } 7575 7576 uwptpg->ref_count = NPTEPG; 7577 } 7578 if ((newpde & PG_MANAGED) != 0) { 7579 /* 7580 * Abort this mapping if its PV entry could not be created. 7581 */ 7582 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) { 7583 if (pdpg != NULL) 7584 pmap_abort_ptp(pmap, va, pdpg); 7585 else { 7586 KASSERT(va >= VM_MAXUSER_ADDRESS && 7587 (*pde & (PG_PS | PG_V)) == PG_V, 7588 ("pmap_enter_pde: invalid kernel PDE")); 7589 mt = pmap_remove_pt_page(pmap, va); 7590 KASSERT(mt != NULL, 7591 ("pmap_enter_pde: missing kernel PTP")); 7592 } 7593 if (uwptpg != NULL) { 7594 mt = pmap_remove_pt_page(pmap, va); 7595 KASSERT(mt == uwptpg, 7596 ("removed pt page %p, expected %p", mt, 7597 uwptpg)); 7598 uwptpg->ref_count = 1; 7599 pmap_free_pt_page(pmap, uwptpg, false); 7600 } 7601 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 7602 " in pmap %p", va, pmap); 7603 return (KERN_RESOURCE_SHORTAGE); 7604 } 7605 if ((newpde & PG_RW) != 0) { 7606 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 7607 vm_page_aflag_set(mt, PGA_WRITEABLE); 7608 } 7609 } 7610 7611 /* 7612 * Increment counters. 7613 */ 7614 if ((newpde & PG_W) != 0) 7615 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE; 7616 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE); 7617 7618 /* 7619 * Map the superpage. (This is not a promoted mapping; there will not 7620 * be any lingering 4KB page mappings in the TLB.) 7621 */ 7622 pde_store(pde, newpde); 7623 7624 counter_u64_add(pmap_pde_mappings, 1); 7625 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p", 7626 va, pmap); 7627 return (KERN_SUCCESS); 7628 } 7629 7630 /* 7631 * Maps a sequence of resident pages belonging to the same object. 7632 * The sequence begins with the given page m_start. This page is 7633 * mapped at the given virtual address start. Each subsequent page is 7634 * mapped at a virtual address that is offset from start by the same 7635 * amount as the page is offset from m_start within the object. The 7636 * last page in the sequence is the page with the largest offset from 7637 * m_start that can be mapped at a virtual address less than the given 7638 * virtual address end. Not every virtual page between start and end 7639 * is mapped; only those for which a resident page exists with the 7640 * corresponding offset from m_start are mapped. 7641 */ 7642 void 7643 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 7644 vm_page_t m_start, vm_prot_t prot) 7645 { 7646 struct pctrie_iter pages; 7647 struct rwlock *lock; 7648 vm_offset_t va; 7649 vm_page_t m, mpte; 7650 int rv; 7651 7652 VM_OBJECT_ASSERT_LOCKED(m_start->object); 7653 7654 mpte = NULL; 7655 vm_page_iter_limit_init(&pages, m_start->object, 7656 m_start->pindex + atop(end - start)); 7657 m = vm_radix_iter_lookup(&pages, m_start->pindex); 7658 lock = NULL; 7659 PMAP_LOCK(pmap); 7660 while (m != NULL) { 7661 va = start + ptoa(m->pindex - m_start->pindex); 7662 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 7663 m->psind == 1 && pmap_ps_enabled(pmap) && 7664 ((rv = pmap_enter_2mpage(pmap, va, m, prot, &lock)) == 7665 KERN_SUCCESS || rv == KERN_NO_SPACE)) 7666 m = vm_radix_iter_jump(&pages, NBPDR / PAGE_SIZE); 7667 else { 7668 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 7669 mpte, &lock); 7670 m = vm_radix_iter_step(&pages); 7671 } 7672 } 7673 if (lock != NULL) 7674 rw_wunlock(lock); 7675 PMAP_UNLOCK(pmap); 7676 } 7677 7678 /* 7679 * this code makes some *MAJOR* assumptions: 7680 * 1. Current pmap & pmap exists. 7681 * 2. Not wired. 7682 * 3. Read access. 7683 * 4. No page table pages. 7684 * but is *MUCH* faster than pmap_enter... 7685 */ 7686 7687 void 7688 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 7689 { 7690 struct rwlock *lock; 7691 7692 lock = NULL; 7693 PMAP_LOCK(pmap); 7694 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock); 7695 if (lock != NULL) 7696 rw_wunlock(lock); 7697 PMAP_UNLOCK(pmap); 7698 } 7699 7700 static vm_page_t 7701 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 7702 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp) 7703 { 7704 pd_entry_t *pde; 7705 pt_entry_t newpte, *pte, PG_V; 7706 7707 KASSERT(!VA_IS_CLEANMAP(va) || 7708 (m->oflags & VPO_UNMANAGED) != 0, 7709 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 7710 PG_V = pmap_valid_bit(pmap); 7711 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 7712 pde = NULL; 7713 7714 /* 7715 * In the case that a page table page is not 7716 * resident, we are creating it here. 7717 */ 7718 if (va < VM_MAXUSER_ADDRESS) { 7719 pdp_entry_t *pdpe; 7720 vm_pindex_t ptepindex; 7721 7722 /* 7723 * Calculate pagetable page index 7724 */ 7725 ptepindex = pmap_pde_pindex(va); 7726 if (mpte && (mpte->pindex == ptepindex)) { 7727 mpte->ref_count++; 7728 } else { 7729 /* 7730 * If the page table page is mapped, we just increment 7731 * the hold count, and activate it. Otherwise, we 7732 * attempt to allocate a page table page, passing NULL 7733 * instead of the PV list lock pointer because we don't 7734 * intend to sleep. If this attempt fails, we don't 7735 * retry. Instead, we give up. 7736 */ 7737 pdpe = pmap_pdpe(pmap, va); 7738 if (pdpe != NULL && (*pdpe & PG_V) != 0) { 7739 if ((*pdpe & PG_PS) != 0) 7740 return (NULL); 7741 pde = pmap_pdpe_to_pde(pdpe, va); 7742 if ((*pde & PG_V) != 0) { 7743 if ((*pde & PG_PS) != 0) 7744 return (NULL); 7745 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 7746 mpte->ref_count++; 7747 } else { 7748 mpte = pmap_allocpte_alloc(pmap, 7749 ptepindex, NULL, va); 7750 if (mpte == NULL) 7751 return (NULL); 7752 } 7753 } else { 7754 mpte = pmap_allocpte_alloc(pmap, ptepindex, 7755 NULL, va); 7756 if (mpte == NULL) 7757 return (NULL); 7758 } 7759 } 7760 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte)); 7761 pte = &pte[pmap_pte_index(va)]; 7762 } else { 7763 mpte = NULL; 7764 pte = vtopte(va); 7765 } 7766 if (*pte) { 7767 if (mpte != NULL) 7768 mpte->ref_count--; 7769 return (NULL); 7770 } 7771 7772 /* 7773 * Enter on the PV list if part of our managed memory. 7774 */ 7775 if ((m->oflags & VPO_UNMANAGED) == 0 && 7776 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) { 7777 if (mpte != NULL) 7778 pmap_abort_ptp(pmap, va, mpte); 7779 return (NULL); 7780 } 7781 7782 /* 7783 * Increment counters 7784 */ 7785 pmap_resident_count_adj(pmap, 1); 7786 7787 newpte = VM_PAGE_TO_PHYS(m) | PG_V | 7788 pmap_cache_bits(pmap, m->md.pat_mode, false); 7789 if ((m->oflags & VPO_UNMANAGED) == 0) 7790 newpte |= PG_MANAGED; 7791 if ((prot & VM_PROT_EXECUTE) == 0) 7792 newpte |= pg_nx; 7793 if (va < VM_MAXUSER_ADDRESS) 7794 newpte |= PG_U | pmap_pkru_get(pmap, va); 7795 pte_store(pte, newpte); 7796 7797 #if VM_NRESERVLEVEL > 0 7798 /* 7799 * If both the PTP and the reservation are fully populated, then 7800 * attempt promotion. 7801 */ 7802 if ((prot & VM_PROT_NO_PROMOTE) == 0 && 7803 (mpte == NULL || mpte->ref_count == NPTEPG) && 7804 (m->flags & PG_FICTITIOUS) == 0 && 7805 vm_reserv_level_iffullpop(m) == 0) { 7806 if (pde == NULL) 7807 pde = pmap_pde(pmap, va); 7808 7809 /* 7810 * If promotion succeeds, then the next call to this function 7811 * should not be given the unmapped PTP as a hint. 7812 */ 7813 if (pmap_promote_pde(pmap, pde, va, mpte, lockp)) 7814 mpte = NULL; 7815 } 7816 #endif 7817 7818 return (mpte); 7819 } 7820 7821 /* 7822 * Make a temporary mapping for a physical address. This is only intended 7823 * to be used for panic dumps. 7824 */ 7825 void * 7826 pmap_kenter_temporary(vm_paddr_t pa, int i) 7827 { 7828 vm_offset_t va; 7829 7830 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 7831 pmap_kenter(va, pa); 7832 pmap_invlpg(kernel_pmap, va); 7833 return ((void *)crashdumpmap); 7834 } 7835 7836 /* 7837 * This code maps large physical mmap regions into the 7838 * processor address space. Note that some shortcuts 7839 * are taken, but the code works. 7840 */ 7841 void 7842 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 7843 vm_pindex_t pindex, vm_size_t size) 7844 { 7845 struct pctrie_iter pages; 7846 pd_entry_t *pde; 7847 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 7848 vm_paddr_t pa, ptepa; 7849 vm_page_t p, pdpg; 7850 int pat_mode; 7851 7852 PG_A = pmap_accessed_bit(pmap); 7853 PG_M = pmap_modified_bit(pmap); 7854 PG_V = pmap_valid_bit(pmap); 7855 PG_RW = pmap_rw_bit(pmap); 7856 7857 VM_OBJECT_ASSERT_WLOCKED(object); 7858 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 7859 ("pmap_object_init_pt: non-device object")); 7860 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 7861 if (!pmap_ps_enabled(pmap)) 7862 return; 7863 if (!vm_object_populate(object, pindex, pindex + atop(size))) 7864 return; 7865 vm_page_iter_init(&pages, object); 7866 p = vm_radix_iter_lookup(&pages, pindex); 7867 KASSERT(vm_page_all_valid(p), 7868 ("pmap_object_init_pt: invalid page %p", p)); 7869 pat_mode = p->md.pat_mode; 7870 7871 /* 7872 * Abort the mapping if the first page is not physically 7873 * aligned to a 2MB page boundary. 7874 */ 7875 ptepa = VM_PAGE_TO_PHYS(p); 7876 if (ptepa & (NBPDR - 1)) 7877 return; 7878 7879 /* 7880 * Skip the first page. Abort the mapping if the rest of 7881 * the pages are not physically contiguous or have differing 7882 * memory attributes. 7883 */ 7884 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 7885 pa += PAGE_SIZE) { 7886 p = vm_radix_iter_next(&pages); 7887 KASSERT(vm_page_all_valid(p), 7888 ("pmap_object_init_pt: invalid page %p", p)); 7889 if (pa != VM_PAGE_TO_PHYS(p) || 7890 pat_mode != p->md.pat_mode) 7891 return; 7892 } 7893 7894 /* 7895 * Map using 2MB pages. Since "ptepa" is 2M aligned and 7896 * "size" is a multiple of 2M, adding the PAT setting to "pa" 7897 * will not affect the termination of this loop. 7898 */ 7899 PMAP_LOCK(pmap); 7900 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, true); 7901 pa < ptepa + size; pa += NBPDR) { 7902 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL); 7903 if (pde == NULL) { 7904 /* 7905 * The creation of mappings below is only an 7906 * optimization. If a page directory page 7907 * cannot be allocated without blocking, 7908 * continue on to the next mapping rather than 7909 * blocking. 7910 */ 7911 addr += NBPDR; 7912 continue; 7913 } 7914 if ((*pde & PG_V) == 0) { 7915 pde_store(pde, pa | PG_PS | PG_M | PG_A | 7916 PG_U | PG_RW | PG_V); 7917 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE); 7918 counter_u64_add(pmap_pde_mappings, 1); 7919 } else { 7920 /* Continue on if the PDE is already valid. */ 7921 pdpg->ref_count--; 7922 KASSERT(pdpg->ref_count > 0, 7923 ("pmap_object_init_pt: missing reference " 7924 "to page directory page, va: 0x%lx", addr)); 7925 } 7926 addr += NBPDR; 7927 } 7928 PMAP_UNLOCK(pmap); 7929 } 7930 } 7931 7932 /* 7933 * Clear the wired attribute from the mappings for the specified range of 7934 * addresses in the given pmap. Every valid mapping within that range 7935 * must have the wired attribute set. In contrast, invalid mappings 7936 * cannot have the wired attribute set, so they are ignored. 7937 * 7938 * The wired attribute of the page table entry is not a hardware 7939 * feature, so there is no need to invalidate any TLB entries. 7940 * Since pmap_demote_pde() for the wired entry must never fail, 7941 * pmap_delayed_invl_start()/finish() calls around the 7942 * function are not needed. 7943 */ 7944 void 7945 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 7946 { 7947 vm_offset_t va_next; 7948 pml4_entry_t *pml4e; 7949 pdp_entry_t *pdpe; 7950 pd_entry_t *pde; 7951 pt_entry_t *pte, PG_V, PG_G __diagused; 7952 7953 PG_V = pmap_valid_bit(pmap); 7954 PG_G = pmap_global_bit(pmap); 7955 PMAP_LOCK(pmap); 7956 for (; sva < eva; sva = va_next) { 7957 pml4e = pmap_pml4e(pmap, sva); 7958 if (pml4e == NULL || (*pml4e & PG_V) == 0) { 7959 va_next = (sva + NBPML4) & ~PML4MASK; 7960 if (va_next < sva) 7961 va_next = eva; 7962 continue; 7963 } 7964 7965 va_next = (sva + NBPDP) & ~PDPMASK; 7966 if (va_next < sva) 7967 va_next = eva; 7968 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 7969 if ((*pdpe & PG_V) == 0) 7970 continue; 7971 if ((*pdpe & PG_PS) != 0) { 7972 KASSERT(va_next <= eva, 7973 ("partial update of non-transparent 1G mapping " 7974 "pdpe %#lx sva %#lx eva %#lx va_next %#lx", 7975 *pdpe, sva, eva, va_next)); 7976 MPASS(pmap != kernel_pmap); /* XXXKIB */ 7977 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0); 7978 atomic_clear_long(pdpe, PG_W); 7979 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE; 7980 continue; 7981 } 7982 7983 va_next = (sva + NBPDR) & ~PDRMASK; 7984 if (va_next < sva) 7985 va_next = eva; 7986 pde = pmap_pdpe_to_pde(pdpe, sva); 7987 if ((*pde & PG_V) == 0) 7988 continue; 7989 if ((*pde & PG_PS) != 0) { 7990 if ((*pde & PG_W) == 0) 7991 panic("pmap_unwire: pde %#jx is missing PG_W", 7992 (uintmax_t)*pde); 7993 7994 /* 7995 * Are we unwiring the entire large page? If not, 7996 * demote the mapping and fall through. 7997 */ 7998 if (sva + NBPDR == va_next && eva >= va_next) { 7999 atomic_clear_long(pde, PG_W); 8000 pmap->pm_stats.wired_count -= NBPDR / 8001 PAGE_SIZE; 8002 continue; 8003 } else if (!pmap_demote_pde(pmap, pde, sva)) 8004 panic("pmap_unwire: demotion failed"); 8005 } 8006 if (va_next > eva) 8007 va_next = eva; 8008 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 8009 sva += PAGE_SIZE) { 8010 if ((*pte & PG_V) == 0) 8011 continue; 8012 if ((*pte & PG_W) == 0) 8013 panic("pmap_unwire: pte %#jx is missing PG_W", 8014 (uintmax_t)*pte); 8015 8016 /* 8017 * PG_W must be cleared atomically. Although the pmap 8018 * lock synchronizes access to PG_W, another processor 8019 * could be setting PG_M and/or PG_A concurrently. 8020 */ 8021 atomic_clear_long(pte, PG_W); 8022 pmap->pm_stats.wired_count--; 8023 } 8024 } 8025 PMAP_UNLOCK(pmap); 8026 } 8027 8028 /* 8029 * Copy the range specified by src_addr/len 8030 * from the source map to the range dst_addr/len 8031 * in the destination map. 8032 * 8033 * This routine is only advisory and need not do anything. 8034 */ 8035 void 8036 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 8037 vm_offset_t src_addr) 8038 { 8039 struct rwlock *lock; 8040 pml4_entry_t *pml4e; 8041 pdp_entry_t *pdpe; 8042 pd_entry_t *pde, srcptepaddr; 8043 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte; 8044 vm_offset_t addr, end_addr, va_next; 8045 vm_page_t dst_pdpg, dstmpte, srcmpte; 8046 8047 if (dst_addr != src_addr) 8048 return; 8049 8050 if (dst_pmap->pm_type != src_pmap->pm_type) 8051 return; 8052 8053 /* 8054 * EPT page table entries that require emulation of A/D bits are 8055 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although 8056 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit 8057 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT 8058 * implementations flag an EPT misconfiguration for exec-only 8059 * mappings we skip this function entirely for emulated pmaps. 8060 */ 8061 if (pmap_emulate_ad_bits(dst_pmap)) 8062 return; 8063 8064 end_addr = src_addr + len; 8065 lock = NULL; 8066 if (dst_pmap < src_pmap) { 8067 PMAP_LOCK(dst_pmap); 8068 PMAP_LOCK(src_pmap); 8069 } else { 8070 PMAP_LOCK(src_pmap); 8071 PMAP_LOCK(dst_pmap); 8072 } 8073 8074 PG_A = pmap_accessed_bit(dst_pmap); 8075 PG_M = pmap_modified_bit(dst_pmap); 8076 PG_V = pmap_valid_bit(dst_pmap); 8077 8078 for (addr = src_addr; addr < end_addr; addr = va_next) { 8079 KASSERT(addr < UPT_MIN_ADDRESS, 8080 ("pmap_copy: invalid to pmap_copy page tables")); 8081 8082 pml4e = pmap_pml4e(src_pmap, addr); 8083 if (pml4e == NULL || (*pml4e & PG_V) == 0) { 8084 va_next = (addr + NBPML4) & ~PML4MASK; 8085 if (va_next < addr) 8086 va_next = end_addr; 8087 continue; 8088 } 8089 8090 va_next = (addr + NBPDP) & ~PDPMASK; 8091 if (va_next < addr) 8092 va_next = end_addr; 8093 pdpe = pmap_pml4e_to_pdpe(pml4e, addr); 8094 if ((*pdpe & PG_V) == 0) 8095 continue; 8096 if ((*pdpe & PG_PS) != 0) { 8097 KASSERT(va_next <= end_addr, 8098 ("partial update of non-transparent 1G mapping " 8099 "pdpe %#lx sva %#lx eva %#lx va_next %#lx", 8100 *pdpe, addr, end_addr, va_next)); 8101 MPASS((addr & PDPMASK) == 0); 8102 MPASS((*pdpe & PG_MANAGED) == 0); 8103 srcptepaddr = *pdpe; 8104 pdpe = pmap_pdpe(dst_pmap, addr); 8105 if (pdpe == NULL) { 8106 if (pmap_allocpte_alloc(dst_pmap, 8107 pmap_pml4e_pindex(addr), NULL, addr) == 8108 NULL) 8109 break; 8110 pdpe = pmap_pdpe(dst_pmap, addr); 8111 } else { 8112 pml4e = pmap_pml4e(dst_pmap, addr); 8113 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME); 8114 dst_pdpg->ref_count++; 8115 } 8116 KASSERT(*pdpe == 0, 8117 ("1G mapping present in dst pmap " 8118 "pdpe %#lx sva %#lx eva %#lx va_next %#lx", 8119 *pdpe, addr, end_addr, va_next)); 8120 *pdpe = srcptepaddr & ~PG_W; 8121 pmap_resident_count_adj(dst_pmap, NBPDP / PAGE_SIZE); 8122 continue; 8123 } 8124 8125 va_next = (addr + NBPDR) & ~PDRMASK; 8126 if (va_next < addr) 8127 va_next = end_addr; 8128 8129 pde = pmap_pdpe_to_pde(pdpe, addr); 8130 srcptepaddr = *pde; 8131 if (srcptepaddr == 0) 8132 continue; 8133 8134 if (srcptepaddr & PG_PS) { 8135 /* 8136 * We can only virtual copy whole superpages. 8137 */ 8138 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 8139 continue; 8140 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL); 8141 if (pde == NULL) 8142 break; 8143 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 || 8144 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr, 8145 PMAP_ENTER_NORECLAIM, &lock))) { 8146 /* 8147 * We leave the dirty bit unchanged because 8148 * managed read/write superpage mappings are 8149 * required to be dirty. However, managed 8150 * superpage mappings are not required to 8151 * have their accessed bit set, so we clear 8152 * it because we don't know if this mapping 8153 * will be used. 8154 */ 8155 srcptepaddr &= ~PG_W; 8156 if ((srcptepaddr & PG_MANAGED) != 0) 8157 srcptepaddr &= ~PG_A; 8158 *pde = srcptepaddr; 8159 pmap_resident_count_adj(dst_pmap, NBPDR / 8160 PAGE_SIZE); 8161 counter_u64_add(pmap_pde_mappings, 1); 8162 } else 8163 pmap_abort_ptp(dst_pmap, addr, dst_pdpg); 8164 continue; 8165 } 8166 8167 srcptepaddr &= PG_FRAME; 8168 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr); 8169 KASSERT(srcmpte->ref_count > 0, 8170 ("pmap_copy: source page table page is unused")); 8171 8172 if (va_next > end_addr) 8173 va_next = end_addr; 8174 8175 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr); 8176 src_pte = &src_pte[pmap_pte_index(addr)]; 8177 dstmpte = NULL; 8178 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) { 8179 ptetemp = *src_pte; 8180 8181 /* 8182 * We only virtual copy managed pages. 8183 */ 8184 if ((ptetemp & PG_MANAGED) == 0) 8185 continue; 8186 8187 if (dstmpte != NULL) { 8188 KASSERT(dstmpte->pindex == 8189 pmap_pde_pindex(addr), 8190 ("dstmpte pindex/addr mismatch")); 8191 dstmpte->ref_count++; 8192 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr, 8193 NULL)) == NULL) 8194 goto out; 8195 dst_pte = (pt_entry_t *) 8196 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte)); 8197 dst_pte = &dst_pte[pmap_pte_index(addr)]; 8198 if (*dst_pte == 0 && 8199 pmap_try_insert_pv_entry(dst_pmap, addr, 8200 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) { 8201 /* 8202 * Clear the wired, modified, and accessed 8203 * (referenced) bits during the copy. 8204 */ 8205 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A); 8206 pmap_resident_count_adj(dst_pmap, 1); 8207 } else { 8208 pmap_abort_ptp(dst_pmap, addr, dstmpte); 8209 goto out; 8210 } 8211 /* Have we copied all of the valid mappings? */ 8212 if (dstmpte->ref_count >= srcmpte->ref_count) 8213 break; 8214 } 8215 } 8216 out: 8217 if (lock != NULL) 8218 rw_wunlock(lock); 8219 PMAP_UNLOCK(src_pmap); 8220 PMAP_UNLOCK(dst_pmap); 8221 } 8222 8223 int 8224 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap) 8225 { 8226 int error; 8227 8228 if (dst_pmap->pm_type != src_pmap->pm_type || 8229 dst_pmap->pm_type != PT_X86 || 8230 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0) 8231 return (0); 8232 for (;;) { 8233 if (dst_pmap < src_pmap) { 8234 PMAP_LOCK(dst_pmap); 8235 PMAP_LOCK(src_pmap); 8236 } else { 8237 PMAP_LOCK(src_pmap); 8238 PMAP_LOCK(dst_pmap); 8239 } 8240 error = pmap_pkru_copy(dst_pmap, src_pmap); 8241 /* Clean up partial copy on failure due to no memory. */ 8242 if (error == ENOMEM) 8243 pmap_pkru_deassign_all(dst_pmap); 8244 PMAP_UNLOCK(src_pmap); 8245 PMAP_UNLOCK(dst_pmap); 8246 if (error != ENOMEM) 8247 break; 8248 vm_wait(NULL); 8249 } 8250 return (error); 8251 } 8252 8253 /* 8254 * Zero the specified hardware page. 8255 */ 8256 void 8257 pmap_zero_page(vm_page_t m) 8258 { 8259 vm_offset_t va; 8260 8261 #ifdef TSLOG_PAGEZERO 8262 TSENTER(); 8263 #endif 8264 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 8265 pagezero((void *)va); 8266 #ifdef TSLOG_PAGEZERO 8267 TSEXIT(); 8268 #endif 8269 } 8270 8271 /* 8272 * Zero an area within a single hardware page. off and size must not 8273 * cover an area beyond a single hardware page. 8274 */ 8275 void 8276 pmap_zero_page_area(vm_page_t m, int off, int size) 8277 { 8278 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 8279 8280 if (off == 0 && size == PAGE_SIZE) 8281 pagezero((void *)va); 8282 else 8283 bzero((char *)va + off, size); 8284 } 8285 8286 /* 8287 * Copy 1 specified hardware page to another. 8288 */ 8289 void 8290 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 8291 { 8292 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc)); 8293 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst)); 8294 8295 pagecopy((void *)src, (void *)dst); 8296 } 8297 8298 int unmapped_buf_allowed = 1; 8299 8300 void 8301 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 8302 vm_offset_t b_offset, int xfersize) 8303 { 8304 void *a_cp, *b_cp; 8305 vm_page_t pages[2]; 8306 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset; 8307 int cnt; 8308 bool mapped; 8309 8310 while (xfersize > 0) { 8311 a_pg_offset = a_offset & PAGE_MASK; 8312 pages[0] = ma[a_offset >> PAGE_SHIFT]; 8313 b_pg_offset = b_offset & PAGE_MASK; 8314 pages[1] = mb[b_offset >> PAGE_SHIFT]; 8315 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 8316 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 8317 mapped = pmap_map_io_transient(pages, vaddr, 2, false); 8318 a_cp = (char *)vaddr[0] + a_pg_offset; 8319 b_cp = (char *)vaddr[1] + b_pg_offset; 8320 bcopy(a_cp, b_cp, cnt); 8321 if (__predict_false(mapped)) 8322 pmap_unmap_io_transient(pages, vaddr, 2, false); 8323 a_offset += cnt; 8324 b_offset += cnt; 8325 xfersize -= cnt; 8326 } 8327 } 8328 8329 /* 8330 * Returns true if the pmap's pv is one of the first 8331 * 16 pvs linked to from this page. This count may 8332 * be changed upwards or downwards in the future; it 8333 * is only necessary that true be returned for a small 8334 * subset of pmaps for proper page aging. 8335 */ 8336 bool 8337 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 8338 { 8339 struct md_page *pvh; 8340 struct rwlock *lock; 8341 pv_entry_t pv; 8342 int loops = 0; 8343 bool rv; 8344 8345 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 8346 ("pmap_page_exists_quick: page %p is not managed", m)); 8347 rv = false; 8348 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 8349 rw_rlock(lock); 8350 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 8351 if (PV_PMAP(pv) == pmap) { 8352 rv = true; 8353 break; 8354 } 8355 loops++; 8356 if (loops >= 16) 8357 break; 8358 } 8359 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 8360 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 8361 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 8362 if (PV_PMAP(pv) == pmap) { 8363 rv = true; 8364 break; 8365 } 8366 loops++; 8367 if (loops >= 16) 8368 break; 8369 } 8370 } 8371 rw_runlock(lock); 8372 return (rv); 8373 } 8374 8375 /* 8376 * pmap_page_wired_mappings: 8377 * 8378 * Return the number of managed mappings to the given physical page 8379 * that are wired. 8380 */ 8381 int 8382 pmap_page_wired_mappings(vm_page_t m) 8383 { 8384 struct rwlock *lock; 8385 struct md_page *pvh; 8386 pmap_t pmap; 8387 pt_entry_t *pte; 8388 pv_entry_t pv; 8389 int count, md_gen, pvh_gen; 8390 8391 if ((m->oflags & VPO_UNMANAGED) != 0) 8392 return (0); 8393 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 8394 rw_rlock(lock); 8395 restart: 8396 count = 0; 8397 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 8398 pmap = PV_PMAP(pv); 8399 if (!PMAP_TRYLOCK(pmap)) { 8400 md_gen = m->md.pv_gen; 8401 rw_runlock(lock); 8402 PMAP_LOCK(pmap); 8403 rw_rlock(lock); 8404 if (md_gen != m->md.pv_gen) { 8405 PMAP_UNLOCK(pmap); 8406 goto restart; 8407 } 8408 } 8409 pte = pmap_pte(pmap, pv->pv_va); 8410 if ((*pte & PG_W) != 0) 8411 count++; 8412 PMAP_UNLOCK(pmap); 8413 } 8414 if ((m->flags & PG_FICTITIOUS) == 0) { 8415 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 8416 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 8417 pmap = PV_PMAP(pv); 8418 if (!PMAP_TRYLOCK(pmap)) { 8419 md_gen = m->md.pv_gen; 8420 pvh_gen = pvh->pv_gen; 8421 rw_runlock(lock); 8422 PMAP_LOCK(pmap); 8423 rw_rlock(lock); 8424 if (md_gen != m->md.pv_gen || 8425 pvh_gen != pvh->pv_gen) { 8426 PMAP_UNLOCK(pmap); 8427 goto restart; 8428 } 8429 } 8430 pte = pmap_pde(pmap, pv->pv_va); 8431 if ((*pte & PG_W) != 0) 8432 count++; 8433 PMAP_UNLOCK(pmap); 8434 } 8435 } 8436 rw_runlock(lock); 8437 return (count); 8438 } 8439 8440 /* 8441 * Returns true if the given page is mapped individually or as part of 8442 * a 2mpage. Otherwise, returns false. 8443 */ 8444 bool 8445 pmap_page_is_mapped(vm_page_t m) 8446 { 8447 struct rwlock *lock; 8448 bool rv; 8449 8450 if ((m->oflags & VPO_UNMANAGED) != 0) 8451 return (false); 8452 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 8453 rw_rlock(lock); 8454 rv = !TAILQ_EMPTY(&m->md.pv_list) || 8455 ((m->flags & PG_FICTITIOUS) == 0 && 8456 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 8457 rw_runlock(lock); 8458 return (rv); 8459 } 8460 8461 /* 8462 * Destroy all managed, non-wired mappings in the given user-space 8463 * pmap. This pmap cannot be active on any processor besides the 8464 * caller. 8465 * 8466 * This function cannot be applied to the kernel pmap. Moreover, it 8467 * is not intended for general use. It is only to be used during 8468 * process termination. Consequently, it can be implemented in ways 8469 * that make it faster than pmap_remove(). First, it can more quickly 8470 * destroy mappings by iterating over the pmap's collection of PV 8471 * entries, rather than searching the page table. Second, it doesn't 8472 * have to test and clear the page table entries atomically, because 8473 * no processor is currently accessing the user address space. In 8474 * particular, a page table entry's dirty bit won't change state once 8475 * this function starts. 8476 * 8477 * Although this function destroys all of the pmap's managed, 8478 * non-wired mappings, it can delay and batch the invalidation of TLB 8479 * entries without calling pmap_delayed_invl_start() and 8480 * pmap_delayed_invl_finish(). Because the pmap is not active on 8481 * any other processor, none of these TLB entries will ever be used 8482 * before their eventual invalidation. Consequently, there is no need 8483 * for either pmap_remove_all() or pmap_remove_write() to wait for 8484 * that eventual TLB invalidation. 8485 */ 8486 void 8487 pmap_remove_pages(pmap_t pmap) 8488 { 8489 pd_entry_t ptepde; 8490 pt_entry_t *pte, tpte; 8491 pt_entry_t PG_M, PG_RW, PG_V; 8492 struct spglist free; 8493 struct pv_chunklist free_chunks[PMAP_MEMDOM]; 8494 vm_page_t m, mpte, mt; 8495 pv_entry_t pv; 8496 struct md_page *pvh; 8497 struct pv_chunk *pc, *npc; 8498 struct rwlock *lock; 8499 int64_t bit; 8500 uint64_t inuse, bitmask; 8501 int allfree, field, i, idx; 8502 #ifdef PV_STATS 8503 int freed; 8504 #endif 8505 bool superpage; 8506 vm_paddr_t pa; 8507 8508 /* 8509 * Assert that the given pmap is only active on the current 8510 * CPU. Unfortunately, we cannot block another CPU from 8511 * activating the pmap while this function is executing. 8512 */ 8513 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap)); 8514 #ifdef INVARIANTS 8515 { 8516 cpuset_t other_cpus; 8517 8518 other_cpus = all_cpus; 8519 critical_enter(); 8520 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 8521 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active); 8522 critical_exit(); 8523 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap)); 8524 } 8525 #endif 8526 8527 lock = NULL; 8528 PG_M = pmap_modified_bit(pmap); 8529 PG_V = pmap_valid_bit(pmap); 8530 PG_RW = pmap_rw_bit(pmap); 8531 8532 for (i = 0; i < PMAP_MEMDOM; i++) 8533 TAILQ_INIT(&free_chunks[i]); 8534 SLIST_INIT(&free); 8535 PMAP_LOCK(pmap); 8536 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 8537 allfree = 1; 8538 #ifdef PV_STATS 8539 freed = 0; 8540 #endif 8541 for (field = 0; field < _NPCM; field++) { 8542 inuse = ~pc->pc_map[field] & pc_freemask[field]; 8543 while (inuse != 0) { 8544 bit = bsfq(inuse); 8545 bitmask = 1UL << bit; 8546 idx = field * 64 + bit; 8547 pv = &pc->pc_pventry[idx]; 8548 inuse &= ~bitmask; 8549 8550 pte = pmap_pdpe(pmap, pv->pv_va); 8551 ptepde = *pte; 8552 pte = pmap_pdpe_to_pde(pte, pv->pv_va); 8553 tpte = *pte; 8554 if ((tpte & (PG_PS | PG_V)) == PG_V) { 8555 superpage = false; 8556 ptepde = tpte; 8557 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte & 8558 PG_FRAME); 8559 pte = &pte[pmap_pte_index(pv->pv_va)]; 8560 tpte = *pte; 8561 } else { 8562 /* 8563 * Keep track whether 'tpte' is a 8564 * superpage explicitly instead of 8565 * relying on PG_PS being set. 8566 * 8567 * This is because PG_PS is numerically 8568 * identical to PG_PTE_PAT and thus a 8569 * regular page could be mistaken for 8570 * a superpage. 8571 */ 8572 superpage = true; 8573 } 8574 8575 if ((tpte & PG_V) == 0) { 8576 panic("bad pte va %lx pte %lx", 8577 pv->pv_va, tpte); 8578 } 8579 8580 /* 8581 * We cannot remove wired pages from a process' mapping at this time 8582 */ 8583 if (tpte & PG_W) { 8584 allfree = 0; 8585 continue; 8586 } 8587 8588 /* Mark free */ 8589 pc->pc_map[field] |= bitmask; 8590 8591 /* 8592 * Because this pmap is not active on other 8593 * processors, the dirty bit cannot have 8594 * changed state since we last loaded pte. 8595 */ 8596 pte_clear(pte); 8597 8598 if (superpage) 8599 pa = tpte & PG_PS_FRAME; 8600 else 8601 pa = tpte & PG_FRAME; 8602 8603 m = PHYS_TO_VM_PAGE(pa); 8604 KASSERT(m->phys_addr == pa, 8605 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 8606 m, (uintmax_t)m->phys_addr, 8607 (uintmax_t)tpte)); 8608 8609 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 8610 m < &vm_page_array[vm_page_array_size], 8611 ("pmap_remove_pages: bad tpte %#jx", 8612 (uintmax_t)tpte)); 8613 8614 /* 8615 * Update the vm_page_t clean/reference bits. 8616 */ 8617 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 8618 if (superpage) { 8619 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 8620 vm_page_dirty(mt); 8621 } else 8622 vm_page_dirty(m); 8623 } 8624 8625 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 8626 8627 if (superpage) { 8628 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE); 8629 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 8630 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 8631 pvh->pv_gen++; 8632 if (TAILQ_EMPTY(&pvh->pv_list)) { 8633 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 8634 if ((mt->a.flags & PGA_WRITEABLE) != 0 && 8635 TAILQ_EMPTY(&mt->md.pv_list)) 8636 vm_page_aflag_clear(mt, PGA_WRITEABLE); 8637 } 8638 mpte = pmap_remove_pt_page(pmap, pv->pv_va); 8639 if (mpte != NULL) { 8640 KASSERT(vm_page_any_valid(mpte), 8641 ("pmap_remove_pages: pte page not promoted")); 8642 pmap_pt_page_count_adj(pmap, -1); 8643 KASSERT(mpte->ref_count == NPTEPG, 8644 ("pmap_remove_pages: pte page reference count error")); 8645 mpte->ref_count = 0; 8646 pmap_add_delayed_free_list(mpte, &free, false); 8647 } 8648 } else { 8649 pmap_resident_count_adj(pmap, -1); 8650 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 8651 m->md.pv_gen++; 8652 if ((m->a.flags & PGA_WRITEABLE) != 0 && 8653 TAILQ_EMPTY(&m->md.pv_list) && 8654 (m->flags & PG_FICTITIOUS) == 0) { 8655 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 8656 if (TAILQ_EMPTY(&pvh->pv_list)) 8657 vm_page_aflag_clear(m, PGA_WRITEABLE); 8658 } 8659 } 8660 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free); 8661 #ifdef PV_STATS 8662 freed++; 8663 #endif 8664 } 8665 } 8666 PV_STAT(counter_u64_add(pv_entry_frees, freed)); 8667 PV_STAT(counter_u64_add(pv_entry_spare, freed)); 8668 PV_STAT(counter_u64_add(pv_entry_count, -freed)); 8669 if (allfree) { 8670 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 8671 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list); 8672 } 8673 } 8674 if (lock != NULL) 8675 rw_wunlock(lock); 8676 pmap_invalidate_all(pmap); 8677 pmap_pkru_deassign_all(pmap); 8678 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks); 8679 PMAP_UNLOCK(pmap); 8680 vm_page_free_pages_toq(&free, true); 8681 } 8682 8683 static bool 8684 pmap_page_test_mappings(vm_page_t m, bool accessed, bool modified) 8685 { 8686 struct rwlock *lock; 8687 pv_entry_t pv; 8688 struct md_page *pvh; 8689 pt_entry_t *pte, mask; 8690 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 8691 pmap_t pmap; 8692 int md_gen, pvh_gen; 8693 bool rv; 8694 8695 rv = false; 8696 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 8697 rw_rlock(lock); 8698 restart: 8699 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 8700 pmap = PV_PMAP(pv); 8701 if (!PMAP_TRYLOCK(pmap)) { 8702 md_gen = m->md.pv_gen; 8703 rw_runlock(lock); 8704 PMAP_LOCK(pmap); 8705 rw_rlock(lock); 8706 if (md_gen != m->md.pv_gen) { 8707 PMAP_UNLOCK(pmap); 8708 goto restart; 8709 } 8710 } 8711 pte = pmap_pte(pmap, pv->pv_va); 8712 mask = 0; 8713 if (modified) { 8714 PG_M = pmap_modified_bit(pmap); 8715 PG_RW = pmap_rw_bit(pmap); 8716 mask |= PG_RW | PG_M; 8717 } 8718 if (accessed) { 8719 PG_A = pmap_accessed_bit(pmap); 8720 PG_V = pmap_valid_bit(pmap); 8721 mask |= PG_V | PG_A; 8722 } 8723 rv = (*pte & mask) == mask; 8724 PMAP_UNLOCK(pmap); 8725 if (rv) 8726 goto out; 8727 } 8728 if ((m->flags & PG_FICTITIOUS) == 0) { 8729 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 8730 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 8731 pmap = PV_PMAP(pv); 8732 if (!PMAP_TRYLOCK(pmap)) { 8733 md_gen = m->md.pv_gen; 8734 pvh_gen = pvh->pv_gen; 8735 rw_runlock(lock); 8736 PMAP_LOCK(pmap); 8737 rw_rlock(lock); 8738 if (md_gen != m->md.pv_gen || 8739 pvh_gen != pvh->pv_gen) { 8740 PMAP_UNLOCK(pmap); 8741 goto restart; 8742 } 8743 } 8744 pte = pmap_pde(pmap, pv->pv_va); 8745 mask = 0; 8746 if (modified) { 8747 PG_M = pmap_modified_bit(pmap); 8748 PG_RW = pmap_rw_bit(pmap); 8749 mask |= PG_RW | PG_M; 8750 } 8751 if (accessed) { 8752 PG_A = pmap_accessed_bit(pmap); 8753 PG_V = pmap_valid_bit(pmap); 8754 mask |= PG_V | PG_A; 8755 } 8756 rv = (*pte & mask) == mask; 8757 PMAP_UNLOCK(pmap); 8758 if (rv) 8759 goto out; 8760 } 8761 } 8762 out: 8763 rw_runlock(lock); 8764 return (rv); 8765 } 8766 8767 /* 8768 * pmap_is_modified: 8769 * 8770 * Return whether or not the specified physical page was modified 8771 * in any physical maps. 8772 */ 8773 bool 8774 pmap_is_modified(vm_page_t m) 8775 { 8776 8777 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 8778 ("pmap_is_modified: page %p is not managed", m)); 8779 8780 /* 8781 * If the page is not busied then this check is racy. 8782 */ 8783 if (!pmap_page_is_write_mapped(m)) 8784 return (false); 8785 return (pmap_page_test_mappings(m, false, true)); 8786 } 8787 8788 /* 8789 * pmap_is_prefaultable: 8790 * 8791 * Return whether or not the specified virtual address is eligible 8792 * for prefault. 8793 */ 8794 bool 8795 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 8796 { 8797 pd_entry_t *pde; 8798 pt_entry_t *pte, PG_V; 8799 bool rv; 8800 8801 PG_V = pmap_valid_bit(pmap); 8802 8803 /* 8804 * Return true if and only if the PTE for the specified virtual 8805 * address is allocated but invalid. 8806 */ 8807 rv = false; 8808 PMAP_LOCK(pmap); 8809 pde = pmap_pde(pmap, addr); 8810 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) { 8811 pte = pmap_pde_to_pte(pde, addr); 8812 rv = (*pte & PG_V) == 0; 8813 } 8814 PMAP_UNLOCK(pmap); 8815 return (rv); 8816 } 8817 8818 /* 8819 * pmap_is_referenced: 8820 * 8821 * Return whether or not the specified physical page was referenced 8822 * in any physical maps. 8823 */ 8824 bool 8825 pmap_is_referenced(vm_page_t m) 8826 { 8827 8828 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 8829 ("pmap_is_referenced: page %p is not managed", m)); 8830 return (pmap_page_test_mappings(m, true, false)); 8831 } 8832 8833 /* 8834 * Clear the write and modified bits in each of the given page's mappings. 8835 */ 8836 void 8837 pmap_remove_write(vm_page_t m) 8838 { 8839 struct md_page *pvh; 8840 pmap_t pmap; 8841 struct rwlock *lock; 8842 pv_entry_t next_pv, pv; 8843 pd_entry_t *pde; 8844 pt_entry_t oldpte, *pte, PG_M, PG_RW; 8845 vm_offset_t va; 8846 int pvh_gen, md_gen; 8847 8848 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 8849 ("pmap_remove_write: page %p is not managed", m)); 8850 8851 vm_page_assert_busied(m); 8852 if (!pmap_page_is_write_mapped(m)) 8853 return; 8854 8855 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 8856 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 8857 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 8858 rw_wlock(lock); 8859 retry: 8860 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 8861 pmap = PV_PMAP(pv); 8862 if (!PMAP_TRYLOCK(pmap)) { 8863 pvh_gen = pvh->pv_gen; 8864 rw_wunlock(lock); 8865 PMAP_LOCK(pmap); 8866 rw_wlock(lock); 8867 if (pvh_gen != pvh->pv_gen) { 8868 PMAP_UNLOCK(pmap); 8869 goto retry; 8870 } 8871 } 8872 PG_RW = pmap_rw_bit(pmap); 8873 va = pv->pv_va; 8874 pde = pmap_pde(pmap, va); 8875 if ((*pde & PG_RW) != 0) 8876 (void)pmap_demote_pde_locked(pmap, pde, va, &lock); 8877 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 8878 ("inconsistent pv lock %p %p for page %p", 8879 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 8880 PMAP_UNLOCK(pmap); 8881 } 8882 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 8883 pmap = PV_PMAP(pv); 8884 if (!PMAP_TRYLOCK(pmap)) { 8885 pvh_gen = pvh->pv_gen; 8886 md_gen = m->md.pv_gen; 8887 rw_wunlock(lock); 8888 PMAP_LOCK(pmap); 8889 rw_wlock(lock); 8890 if (pvh_gen != pvh->pv_gen || 8891 md_gen != m->md.pv_gen) { 8892 PMAP_UNLOCK(pmap); 8893 goto retry; 8894 } 8895 } 8896 PG_M = pmap_modified_bit(pmap); 8897 PG_RW = pmap_rw_bit(pmap); 8898 pde = pmap_pde(pmap, pv->pv_va); 8899 KASSERT((*pde & PG_PS) == 0, 8900 ("pmap_remove_write: found a 2mpage in page %p's pv list", 8901 m)); 8902 pte = pmap_pde_to_pte(pde, pv->pv_va); 8903 oldpte = *pte; 8904 if (oldpte & PG_RW) { 8905 while (!atomic_fcmpset_long(pte, &oldpte, oldpte & 8906 ~(PG_RW | PG_M))) 8907 cpu_spinwait(); 8908 if ((oldpte & PG_M) != 0) 8909 vm_page_dirty(m); 8910 pmap_invalidate_page(pmap, pv->pv_va); 8911 } 8912 PMAP_UNLOCK(pmap); 8913 } 8914 rw_wunlock(lock); 8915 vm_page_aflag_clear(m, PGA_WRITEABLE); 8916 pmap_delayed_invl_wait(m); 8917 } 8918 8919 /* 8920 * pmap_ts_referenced: 8921 * 8922 * Return a count of reference bits for a page, clearing those bits. 8923 * It is not necessary for every reference bit to be cleared, but it 8924 * is necessary that 0 only be returned when there are truly no 8925 * reference bits set. 8926 * 8927 * As an optimization, update the page's dirty field if a modified bit is 8928 * found while counting reference bits. This opportunistic update can be 8929 * performed at low cost and can eliminate the need for some future calls 8930 * to pmap_is_modified(). However, since this function stops after 8931 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 8932 * dirty pages. Those dirty pages will only be detected by a future call 8933 * to pmap_is_modified(). 8934 * 8935 * A DI block is not needed within this function, because 8936 * invalidations are performed before the PV list lock is 8937 * released. 8938 */ 8939 int 8940 pmap_ts_referenced(vm_page_t m) 8941 { 8942 struct md_page *pvh; 8943 pv_entry_t pv, pvf; 8944 pmap_t pmap; 8945 struct rwlock *lock; 8946 pd_entry_t oldpde, *pde; 8947 pt_entry_t *pte, PG_A, PG_M, PG_RW; 8948 vm_offset_t va; 8949 vm_paddr_t pa; 8950 int cleared, md_gen, not_cleared, pvh_gen; 8951 struct spglist free; 8952 bool demoted; 8953 8954 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 8955 ("pmap_ts_referenced: page %p is not managed", m)); 8956 SLIST_INIT(&free); 8957 cleared = 0; 8958 pa = VM_PAGE_TO_PHYS(m); 8959 lock = PHYS_TO_PV_LIST_LOCK(pa); 8960 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa); 8961 rw_wlock(lock); 8962 retry: 8963 not_cleared = 0; 8964 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 8965 goto small_mappings; 8966 pv = pvf; 8967 do { 8968 if (pvf == NULL) 8969 pvf = pv; 8970 pmap = PV_PMAP(pv); 8971 if (!PMAP_TRYLOCK(pmap)) { 8972 pvh_gen = pvh->pv_gen; 8973 rw_wunlock(lock); 8974 PMAP_LOCK(pmap); 8975 rw_wlock(lock); 8976 if (pvh_gen != pvh->pv_gen) { 8977 PMAP_UNLOCK(pmap); 8978 goto retry; 8979 } 8980 } 8981 PG_A = pmap_accessed_bit(pmap); 8982 PG_M = pmap_modified_bit(pmap); 8983 PG_RW = pmap_rw_bit(pmap); 8984 va = pv->pv_va; 8985 pde = pmap_pde(pmap, pv->pv_va); 8986 oldpde = *pde; 8987 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 8988 /* 8989 * Although "oldpde" is mapping a 2MB page, because 8990 * this function is called at a 4KB page granularity, 8991 * we only update the 4KB page under test. 8992 */ 8993 vm_page_dirty(m); 8994 } 8995 if ((oldpde & PG_A) != 0) { 8996 /* 8997 * Since this reference bit is shared by 512 4KB 8998 * pages, it should not be cleared every time it is 8999 * tested. Apply a simple "hash" function on the 9000 * physical page number, the virtual superpage number, 9001 * and the pmap address to select one 4KB page out of 9002 * the 512 on which testing the reference bit will 9003 * result in clearing that reference bit. This 9004 * function is designed to avoid the selection of the 9005 * same 4KB page for every 2MB page mapping. 9006 * 9007 * On demotion, a mapping that hasn't been referenced 9008 * is simply destroyed. To avoid the possibility of a 9009 * subsequent page fault on a demoted wired mapping, 9010 * always leave its reference bit set. Moreover, 9011 * since the superpage is wired, the current state of 9012 * its reference bit won't affect page replacement. 9013 */ 9014 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 9015 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 9016 (oldpde & PG_W) == 0) { 9017 if (safe_to_clear_referenced(pmap, oldpde)) { 9018 atomic_clear_long(pde, PG_A); 9019 pmap_invalidate_page(pmap, pv->pv_va); 9020 demoted = false; 9021 } else if (pmap_demote_pde_locked(pmap, pde, 9022 pv->pv_va, &lock)) { 9023 /* 9024 * Remove the mapping to a single page 9025 * so that a subsequent access may 9026 * repromote. Since the underlying 9027 * page table page is fully populated, 9028 * this removal never frees a page 9029 * table page. 9030 */ 9031 demoted = true; 9032 va += VM_PAGE_TO_PHYS(m) - (oldpde & 9033 PG_PS_FRAME); 9034 pte = pmap_pde_to_pte(pde, va); 9035 pmap_remove_pte(pmap, pte, va, *pde, 9036 NULL, &lock); 9037 pmap_invalidate_page(pmap, va); 9038 } else 9039 demoted = true; 9040 9041 if (demoted) { 9042 /* 9043 * The superpage mapping was removed 9044 * entirely and therefore 'pv' is no 9045 * longer valid. 9046 */ 9047 if (pvf == pv) 9048 pvf = NULL; 9049 pv = NULL; 9050 } 9051 cleared++; 9052 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 9053 ("inconsistent pv lock %p %p for page %p", 9054 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 9055 } else 9056 not_cleared++; 9057 } 9058 PMAP_UNLOCK(pmap); 9059 /* Rotate the PV list if it has more than one entry. */ 9060 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 9061 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 9062 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 9063 pvh->pv_gen++; 9064 } 9065 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX) 9066 goto out; 9067 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 9068 small_mappings: 9069 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 9070 goto out; 9071 pv = pvf; 9072 do { 9073 if (pvf == NULL) 9074 pvf = pv; 9075 pmap = PV_PMAP(pv); 9076 if (!PMAP_TRYLOCK(pmap)) { 9077 pvh_gen = pvh->pv_gen; 9078 md_gen = m->md.pv_gen; 9079 rw_wunlock(lock); 9080 PMAP_LOCK(pmap); 9081 rw_wlock(lock); 9082 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 9083 PMAP_UNLOCK(pmap); 9084 goto retry; 9085 } 9086 } 9087 PG_A = pmap_accessed_bit(pmap); 9088 PG_M = pmap_modified_bit(pmap); 9089 PG_RW = pmap_rw_bit(pmap); 9090 pde = pmap_pde(pmap, pv->pv_va); 9091 KASSERT((*pde & PG_PS) == 0, 9092 ("pmap_ts_referenced: found a 2mpage in page %p's pv list", 9093 m)); 9094 pte = pmap_pde_to_pte(pde, pv->pv_va); 9095 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 9096 vm_page_dirty(m); 9097 if ((*pte & PG_A) != 0) { 9098 if (safe_to_clear_referenced(pmap, *pte)) { 9099 atomic_clear_long(pte, PG_A); 9100 pmap_invalidate_page(pmap, pv->pv_va); 9101 cleared++; 9102 } else if ((*pte & PG_W) == 0) { 9103 /* 9104 * Wired pages cannot be paged out so 9105 * doing accessed bit emulation for 9106 * them is wasted effort. We do the 9107 * hard work for unwired pages only. 9108 */ 9109 pmap_remove_pte(pmap, pte, pv->pv_va, 9110 *pde, &free, &lock); 9111 pmap_invalidate_page(pmap, pv->pv_va); 9112 cleared++; 9113 if (pvf == pv) 9114 pvf = NULL; 9115 pv = NULL; 9116 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 9117 ("inconsistent pv lock %p %p for page %p", 9118 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 9119 } else 9120 not_cleared++; 9121 } 9122 PMAP_UNLOCK(pmap); 9123 /* Rotate the PV list if it has more than one entry. */ 9124 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 9125 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 9126 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 9127 m->md.pv_gen++; 9128 } 9129 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared + 9130 not_cleared < PMAP_TS_REFERENCED_MAX); 9131 out: 9132 rw_wunlock(lock); 9133 vm_page_free_pages_toq(&free, true); 9134 return (cleared + not_cleared); 9135 } 9136 9137 /* 9138 * Apply the given advice to the specified range of addresses within the 9139 * given pmap. Depending on the advice, clear the referenced and/or 9140 * modified flags in each mapping and set the mapped page's dirty field. 9141 */ 9142 void 9143 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 9144 { 9145 struct rwlock *lock; 9146 pml4_entry_t *pml4e; 9147 pdp_entry_t *pdpe; 9148 pd_entry_t oldpde, *pde; 9149 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V; 9150 vm_offset_t va, va_next; 9151 vm_page_t m; 9152 bool anychanged; 9153 9154 if (advice != MADV_DONTNEED && advice != MADV_FREE) 9155 return; 9156 9157 /* 9158 * A/D bit emulation requires an alternate code path when clearing 9159 * the modified and accessed bits below. Since this function is 9160 * advisory in nature we skip it entirely for pmaps that require 9161 * A/D bit emulation. 9162 */ 9163 if (pmap_emulate_ad_bits(pmap)) 9164 return; 9165 9166 PG_A = pmap_accessed_bit(pmap); 9167 PG_G = pmap_global_bit(pmap); 9168 PG_M = pmap_modified_bit(pmap); 9169 PG_V = pmap_valid_bit(pmap); 9170 PG_RW = pmap_rw_bit(pmap); 9171 anychanged = false; 9172 pmap_delayed_invl_start(); 9173 PMAP_LOCK(pmap); 9174 for (; sva < eva; sva = va_next) { 9175 pml4e = pmap_pml4e(pmap, sva); 9176 if (pml4e == NULL || (*pml4e & PG_V) == 0) { 9177 va_next = (sva + NBPML4) & ~PML4MASK; 9178 if (va_next < sva) 9179 va_next = eva; 9180 continue; 9181 } 9182 9183 va_next = (sva + NBPDP) & ~PDPMASK; 9184 if (va_next < sva) 9185 va_next = eva; 9186 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 9187 if ((*pdpe & PG_V) == 0) 9188 continue; 9189 if ((*pdpe & PG_PS) != 0) 9190 continue; 9191 9192 va_next = (sva + NBPDR) & ~PDRMASK; 9193 if (va_next < sva) 9194 va_next = eva; 9195 pde = pmap_pdpe_to_pde(pdpe, sva); 9196 oldpde = *pde; 9197 if ((oldpde & PG_V) == 0) 9198 continue; 9199 else if ((oldpde & PG_PS) != 0) { 9200 if ((oldpde & PG_MANAGED) == 0) 9201 continue; 9202 lock = NULL; 9203 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) { 9204 if (lock != NULL) 9205 rw_wunlock(lock); 9206 9207 /* 9208 * The large page mapping was destroyed. 9209 */ 9210 continue; 9211 } 9212 9213 /* 9214 * Unless the page mappings are wired, remove the 9215 * mapping to a single page so that a subsequent 9216 * access may repromote. Choosing the last page 9217 * within the address range [sva, min(va_next, eva)) 9218 * generally results in more repromotions. Since the 9219 * underlying page table page is fully populated, this 9220 * removal never frees a page table page. 9221 */ 9222 if ((oldpde & PG_W) == 0) { 9223 va = eva; 9224 if (va > va_next) 9225 va = va_next; 9226 va -= PAGE_SIZE; 9227 KASSERT(va >= sva, 9228 ("pmap_advise: no address gap")); 9229 pte = pmap_pde_to_pte(pde, va); 9230 KASSERT((*pte & PG_V) != 0, 9231 ("pmap_advise: invalid PTE")); 9232 pmap_remove_pte(pmap, pte, va, *pde, NULL, 9233 &lock); 9234 anychanged = true; 9235 } 9236 if (lock != NULL) 9237 rw_wunlock(lock); 9238 } 9239 if (va_next > eva) 9240 va_next = eva; 9241 va = va_next; 9242 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 9243 sva += PAGE_SIZE) { 9244 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V)) 9245 goto maybe_invlrng; 9246 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 9247 if (advice == MADV_DONTNEED) { 9248 /* 9249 * Future calls to pmap_is_modified() 9250 * can be avoided by making the page 9251 * dirty now. 9252 */ 9253 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 9254 vm_page_dirty(m); 9255 } 9256 atomic_clear_long(pte, PG_M | PG_A); 9257 } else if ((*pte & PG_A) != 0) 9258 atomic_clear_long(pte, PG_A); 9259 else 9260 goto maybe_invlrng; 9261 9262 if ((*pte & PG_G) != 0) { 9263 if (va == va_next) 9264 va = sva; 9265 } else 9266 anychanged = true; 9267 continue; 9268 maybe_invlrng: 9269 if (va != va_next) { 9270 pmap_invalidate_range(pmap, va, sva); 9271 va = va_next; 9272 } 9273 } 9274 if (va != va_next) 9275 pmap_invalidate_range(pmap, va, sva); 9276 } 9277 if (anychanged) 9278 pmap_invalidate_all(pmap); 9279 PMAP_UNLOCK(pmap); 9280 pmap_delayed_invl_finish(); 9281 } 9282 9283 /* 9284 * Clear the modify bits on the specified physical page. 9285 */ 9286 void 9287 pmap_clear_modify(vm_page_t m) 9288 { 9289 struct md_page *pvh; 9290 pmap_t pmap; 9291 pv_entry_t next_pv, pv; 9292 pd_entry_t oldpde, *pde; 9293 pt_entry_t *pte, PG_M, PG_RW; 9294 struct rwlock *lock; 9295 vm_offset_t va; 9296 int md_gen, pvh_gen; 9297 9298 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 9299 ("pmap_clear_modify: page %p is not managed", m)); 9300 vm_page_assert_busied(m); 9301 9302 if (!pmap_page_is_write_mapped(m)) 9303 return; 9304 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 9305 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 9306 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 9307 rw_wlock(lock); 9308 restart: 9309 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 9310 pmap = PV_PMAP(pv); 9311 if (!PMAP_TRYLOCK(pmap)) { 9312 pvh_gen = pvh->pv_gen; 9313 rw_wunlock(lock); 9314 PMAP_LOCK(pmap); 9315 rw_wlock(lock); 9316 if (pvh_gen != pvh->pv_gen) { 9317 PMAP_UNLOCK(pmap); 9318 goto restart; 9319 } 9320 } 9321 PG_M = pmap_modified_bit(pmap); 9322 PG_RW = pmap_rw_bit(pmap); 9323 va = pv->pv_va; 9324 pde = pmap_pde(pmap, va); 9325 oldpde = *pde; 9326 /* If oldpde has PG_RW set, then it also has PG_M set. */ 9327 if ((oldpde & PG_RW) != 0 && 9328 pmap_demote_pde_locked(pmap, pde, va, &lock) && 9329 (oldpde & PG_W) == 0) { 9330 /* 9331 * Write protect the mapping to a single page so that 9332 * a subsequent write access may repromote. 9333 */ 9334 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME); 9335 pte = pmap_pde_to_pte(pde, va); 9336 atomic_clear_long(pte, PG_M | PG_RW); 9337 vm_page_dirty(m); 9338 pmap_invalidate_page(pmap, va); 9339 } 9340 PMAP_UNLOCK(pmap); 9341 } 9342 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 9343 pmap = PV_PMAP(pv); 9344 if (!PMAP_TRYLOCK(pmap)) { 9345 md_gen = m->md.pv_gen; 9346 pvh_gen = pvh->pv_gen; 9347 rw_wunlock(lock); 9348 PMAP_LOCK(pmap); 9349 rw_wlock(lock); 9350 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 9351 PMAP_UNLOCK(pmap); 9352 goto restart; 9353 } 9354 } 9355 PG_M = pmap_modified_bit(pmap); 9356 PG_RW = pmap_rw_bit(pmap); 9357 pde = pmap_pde(pmap, pv->pv_va); 9358 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 9359 " a 2mpage in page %p's pv list", m)); 9360 pte = pmap_pde_to_pte(pde, pv->pv_va); 9361 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 9362 atomic_clear_long(pte, PG_M); 9363 pmap_invalidate_page(pmap, pv->pv_va); 9364 } 9365 PMAP_UNLOCK(pmap); 9366 } 9367 rw_wunlock(lock); 9368 } 9369 9370 /* 9371 * Miscellaneous support routines follow 9372 */ 9373 9374 /* Adjust the properties for a leaf page table entry. */ 9375 static __inline void 9376 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask) 9377 { 9378 u_long opte, npte; 9379 9380 opte = *(u_long *)pte; 9381 do { 9382 npte = opte & ~mask; 9383 npte |= bits; 9384 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte, 9385 npte)); 9386 } 9387 9388 /* 9389 * Map a set of physical memory pages into the kernel virtual 9390 * address space. Return a pointer to where it is mapped. This 9391 * routine is intended to be used for mapping device memory, 9392 * NOT real memory. 9393 */ 9394 static void * 9395 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags) 9396 { 9397 struct pmap_preinit_mapping *ppim; 9398 vm_offset_t va, offset; 9399 vm_size_t tmpsize; 9400 int i; 9401 9402 offset = pa & PAGE_MASK; 9403 size = round_page(offset + size); 9404 pa = trunc_page(pa); 9405 9406 if (!pmap_initialized) { 9407 va = 0; 9408 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 9409 ppim = pmap_preinit_mapping + i; 9410 if (ppim->va == 0) { 9411 ppim->pa = pa; 9412 ppim->sz = size; 9413 ppim->mode = mode; 9414 ppim->va = virtual_avail; 9415 virtual_avail += size; 9416 va = ppim->va; 9417 break; 9418 } 9419 } 9420 if (va == 0) 9421 panic("%s: too many preinit mappings", __func__); 9422 } else { 9423 /* 9424 * If we have a preinit mapping, reuse it. 9425 */ 9426 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 9427 ppim = pmap_preinit_mapping + i; 9428 if (ppim->pa == pa && ppim->sz == size && 9429 (ppim->mode == mode || 9430 (flags & MAPDEV_SETATTR) == 0)) 9431 return ((void *)(ppim->va + offset)); 9432 } 9433 /* 9434 * If the specified range of physical addresses fits within 9435 * the direct map window, use the direct map. 9436 */ 9437 if (pa < dmaplimit && pa + size <= dmaplimit) { 9438 va = PHYS_TO_DMAP(pa); 9439 if ((flags & MAPDEV_SETATTR) != 0) { 9440 PMAP_LOCK(kernel_pmap); 9441 i = pmap_change_props_locked(va, size, 9442 PROT_NONE, mode, flags); 9443 PMAP_UNLOCK(kernel_pmap); 9444 } else 9445 i = 0; 9446 if (!i) 9447 return ((void *)(va + offset)); 9448 } 9449 va = kva_alloc(size); 9450 if (va == 0) 9451 panic("%s: Couldn't allocate KVA", __func__); 9452 } 9453 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 9454 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 9455 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 9456 if ((flags & MAPDEV_FLUSHCACHE) != 0) 9457 pmap_invalidate_cache_range(va, va + tmpsize); 9458 return ((void *)(va + offset)); 9459 } 9460 9461 void * 9462 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 9463 { 9464 9465 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE | 9466 MAPDEV_SETATTR)); 9467 } 9468 9469 void * 9470 pmap_mapdev(vm_paddr_t pa, vm_size_t size) 9471 { 9472 9473 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 9474 } 9475 9476 void * 9477 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size) 9478 { 9479 9480 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, 9481 MAPDEV_SETATTR)); 9482 } 9483 9484 void * 9485 pmap_mapbios(vm_paddr_t pa, vm_size_t size) 9486 { 9487 9488 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK, 9489 MAPDEV_FLUSHCACHE)); 9490 } 9491 9492 void 9493 pmap_unmapdev(void *p, vm_size_t size) 9494 { 9495 struct pmap_preinit_mapping *ppim; 9496 vm_offset_t offset, va; 9497 int i; 9498 9499 va = (vm_offset_t)p; 9500 9501 /* If we gave a direct map region in pmap_mapdev, do nothing */ 9502 if (va >= kva_layout.dmap_low && va < kva_layout.dmap_high) 9503 return; 9504 offset = va & PAGE_MASK; 9505 size = round_page(offset + size); 9506 va = trunc_page(va); 9507 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 9508 ppim = pmap_preinit_mapping + i; 9509 if (ppim->va == va && ppim->sz == size) { 9510 if (pmap_initialized) 9511 return; 9512 ppim->pa = 0; 9513 ppim->va = 0; 9514 ppim->sz = 0; 9515 ppim->mode = 0; 9516 if (va + size == virtual_avail) 9517 virtual_avail = va; 9518 return; 9519 } 9520 } 9521 if (pmap_initialized) { 9522 pmap_qremove(va, atop(size)); 9523 kva_free(va, size); 9524 } 9525 } 9526 9527 /* 9528 * Tries to demote a 1GB page mapping. 9529 */ 9530 static bool 9531 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va, vm_page_t m) 9532 { 9533 pdp_entry_t newpdpe, oldpdpe; 9534 pd_entry_t *firstpde, newpde, *pde; 9535 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 9536 vm_paddr_t pdpgpa; 9537 vm_page_t pdpg; 9538 9539 PG_A = pmap_accessed_bit(pmap); 9540 PG_M = pmap_modified_bit(pmap); 9541 PG_V = pmap_valid_bit(pmap); 9542 PG_RW = pmap_rw_bit(pmap); 9543 9544 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 9545 oldpdpe = *pdpe; 9546 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V), 9547 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V")); 9548 if (m == NULL) { 9549 pdpg = pmap_alloc_pt_page(pmap, va >> PDPSHIFT, 9550 VM_ALLOC_WIRED); 9551 if (pdpg == NULL) { 9552 CTR2(KTR_PMAP, 9553 "pmap_demote_pdpe: failure for va %#lx in pmap %p", 9554 va, pmap); 9555 return (false); 9556 } 9557 } else { 9558 pdpg = m; 9559 pdpg->pindex = va >> PDPSHIFT; 9560 pmap_pt_page_count_adj(pmap, 1); 9561 } 9562 pdpgpa = VM_PAGE_TO_PHYS(pdpg); 9563 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa); 9564 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V; 9565 KASSERT((oldpdpe & PG_A) != 0, 9566 ("pmap_demote_pdpe: oldpdpe is missing PG_A")); 9567 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW, 9568 ("pmap_demote_pdpe: oldpdpe is missing PG_M")); 9569 newpde = oldpdpe; 9570 9571 /* 9572 * Initialize the page directory page. 9573 */ 9574 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) { 9575 *pde = newpde; 9576 newpde += NBPDR; 9577 } 9578 9579 /* 9580 * Demote the mapping. 9581 */ 9582 *pdpe = newpdpe; 9583 9584 /* 9585 * Invalidate a stale recursive mapping of the page directory page. 9586 */ 9587 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va)); 9588 9589 counter_u64_add(pmap_pdpe_demotions, 1); 9590 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx" 9591 " in pmap %p", va, pmap); 9592 return (true); 9593 } 9594 9595 /* 9596 * Sets the memory attribute for the specified page. 9597 */ 9598 void 9599 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 9600 { 9601 if (m->md.pat_mode == ma) 9602 return; 9603 9604 m->md.pat_mode = ma; 9605 9606 /* 9607 * If "m" is a normal page, update its direct mapping. This update 9608 * can be relied upon to perform any cache operations that are 9609 * required for data coherence. 9610 */ 9611 if ((m->flags & PG_FICTITIOUS) == 0 && 9612 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE, 9613 m->md.pat_mode)) 9614 panic("memory attribute change on the direct map failed"); 9615 } 9616 9617 void 9618 pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma) 9619 { 9620 int error; 9621 9622 if (m->md.pat_mode == ma) 9623 return; 9624 9625 m->md.pat_mode = ma; 9626 9627 if ((m->flags & PG_FICTITIOUS) != 0) 9628 return; 9629 PMAP_LOCK(kernel_pmap); 9630 error = pmap_change_props_locked(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), 9631 PAGE_SIZE, PROT_NONE, m->md.pat_mode, 0); 9632 PMAP_UNLOCK(kernel_pmap); 9633 if (error != 0) 9634 panic("memory attribute change on the direct map failed"); 9635 } 9636 9637 /* 9638 * Changes the specified virtual address range's memory type to that given by 9639 * the parameter "mode". The specified virtual address range must be 9640 * completely contained within either the direct map or the kernel map. If 9641 * the virtual address range is contained within the kernel map, then the 9642 * memory type for each of the corresponding ranges of the direct map is also 9643 * changed. (The corresponding ranges of the direct map are those ranges that 9644 * map the same physical pages as the specified virtual address range.) These 9645 * changes to the direct map are necessary because Intel describes the 9646 * behavior of their processors as "undefined" if two or more mappings to the 9647 * same physical page have different memory types. 9648 * 9649 * Returns zero if the change completed successfully, and either EINVAL or 9650 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 9651 * of the virtual address range was not mapped, and ENOMEM is returned if 9652 * there was insufficient memory available to complete the change. In the 9653 * latter case, the memory type may have been changed on some part of the 9654 * virtual address range or the direct map. 9655 */ 9656 int 9657 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 9658 { 9659 int error; 9660 9661 PMAP_LOCK(kernel_pmap); 9662 error = pmap_change_props_locked(va, size, PROT_NONE, mode, 9663 MAPDEV_FLUSHCACHE); 9664 PMAP_UNLOCK(kernel_pmap); 9665 return (error); 9666 } 9667 9668 /* 9669 * Changes the specified virtual address range's protections to those 9670 * specified by "prot". Like pmap_change_attr(), protections for aliases 9671 * in the direct map are updated as well. Protections on aliasing mappings may 9672 * be a subset of the requested protections; for example, mappings in the direct 9673 * map are never executable. 9674 */ 9675 int 9676 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot) 9677 { 9678 int error; 9679 9680 /* Only supported within the kernel map. */ 9681 if (va < kva_layout.km_low) 9682 return (EINVAL); 9683 9684 PMAP_LOCK(kernel_pmap); 9685 error = pmap_change_props_locked(va, size, prot, -1, 9686 MAPDEV_ASSERTVALID); 9687 PMAP_UNLOCK(kernel_pmap); 9688 return (error); 9689 } 9690 9691 static int 9692 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot, 9693 int mode, int flags) 9694 { 9695 vm_offset_t base, offset, tmpva; 9696 vm_paddr_t pa_start, pa_end, pa_end1; 9697 pdp_entry_t *pdpe; 9698 pd_entry_t *pde, pde_bits, pde_mask; 9699 pt_entry_t *pte, pte_bits, pte_mask; 9700 int error; 9701 bool changed; 9702 9703 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 9704 base = trunc_page(va); 9705 offset = va & PAGE_MASK; 9706 size = round_page(offset + size); 9707 9708 /* 9709 * Only supported on kernel virtual addresses, including the direct 9710 * map but excluding the recursive map. 9711 */ 9712 if (base < kva_layout.dmap_low) 9713 return (EINVAL); 9714 9715 /* 9716 * Construct our flag sets and masks. "bits" is the subset of 9717 * "mask" that will be set in each modified PTE. 9718 * 9719 * Mappings in the direct map are never allowed to be executable. 9720 */ 9721 pde_bits = pte_bits = 0; 9722 pde_mask = pte_mask = 0; 9723 if (mode != -1) { 9724 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true); 9725 pde_mask |= X86_PG_PDE_CACHE; 9726 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false); 9727 pte_mask |= X86_PG_PTE_CACHE; 9728 } 9729 if (prot != VM_PROT_NONE) { 9730 if ((prot & VM_PROT_WRITE) != 0) { 9731 pde_bits |= X86_PG_RW; 9732 pte_bits |= X86_PG_RW; 9733 } 9734 if ((prot & VM_PROT_EXECUTE) == 0 || 9735 va < kva_layout.km_low) { 9736 pde_bits |= pg_nx; 9737 pte_bits |= pg_nx; 9738 } 9739 pde_mask |= X86_PG_RW | pg_nx; 9740 pte_mask |= X86_PG_RW | pg_nx; 9741 } 9742 9743 /* 9744 * Pages that aren't mapped aren't supported. Also break down 2MB pages 9745 * into 4KB pages if required. 9746 */ 9747 for (tmpva = base; tmpva < base + size; ) { 9748 pdpe = pmap_pdpe(kernel_pmap, tmpva); 9749 if (pdpe == NULL || *pdpe == 0) { 9750 KASSERT((flags & MAPDEV_ASSERTVALID) == 0, 9751 ("%s: addr %#lx is not mapped", __func__, tmpva)); 9752 return (EINVAL); 9753 } 9754 if (*pdpe & PG_PS) { 9755 /* 9756 * If the current 1GB page already has the required 9757 * properties, then we need not demote this page. Just 9758 * increment tmpva to the next 1GB page frame. 9759 */ 9760 if ((*pdpe & pde_mask) == pde_bits) { 9761 tmpva = trunc_1gpage(tmpva) + NBPDP; 9762 continue; 9763 } 9764 9765 /* 9766 * If the current offset aligns with a 1GB page frame 9767 * and there is at least 1GB left within the range, then 9768 * we need not break down this page into 2MB pages. 9769 */ 9770 if ((tmpva & PDPMASK) == 0 && 9771 tmpva + PDPMASK < base + size) { 9772 tmpva += NBPDP; 9773 continue; 9774 } 9775 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva, NULL)) 9776 return (ENOMEM); 9777 } 9778 pde = pmap_pdpe_to_pde(pdpe, tmpva); 9779 if (*pde == 0) { 9780 KASSERT((flags & MAPDEV_ASSERTVALID) == 0, 9781 ("%s: addr %#lx is not mapped", __func__, tmpva)); 9782 return (EINVAL); 9783 } 9784 if (*pde & PG_PS) { 9785 /* 9786 * If the current 2MB page already has the required 9787 * properties, then we need not demote this page. Just 9788 * increment tmpva to the next 2MB page frame. 9789 */ 9790 if ((*pde & pde_mask) == pde_bits) { 9791 tmpva = trunc_2mpage(tmpva) + NBPDR; 9792 continue; 9793 } 9794 9795 /* 9796 * If the current offset aligns with a 2MB page frame 9797 * and there is at least 2MB left within the range, then 9798 * we need not break down this page into 4KB pages. 9799 */ 9800 if ((tmpva & PDRMASK) == 0 && 9801 tmpva + PDRMASK < base + size) { 9802 tmpva += NBPDR; 9803 continue; 9804 } 9805 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) 9806 return (ENOMEM); 9807 } 9808 pte = pmap_pde_to_pte(pde, tmpva); 9809 if (*pte == 0) { 9810 KASSERT((flags & MAPDEV_ASSERTVALID) == 0, 9811 ("%s: addr %#lx is not mapped", __func__, tmpva)); 9812 return (EINVAL); 9813 } 9814 tmpva += PAGE_SIZE; 9815 } 9816 error = 0; 9817 9818 /* 9819 * Ok, all the pages exist, so run through them updating their 9820 * properties if required. 9821 */ 9822 changed = false; 9823 pa_start = pa_end = 0; 9824 for (tmpva = base; tmpva < base + size; ) { 9825 pdpe = pmap_pdpe(kernel_pmap, tmpva); 9826 if (*pdpe & PG_PS) { 9827 if ((*pdpe & pde_mask) != pde_bits) { 9828 pmap_pte_props(pdpe, pde_bits, pde_mask); 9829 changed = true; 9830 } 9831 if (tmpva >= kva_layout.km_low && 9832 (*pdpe & PG_PS_FRAME) < dmaplimit) { 9833 if (pa_start == pa_end) { 9834 /* Start physical address run. */ 9835 pa_start = *pdpe & PG_PS_FRAME; 9836 pa_end = pa_start + NBPDP; 9837 } else if (pa_end == (*pdpe & PG_PS_FRAME)) 9838 pa_end += NBPDP; 9839 else { 9840 /* Run ended, update direct map. */ 9841 error = pmap_change_props_locked( 9842 PHYS_TO_DMAP(pa_start), 9843 pa_end - pa_start, prot, mode, 9844 flags); 9845 if (error != 0) 9846 break; 9847 /* Start physical address run. */ 9848 pa_start = *pdpe & PG_PS_FRAME; 9849 pa_end = pa_start + NBPDP; 9850 } 9851 } 9852 tmpva = trunc_1gpage(tmpva) + NBPDP; 9853 continue; 9854 } 9855 pde = pmap_pdpe_to_pde(pdpe, tmpva); 9856 if (*pde & PG_PS) { 9857 if ((*pde & pde_mask) != pde_bits) { 9858 pmap_pte_props(pde, pde_bits, pde_mask); 9859 changed = true; 9860 } 9861 if (tmpva >= kva_layout.km_low && 9862 (*pde & PG_PS_FRAME) < dmaplimit) { 9863 if (pa_start == pa_end) { 9864 /* Start physical address run. */ 9865 pa_start = *pde & PG_PS_FRAME; 9866 pa_end = pa_start + NBPDR; 9867 } else if (pa_end == (*pde & PG_PS_FRAME)) 9868 pa_end += NBPDR; 9869 else { 9870 /* Run ended, update direct map. */ 9871 error = pmap_change_props_locked( 9872 PHYS_TO_DMAP(pa_start), 9873 pa_end - pa_start, prot, mode, 9874 flags); 9875 if (error != 0) 9876 break; 9877 /* Start physical address run. */ 9878 pa_start = *pde & PG_PS_FRAME; 9879 pa_end = pa_start + NBPDR; 9880 } 9881 } 9882 tmpva = trunc_2mpage(tmpva) + NBPDR; 9883 } else { 9884 pte = pmap_pde_to_pte(pde, tmpva); 9885 if ((*pte & pte_mask) != pte_bits) { 9886 pmap_pte_props(pte, pte_bits, pte_mask); 9887 changed = true; 9888 } 9889 if (tmpva >= kva_layout.km_low && 9890 (*pte & PG_FRAME) < dmaplimit) { 9891 if (pa_start == pa_end) { 9892 /* Start physical address run. */ 9893 pa_start = *pte & PG_FRAME; 9894 pa_end = pa_start + PAGE_SIZE; 9895 } else if (pa_end == (*pte & PG_FRAME)) 9896 pa_end += PAGE_SIZE; 9897 else { 9898 /* Run ended, update direct map. */ 9899 error = pmap_change_props_locked( 9900 PHYS_TO_DMAP(pa_start), 9901 pa_end - pa_start, prot, mode, 9902 flags); 9903 if (error != 0) 9904 break; 9905 /* Start physical address run. */ 9906 pa_start = *pte & PG_FRAME; 9907 pa_end = pa_start + PAGE_SIZE; 9908 } 9909 } 9910 tmpva += PAGE_SIZE; 9911 } 9912 } 9913 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) { 9914 pa_end1 = MIN(pa_end, dmaplimit); 9915 if (pa_start != pa_end1) 9916 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start), 9917 pa_end1 - pa_start, prot, mode, flags); 9918 } 9919 9920 /* 9921 * Flush CPU caches if required to make sure any data isn't cached that 9922 * shouldn't be, etc. 9923 */ 9924 if (changed) { 9925 pmap_invalidate_range(kernel_pmap, base, tmpva); 9926 if ((flags & MAPDEV_FLUSHCACHE) != 0) 9927 pmap_invalidate_cache_range(base, tmpva); 9928 } 9929 return (error); 9930 } 9931 9932 /* 9933 * Demotes any mapping within the direct map region that covers more 9934 * than the specified range of physical addresses. This range's size 9935 * must be a power of two and its starting address must be a multiple 9936 * of its size, which means that any pdp from the mapping is fully 9937 * covered by the range if len > NBPDP. Since the demotion does not 9938 * change any attributes of the mapping, a TLB invalidation is not 9939 * mandatory. The caller may, however, request a TLB invalidation. 9940 */ 9941 void 9942 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, bool invalidate) 9943 { 9944 pdp_entry_t *pdpe; 9945 pd_entry_t *pde; 9946 vm_offset_t va; 9947 vm_page_t m, mpte; 9948 bool changed, rv __diagused; 9949 9950 if (len == 0) 9951 return; 9952 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2")); 9953 KASSERT((base & (len - 1)) == 0, 9954 ("pmap_demote_DMAP: base is not a multiple of len")); 9955 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, "pmap_demote_DMAP"); 9956 9957 if (len < NBPDP && base < dmaplimit) { 9958 va = PHYS_TO_DMAP(base); 9959 changed = false; 9960 9961 /* 9962 * Assume that it is fine to sleep there. 9963 * The only existing caller of pmap_demote_DMAP() is the 9964 * x86_mr_split_dmap() function. 9965 */ 9966 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_WAITOK); 9967 if (len < NBPDR) { 9968 mpte = vm_page_alloc_noobj(VM_ALLOC_WIRED | 9969 VM_ALLOC_WAITOK); 9970 } else 9971 mpte = NULL; 9972 9973 PMAP_LOCK(kernel_pmap); 9974 pdpe = pmap_pdpe(kernel_pmap, va); 9975 if ((*pdpe & X86_PG_V) == 0) 9976 panic("pmap_demote_DMAP: invalid PDPE"); 9977 if ((*pdpe & PG_PS) != 0) { 9978 rv = pmap_demote_pdpe(kernel_pmap, pdpe, va, m); 9979 KASSERT(rv, ("pmap_demote_DMAP: PDPE failed")); 9980 changed = true; 9981 m = NULL; 9982 } 9983 if (len < NBPDR) { 9984 pde = pmap_pdpe_to_pde(pdpe, va); 9985 if ((*pde & X86_PG_V) == 0) 9986 panic("pmap_demote_DMAP: invalid PDE"); 9987 if ((*pde & PG_PS) != 0) { 9988 mpte->pindex = pmap_pde_pindex(va); 9989 pmap_pt_page_count_adj(kernel_pmap, 1); 9990 rv = pmap_demote_pde_mpte(kernel_pmap, pde, va, 9991 NULL, mpte); 9992 KASSERT(rv, ("pmap_demote_DMAP: PDE failed")); 9993 changed = true; 9994 mpte = NULL; 9995 } 9996 } 9997 if (changed && invalidate) 9998 pmap_invalidate_page(kernel_pmap, va); 9999 PMAP_UNLOCK(kernel_pmap); 10000 if (m != NULL) { 10001 vm_page_unwire_noq(m); 10002 vm_page_free(m); 10003 } 10004 if (mpte != NULL) { 10005 vm_page_unwire_noq(mpte); 10006 vm_page_free(mpte); 10007 } 10008 } 10009 } 10010 10011 /* 10012 * Perform the pmap work for mincore(2). If the page is not both referenced and 10013 * modified by this pmap, returns its physical address so that the caller can 10014 * find other mappings. 10015 */ 10016 int 10017 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 10018 { 10019 pdp_entry_t *pdpe; 10020 pd_entry_t *pdep; 10021 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V; 10022 vm_paddr_t pa; 10023 int val; 10024 10025 PG_A = pmap_accessed_bit(pmap); 10026 PG_M = pmap_modified_bit(pmap); 10027 PG_V = pmap_valid_bit(pmap); 10028 PG_RW = pmap_rw_bit(pmap); 10029 10030 PMAP_LOCK(pmap); 10031 pte = 0; 10032 pa = 0; 10033 val = 0; 10034 pdpe = pmap_pdpe(pmap, addr); 10035 if (pdpe == NULL) 10036 goto out; 10037 if ((*pdpe & PG_V) != 0) { 10038 if ((*pdpe & PG_PS) != 0) { 10039 pte = *pdpe; 10040 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) & 10041 PG_FRAME; 10042 val = MINCORE_PSIND(2); 10043 } else { 10044 pdep = pmap_pde(pmap, addr); 10045 if (pdep != NULL && (*pdep & PG_V) != 0) { 10046 if ((*pdep & PG_PS) != 0) { 10047 pte = *pdep; 10048 /* Compute the physical address of the 4KB page. */ 10049 pa = ((pte & PG_PS_FRAME) | (addr & 10050 PDRMASK)) & PG_FRAME; 10051 val = MINCORE_PSIND(1); 10052 } else { 10053 pte = *pmap_pde_to_pte(pdep, addr); 10054 pa = pte & PG_FRAME; 10055 val = 0; 10056 } 10057 } 10058 } 10059 } 10060 if ((pte & PG_V) != 0) { 10061 val |= MINCORE_INCORE; 10062 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 10063 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 10064 if ((pte & PG_A) != 0) 10065 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 10066 } 10067 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 10068 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 10069 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 10070 *pap = pa; 10071 } 10072 out: 10073 PMAP_UNLOCK(pmap); 10074 return (val); 10075 } 10076 10077 static uint64_t 10078 pmap_pcid_alloc(pmap_t pmap, struct pmap_pcid *pcidp) 10079 { 10080 uint32_t gen, new_gen, pcid_next; 10081 10082 CRITICAL_ASSERT(curthread); 10083 gen = PCPU_GET(pcid_gen); 10084 if (pcidp->pm_pcid == PMAP_PCID_KERN) 10085 return (pti ? 0 : CR3_PCID_SAVE); 10086 if (pcidp->pm_gen == gen) 10087 return (CR3_PCID_SAVE); 10088 pcid_next = PCPU_GET(pcid_next); 10089 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) || 10090 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN), 10091 ("cpu %d pcid_next %#x", PCPU_GET(cpuid), pcid_next)); 10092 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) || 10093 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) { 10094 new_gen = gen + 1; 10095 if (new_gen == 0) 10096 new_gen = 1; 10097 PCPU_SET(pcid_gen, new_gen); 10098 pcid_next = PMAP_PCID_KERN + 1; 10099 } else { 10100 new_gen = gen; 10101 } 10102 pcidp->pm_pcid = pcid_next; 10103 pcidp->pm_gen = new_gen; 10104 PCPU_SET(pcid_next, pcid_next + 1); 10105 return (0); 10106 } 10107 10108 static uint64_t 10109 pmap_pcid_alloc_checked(pmap_t pmap, struct pmap_pcid *pcidp) 10110 { 10111 uint64_t cached; 10112 10113 cached = pmap_pcid_alloc(pmap, pcidp); 10114 KASSERT(pcidp->pm_pcid < PMAP_PCID_OVERMAX, 10115 ("pmap %p cpu %d pcid %#x", pmap, PCPU_GET(cpuid), pcidp->pm_pcid)); 10116 KASSERT(pcidp->pm_pcid != PMAP_PCID_KERN || pmap == kernel_pmap, 10117 ("non-kernel pmap pmap %p cpu %d pcid %#x", 10118 pmap, PCPU_GET(cpuid), pcidp->pm_pcid)); 10119 return (cached); 10120 } 10121 10122 static void 10123 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap) 10124 { 10125 10126 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ? 10127 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base; 10128 } 10129 10130 static void 10131 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid) 10132 { 10133 pmap_t old_pmap; 10134 struct pmap_pcid *pcidp, *old_pcidp; 10135 uint64_t cached, cr3, kcr3, ucr3; 10136 10137 KASSERT((read_rflags() & PSL_I) == 0, 10138 ("PCID needs interrupts disabled in pmap_activate_sw()")); 10139 10140 /* See the comment in pmap_invalidate_page_pcid(). */ 10141 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) { 10142 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK); 10143 old_pmap = PCPU_GET(curpmap); 10144 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3); 10145 old_pcidp = zpcpu_get_cpu(old_pmap->pm_pcidp, cpuid); 10146 old_pcidp->pm_gen = 0; 10147 } 10148 10149 pcidp = zpcpu_get_cpu(pmap->pm_pcidp, cpuid); 10150 cached = pmap_pcid_alloc_checked(pmap, pcidp); 10151 cr3 = rcr3(); 10152 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) 10153 load_cr3(pmap->pm_cr3 | pcidp->pm_pcid); 10154 PCPU_SET(curpmap, pmap); 10155 kcr3 = pmap->pm_cr3 | pcidp->pm_pcid; 10156 ucr3 = pmap->pm_ucr3 | pcidp->pm_pcid | PMAP_PCID_USER_PT; 10157 10158 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) 10159 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE); 10160 10161 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE); 10162 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE); 10163 if (cached) 10164 counter_u64_add(pcid_save_cnt, 1); 10165 10166 pmap_activate_sw_pti_post(td, pmap); 10167 } 10168 10169 static void 10170 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap, 10171 u_int cpuid) 10172 { 10173 struct pmap_pcid *pcidp; 10174 uint64_t cached, cr3; 10175 10176 KASSERT((read_rflags() & PSL_I) == 0, 10177 ("PCID needs interrupts disabled in pmap_activate_sw()")); 10178 10179 pcidp = zpcpu_get_cpu(pmap->pm_pcidp, cpuid); 10180 cached = pmap_pcid_alloc_checked(pmap, pcidp); 10181 cr3 = rcr3(); 10182 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) 10183 load_cr3(pmap->pm_cr3 | pcidp->pm_pcid | cached); 10184 PCPU_SET(curpmap, pmap); 10185 if (cached) 10186 counter_u64_add(pcid_save_cnt, 1); 10187 } 10188 10189 static void 10190 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap, 10191 u_int cpuid __unused) 10192 { 10193 10194 load_cr3(pmap->pm_cr3); 10195 PCPU_SET(curpmap, pmap); 10196 } 10197 10198 static void 10199 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap, 10200 u_int cpuid __unused) 10201 { 10202 10203 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid); 10204 PCPU_SET(kcr3, pmap->pm_cr3); 10205 PCPU_SET(ucr3, pmap->pm_ucr3); 10206 pmap_activate_sw_pti_post(td, pmap); 10207 } 10208 10209 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t, 10210 u_int)) 10211 { 10212 10213 if (pmap_pcid_enabled && pti) 10214 return (pmap_activate_sw_pcid_pti); 10215 else if (pmap_pcid_enabled && !pti) 10216 return (pmap_activate_sw_pcid_nopti); 10217 else if (!pmap_pcid_enabled && pti) 10218 return (pmap_activate_sw_nopcid_pti); 10219 else /* if (!pmap_pcid_enabled && !pti) */ 10220 return (pmap_activate_sw_nopcid_nopti); 10221 } 10222 10223 void 10224 pmap_activate_sw(struct thread *td) 10225 { 10226 pmap_t oldpmap, pmap; 10227 u_int cpuid; 10228 10229 oldpmap = PCPU_GET(curpmap); 10230 pmap = vmspace_pmap(td->td_proc->p_vmspace); 10231 if (oldpmap == pmap) { 10232 if (cpu_vendor_id != CPU_VENDOR_INTEL) 10233 mfence(); 10234 return; 10235 } 10236 cpuid = PCPU_GET(cpuid); 10237 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 10238 pmap_activate_sw_mode(td, pmap, cpuid); 10239 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 10240 } 10241 10242 void 10243 pmap_activate(struct thread *td) 10244 { 10245 /* 10246 * invltlb_{invpcid,}_pcid_handler() is used to handle an 10247 * invalidate_all IPI, which checks for curpmap == 10248 * smp_tlb_pmap. The below sequence of operations has a 10249 * window where %CR3 is loaded with the new pmap's PML4 10250 * address, but the curpmap value has not yet been updated. 10251 * This causes the invltlb IPI handler, which is called 10252 * between the updates, to execute as a NOP, which leaves 10253 * stale TLB entries. 10254 * 10255 * Note that the most common use of pmap_activate_sw(), from 10256 * a context switch, is immune to this race, because 10257 * interrupts are disabled (while the thread lock is owned), 10258 * so the IPI is delayed until after curpmap is updated. Protect 10259 * other callers in a similar way, by disabling interrupts 10260 * around the %cr3 register reload and curpmap assignment. 10261 */ 10262 spinlock_enter(); 10263 pmap_activate_sw(td); 10264 spinlock_exit(); 10265 } 10266 10267 void 10268 pmap_activate_boot(pmap_t pmap) 10269 { 10270 uint64_t kcr3; 10271 u_int cpuid; 10272 10273 /* 10274 * kernel_pmap must be never deactivated, and we ensure that 10275 * by never activating it at all. 10276 */ 10277 MPASS(pmap != kernel_pmap); 10278 10279 cpuid = PCPU_GET(cpuid); 10280 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 10281 PCPU_SET(curpmap, pmap); 10282 if (pti) { 10283 kcr3 = pmap->pm_cr3; 10284 if (pmap_pcid_enabled) 10285 kcr3 |= pmap_get_pcid(pmap) | CR3_PCID_SAVE; 10286 } else { 10287 kcr3 = PMAP_NO_CR3; 10288 } 10289 PCPU_SET(kcr3, kcr3); 10290 PCPU_SET(ucr3, PMAP_NO_CR3); 10291 } 10292 10293 void 10294 pmap_active_cpus(pmap_t pmap, cpuset_t *res) 10295 { 10296 *res = pmap->pm_active; 10297 } 10298 10299 void 10300 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 10301 { 10302 } 10303 10304 /* 10305 * Increase the starting virtual address of the given mapping if a 10306 * different alignment might result in more superpage mappings. 10307 */ 10308 void 10309 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 10310 vm_offset_t *addr, vm_size_t size) 10311 { 10312 vm_offset_t superpage_offset; 10313 10314 if (size < NBPDR) 10315 return; 10316 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 10317 offset += ptoa(object->pg_color); 10318 superpage_offset = offset & PDRMASK; 10319 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 10320 (*addr & PDRMASK) == superpage_offset) 10321 return; 10322 if ((*addr & PDRMASK) < superpage_offset) 10323 *addr = (*addr & ~PDRMASK) + superpage_offset; 10324 else 10325 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 10326 } 10327 10328 #ifdef INVARIANTS 10329 static unsigned long num_dirty_emulations; 10330 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW, 10331 &num_dirty_emulations, 0, NULL); 10332 10333 static unsigned long num_accessed_emulations; 10334 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW, 10335 &num_accessed_emulations, 0, NULL); 10336 10337 static unsigned long num_superpage_accessed_emulations; 10338 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW, 10339 &num_superpage_accessed_emulations, 0, NULL); 10340 10341 static unsigned long ad_emulation_superpage_promotions; 10342 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW, 10343 &ad_emulation_superpage_promotions, 0, NULL); 10344 #endif /* INVARIANTS */ 10345 10346 int 10347 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype) 10348 { 10349 int rv; 10350 struct rwlock *lock; 10351 #if VM_NRESERVLEVEL > 0 10352 vm_page_t m, mpte; 10353 #endif 10354 pd_entry_t *pde; 10355 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V; 10356 10357 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE, 10358 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype)); 10359 10360 if (!pmap_emulate_ad_bits(pmap)) 10361 return (-1); 10362 10363 PG_A = pmap_accessed_bit(pmap); 10364 PG_M = pmap_modified_bit(pmap); 10365 PG_V = pmap_valid_bit(pmap); 10366 PG_RW = pmap_rw_bit(pmap); 10367 10368 rv = -1; 10369 lock = NULL; 10370 PMAP_LOCK(pmap); 10371 10372 pde = pmap_pde(pmap, va); 10373 if (pde == NULL || (*pde & PG_V) == 0) 10374 goto done; 10375 10376 if ((*pde & PG_PS) != 0) { 10377 if (ftype == VM_PROT_READ) { 10378 #ifdef INVARIANTS 10379 atomic_add_long(&num_superpage_accessed_emulations, 1); 10380 #endif 10381 *pde |= PG_A; 10382 rv = 0; 10383 } 10384 goto done; 10385 } 10386 10387 pte = pmap_pde_to_pte(pde, va); 10388 if ((*pte & PG_V) == 0) 10389 goto done; 10390 10391 if (ftype == VM_PROT_WRITE) { 10392 if ((*pte & PG_RW) == 0) 10393 goto done; 10394 /* 10395 * Set the modified and accessed bits simultaneously. 10396 * 10397 * Intel EPT PTEs that do software emulation of A/D bits map 10398 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively. 10399 * An EPT misconfiguration is triggered if the PTE is writable 10400 * but not readable (WR=10). This is avoided by setting PG_A 10401 * and PG_M simultaneously. 10402 */ 10403 *pte |= PG_M | PG_A; 10404 } else { 10405 *pte |= PG_A; 10406 } 10407 10408 #if VM_NRESERVLEVEL > 0 10409 /* try to promote the mapping */ 10410 if (va < VM_MAXUSER_ADDRESS) 10411 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 10412 else 10413 mpte = NULL; 10414 10415 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 10416 10417 if ((mpte == NULL || mpte->ref_count == NPTEPG) && 10418 (m->flags & PG_FICTITIOUS) == 0 && 10419 vm_reserv_level_iffullpop(m) == 0 && 10420 pmap_promote_pde(pmap, pde, va, mpte, &lock)) { 10421 #ifdef INVARIANTS 10422 atomic_add_long(&ad_emulation_superpage_promotions, 1); 10423 #endif 10424 } 10425 #endif 10426 10427 #ifdef INVARIANTS 10428 if (ftype == VM_PROT_WRITE) 10429 atomic_add_long(&num_dirty_emulations, 1); 10430 else 10431 atomic_add_long(&num_accessed_emulations, 1); 10432 #endif 10433 rv = 0; /* success */ 10434 done: 10435 if (lock != NULL) 10436 rw_wunlock(lock); 10437 PMAP_UNLOCK(pmap); 10438 return (rv); 10439 } 10440 10441 void 10442 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num) 10443 { 10444 pml4_entry_t *pml4; 10445 pdp_entry_t *pdp; 10446 pd_entry_t *pde; 10447 pt_entry_t *pte, PG_V; 10448 int idx; 10449 10450 idx = 0; 10451 PG_V = pmap_valid_bit(pmap); 10452 PMAP_LOCK(pmap); 10453 10454 pml4 = pmap_pml4e(pmap, va); 10455 if (pml4 == NULL) 10456 goto done; 10457 ptr[idx++] = *pml4; 10458 if ((*pml4 & PG_V) == 0) 10459 goto done; 10460 10461 pdp = pmap_pml4e_to_pdpe(pml4, va); 10462 ptr[idx++] = *pdp; 10463 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) 10464 goto done; 10465 10466 pde = pmap_pdpe_to_pde(pdp, va); 10467 ptr[idx++] = *pde; 10468 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) 10469 goto done; 10470 10471 pte = pmap_pde_to_pte(pde, va); 10472 ptr[idx++] = *pte; 10473 10474 done: 10475 PMAP_UNLOCK(pmap); 10476 *num = idx; 10477 } 10478 10479 /** 10480 * Get the kernel virtual address of a set of physical pages. If there are 10481 * physical addresses not covered by the DMAP perform a transient mapping 10482 * that will be removed when calling pmap_unmap_io_transient. 10483 * 10484 * \param page The pages the caller wishes to obtain the virtual 10485 * address on the kernel memory map. 10486 * \param vaddr On return contains the kernel virtual memory address 10487 * of the pages passed in the page parameter. 10488 * \param count Number of pages passed in. 10489 * \param can_fault true if the thread using the mapped pages can take 10490 * page faults, false otherwise. 10491 * 10492 * \returns true if the caller must call pmap_unmap_io_transient when 10493 * finished or false otherwise. 10494 * 10495 */ 10496 bool 10497 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 10498 bool can_fault) 10499 { 10500 vm_paddr_t paddr; 10501 bool needs_mapping; 10502 int error __unused, i; 10503 10504 /* 10505 * Allocate any KVA space that we need, this is done in a separate 10506 * loop to prevent calling vmem_alloc while pinned. 10507 */ 10508 needs_mapping = false; 10509 for (i = 0; i < count; i++) { 10510 paddr = VM_PAGE_TO_PHYS(page[i]); 10511 if (__predict_false(paddr >= dmaplimit)) { 10512 error = vmem_alloc(kernel_arena, PAGE_SIZE, 10513 M_BESTFIT | M_WAITOK, &vaddr[i]); 10514 KASSERT(error == 0, ("vmem_alloc failed: %d", error)); 10515 needs_mapping = true; 10516 } else { 10517 vaddr[i] = PHYS_TO_DMAP(paddr); 10518 } 10519 } 10520 10521 /* Exit early if everything is covered by the DMAP */ 10522 if (!needs_mapping) 10523 return (false); 10524 10525 /* 10526 * NB: The sequence of updating a page table followed by accesses 10527 * to the corresponding pages used in the !DMAP case is subject to 10528 * the situation described in the "AMD64 Architecture Programmer's 10529 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special 10530 * Coherency Considerations". Therefore, issuing the INVLPG right 10531 * after modifying the PTE bits is crucial. 10532 */ 10533 if (!can_fault) 10534 sched_pin(); 10535 for (i = 0; i < count; i++) { 10536 paddr = VM_PAGE_TO_PHYS(page[i]); 10537 if (paddr >= dmaplimit) { 10538 if (can_fault) { 10539 /* 10540 * Slow path, since we can get page faults 10541 * while mappings are active don't pin the 10542 * thread to the CPU and instead add a global 10543 * mapping visible to all CPUs. 10544 */ 10545 pmap_qenter(vaddr[i], &page[i], 1); 10546 } else { 10547 pmap_kenter_attr(vaddr[i], paddr, 10548 page[i]->md.pat_mode); 10549 pmap_invlpg(kernel_pmap, vaddr[i]); 10550 } 10551 } 10552 } 10553 10554 return (needs_mapping); 10555 } 10556 10557 void 10558 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 10559 bool can_fault) 10560 { 10561 vm_paddr_t paddr; 10562 int i; 10563 10564 if (!can_fault) 10565 sched_unpin(); 10566 for (i = 0; i < count; i++) { 10567 paddr = VM_PAGE_TO_PHYS(page[i]); 10568 if (paddr >= dmaplimit) { 10569 if (can_fault) 10570 pmap_qremove(vaddr[i], 1); 10571 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE); 10572 } 10573 } 10574 } 10575 10576 vm_offset_t 10577 pmap_quick_enter_page(vm_page_t m) 10578 { 10579 vm_paddr_t paddr; 10580 10581 paddr = VM_PAGE_TO_PHYS(m); 10582 if (paddr < dmaplimit) 10583 return (PHYS_TO_DMAP(paddr)); 10584 mtx_lock_spin(&qframe_mtx); 10585 KASSERT(*vtopte(qframe) == 0, ("qframe busy")); 10586 10587 /* 10588 * Since qframe is exclusively mapped by us, and we do not set 10589 * PG_G, we can use INVLPG here. 10590 */ 10591 invlpg(qframe); 10592 10593 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A | 10594 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, false)); 10595 return (qframe); 10596 } 10597 10598 void 10599 pmap_quick_remove_page(vm_offset_t addr) 10600 { 10601 10602 if (addr != qframe) 10603 return; 10604 pte_store(vtopte(qframe), 0); 10605 mtx_unlock_spin(&qframe_mtx); 10606 } 10607 10608 /* 10609 * Pdp pages from the large map are managed differently from either 10610 * kernel or user page table pages. They are permanently allocated at 10611 * initialization time, and their reference count is permanently set to 10612 * zero. The pml4 entries pointing to those pages are copied into 10613 * each allocated pmap. 10614 * 10615 * In contrast, pd and pt pages are managed like user page table 10616 * pages. They are dynamically allocated, and their reference count 10617 * represents the number of valid entries within the page. 10618 */ 10619 static vm_page_t 10620 pmap_large_map_getptp_unlocked(void) 10621 { 10622 return (pmap_alloc_pt_page(kernel_pmap, 0, VM_ALLOC_ZERO)); 10623 } 10624 10625 static vm_page_t 10626 pmap_large_map_getptp(void) 10627 { 10628 vm_page_t m; 10629 10630 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 10631 m = pmap_large_map_getptp_unlocked(); 10632 if (m == NULL) { 10633 PMAP_UNLOCK(kernel_pmap); 10634 vm_wait(NULL); 10635 PMAP_LOCK(kernel_pmap); 10636 /* Callers retry. */ 10637 } 10638 return (m); 10639 } 10640 10641 static pdp_entry_t * 10642 pmap_large_map_pdpe(vm_offset_t va) 10643 { 10644 pml4_entry_t *pml4; 10645 vm_pindex_t pml4_idx; 10646 vm_paddr_t mphys; 10647 10648 KASSERT(va >= kva_layout.lm_low && va < kva_layout.lm_low + 10649 (vm_offset_t)NBPML4 * lm_ents, ("va %#lx not in large map", va)); 10650 if (la57) { 10651 pml4 = pmap_pml4e(kernel_pmap, va); 10652 mphys = *pml4 & PG_FRAME; 10653 } else { 10654 pml4_idx = pmap_pml4e_index(va); 10655 10656 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents, 10657 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx " 10658 "LMSPML4I %#jx lm_ents %d", 10659 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents)); 10660 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0, 10661 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx " 10662 "LMSPML4I %#jx lm_ents %d", 10663 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents)); 10664 mphys = kernel_pml4[pml4_idx] & PG_FRAME; 10665 } 10666 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va)); 10667 } 10668 10669 static pd_entry_t * 10670 pmap_large_map_pde(vm_offset_t va) 10671 { 10672 pdp_entry_t *pdpe; 10673 vm_page_t m; 10674 vm_paddr_t mphys; 10675 10676 retry: 10677 pdpe = pmap_large_map_pdpe(va); 10678 if (*pdpe == 0) { 10679 m = pmap_large_map_getptp(); 10680 if (m == NULL) 10681 goto retry; 10682 mphys = VM_PAGE_TO_PHYS(m); 10683 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx; 10684 } else { 10685 MPASS((*pdpe & X86_PG_PS) == 0); 10686 mphys = *pdpe & PG_FRAME; 10687 } 10688 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va)); 10689 } 10690 10691 static pt_entry_t * 10692 pmap_large_map_pte(vm_offset_t va) 10693 { 10694 pd_entry_t *pde; 10695 vm_page_t m; 10696 vm_paddr_t mphys; 10697 10698 retry: 10699 pde = pmap_large_map_pde(va); 10700 if (*pde == 0) { 10701 m = pmap_large_map_getptp(); 10702 if (m == NULL) 10703 goto retry; 10704 mphys = VM_PAGE_TO_PHYS(m); 10705 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx; 10706 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++; 10707 } else { 10708 MPASS((*pde & X86_PG_PS) == 0); 10709 mphys = *pde & PG_FRAME; 10710 } 10711 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va)); 10712 } 10713 10714 static vm_paddr_t 10715 pmap_large_map_kextract(vm_offset_t va) 10716 { 10717 pdp_entry_t *pdpe, pdp; 10718 pd_entry_t *pde, pd; 10719 pt_entry_t *pte, pt; 10720 10721 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va), 10722 ("not largemap range %#lx", (u_long)va)); 10723 pdpe = pmap_large_map_pdpe(va); 10724 pdp = *pdpe; 10725 KASSERT((pdp & X86_PG_V) != 0, 10726 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va, 10727 (u_long)pdpe, pdp)); 10728 if ((pdp & X86_PG_PS) != 0) { 10729 KASSERT((amd_feature & AMDID_PAGE1GB) != 0, 10730 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va, 10731 (u_long)pdpe, pdp)); 10732 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK)); 10733 } 10734 pde = pmap_pdpe_to_pde(pdpe, va); 10735 pd = *pde; 10736 KASSERT((pd & X86_PG_V) != 0, 10737 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd)); 10738 if ((pd & X86_PG_PS) != 0) 10739 return ((pd & PG_PS_FRAME) | (va & PDRMASK)); 10740 pte = pmap_pde_to_pte(pde, va); 10741 pt = *pte; 10742 KASSERT((pt & X86_PG_V) != 0, 10743 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt)); 10744 return ((pt & PG_FRAME) | (va & PAGE_MASK)); 10745 } 10746 10747 static int 10748 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase, 10749 vmem_addr_t *vmem_res) 10750 { 10751 10752 /* 10753 * Large mappings are all but static. Consequently, there 10754 * is no point in waiting for an earlier allocation to be 10755 * freed. 10756 */ 10757 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN, 10758 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res)); 10759 } 10760 10761 int 10762 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr, 10763 vm_memattr_t mattr) 10764 { 10765 pdp_entry_t *pdpe; 10766 pd_entry_t *pde; 10767 pt_entry_t *pte; 10768 vm_offset_t va, inc; 10769 vmem_addr_t vmem_res; 10770 vm_paddr_t pa; 10771 int error; 10772 10773 if (len == 0 || spa + len < spa) 10774 return (EINVAL); 10775 10776 /* See if DMAP can serve. */ 10777 if (spa + len <= dmaplimit) { 10778 va = PHYS_TO_DMAP(spa); 10779 *addr = (void *)va; 10780 return (pmap_change_attr(va, len, mattr)); 10781 } 10782 10783 /* 10784 * No, allocate KVA. Fit the address with best possible 10785 * alignment for superpages. Fall back to worse align if 10786 * failed. 10787 */ 10788 error = ENOMEM; 10789 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len, 10790 NBPDP) >= roundup2(spa, NBPDP) + NBPDP) 10791 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK, 10792 &vmem_res); 10793 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa, 10794 NBPDR) + NBPDR) 10795 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK, 10796 &vmem_res); 10797 if (error != 0) 10798 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res); 10799 if (error != 0) 10800 return (error); 10801 10802 /* 10803 * Fill pagetable. PG_M is not pre-set, we scan modified bits 10804 * in the pagetable to minimize flushing. No need to 10805 * invalidate TLB, since we only update invalid entries. 10806 */ 10807 PMAP_LOCK(kernel_pmap); 10808 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc, 10809 len -= inc) { 10810 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP && 10811 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) { 10812 pdpe = pmap_large_map_pdpe(va); 10813 MPASS(*pdpe == 0); 10814 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW | 10815 X86_PG_V | X86_PG_A | pg_nx | 10816 pmap_cache_bits(kernel_pmap, mattr, true); 10817 inc = NBPDP; 10818 } else if (len >= NBPDR && (pa & PDRMASK) == 0 && 10819 (va & PDRMASK) == 0) { 10820 pde = pmap_large_map_pde(va); 10821 MPASS(*pde == 0); 10822 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW | 10823 X86_PG_V | X86_PG_A | pg_nx | 10824 pmap_cache_bits(kernel_pmap, mattr, true); 10825 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))-> 10826 ref_count++; 10827 inc = NBPDR; 10828 } else { 10829 pte = pmap_large_map_pte(va); 10830 MPASS(*pte == 0); 10831 *pte = pa | pg_g | X86_PG_RW | X86_PG_V | 10832 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap, 10833 mattr, false); 10834 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))-> 10835 ref_count++; 10836 inc = PAGE_SIZE; 10837 } 10838 } 10839 PMAP_UNLOCK(kernel_pmap); 10840 MPASS(len == 0); 10841 10842 *addr = (void *)vmem_res; 10843 return (0); 10844 } 10845 10846 void 10847 pmap_large_unmap(void *svaa, vm_size_t len) 10848 { 10849 vm_offset_t sva, va; 10850 vm_size_t inc; 10851 pdp_entry_t *pdpe, pdp; 10852 pd_entry_t *pde, pd; 10853 pt_entry_t *pte; 10854 vm_page_t m; 10855 struct spglist spgf; 10856 10857 sva = (vm_offset_t)svaa; 10858 if (len == 0 || sva + len < sva || (sva >= kva_layout.dmap_low && 10859 sva + len < kva_layout.dmap_high)) 10860 return; 10861 10862 SLIST_INIT(&spgf); 10863 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) && 10864 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1), 10865 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len)); 10866 PMAP_LOCK(kernel_pmap); 10867 for (va = sva; va < sva + len; va += inc) { 10868 pdpe = pmap_large_map_pdpe(va); 10869 pdp = *pdpe; 10870 KASSERT((pdp & X86_PG_V) != 0, 10871 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va, 10872 (u_long)pdpe, pdp)); 10873 if ((pdp & X86_PG_PS) != 0) { 10874 KASSERT((amd_feature & AMDID_PAGE1GB) != 0, 10875 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va, 10876 (u_long)pdpe, pdp)); 10877 KASSERT((va & PDPMASK) == 0, 10878 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va, 10879 (u_long)pdpe, pdp)); 10880 KASSERT(va + NBPDP <= sva + len, 10881 ("unmap covers partial 1GB page, sva %#lx va %#lx " 10882 "pdpe %#lx pdp %#lx len %#lx", sva, va, 10883 (u_long)pdpe, pdp, len)); 10884 *pdpe = 0; 10885 inc = NBPDP; 10886 continue; 10887 } 10888 pde = pmap_pdpe_to_pde(pdpe, va); 10889 pd = *pde; 10890 KASSERT((pd & X86_PG_V) != 0, 10891 ("invalid pd va %#lx pde %#lx pd %#lx", va, 10892 (u_long)pde, pd)); 10893 if ((pd & X86_PG_PS) != 0) { 10894 KASSERT((va & PDRMASK) == 0, 10895 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va, 10896 (u_long)pde, pd)); 10897 KASSERT(va + NBPDR <= sva + len, 10898 ("unmap covers partial 2MB page, sva %#lx va %#lx " 10899 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde, 10900 pd, len)); 10901 pde_store(pde, 0); 10902 inc = NBPDR; 10903 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde)); 10904 m->ref_count--; 10905 if (m->ref_count == 0) { 10906 *pdpe = 0; 10907 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss); 10908 } 10909 continue; 10910 } 10911 pte = pmap_pde_to_pte(pde, va); 10912 KASSERT((*pte & X86_PG_V) != 0, 10913 ("invalid pte va %#lx pte %#lx pt %#lx", va, 10914 (u_long)pte, *pte)); 10915 pte_clear(pte); 10916 inc = PAGE_SIZE; 10917 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte)); 10918 m->ref_count--; 10919 if (m->ref_count == 0) { 10920 *pde = 0; 10921 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss); 10922 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde)); 10923 m->ref_count--; 10924 if (m->ref_count == 0) { 10925 *pdpe = 0; 10926 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss); 10927 } 10928 } 10929 } 10930 pmap_invalidate_range(kernel_pmap, sva, sva + len); 10931 PMAP_UNLOCK(kernel_pmap); 10932 vm_page_free_pages_toq(&spgf, false); 10933 vmem_free(large_vmem, sva, len); 10934 } 10935 10936 static void 10937 pmap_large_map_wb_fence_mfence(void) 10938 { 10939 10940 mfence(); 10941 } 10942 10943 static void 10944 pmap_large_map_wb_fence_atomic(void) 10945 { 10946 10947 atomic_thread_fence_seq_cst(); 10948 } 10949 10950 static void 10951 pmap_large_map_wb_fence_nop(void) 10952 { 10953 } 10954 10955 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void)) 10956 { 10957 10958 if (cpu_vendor_id != CPU_VENDOR_INTEL) 10959 return (pmap_large_map_wb_fence_mfence); 10960 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB | 10961 CPUID_STDEXT_CLFLUSHOPT)) == 0) 10962 return (pmap_large_map_wb_fence_atomic); 10963 else 10964 /* clflush is strongly enough ordered */ 10965 return (pmap_large_map_wb_fence_nop); 10966 } 10967 10968 static void 10969 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len) 10970 { 10971 10972 for (; len > 0; len -= cpu_clflush_line_size, 10973 va += cpu_clflush_line_size) 10974 clwb(va); 10975 } 10976 10977 static void 10978 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len) 10979 { 10980 10981 for (; len > 0; len -= cpu_clflush_line_size, 10982 va += cpu_clflush_line_size) 10983 clflushopt(va); 10984 } 10985 10986 static void 10987 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len) 10988 { 10989 10990 for (; len > 0; len -= cpu_clflush_line_size, 10991 va += cpu_clflush_line_size) 10992 clflush(va); 10993 } 10994 10995 static void 10996 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused) 10997 { 10998 } 10999 11000 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t)) 11001 { 11002 11003 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0) 11004 return (pmap_large_map_flush_range_clwb); 11005 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) 11006 return (pmap_large_map_flush_range_clflushopt); 11007 else if ((cpu_feature & CPUID_CLFSH) != 0) 11008 return (pmap_large_map_flush_range_clflush); 11009 else 11010 return (pmap_large_map_flush_range_nop); 11011 } 11012 11013 static void 11014 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva) 11015 { 11016 volatile u_long *pe; 11017 u_long p; 11018 vm_offset_t va; 11019 vm_size_t inc; 11020 bool seen_other; 11021 11022 for (va = sva; va < eva; va += inc) { 11023 inc = 0; 11024 if ((amd_feature & AMDID_PAGE1GB) != 0) { 11025 pe = (volatile u_long *)pmap_large_map_pdpe(va); 11026 p = *pe; 11027 if ((p & X86_PG_PS) != 0) 11028 inc = NBPDP; 11029 } 11030 if (inc == 0) { 11031 pe = (volatile u_long *)pmap_large_map_pde(va); 11032 p = *pe; 11033 if ((p & X86_PG_PS) != 0) 11034 inc = NBPDR; 11035 } 11036 if (inc == 0) { 11037 pe = (volatile u_long *)pmap_large_map_pte(va); 11038 p = *pe; 11039 inc = PAGE_SIZE; 11040 } 11041 seen_other = false; 11042 for (;;) { 11043 if ((p & X86_PG_AVAIL1) != 0) { 11044 /* 11045 * Spin-wait for the end of a parallel 11046 * write-back. 11047 */ 11048 cpu_spinwait(); 11049 p = *pe; 11050 11051 /* 11052 * If we saw other write-back 11053 * occurring, we cannot rely on PG_M to 11054 * indicate state of the cache. The 11055 * PG_M bit is cleared before the 11056 * flush to avoid ignoring new writes, 11057 * and writes which are relevant for 11058 * us might happen after. 11059 */ 11060 seen_other = true; 11061 continue; 11062 } 11063 11064 if ((p & X86_PG_M) != 0 || seen_other) { 11065 if (!atomic_fcmpset_long(pe, &p, 11066 (p & ~X86_PG_M) | X86_PG_AVAIL1)) 11067 /* 11068 * If we saw PG_M without 11069 * PG_AVAIL1, and then on the 11070 * next attempt we do not 11071 * observe either PG_M or 11072 * PG_AVAIL1, the other 11073 * write-back started after us 11074 * and finished before us. We 11075 * can rely on it doing our 11076 * work. 11077 */ 11078 continue; 11079 pmap_large_map_flush_range(va, inc); 11080 atomic_clear_long(pe, X86_PG_AVAIL1); 11081 } 11082 break; 11083 } 11084 maybe_yield(); 11085 } 11086 } 11087 11088 /* 11089 * Write-back cache lines for the given address range. 11090 * 11091 * Must be called only on the range or sub-range returned from 11092 * pmap_large_map(). Must not be called on the coalesced ranges. 11093 * 11094 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH 11095 * instructions support. 11096 */ 11097 void 11098 pmap_large_map_wb(void *svap, vm_size_t len) 11099 { 11100 vm_offset_t eva, sva; 11101 11102 sva = (vm_offset_t)svap; 11103 eva = sva + len; 11104 pmap_large_map_wb_fence(); 11105 if (sva >= kva_layout.dmap_low && eva < kva_layout.dmap_high) { 11106 pmap_large_map_flush_range(sva, len); 11107 } else { 11108 KASSERT(sva >= kva_layout.lm_low && eva < kva_layout.lm_high, 11109 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len)); 11110 pmap_large_map_wb_large(sva, eva); 11111 } 11112 pmap_large_map_wb_fence(); 11113 } 11114 11115 static vm_page_t 11116 pmap_pti_alloc_page(void) 11117 { 11118 vm_page_t m; 11119 11120 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11121 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_WIRED | VM_ALLOC_ZERO); 11122 return (m); 11123 } 11124 11125 static bool 11126 pmap_pti_free_page(vm_page_t m) 11127 { 11128 if (!vm_page_unwire_noq(m)) 11129 return (false); 11130 vm_page_xbusy_claim(m); 11131 vm_page_free_zero(m); 11132 return (true); 11133 } 11134 11135 static void 11136 pmap_pti_init(void) 11137 { 11138 vm_page_t pml4_pg; 11139 pdp_entry_t *pdpe; 11140 vm_offset_t va; 11141 int i; 11142 11143 if (!pti) 11144 return; 11145 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL); 11146 VM_OBJECT_WLOCK(pti_obj); 11147 pml4_pg = pmap_pti_alloc_page(); 11148 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg)); 11149 for (va = kva_layout.km_low; va <= kva_layout.km_high && 11150 va >= kva_layout.km_low && va > NBPML4; va += NBPML4) { 11151 pdpe = pmap_pti_pdpe(va); 11152 pmap_pti_wire_pte(pdpe); 11153 } 11154 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0], 11155 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false); 11156 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt + 11157 sizeof(struct gate_descriptor) * NIDT, false); 11158 CPU_FOREACH(i) { 11159 /* Doublefault stack IST 1 */ 11160 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu); 11161 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false); 11162 /* NMI stack IST 2 */ 11163 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu); 11164 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false); 11165 /* MC# stack IST 3 */ 11166 va = __pcpu[i].pc_common_tss.tss_ist3 + 11167 sizeof(struct nmi_pcpu); 11168 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false); 11169 /* DB# stack IST 4 */ 11170 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu); 11171 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false); 11172 } 11173 pmap_pti_add_kva_locked((vm_offset_t)KERNSTART, (vm_offset_t)etext, 11174 true); 11175 pti_finalized = true; 11176 VM_OBJECT_WUNLOCK(pti_obj); 11177 } 11178 11179 static void 11180 pmap_cpu_init(void *arg __unused) 11181 { 11182 CPU_COPY(&all_cpus, &kernel_pmap->pm_active); 11183 pmap_pti_init(); 11184 } 11185 SYSINIT(pmap_cpu, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_cpu_init, NULL); 11186 11187 static pdp_entry_t * 11188 pmap_pti_pdpe(vm_offset_t va) 11189 { 11190 pml4_entry_t *pml4e; 11191 pdp_entry_t *pdpe; 11192 vm_page_t m; 11193 vm_pindex_t pml4_idx; 11194 vm_paddr_t mphys; 11195 11196 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11197 11198 pml4_idx = pmap_pml4e_index(va); 11199 pml4e = &pti_pml4[pml4_idx]; 11200 m = NULL; 11201 if (*pml4e == 0) { 11202 if (pti_finalized) 11203 panic("pml4 alloc after finalization\n"); 11204 m = pmap_pti_alloc_page(); 11205 if (*pml4e != 0) { 11206 pmap_pti_free_page(m); 11207 mphys = *pml4e & ~PAGE_MASK; 11208 } else { 11209 mphys = VM_PAGE_TO_PHYS(m); 11210 *pml4e = mphys | X86_PG_RW | X86_PG_V; 11211 } 11212 } else { 11213 mphys = *pml4e & ~PAGE_MASK; 11214 } 11215 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va); 11216 return (pdpe); 11217 } 11218 11219 static void 11220 pmap_pti_wire_pte(void *pte) 11221 { 11222 vm_page_t m; 11223 11224 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11225 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte)); 11226 m->ref_count++; 11227 } 11228 11229 static void 11230 pmap_pti_unwire_pde(void *pde, bool only_ref) 11231 { 11232 vm_page_t m; 11233 11234 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11235 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde)); 11236 MPASS(only_ref || m->ref_count > 1); 11237 pmap_pti_free_page(m); 11238 } 11239 11240 static void 11241 pmap_pti_unwire_pte(void *pte, vm_offset_t va) 11242 { 11243 vm_page_t m; 11244 pd_entry_t *pde; 11245 11246 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11247 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte)); 11248 if (pmap_pti_free_page(m)) { 11249 pde = pmap_pti_pde(va); 11250 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V); 11251 *pde = 0; 11252 pmap_pti_unwire_pde(pde, false); 11253 } 11254 } 11255 11256 static pd_entry_t * 11257 pmap_pti_pde(vm_offset_t va) 11258 { 11259 pdp_entry_t *pdpe; 11260 pd_entry_t *pde; 11261 vm_page_t m; 11262 vm_pindex_t pd_idx; 11263 vm_paddr_t mphys; 11264 11265 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11266 11267 pdpe = pmap_pti_pdpe(va); 11268 if (*pdpe == 0) { 11269 m = pmap_pti_alloc_page(); 11270 if (*pdpe != 0) { 11271 pmap_pti_free_page(m); 11272 MPASS((*pdpe & X86_PG_PS) == 0); 11273 mphys = *pdpe & ~PAGE_MASK; 11274 } else { 11275 mphys = VM_PAGE_TO_PHYS(m); 11276 *pdpe = mphys | X86_PG_RW | X86_PG_V; 11277 } 11278 } else { 11279 MPASS((*pdpe & X86_PG_PS) == 0); 11280 mphys = *pdpe & ~PAGE_MASK; 11281 } 11282 11283 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys); 11284 pd_idx = pmap_pde_index(va); 11285 pde += pd_idx; 11286 return (pde); 11287 } 11288 11289 static pt_entry_t * 11290 pmap_pti_pte(vm_offset_t va, bool *unwire_pde) 11291 { 11292 pd_entry_t *pde; 11293 pt_entry_t *pte; 11294 vm_page_t m; 11295 vm_paddr_t mphys; 11296 11297 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11298 11299 pde = pmap_pti_pde(va); 11300 if (unwire_pde != NULL) { 11301 *unwire_pde = true; 11302 pmap_pti_wire_pte(pde); 11303 } 11304 if (*pde == 0) { 11305 m = pmap_pti_alloc_page(); 11306 if (*pde != 0) { 11307 pmap_pti_free_page(m); 11308 MPASS((*pde & X86_PG_PS) == 0); 11309 mphys = *pde & ~(PAGE_MASK | pg_nx); 11310 } else { 11311 mphys = VM_PAGE_TO_PHYS(m); 11312 *pde = mphys | X86_PG_RW | X86_PG_V; 11313 if (unwire_pde != NULL) 11314 *unwire_pde = false; 11315 } 11316 } else { 11317 MPASS((*pde & X86_PG_PS) == 0); 11318 mphys = *pde & ~(PAGE_MASK | pg_nx); 11319 } 11320 11321 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys); 11322 pte += pmap_pte_index(va); 11323 11324 return (pte); 11325 } 11326 11327 static void 11328 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec) 11329 { 11330 vm_paddr_t pa; 11331 pd_entry_t *pde; 11332 pt_entry_t *pte, ptev; 11333 bool unwire_pde; 11334 11335 VM_OBJECT_ASSERT_WLOCKED(pti_obj); 11336 11337 sva = trunc_page(sva); 11338 MPASS(sva > VM_MAXUSER_ADDRESS); 11339 eva = round_page(eva); 11340 MPASS(sva < eva); 11341 for (; sva < eva; sva += PAGE_SIZE) { 11342 pte = pmap_pti_pte(sva, &unwire_pde); 11343 pa = pmap_kextract(sva); 11344 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G | 11345 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap, 11346 VM_MEMATTR_DEFAULT, false); 11347 if (*pte == 0) { 11348 pte_store(pte, ptev); 11349 pmap_pti_wire_pte(pte); 11350 } else { 11351 KASSERT(!pti_finalized, 11352 ("pti overlap after fin %#lx %#lx %#lx", 11353 sva, *pte, ptev)); 11354 KASSERT(*pte == ptev, 11355 ("pti non-identical pte after fin %#lx %#lx %#lx", 11356 sva, *pte, ptev)); 11357 } 11358 if (unwire_pde) { 11359 pde = pmap_pti_pde(sva); 11360 pmap_pti_unwire_pde(pde, true); 11361 } 11362 } 11363 } 11364 11365 void 11366 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec) 11367 { 11368 11369 if (!pti) 11370 return; 11371 VM_OBJECT_WLOCK(pti_obj); 11372 pmap_pti_add_kva_locked(sva, eva, exec); 11373 VM_OBJECT_WUNLOCK(pti_obj); 11374 } 11375 11376 void 11377 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva) 11378 { 11379 pt_entry_t *pte; 11380 vm_offset_t va; 11381 11382 if (!pti) 11383 return; 11384 sva = rounddown2(sva, PAGE_SIZE); 11385 MPASS(sva > VM_MAXUSER_ADDRESS); 11386 eva = roundup2(eva, PAGE_SIZE); 11387 MPASS(sva < eva); 11388 VM_OBJECT_WLOCK(pti_obj); 11389 for (va = sva; va < eva; va += PAGE_SIZE) { 11390 pte = pmap_pti_pte(va, NULL); 11391 KASSERT((*pte & X86_PG_V) != 0, 11392 ("invalid pte va %#lx pte %#lx pt %#lx", va, 11393 (u_long)pte, *pte)); 11394 pte_clear(pte); 11395 pmap_pti_unwire_pte(pte, va); 11396 } 11397 pmap_invalidate_range(kernel_pmap, sva, eva); 11398 VM_OBJECT_WUNLOCK(pti_obj); 11399 } 11400 11401 static void * 11402 pkru_dup_range(void *ctx __unused, void *data) 11403 { 11404 struct pmap_pkru_range *node, *new_node; 11405 11406 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT); 11407 if (new_node == NULL) 11408 return (NULL); 11409 node = data; 11410 memcpy(new_node, node, sizeof(*node)); 11411 return (new_node); 11412 } 11413 11414 static void 11415 pkru_free_range(void *ctx __unused, void *node) 11416 { 11417 11418 uma_zfree(pmap_pkru_ranges_zone, node); 11419 } 11420 11421 static int 11422 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx, 11423 int flags) 11424 { 11425 struct pmap_pkru_range *ppr; 11426 int error; 11427 11428 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11429 MPASS(pmap->pm_type == PT_X86); 11430 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0); 11431 if ((flags & AMD64_PKRU_EXCL) != 0 && 11432 !rangeset_check_empty(&pmap->pm_pkru, sva, eva)) 11433 return (EBUSY); 11434 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT); 11435 if (ppr == NULL) 11436 return (ENOMEM); 11437 ppr->pkru_keyidx = keyidx; 11438 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST; 11439 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr); 11440 if (error != 0) 11441 uma_zfree(pmap_pkru_ranges_zone, ppr); 11442 return (error); 11443 } 11444 11445 static int 11446 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 11447 { 11448 11449 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11450 MPASS(pmap->pm_type == PT_X86); 11451 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0); 11452 return (rangeset_remove(&pmap->pm_pkru, sva, eva)); 11453 } 11454 11455 static void 11456 pmap_pkru_deassign_all(pmap_t pmap) 11457 { 11458 11459 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11460 if (pmap->pm_type == PT_X86 && 11461 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) 11462 rangeset_remove_all(&pmap->pm_pkru); 11463 } 11464 11465 /* 11466 * Returns true if the PKU setting is the same across the specified address 11467 * range, and false otherwise. When returning true, updates the referenced PTE 11468 * to reflect the PKU setting. 11469 */ 11470 static bool 11471 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t *pte) 11472 { 11473 struct pmap_pkru_range *ppr; 11474 vm_offset_t va; 11475 u_int keyidx; 11476 11477 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11478 KASSERT(pmap->pm_type != PT_X86 || (*pte & X86_PG_PKU_MASK) == 0, 11479 ("pte %p has unexpected PKU %ld", pte, *pte & X86_PG_PKU_MASK)); 11480 if (pmap->pm_type != PT_X86 || 11481 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 || 11482 sva >= VM_MAXUSER_ADDRESS) 11483 return (true); 11484 MPASS(eva <= VM_MAXUSER_ADDRESS); 11485 ppr = rangeset_containing(&pmap->pm_pkru, sva); 11486 if (ppr == NULL) 11487 return (rangeset_empty(&pmap->pm_pkru, sva, eva)); 11488 keyidx = ppr->pkru_keyidx; 11489 while ((va = ppr->pkru_rs_el.re_end) < eva) { 11490 if ((ppr = rangeset_beginning(&pmap->pm_pkru, va)) == NULL || 11491 keyidx != ppr->pkru_keyidx) 11492 return (false); 11493 } 11494 *pte |= X86_PG_PKU(keyidx); 11495 return (true); 11496 } 11497 11498 static pt_entry_t 11499 pmap_pkru_get(pmap_t pmap, vm_offset_t va) 11500 { 11501 struct pmap_pkru_range *ppr; 11502 11503 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11504 if (pmap->pm_type != PT_X86 || 11505 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 || 11506 va >= VM_MAXUSER_ADDRESS) 11507 return (0); 11508 ppr = rangeset_containing(&pmap->pm_pkru, va); 11509 if (ppr != NULL) 11510 return (X86_PG_PKU(ppr->pkru_keyidx)); 11511 return (0); 11512 } 11513 11514 static bool 11515 pred_pkru_on_remove(void *ctx __unused, void *r) 11516 { 11517 struct pmap_pkru_range *ppr; 11518 11519 ppr = r; 11520 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0); 11521 } 11522 11523 static void 11524 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 11525 { 11526 11527 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11528 if (pmap->pm_type == PT_X86 && 11529 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) { 11530 rangeset_remove_pred(&pmap->pm_pkru, sva, eva, 11531 pred_pkru_on_remove); 11532 } 11533 } 11534 11535 static int 11536 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap) 11537 { 11538 11539 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED); 11540 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED); 11541 MPASS(dst_pmap->pm_type == PT_X86); 11542 MPASS(src_pmap->pm_type == PT_X86); 11543 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0); 11544 if (src_pmap->pm_pkru.rs_data_ctx == NULL) 11545 return (0); 11546 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru)); 11547 } 11548 11549 static void 11550 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 11551 u_int keyidx) 11552 { 11553 pml4_entry_t *pml4e; 11554 pdp_entry_t *pdpe; 11555 pd_entry_t newpde, ptpaddr, *pde; 11556 pt_entry_t newpte, *ptep, pte; 11557 vm_offset_t va, va_next; 11558 bool changed; 11559 11560 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 11561 MPASS(pmap->pm_type == PT_X86); 11562 MPASS(keyidx <= PMAP_MAX_PKRU_IDX); 11563 11564 for (changed = false, va = sva; va < eva; va = va_next) { 11565 pml4e = pmap_pml4e(pmap, va); 11566 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) { 11567 va_next = (va + NBPML4) & ~PML4MASK; 11568 if (va_next < va) 11569 va_next = eva; 11570 continue; 11571 } 11572 11573 pdpe = pmap_pml4e_to_pdpe(pml4e, va); 11574 if ((*pdpe & X86_PG_V) == 0) { 11575 va_next = (va + NBPDP) & ~PDPMASK; 11576 if (va_next < va) 11577 va_next = eva; 11578 continue; 11579 } 11580 11581 va_next = (va + NBPDR) & ~PDRMASK; 11582 if (va_next < va) 11583 va_next = eva; 11584 11585 pde = pmap_pdpe_to_pde(pdpe, va); 11586 ptpaddr = *pde; 11587 if (ptpaddr == 0) 11588 continue; 11589 11590 MPASS((ptpaddr & X86_PG_V) != 0); 11591 if ((ptpaddr & PG_PS) != 0) { 11592 if (va + NBPDR == va_next && eva >= va_next) { 11593 newpde = (ptpaddr & ~X86_PG_PKU_MASK) | 11594 X86_PG_PKU(keyidx); 11595 if (newpde != ptpaddr) { 11596 *pde = newpde; 11597 changed = true; 11598 } 11599 continue; 11600 } else if (!pmap_demote_pde(pmap, pde, va)) { 11601 continue; 11602 } 11603 } 11604 11605 if (va_next > eva) 11606 va_next = eva; 11607 11608 for (ptep = pmap_pde_to_pte(pde, va); va != va_next; 11609 ptep++, va += PAGE_SIZE) { 11610 pte = *ptep; 11611 if ((pte & X86_PG_V) == 0) 11612 continue; 11613 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx); 11614 if (newpte != pte) { 11615 *ptep = newpte; 11616 changed = true; 11617 } 11618 } 11619 } 11620 if (changed) 11621 pmap_invalidate_range(pmap, sva, eva); 11622 } 11623 11624 static int 11625 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 11626 u_int keyidx, int flags) 11627 { 11628 11629 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX || 11630 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0) 11631 return (EINVAL); 11632 if (eva <= sva || eva > VM_MAXUSER_ADDRESS) 11633 return (EFAULT); 11634 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0) 11635 return (ENOTSUP); 11636 return (0); 11637 } 11638 11639 int 11640 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx, 11641 int flags) 11642 { 11643 int error; 11644 11645 sva = trunc_page(sva); 11646 eva = round_page(eva); 11647 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags); 11648 if (error != 0) 11649 return (error); 11650 for (;;) { 11651 PMAP_LOCK(pmap); 11652 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags); 11653 if (error == 0) 11654 pmap_pkru_update_range(pmap, sva, eva, keyidx); 11655 PMAP_UNLOCK(pmap); 11656 if (error != ENOMEM) 11657 break; 11658 vm_wait(NULL); 11659 } 11660 return (error); 11661 } 11662 11663 int 11664 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 11665 { 11666 int error; 11667 11668 sva = trunc_page(sva); 11669 eva = round_page(eva); 11670 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0); 11671 if (error != 0) 11672 return (error); 11673 for (;;) { 11674 PMAP_LOCK(pmap); 11675 error = pmap_pkru_deassign(pmap, sva, eva); 11676 if (error == 0) 11677 pmap_pkru_update_range(pmap, sva, eva, 0); 11678 PMAP_UNLOCK(pmap); 11679 if (error != ENOMEM) 11680 break; 11681 vm_wait(NULL); 11682 } 11683 return (error); 11684 } 11685 11686 #if defined(KASAN) || defined(KMSAN) 11687 11688 /* 11689 * Reserve enough memory to: 11690 * 1) allocate PDP pages for the shadow map(s), 11691 * 2) shadow the boot stack of KSTACK_PAGES pages, 11692 * 3) assuming that the kernel stack does not cross a 1GB boundary, 11693 * so we need one or two PD pages, one or two PT pages, and KSTACK_PAGES shadow 11694 * pages per shadow map. 11695 */ 11696 #ifdef KASAN 11697 #define SAN_EARLY_PAGES \ 11698 (NKASANPML4E + 2 + 2 + howmany(KSTACK_PAGES, KASAN_SHADOW_SCALE)) 11699 #else 11700 #define SAN_EARLY_PAGES \ 11701 (NKMSANSHADPML4E + NKMSANORIGPML4E + 2 * (2 + 2 + KSTACK_PAGES)) 11702 #endif 11703 11704 static uint64_t __nosanitizeaddress __nosanitizememory 11705 pmap_san_enter_early_alloc_4k(uint64_t pabase) 11706 { 11707 static uint8_t data[PAGE_SIZE * SAN_EARLY_PAGES] __aligned(PAGE_SIZE); 11708 static size_t offset = 0; 11709 uint64_t pa; 11710 11711 if (offset == sizeof(data)) { 11712 panic("%s: ran out of memory for the bootstrap shadow map", 11713 __func__); 11714 } 11715 11716 pa = pabase + ((vm_offset_t)&data[offset] - KERNSTART); 11717 offset += PAGE_SIZE; 11718 return (pa); 11719 } 11720 11721 /* 11722 * Map a shadow page, before the kernel has bootstrapped its page tables. This 11723 * is currently only used to shadow the temporary boot stack set up by locore. 11724 */ 11725 static void __nosanitizeaddress __nosanitizememory 11726 pmap_san_enter_early(vm_offset_t va) 11727 { 11728 static bool first = true; 11729 pml4_entry_t *pml4e; 11730 pdp_entry_t *pdpe; 11731 pd_entry_t *pde; 11732 pt_entry_t *pte; 11733 uint64_t cr3, pa, base; 11734 int i; 11735 11736 base = amd64_loadaddr(); 11737 cr3 = rcr3(); 11738 11739 if (first) { 11740 /* 11741 * If this the first call, we need to allocate new PML4Es for 11742 * the bootstrap shadow map(s). We don't know how the PML4 page 11743 * was initialized by the boot loader, so we can't simply test 11744 * whether the shadow map's PML4Es are zero. 11745 */ 11746 first = false; 11747 #ifdef KASAN 11748 for (i = 0; i < NKASANPML4E; i++) { 11749 pa = pmap_san_enter_early_alloc_4k(base); 11750 11751 pml4e = (pml4_entry_t *)cr3 + 11752 pmap_pml4e_index(KASAN_MIN_ADDRESS + i * NBPML4); 11753 *pml4e = (pml4_entry_t)(pa | X86_PG_RW | X86_PG_V); 11754 } 11755 #else 11756 for (i = 0; i < NKMSANORIGPML4E; i++) { 11757 pa = pmap_san_enter_early_alloc_4k(base); 11758 11759 pml4e = (pml4_entry_t *)cr3 + 11760 pmap_pml4e_index(KMSAN_ORIG_MIN_ADDRESS + 11761 i * NBPML4); 11762 *pml4e = (pml4_entry_t)(pa | X86_PG_RW | X86_PG_V); 11763 } 11764 for (i = 0; i < NKMSANSHADPML4E; i++) { 11765 pa = pmap_san_enter_early_alloc_4k(base); 11766 11767 pml4e = (pml4_entry_t *)cr3 + 11768 pmap_pml4e_index(KMSAN_SHAD_MIN_ADDRESS + 11769 i * NBPML4); 11770 *pml4e = (pml4_entry_t)(pa | X86_PG_RW | X86_PG_V); 11771 } 11772 #endif 11773 } 11774 pml4e = (pml4_entry_t *)cr3 + pmap_pml4e_index(va); 11775 pdpe = (pdp_entry_t *)(*pml4e & PG_FRAME) + pmap_pdpe_index(va); 11776 if (*pdpe == 0) { 11777 pa = pmap_san_enter_early_alloc_4k(base); 11778 *pdpe = (pdp_entry_t)(pa | X86_PG_RW | X86_PG_V); 11779 } 11780 pde = (pd_entry_t *)(*pdpe & PG_FRAME) + pmap_pde_index(va); 11781 if (*pde == 0) { 11782 pa = pmap_san_enter_early_alloc_4k(base); 11783 *pde = (pd_entry_t)(pa | X86_PG_RW | X86_PG_V); 11784 } 11785 pte = (pt_entry_t *)(*pde & PG_FRAME) + pmap_pte_index(va); 11786 if (*pte != 0) 11787 panic("%s: PTE for %#lx is already initialized", __func__, va); 11788 pa = pmap_san_enter_early_alloc_4k(base); 11789 *pte = (pt_entry_t)(pa | X86_PG_A | X86_PG_M | X86_PG_RW | X86_PG_V); 11790 } 11791 11792 static vm_page_t 11793 pmap_san_enter_alloc_4k(void) 11794 { 11795 vm_page_t m; 11796 11797 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | 11798 VM_ALLOC_ZERO); 11799 if (m == NULL) 11800 panic("%s: no memory to grow shadow map", __func__); 11801 return (m); 11802 } 11803 11804 static vm_page_t 11805 pmap_san_enter_alloc_2m(void) 11806 { 11807 return (vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO, 11808 NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT)); 11809 } 11810 11811 /* 11812 * Grow a shadow map by at least one 4KB page at the specified address. Use 2MB 11813 * pages when possible. 11814 */ 11815 void __nosanitizeaddress __nosanitizememory 11816 pmap_san_enter(vm_offset_t va) 11817 { 11818 pdp_entry_t *pdpe; 11819 pd_entry_t *pde; 11820 pt_entry_t *pte; 11821 vm_page_t m; 11822 11823 if (kernphys == 0) { 11824 /* 11825 * We're creating a temporary shadow map for the boot stack. 11826 */ 11827 pmap_san_enter_early(va); 11828 return; 11829 } 11830 11831 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 11832 11833 pdpe = pmap_pdpe(kernel_pmap, va); 11834 if ((*pdpe & X86_PG_V) == 0) { 11835 m = pmap_san_enter_alloc_4k(); 11836 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | 11837 X86_PG_V | pg_nx); 11838 } 11839 pde = pmap_pdpe_to_pde(pdpe, va); 11840 if ((*pde & X86_PG_V) == 0) { 11841 m = pmap_san_enter_alloc_2m(); 11842 if (m != NULL) { 11843 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | 11844 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx); 11845 } else { 11846 m = pmap_san_enter_alloc_4k(); 11847 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | 11848 X86_PG_V | pg_nx); 11849 } 11850 } 11851 if ((*pde & X86_PG_PS) != 0) 11852 return; 11853 pte = pmap_pde_to_pte(pde, va); 11854 if ((*pte & X86_PG_V) != 0) 11855 return; 11856 m = pmap_san_enter_alloc_4k(); 11857 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V | 11858 X86_PG_M | X86_PG_A | pg_nx); 11859 } 11860 #endif 11861 11862 /* 11863 * Track a range of the kernel's virtual address space that is contiguous 11864 * in various mapping attributes. 11865 */ 11866 struct pmap_kernel_map_range { 11867 vm_offset_t sva; 11868 pt_entry_t attrs; 11869 int ptes; 11870 int pdes; 11871 int pdpes; 11872 }; 11873 11874 static void 11875 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range, 11876 vm_offset_t eva) 11877 { 11878 const char *mode; 11879 int i, pat_idx; 11880 11881 if (eva <= range->sva) 11882 return; 11883 11884 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true); 11885 for (i = 0; i < PAT_INDEX_SIZE; i++) 11886 if (pat_index[i] == pat_idx) 11887 break; 11888 11889 switch (i) { 11890 case PAT_WRITE_BACK: 11891 mode = "WB"; 11892 break; 11893 case PAT_WRITE_THROUGH: 11894 mode = "WT"; 11895 break; 11896 case PAT_UNCACHEABLE: 11897 mode = "UC"; 11898 break; 11899 case PAT_UNCACHED: 11900 mode = "U-"; 11901 break; 11902 case PAT_WRITE_PROTECTED: 11903 mode = "WP"; 11904 break; 11905 case PAT_WRITE_COMBINING: 11906 mode = "WC"; 11907 break; 11908 default: 11909 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n", 11910 __func__, pat_idx, range->sva, eva); 11911 mode = "??"; 11912 break; 11913 } 11914 11915 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n", 11916 range->sva, eva, 11917 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-', 11918 (range->attrs & pg_nx) != 0 ? '-' : 'x', 11919 (range->attrs & X86_PG_U) != 0 ? 'u' : 's', 11920 (range->attrs & X86_PG_G) != 0 ? 'g' : '-', 11921 mode, range->pdpes, range->pdes, range->ptes); 11922 11923 /* Reset to sentinel value. */ 11924 range->sva = kva_layout.kva_max; 11925 } 11926 11927 /* 11928 * Determine whether the attributes specified by a page table entry match those 11929 * being tracked by the current range. This is not quite as simple as a direct 11930 * flag comparison since some PAT modes have multiple representations. 11931 */ 11932 static bool 11933 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs) 11934 { 11935 pt_entry_t diff, mask; 11936 11937 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx; 11938 diff = (range->attrs ^ attrs) & mask; 11939 if (diff == 0) 11940 return (true); 11941 if ((diff & ~X86_PG_PDE_PAT) == 0 && 11942 pmap_pat_index(kernel_pmap, range->attrs, true) == 11943 pmap_pat_index(kernel_pmap, attrs, true)) 11944 return (true); 11945 return (false); 11946 } 11947 11948 static void 11949 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va, 11950 pt_entry_t attrs) 11951 { 11952 11953 memset(range, 0, sizeof(*range)); 11954 range->sva = va; 11955 range->attrs = attrs; 11956 } 11957 11958 /* 11959 * Given a leaf PTE, derive the mapping's attributes. If they do not match 11960 * those of the current run, dump the address range and its attributes, and 11961 * begin a new run. 11962 */ 11963 static void 11964 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range, 11965 vm_offset_t va, pml5_entry_t pml5e, pml4_entry_t pml4e, pdp_entry_t pdpe, 11966 pd_entry_t pde, pt_entry_t pte) 11967 { 11968 pt_entry_t attrs; 11969 11970 if (la57) { 11971 attrs = pml5e & (X86_PG_RW | X86_PG_U | pg_nx); 11972 attrs |= pml4e & pg_nx; 11973 attrs &= pg_nx | (pml4e & (X86_PG_RW | X86_PG_U)); 11974 } else { 11975 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx); 11976 } 11977 11978 attrs |= pdpe & pg_nx; 11979 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U)); 11980 if ((pdpe & PG_PS) != 0) { 11981 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE); 11982 } else if (pde != 0) { 11983 attrs |= pde & pg_nx; 11984 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U)); 11985 } 11986 if ((pde & PG_PS) != 0) { 11987 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE); 11988 } else if (pte != 0) { 11989 attrs |= pte & pg_nx; 11990 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U)); 11991 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE); 11992 11993 /* Canonicalize by always using the PDE PAT bit. */ 11994 if ((attrs & X86_PG_PTE_PAT) != 0) 11995 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT; 11996 } 11997 11998 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) { 11999 sysctl_kmaps_dump(sb, range, va); 12000 sysctl_kmaps_reinit(range, va, attrs); 12001 } 12002 } 12003 12004 static int 12005 sysctl_kmaps(SYSCTL_HANDLER_ARGS) 12006 { 12007 struct pmap_kernel_map_range range; 12008 struct sbuf sbuf, *sb; 12009 pml5_entry_t pml5e; 12010 pml4_entry_t pml4e; 12011 pdp_entry_t *pdp, pdpe; 12012 pd_entry_t *pd, pde; 12013 pt_entry_t *pt, pte; 12014 vm_offset_t sva; 12015 vm_paddr_t pa; 12016 int error, j, k, l; 12017 bool first; 12018 12019 error = sysctl_wire_old_buffer(req, 0); 12020 if (error != 0) 12021 return (error); 12022 sb = &sbuf; 12023 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req); 12024 12025 /* Sentinel value. */ 12026 range.sva = kva_layout.kva_max; 12027 pml5e = 0; /* no UB for la48 */ 12028 12029 /* 12030 * Iterate over the kernel page tables without holding the kernel pmap 12031 * lock. Outside of the large map, kernel page table pages are never 12032 * freed, so at worst we will observe inconsistencies in the output. 12033 * Within the large map, ensure that PDP and PD page addresses are 12034 * valid before descending. 12035 */ 12036 for (first = true, sva = 0; sva != 0 || first; first = false) { 12037 if (sva == kva_layout.rec_pt) 12038 sbuf_printf(sb, "\nRecursive map:\n"); 12039 else if (sva == kva_layout.dmap_low) 12040 sbuf_printf(sb, "\nDirect map:\n"); 12041 #ifdef KASAN 12042 else if (sva == kva_layout.kasan_shadow_low) 12043 sbuf_printf(sb, "\nKASAN shadow map:\n"); 12044 #endif 12045 #ifdef KMSAN 12046 else if (sva == kva_layout.kmsan_shadow_low) 12047 sbuf_printf(sb, "\nKMSAN shadow map:\n"); 12048 else if (sva == kva_layout.kmsan_origin_low) 12049 sbuf_printf(sb, "\nKMSAN origin map:\n"); 12050 #endif 12051 else if (sva == kva_layout.km_low) 12052 sbuf_printf(sb, "\nKernel map:\n"); 12053 else if (sva == kva_layout.lm_low) 12054 sbuf_printf(sb, "\nLarge map:\n"); 12055 12056 /* Convert to canonical form. */ 12057 if (la57) { 12058 if (sva == 1ul << 56) { 12059 sva |= -1ul << 57; 12060 continue; 12061 } 12062 } else { 12063 if (sva == 1ul << 47) { 12064 sva |= -1ul << 48; 12065 continue; 12066 } 12067 } 12068 12069 restart: 12070 if (la57) { 12071 pml5e = *pmap_pml5e(kernel_pmap, sva); 12072 if ((pml5e & X86_PG_V) == 0) { 12073 sva = rounddown2(sva, NBPML5); 12074 sysctl_kmaps_dump(sb, &range, sva); 12075 sva += NBPML5; 12076 continue; 12077 } 12078 } 12079 pml4e = *pmap_pml4e(kernel_pmap, sva); 12080 if ((pml4e & X86_PG_V) == 0) { 12081 sva = rounddown2(sva, NBPML4); 12082 sysctl_kmaps_dump(sb, &range, sva); 12083 sva += NBPML4; 12084 continue; 12085 } 12086 pa = pml4e & PG_FRAME; 12087 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa); 12088 12089 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) { 12090 pdpe = pdp[j]; 12091 if ((pdpe & X86_PG_V) == 0) { 12092 sva = rounddown2(sva, NBPDP); 12093 sysctl_kmaps_dump(sb, &range, sva); 12094 sva += NBPDP; 12095 continue; 12096 } 12097 pa = pdpe & PG_FRAME; 12098 if ((pdpe & PG_PS) != 0) { 12099 sva = rounddown2(sva, NBPDP); 12100 sysctl_kmaps_check(sb, &range, sva, pml5e, 12101 pml4e, pdpe, 0, 0); 12102 range.pdpes++; 12103 sva += NBPDP; 12104 continue; 12105 } 12106 if (PMAP_ADDRESS_IN_LARGEMAP(sva) && 12107 vm_phys_paddr_to_vm_page(pa) == NULL) { 12108 /* 12109 * Page table pages for the large map may be 12110 * freed. Validate the next-level address 12111 * before descending. 12112 */ 12113 sva += NBPDP; 12114 goto restart; 12115 } 12116 pd = (pd_entry_t *)PHYS_TO_DMAP(pa); 12117 12118 for (k = pmap_pde_index(sva); k < NPDEPG; k++) { 12119 pde = pd[k]; 12120 if ((pde & X86_PG_V) == 0) { 12121 sva = rounddown2(sva, NBPDR); 12122 sysctl_kmaps_dump(sb, &range, sva); 12123 sva += NBPDR; 12124 continue; 12125 } 12126 pa = pde & PG_FRAME; 12127 if ((pde & PG_PS) != 0) { 12128 sva = rounddown2(sva, NBPDR); 12129 sysctl_kmaps_check(sb, &range, sva, 12130 pml5e, pml4e, pdpe, pde, 0); 12131 range.pdes++; 12132 sva += NBPDR; 12133 continue; 12134 } 12135 if (PMAP_ADDRESS_IN_LARGEMAP(sva) && 12136 vm_phys_paddr_to_vm_page(pa) == NULL) { 12137 /* 12138 * Page table pages for the large map 12139 * may be freed. Validate the 12140 * next-level address before descending. 12141 */ 12142 sva += NBPDR; 12143 goto restart; 12144 } 12145 pt = (pt_entry_t *)PHYS_TO_DMAP(pa); 12146 12147 for (l = pmap_pte_index(sva); l < NPTEPG; l++, 12148 sva += PAGE_SIZE) { 12149 pte = pt[l]; 12150 if ((pte & X86_PG_V) == 0) { 12151 sysctl_kmaps_dump(sb, &range, 12152 sva); 12153 continue; 12154 } 12155 sysctl_kmaps_check(sb, &range, sva, 12156 pml5e, pml4e, pdpe, pde, pte); 12157 range.ptes++; 12158 } 12159 } 12160 } 12161 } 12162 12163 error = sbuf_finish(sb); 12164 sbuf_delete(sb); 12165 return (error); 12166 } 12167 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps, 12168 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP, 12169 NULL, 0, sysctl_kmaps, "A", 12170 "Dump kernel address layout"); 12171 12172 #ifdef DDB 12173 DB_SHOW_COMMAND(pte, pmap_print_pte) 12174 { 12175 pmap_t pmap; 12176 pml5_entry_t *pml5; 12177 pml4_entry_t *pml4; 12178 pdp_entry_t *pdp; 12179 pd_entry_t *pde; 12180 pt_entry_t *pte, PG_V; 12181 vm_offset_t va; 12182 12183 if (!have_addr) { 12184 db_printf("show pte addr\n"); 12185 return; 12186 } 12187 va = (vm_offset_t)addr; 12188 12189 if (kdb_thread != NULL) 12190 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace); 12191 else 12192 pmap = PCPU_GET(curpmap); 12193 12194 PG_V = pmap_valid_bit(pmap); 12195 db_printf("VA 0x%016lx", va); 12196 12197 if (pmap_is_la57(pmap)) { 12198 pml5 = pmap_pml5e(pmap, va); 12199 db_printf(" pml5e@0x%016lx 0x%016lx", (uint64_t)pml5, *pml5); 12200 if ((*pml5 & PG_V) == 0) { 12201 db_printf("\n"); 12202 return; 12203 } 12204 pml4 = pmap_pml5e_to_pml4e(pml5, va); 12205 } else { 12206 pml4 = pmap_pml4e(pmap, va); 12207 } 12208 db_printf(" pml4e@0x%016lx 0x%016lx", (uint64_t)pml4, *pml4); 12209 if ((*pml4 & PG_V) == 0) { 12210 db_printf("\n"); 12211 return; 12212 } 12213 pdp = pmap_pml4e_to_pdpe(pml4, va); 12214 db_printf(" pdpe@0x%016lx 0x%016lx", (uint64_t)pdp, *pdp); 12215 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) { 12216 db_printf("\n"); 12217 return; 12218 } 12219 pde = pmap_pdpe_to_pde(pdp, va); 12220 db_printf(" pde@0x%016lx 0x%016lx", (uint64_t)pde, *pde); 12221 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) { 12222 db_printf("\n"); 12223 return; 12224 } 12225 pte = pmap_pde_to_pte(pde, va); 12226 db_printf(" pte@0x%016lx 0x%016lx\n", (uint64_t)pte, *pte); 12227 } 12228 12229 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap) 12230 { 12231 vm_paddr_t a; 12232 12233 if (have_addr) { 12234 a = (vm_paddr_t)addr; 12235 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a)); 12236 } else { 12237 db_printf("show phys2dmap addr\n"); 12238 } 12239 } 12240 12241 static void 12242 ptpages_show_page(int level, int idx, vm_page_t pg) 12243 { 12244 db_printf("l %d i %d pg %p phys %#lx ref %x\n", 12245 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count); 12246 } 12247 12248 static void 12249 ptpages_show_complain(int level, int idx, uint64_t pte) 12250 { 12251 db_printf("l %d i %d pte %#lx\n", level, idx, pte); 12252 } 12253 12254 static void 12255 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V) 12256 { 12257 vm_page_t pg3, pg2, pg1; 12258 pml4_entry_t *pml4; 12259 pdp_entry_t *pdp; 12260 pd_entry_t *pd; 12261 int i4, i3, i2; 12262 12263 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4)); 12264 for (i4 = 0; i4 < num_entries; i4++) { 12265 if ((pml4[i4] & PG_V) == 0) 12266 continue; 12267 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME); 12268 if (pg3 == NULL) { 12269 ptpages_show_complain(3, i4, pml4[i4]); 12270 continue; 12271 } 12272 ptpages_show_page(3, i4, pg3); 12273 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3)); 12274 for (i3 = 0; i3 < NPDPEPG; i3++) { 12275 if ((pdp[i3] & PG_V) == 0) 12276 continue; 12277 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME); 12278 if (pg3 == NULL) { 12279 ptpages_show_complain(2, i3, pdp[i3]); 12280 continue; 12281 } 12282 ptpages_show_page(2, i3, pg2); 12283 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2)); 12284 for (i2 = 0; i2 < NPDEPG; i2++) { 12285 if ((pd[i2] & PG_V) == 0) 12286 continue; 12287 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME); 12288 if (pg1 == NULL) { 12289 ptpages_show_complain(1, i2, pd[i2]); 12290 continue; 12291 } 12292 ptpages_show_page(1, i2, pg1); 12293 } 12294 } 12295 } 12296 } 12297 12298 DB_SHOW_COMMAND(ptpages, pmap_ptpages) 12299 { 12300 pmap_t pmap; 12301 vm_page_t pg; 12302 pml5_entry_t *pml5; 12303 uint64_t PG_V; 12304 int i5; 12305 12306 if (have_addr) 12307 pmap = (pmap_t)addr; 12308 else 12309 pmap = PCPU_GET(curpmap); 12310 12311 PG_V = pmap_valid_bit(pmap); 12312 12313 if (pmap_is_la57(pmap)) { 12314 pml5 = pmap->pm_pmltop; 12315 for (i5 = 0; i5 < NUPML5E; i5++) { 12316 if ((pml5[i5] & PG_V) == 0) 12317 continue; 12318 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME); 12319 if (pg == NULL) { 12320 ptpages_show_complain(4, i5, pml5[i5]); 12321 continue; 12322 } 12323 ptpages_show_page(4, i5, pg); 12324 ptpages_show_pml4(pg, NPML4EPG, PG_V); 12325 } 12326 } else { 12327 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS( 12328 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V); 12329 } 12330 } 12331 #endif 12332