1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _SYS_PMC_H_ 34 #define _SYS_PMC_H_ 35 36 #include <dev/hwpmc/pmc_events.h> 37 #include <sys/proc.h> 38 #include <sys/counter.h> 39 #include <machine/pmc_mdep.h> 40 #include <machine/profile.h> 41 #ifdef _KERNEL 42 #include <sys/epoch.h> 43 #include <ck_queue.h> 44 #endif 45 46 #define PMC_MODULE_NAME "hwpmc" 47 #define PMC_NAME_MAX 64 /* HW counter name size */ 48 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 49 50 /* 51 * Kernel<->userland API version number [MMmmpppp] 52 * 53 * Major numbers are to be incremented when an incompatible change to 54 * the ABI occurs that older clients will not be able to handle. 55 * 56 * Minor numbers are incremented when a backwards compatible change 57 * occurs that allows older correct programs to run unchanged. For 58 * example, when support for a new PMC type is added. 59 * 60 * The patch version is incremented for every bug fix. 61 */ 62 #define PMC_VERSION_MAJOR 0x0A 63 #define PMC_VERSION_MINOR 0x03 64 #define PMC_VERSION_PATCH 0x0000 65 66 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 67 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 68 69 #define PMC_CPUID_LEN 64 70 /* cpu model name for pmu lookup */ 71 extern char pmc_cpuid[PMC_CPUID_LEN]; 72 73 /* 74 * Kinds of CPUs known. 75 * 76 * We keep track of CPU variants that need to be distinguished in 77 * some way for PMC operations. CPU names are grouped by manufacturer 78 * and numbered sparsely in order to minimize changes to the ABI involved 79 * when new CPUs are added. 80 * 81 * Please keep the pmc(3) manual page in sync with this list. 82 */ 83 #define __PMC_CPUS() \ 84 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 85 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 86 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 87 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 88 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 89 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 90 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 91 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 92 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 93 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 94 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 95 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 96 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 97 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 98 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 99 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 100 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 101 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 102 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 103 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 104 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ 105 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ 106 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ 107 __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ 108 __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ 109 __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ 110 __PMC_CPU(INTEL_EMERALD_RAPIDS, 0xA0, "Intel Emerald Rapids") \ 111 __PMC_CPU(INTEL_ALDERLAKEN, 0xA1, "Intel AlderlakeN") \ 112 __PMC_CPU(INTEL_GRANITE_RAPIDS, 0xA2, "Intel Granite Rapids") \ 113 __PMC_CPU(INTEL_METEOR_LAKE, 0xA3, "Intel Meteorlake") \ 114 __PMC_CPU(INTEL_SAPPHIRE_RAPIDS, 0xA4, "Intel Sapphire Rapids") \ 115 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 116 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 117 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 118 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ 119 __PMC_CPU(GENERIC, 0x400, "Generic") \ 120 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 121 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 122 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 123 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 124 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 125 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 126 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 127 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ 128 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") 129 130 enum pmc_cputype { 131 #undef __PMC_CPU 132 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 133 __PMC_CPUS() 134 }; 135 136 #define PMC_CPU_FIRST PMC_CPU_AMD_K8 137 #define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76 138 139 /* 140 * Classes of PMCs 141 */ 142 #define __PMC_CLASSES() \ 143 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 144 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 145 __PMC_CLASS(IBS, 0x03, "AMD IBS performance counters") \ 146 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 147 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 148 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 149 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 150 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 151 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 152 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 153 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 154 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 155 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 156 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ 157 __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \ 158 __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \ 159 __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU") \ 160 __PMC_CLASS(RAPL, 0x19, "AMD/Intel RAPL energy counters") \ 161 __PMC_CLASS(PERF, 0x1A, "AMD/Intel PERF MSRs") 162 163 enum pmc_class { 164 #undef __PMC_CLASS 165 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 166 __PMC_CLASSES() 167 }; 168 169 #define PMC_CLASS_FIRST PMC_CLASS_TSC 170 #define PMC_CLASS_LAST PMC_CLASS_RAPL 171 172 /* 173 * A PMC can be in the following states: 174 * 175 * Hardware states: 176 * DISABLED -- administratively prohibited from being used. 177 * FREE -- HW available for use 178 * Software states: 179 * ALLOCATED -- allocated 180 * STOPPED -- allocated, but not counting events 181 * RUNNING -- allocated, and in operation; 'pm_runcount' 182 * holds the number of CPUs using this PMC at 183 * a given instant 184 * DELETED -- being destroyed 185 */ 186 187 #define __PMC_HWSTATES() \ 188 __PMC_STATE(DISABLED) \ 189 __PMC_STATE(FREE) 190 191 #define __PMC_SWSTATES() \ 192 __PMC_STATE(ALLOCATED) \ 193 __PMC_STATE(STOPPED) \ 194 __PMC_STATE(RUNNING) \ 195 __PMC_STATE(DELETED) 196 197 #define __PMC_STATES() \ 198 __PMC_HWSTATES() \ 199 __PMC_SWSTATES() 200 201 enum pmc_state { 202 #undef __PMC_STATE 203 #define __PMC_STATE(S) PMC_STATE_##S, 204 __PMC_STATES() 205 __PMC_STATE(MAX) 206 }; 207 208 #define PMC_STATE_FIRST PMC_STATE_DISABLED 209 #define PMC_STATE_LAST PMC_STATE_DELETED 210 211 /* 212 * An allocated PMC may used as a 'global' counter or as a 213 * 'thread-private' one. Each such mode of use can be in either 214 * statistical sampling mode or in counting mode. Thus a PMC in use 215 * 216 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 217 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 218 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 219 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 220 * 221 * Statistical profiling modes rely on the PMC periodically delivering 222 * a interrupt to the CPU (when the configured number of events have 223 * been measured), so the PMC must have the ability to generate 224 * interrupts. 225 * 226 * In counting modes, the PMC counts its configured events, with the 227 * value of the PMC being read whenever needed by its owner process. 228 * 229 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 230 * to be thread private and count events only when the profiled thread 231 * actually executes on the CPU. 232 * 233 * The system-wide "global" modes keep the PMCs running all the time 234 * and are used to measure the behaviour of the whole system. 235 */ 236 237 #define __PMC_MODES() \ 238 __PMC_MODE(SS, 0) \ 239 __PMC_MODE(SC, 1) \ 240 __PMC_MODE(TS, 2) \ 241 __PMC_MODE(TC, 3) 242 243 enum pmc_mode { 244 #undef __PMC_MODE 245 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 246 __PMC_MODES() 247 }; 248 249 #define PMC_MODE_FIRST PMC_MODE_SS 250 #define PMC_MODE_LAST PMC_MODE_TC 251 252 #define PMC_IS_COUNTING_MODE(mode) \ 253 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 254 #define PMC_IS_SYSTEM_MODE(mode) \ 255 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 256 #define PMC_IS_SAMPLING_MODE(mode) \ 257 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 258 #define PMC_IS_VIRTUAL_MODE(mode) \ 259 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 260 261 /* 262 * PMC row disposition 263 */ 264 265 #define __PMC_DISPOSITIONS(N) \ 266 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 267 __PMC_DISP(FREE) /* free/available */ \ 268 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 269 __PMC_DISP(UNKNOWN) /* sentinel */ 270 271 enum pmc_disp { 272 #undef __PMC_DISP 273 #define __PMC_DISP(D) PMC_DISP_##D , 274 __PMC_DISPOSITIONS() 275 }; 276 277 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 278 #define PMC_DISP_LAST PMC_DISP_THREAD 279 280 /* 281 * Counter capabilities 282 * 283 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 284 */ 285 286 #define __PMC_CAPS() \ 287 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 288 __PMC_CAP(USER, 1, "count user-mode events") \ 289 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 290 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 291 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 292 __PMC_CAP(READ, 5, "read PMC counter") \ 293 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 294 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 295 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 296 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 297 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 298 __PMC_CAP(CASCADE, 11, "cascade counters") \ 299 __PMC_CAP(SYSWIDE, 12, "system wide counter") \ 300 __PMC_CAP(DOMWIDE, 13, "NUMA domain wide counter") 301 302 enum pmc_caps 303 { 304 #undef __PMC_CAP 305 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 306 __PMC_CAPS() 307 }; 308 309 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 310 #define PMC_CAP_LAST PMC_CAP_DOMWIDE 311 312 /* 313 * PMC Event Numbers 314 * 315 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 316 */ 317 318 enum pmc_event { 319 #undef __PMC_EV 320 #undef __PMC_EV_BLOCK 321 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 322 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 323 __PMC_EVENTS() 324 }; 325 326 /* 327 * PMC SYSCALL INTERFACE 328 */ 329 330 /* 331 * "PMC_OPS" -- these are the commands recognized by the kernel 332 * module, and are used when performing a system call from userland. 333 */ 334 #define __PMC_OPS() \ 335 __PMC_OP(CONFIGURELOG, "Set log file") \ 336 __PMC_OP(FLUSHLOG, "Flush log file") \ 337 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 338 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 339 __PMC_OP(GETMODULEVERSION, "Get module version") \ 340 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 341 __PMC_OP(PMCADMIN, "Set PMC state") \ 342 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 343 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 344 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 345 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 346 __PMC_OP(PMCRELEASE, "Release a PMC") \ 347 __PMC_OP(PMCRW, "Read/Set a PMC") \ 348 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 349 __PMC_OP(PMCSTART, "Start a PMC") \ 350 __PMC_OP(PMCSTOP, "Stop a PMC") \ 351 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 352 __PMC_OP(CLOSELOG, "Close log file") \ 353 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") \ 354 __PMC_OP(GETCAPS, "Get capabilities") 355 356 enum pmc_ops { 357 #undef __PMC_OP 358 #define __PMC_OP(N, D) PMC_OP_##N, 359 __PMC_OPS() 360 }; 361 362 /* 363 * Flags used in operations on PMCs. 364 */ 365 366 #define PMC_F_UNUSED1 0x00000001 /* unused */ 367 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 368 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 369 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 370 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 371 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 372 373 /* V2 API */ 374 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 375 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 376 377 /* V10 API */ 378 #define PMC_F_EV_PMU 0x00000200 /* 379 * OP ALLOCATE: pm_ev has special 380 * userspace meaning; counter 381 * configuration is communicated 382 * through class-dependent fields 383 */ 384 385 /* internal flags */ 386 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 387 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 388 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 389 390 #define PMC_CALLCHAIN_DEPTH_MAX 512 391 392 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 393 #define PMC_CC_F_MULTIPART 0x02 /*multipart data*/ 394 395 /* 396 * Cookies used to denote allocated PMCs, and the values of PMCs. 397 */ 398 399 typedef uint32_t pmc_id_t; 400 typedef uint64_t pmc_value_t; 401 402 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 403 404 /* 405 * PMC IDs have the following format: 406 * 407 * +-----------------------+-------+-----------+ 408 * | CPU | PMC MODE | CLASS | ROW INDEX | 409 * +-----------------------+-------+-----------+ 410 * 411 * where CPU is 12 bits, MODE 4, CLASS 8, and ROW INDEX 8 Field 'CPU' 412 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 413 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 414 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 415 * row index for the PMC. 416 * 417 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 418 * number of hardware PMCs on this cpu. 419 */ 420 421 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 422 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 423 #define PMC_ID_TO_MODE(ID) (((ID) & 0xF0000) >> 16) 424 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 425 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 426 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xF) << 16) | \ 427 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 428 429 /* 430 * Data structures for system calls supported by the pmc driver. 431 */ 432 433 /* 434 * OP PMCALLOCATE 435 * 436 * Allocate a PMC on the named CPU. 437 */ 438 439 #define PMC_CPU_ANY ~0 440 441 struct pmc_op_pmcallocate { 442 uint32_t pm_caps; /* PMC_CAP_* */ 443 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 444 enum pmc_class pm_class; /* class of PMC desired */ 445 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 446 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 447 enum pmc_mode pm_mode; /* desired mode */ 448 pmc_id_t pm_pmcid; /* [return] process pmc id */ 449 pmc_value_t pm_count; /* initial/sample count */ 450 451 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 452 }; 453 454 /* 455 * OP PMCADMIN 456 * 457 * Set the administrative state (i.e., whether enabled or disabled) of 458 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 459 * absolute PMC number and need not have been first allocated by the 460 * calling process. 461 */ 462 463 struct pmc_op_pmcadmin { 464 int pm_cpu; /* CPU# */ 465 uint32_t pm_flags; /* flags */ 466 int pm_pmc; /* PMC# */ 467 enum pmc_state pm_state; /* desired state */ 468 }; 469 470 /* 471 * OP PMCATTACH / OP PMCDETACH 472 * 473 * Attach/detach a PMC and a process. 474 */ 475 476 struct pmc_op_pmcattach { 477 pmc_id_t pm_pmc; /* PMC to attach to */ 478 pid_t pm_pid; /* target process */ 479 }; 480 481 /* 482 * OP PMCSETCOUNT 483 * 484 * Set the sampling rate (i.e., the reload count) for statistical counters. 485 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 486 */ 487 488 struct pmc_op_pmcsetcount { 489 pmc_value_t pm_count; /* initial/sample count */ 490 pmc_id_t pm_pmcid; /* PMC id to set */ 491 }; 492 493 /* 494 * OP PMCRW 495 * 496 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 497 * to have been previously allocated using PMCALLOCATE. 498 */ 499 500 struct pmc_op_pmcrw { 501 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 502 pmc_id_t pm_pmcid; /* pmc id */ 503 pmc_value_t pm_value; /* new&returned value */ 504 }; 505 506 /* 507 * OP GETPMCINFO 508 * 509 * retrieve PMC state for a named CPU. The caller is expected to 510 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 511 * values. 512 */ 513 514 struct pmc_info { 515 char pm_name[PMC_NAME_MAX]; /* pmc name */ 516 enum pmc_class pm_class; /* enum pmc_class */ 517 int pm_enabled; /* whether enabled */ 518 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 519 pid_t pm_ownerpid; /* owner, or -1 */ 520 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 521 enum pmc_event pm_event; /* current event */ 522 uint32_t pm_flags; /* current flags */ 523 pmc_value_t pm_reloadcount; /* sampling counters only */ 524 }; 525 526 struct pmc_op_getpmcinfo { 527 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 528 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 529 }; 530 531 /* 532 * OP GETCPUINFO 533 * 534 * Retrieve system CPU information. 535 */ 536 537 struct pmc_classinfo { 538 enum pmc_class pm_class; /* class id */ 539 uint32_t pm_caps; /* counter capabilities */ 540 uint32_t pm_width; /* width of the PMC */ 541 uint32_t pm_num; /* number of PMCs in class */ 542 }; 543 544 struct pmc_op_getcpuinfo { 545 enum pmc_cputype pm_cputype; /* what kind of CPU */ 546 uint32_t pm_ncpu; /* max CPU number */ 547 uint32_t pm_npmc; /* #PMCs per CPU */ 548 uint32_t pm_nclass; /* #classes of PMCs */ 549 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 550 }; 551 552 /* 553 * OP CONFIGURELOG 554 * 555 * Configure a log file for writing system-wide statistics to. 556 */ 557 558 struct pmc_op_configurelog { 559 int pm_flags; 560 int pm_logfd; /* logfile fd (or -1) */ 561 }; 562 563 /* 564 * OP GETDRIVERSTATS 565 * 566 * Retrieve pmc(4) driver-wide statistics. 567 */ 568 #ifdef _KERNEL 569 struct pmc_driverstats { 570 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 571 counter_u64_t pm_intr_processed; /* #interrupts processed */ 572 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 573 counter_u64_t pm_syscalls; /* #syscalls */ 574 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 575 counter_u64_t pm_buffer_requests; /* #buffer requests */ 576 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 577 counter_u64_t pm_log_sweeps; /* #sample buffer processing 578 passes */ 579 counter_u64_t pm_merges; /* merged k+u */ 580 counter_u64_t pm_overwrites; /* UR overwrites */ 581 }; 582 #endif 583 584 struct pmc_op_getdriverstats { 585 unsigned int pm_intr_ignored; /* #interrupts ignored */ 586 unsigned int pm_intr_processed; /* #interrupts processed */ 587 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 588 unsigned int pm_syscalls; /* #syscalls */ 589 unsigned int pm_syscall_errors; /* #syscalls with errors */ 590 unsigned int pm_buffer_requests; /* #buffer requests */ 591 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 592 unsigned int pm_log_sweeps; /* #sample buffer processing 593 passes */ 594 }; 595 596 /* 597 * OP RELEASE / OP START / OP STOP 598 * 599 * Simple operations on a PMC id. 600 */ 601 602 struct pmc_op_simple { 603 pmc_id_t pm_pmcid; 604 }; 605 606 /* 607 * OP WRITELOG 608 * 609 * Flush the current log buffer and write 4 bytes of user data to it. 610 */ 611 612 struct pmc_op_writelog { 613 uint32_t pm_userdata; 614 }; 615 616 /* 617 * OP GETMSR 618 * 619 * Retrieve the machine specific address associated with the allocated 620 * PMC. This number can be used subsequently with a read-performance-counter 621 * instruction. 622 */ 623 624 struct pmc_op_getmsr { 625 uint32_t pm_msr; /* machine specific address */ 626 pmc_id_t pm_pmcid; /* allocated pmc id */ 627 }; 628 629 /* 630 * OP GETDYNEVENTINFO 631 * 632 * Retrieve a PMC dynamic class events list. 633 */ 634 635 struct pmc_dyn_event_descr { 636 char pm_ev_name[PMC_NAME_MAX]; 637 enum pmc_event pm_ev_code; 638 }; 639 640 struct pmc_op_getdyneventinfo { 641 enum pmc_class pm_class; 642 unsigned int pm_nevent; 643 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 644 }; 645 646 /* 647 * OP GETCAPS 648 * 649 * Retrieve the PMC capabilties flags for this type of counter. 650 */ 651 652 struct pmc_op_caps { 653 pmc_id_t pm_pmcid; /* allocated pmc id */ 654 uint32_t pm_caps; /* capabilities */ 655 }; 656 657 #ifdef _KERNEL 658 659 #include <sys/malloc.h> 660 #include <sys/sysctl.h> 661 #include <sys/_cpuset.h> 662 663 #include <machine/frame.h> 664 665 #define PMC_HASH_SIZE 1024 666 #define PMC_MTXPOOL_SIZE 2048 667 #define PMC_LOG_BUFFER_SIZE 256 668 #define PMC_LOG_BUFFER_SIZE_MAX (16 * 1024) 669 #define PMC_NLOGBUFFERS_PCPU 32 670 #define PMC_NLOGBUFFERS_PCPU_MEM_MAX (32 * 1024) 671 #define PMC_NSAMPLES 256 672 #define PMC_CALLCHAIN_DEPTH 128 673 #define PMC_THREADLIST_MAX 128 674 675 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 676 677 /* 678 * Locking keys 679 * 680 * (b) - pmc_bufferlist_mtx (spin lock) 681 * (k) - pmc_kthread_mtx (sleep lock) 682 * (o) - po->po_mtx (spin lock) 683 * (g) - global_epoch_preempt (epoch) 684 * (p) - pmc_sx (sx) 685 */ 686 687 /* 688 * PMC commands 689 */ 690 691 struct pmc_syscall_args { 692 register_t pmop_code; /* one of PMC_OP_* */ 693 void *pmop_data; /* syscall parameter */ 694 }; 695 696 /* 697 * Interface to processor specific s1tuff 698 */ 699 700 /* 701 * struct pmc_descr 702 * 703 * Machine independent (i.e., the common parts) of a human readable 704 * PMC description. 705 */ 706 707 struct pmc_descr { 708 char pd_name[PMC_NAME_MAX]; /* name */ 709 uint32_t pd_caps; /* capabilities */ 710 enum pmc_class pd_class; /* class of the PMC */ 711 uint32_t pd_width; /* width in bits */ 712 }; 713 714 /* 715 * struct pmc_target 716 * 717 * This structure records all the target processes associated with a 718 * PMC. 719 */ 720 721 struct pmc_target { 722 LIST_ENTRY(pmc_target) pt_next; 723 struct pmc_process *pt_process; /* target descriptor */ 724 }; 725 726 /* 727 * struct pmc 728 * 729 * Describes each allocated PMC. 730 * 731 * Each PMC has precisely one owner, namely the process that allocated 732 * the PMC. 733 * 734 * A PMC may be attached to multiple target processes. The 735 * 'pm_targets' field links all the target processes being monitored 736 * by this PMC. 737 * 738 * The 'pm_savedvalue' field is protected by a mutex. 739 * 740 * On a multi-cpu machine, multiple target threads associated with a 741 * process-virtual PMC could be concurrently executing on different 742 * CPUs. The 'pm_runcount' field is atomically incremented every time 743 * the PMC gets scheduled on a CPU and atomically decremented when it 744 * get descheduled. Deletion of a PMC is only permitted when this 745 * field is '0'. 746 * 747 */ 748 struct pmc_pcpu_state { 749 uint32_t pps_overflowcnt; /* count overflow interrupts */ 750 uint8_t pps_stalled; 751 uint8_t pps_cpustate; 752 } __aligned(CACHE_LINE_SIZE); 753 struct pmc { 754 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 755 LIST_ENTRY(pmc) pm_next; /* owner's list */ 756 757 /* 758 * System-wide PMCs are allocated on a CPU and are not moved 759 * around. For system-wide PMCs we record the CPU the PMC was 760 * allocated on in the 'CPU' field of the pmc ID. 761 * 762 * Virtual PMCs run on whichever CPU is currently executing 763 * their targets' threads. For these PMCs we need to save 764 * their current PMC counter values when they are taken off 765 * CPU. 766 */ 767 768 union { 769 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 770 } pm_gv; 771 772 /* 773 * For sampling mode PMCs, we keep track of the PMC's "reload 774 * count", which is the counter value to be loaded in when 775 * arming the PMC for the next counting session. For counting 776 * modes on PMCs that are read-only (e.g., the x86 TSC), we 777 * keep track of the initial value at the start of 778 * counting-mode operation. 779 */ 780 781 union { 782 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 783 pmc_value_t pm_initial; /* counting PMC modes */ 784 } pm_sc; 785 786 struct pmc_pcpu_state *pm_pcpu_state; 787 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 788 uint32_t pm_caps; /* PMC capabilities */ 789 enum pmc_event pm_event; /* event being measured */ 790 uint32_t pm_flags; /* additional flags PMC_F_... */ 791 struct pmc_owner *pm_owner; /* owner thread state */ 792 counter_u64_t pm_runcount; /* #cpus currently on */ 793 enum pmc_state pm_state; /* current PMC state */ 794 795 /* 796 * The PMC ID field encodes the row-index for the PMC, its 797 * mode, class and the CPU# associated with the PMC. 798 */ 799 800 pmc_id_t pm_id; /* allocated PMC id */ 801 enum pmc_class pm_class; 802 803 /* md extensions */ 804 union pmc_md_pmc pm_md; 805 }; 806 807 /* 808 * Accessor macros for 'struct pmc' 809 */ 810 811 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 812 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 813 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 814 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 815 816 /* 817 * struct pmc_threadpmcstate 818 * 819 * Record per-PMC, per-thread state. 820 */ 821 struct pmc_threadpmcstate { 822 pmc_value_t pt_pmcval; /* per-thread reload count */ 823 }; 824 825 /* 826 * struct pmc_thread 827 * 828 * Record a 'target' thread being profiled. 829 */ 830 struct pmc_thread { 831 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 832 struct thread *pt_td; /* target thread */ 833 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 834 }; 835 836 /* 837 * struct pmc_process 838 * 839 * Record a 'target' process being profiled. 840 * 841 * The target process being profiled could be different from the owner 842 * process which allocated the PMCs. Each target process descriptor 843 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 844 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 845 * array. The size of this structure is thus PMC architecture 846 * dependent. 847 * 848 */ 849 850 struct pmc_targetstate { 851 struct pmc *pp_pmc; /* target PMC */ 852 pmc_value_t pp_pmcval; /* per-process value */ 853 }; 854 855 struct pmc_process { 856 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 857 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 858 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 859 int pp_refcnt; /* reference count */ 860 uint32_t pp_flags; /* flags PMC_PP_* */ 861 struct proc *pp_proc; /* target process */ 862 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 863 }; 864 865 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 866 867 /* 868 * struct pmc_owner 869 * 870 * We associate a PMC with an 'owner' process. 871 * 872 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 873 * lifetime, where NCPUS is the numbers of CPUS in the system and 874 * NHWPMC is the number of hardware PMCs per CPU. These are 875 * maintained in the list headed by the 'po_pmcs' to save on space. 876 * 877 */ 878 879 struct pmc_owner { 880 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 881 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 882 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 883 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 884 struct mtx po_mtx; /* spin lock for (o) */ 885 struct proc *po_owner; /* owner proc */ 886 uint32_t po_flags; /* (k) flags PMC_PO_* */ 887 struct proc *po_kthread; /* (k) helper kthread */ 888 struct file *po_file; /* file reference */ 889 int po_error; /* recorded error */ 890 short po_sscount; /* # SS PMCs owned */ 891 short po_logprocmaps; /* global mappings done */ 892 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 893 }; 894 895 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 896 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 897 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 898 899 /* 900 * struct pmc_hw -- describe the state of the PMC hardware 901 * 902 * When in use, a HW PMC is associated with one allocated 'struct pmc' 903 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 904 * 905 * On an SMP box, one or more HW PMC's in process virtual mode with 906 * the same 'phw_pmc' could be executing on different CPUs. In order 907 * to handle this case correctly, we need to ensure that only 908 * incremental counts get added to the saved value in the associated 909 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 910 * value at the time the hardware is started during this context 911 * switch (i.e., the difference between the new (hardware) count and 912 * the saved count is atomically added to the count field in 'struct 913 * pmc' at context switch time). 914 * 915 */ 916 917 struct pmc_hw { 918 uint32_t phw_state; /* see PHW_* macros below */ 919 struct pmc *phw_pmc; /* current thread PMC */ 920 }; 921 922 #define PMC_PHW_RI_MASK 0x000000FF 923 #define PMC_PHW_CPU_SHIFT 8 924 #define PMC_PHW_CPU_MASK 0x0000FF00 925 #define PMC_PHW_FLAGS_SHIFT 16 926 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 927 928 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 929 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 930 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 931 PMC_PHW_CPU_MASK) 932 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 933 PMC_PHW_CPU_SHIFT) 934 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 935 PMC_PHW_FLAGS_MASK) 936 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 937 PMC_PHW_FLAGS_SHIFT) 938 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 939 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 940 941 /* 942 * struct pmc_sample 943 * 944 * Space for N (tunable) PC samples and associated control data. 945 */ 946 947 struct pmc_sample { 948 uint16_t ps_nsamples; /* callchain depth */ 949 uint16_t ps_nsamples_actual; 950 uint16_t ps_cpu; /* cpu number */ 951 uint16_t ps_flags; /* other flags */ 952 lwpid_t ps_tid; /* thread id */ 953 pid_t ps_pid; /* process PID or -1 */ 954 int ps_ticks; /* ticks at sample time */ 955 /* pad */ 956 struct thread *ps_td; /* which thread */ 957 struct pmc *ps_pmc; /* interrupting PMC */ 958 uintptr_t *ps_pc; /* (const) callchain start */ 959 uint64_t ps_tsc; /* tsc value */ 960 }; 961 962 #define PMC_SAMPLE_FREE ((uint16_t) 0) 963 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 964 965 struct pmc_samplebuffer { 966 volatile uint64_t ps_prodidx; /* producer index */ 967 volatile uint64_t ps_considx; /* consumer index */ 968 uintptr_t *ps_callchains; /* all saved call chains */ 969 struct pmc_sample ps_samples[]; /* array of sample entries */ 970 }; 971 972 #define PMC_CONS_SAMPLE(psb) \ 973 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 974 975 #define PMC_CONS_SAMPLE_OFF(psb, off) \ 976 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 977 978 #define PMC_PROD_SAMPLE(psb) \ 979 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 980 981 982 /* 983 * struct pmc_multipart 984 * 985 * Multipart payload 986 */ 987 struct pmc_multipart { 988 char pl_type; 989 char pl_length; 990 uint64_t pl_mpdata[10]; 991 }; 992 993 /* 994 * struct pmc_cpustate 995 * 996 * A CPU is modelled as a collection of HW PMCs with space for additional 997 * flags. 998 */ 999 1000 struct pmc_cpu { 1001 uint32_t pc_state; /* physical cpu number + flags */ 1002 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 1003 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 1004 }; 1005 1006 #define PMC_PCPU_CPU_MASK 0x000000FF 1007 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 1008 #define PMC_PCPU_FLAGS_SHIFT 8 1009 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 1010 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 1011 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 1012 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 1013 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 1014 1015 /* 1016 * struct pmc_binding 1017 * 1018 * CPU binding information. 1019 */ 1020 1021 struct pmc_binding { 1022 int pb_bound; /* is bound? */ 1023 int pb_cpu; /* if so, to which CPU */ 1024 u_char pb_priority; /* Thread active priority. */ 1025 }; 1026 1027 struct pmc_mdep; 1028 1029 /* 1030 * struct pmc_classdep 1031 * 1032 * PMC class-dependent operations. 1033 */ 1034 struct pmc_classdep { 1035 uint32_t pcd_caps; /* class capabilities */ 1036 enum pmc_class pcd_class; /* class id */ 1037 int pcd_num; /* number of PMCs */ 1038 int pcd_ri; /* row index of the first PMC in class */ 1039 int pcd_width; /* width of the PMC */ 1040 1041 /* configuring/reading/writing the hardware PMCs */ 1042 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1043 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1044 int (*pcd_read_pmc)(int _cpu, int _ri, struct pmc *_pm, 1045 pmc_value_t *_value); 1046 int (*pcd_write_pmc)(int _cpu, int _ri, struct pmc *_pm, 1047 pmc_value_t _value); 1048 1049 /* pmc allocation/release */ 1050 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1051 const struct pmc_op_pmcallocate *_a); 1052 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1053 1054 /* starting and stopping PMCs */ 1055 int (*pcd_start_pmc)(int _cpu, int _ri, struct pmc *_pm); 1056 int (*pcd_stop_pmc)(int _cpu, int _ri, struct pmc *_pm); 1057 1058 /* description */ 1059 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1060 struct pmc **_ppmc); 1061 int (*pcd_get_caps)(int _ri, uint32_t *_caps); 1062 1063 /* class-dependent initialization & finalization */ 1064 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1065 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1066 1067 /* machine-specific interface */ 1068 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1069 }; 1070 1071 /* 1072 * struct pmc_mdep 1073 * 1074 * Machine dependent bits needed per CPU type. 1075 */ 1076 1077 struct pmc_mdep { 1078 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1079 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1080 uint32_t pmd_nclass; /* number of PMC classes present */ 1081 1082 /* 1083 * Machine dependent methods. 1084 */ 1085 1086 /* thread context switch in/out */ 1087 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1088 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1089 1090 /* handle a PMC interrupt */ 1091 int (*pmd_intr)(struct trapframe *_tf); 1092 1093 /* 1094 * PMC class dependent information. 1095 */ 1096 struct pmc_classdep pmd_classdep[]; 1097 }; 1098 1099 /* 1100 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1101 * to struct pmc_cpu descriptors. 1102 */ 1103 1104 extern struct pmc_cpu **pmc_pcpu; 1105 1106 /* driver statistics */ 1107 extern struct pmc_driverstats pmc_stats; 1108 1109 #if defined(HWPMC_DEBUG) 1110 1111 /* HWPMC_DEBUG without KTR will compile but is a no-op. */ 1112 #if !defined(KTR) || !defined(KTR_COMPILE) || ((KTR_COMPILE & KTR_SUBSYS) == 0) 1113 #error "HWPMC_DEBUG requires KTR and KTR_COMPILE=KTR_SUBSYS -- see ktr(4)" 1114 #endif 1115 1116 #include <sys/ktr.h> 1117 1118 #define __pmcdbg_used /* unused variable annotation */ 1119 1120 /* 1121 * Debug flags, major flag groups. 1122 * 1123 * Please keep the DEBUGGING section of the hwpmc(4) man page in sync. 1124 */ 1125 struct pmc_debugflags { 1126 int pdb_CPU; 1127 int pdb_CSW; 1128 int pdb_LOG; 1129 int pdb_MDP; 1130 int pdb_MOD; 1131 int pdb_OWN; 1132 int pdb_PMC; 1133 int pdb_PRC; 1134 int pdb_SAM; 1135 }; 1136 1137 extern struct pmc_debugflags pmc_debugflags; 1138 1139 #define KTR_PMC KTR_SUBSYS 1140 1141 #define PMC_DEBUG_STRSIZE 128 1142 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1143 1144 #define PMCDBG0(M, N, L, F) do { \ 1145 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1146 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1147 } while (0) 1148 #define PMCDBG1(M, N, L, F, p1) do { \ 1149 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1150 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1151 } while (0) 1152 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1153 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1154 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1155 } while (0) 1156 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1157 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1158 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1159 } while (0) 1160 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1161 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1162 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1163 } while (0) 1164 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1165 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1166 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1167 p5); \ 1168 } while (0) 1169 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1170 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1171 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1172 p5, p6); \ 1173 } while (0) 1174 1175 /* Major numbers */ 1176 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1177 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1178 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1179 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1180 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1181 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1182 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1183 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1184 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1185 1186 /* Minor numbers */ 1187 1188 /* Common (8 bits) */ 1189 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1190 #define PMC_DEBUG_MIN_REL 1 /* release */ 1191 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1192 #define PMC_DEBUG_MIN_INI 3 /* init */ 1193 #define PMC_DEBUG_MIN_FND 4 /* find */ 1194 1195 /* MODULE */ 1196 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1197 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1198 1199 /* OWN */ 1200 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1201 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1202 1203 /* PROCESSES */ 1204 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1205 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1206 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1207 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1208 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1209 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1210 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1211 1212 /* CONTEXT SWITCHES */ 1213 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1214 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1215 1216 /* PMC */ 1217 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1218 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1219 1220 /* MACHINE DEPENDENT LAYER */ 1221 #define PMC_DEBUG_MIN_REA 8 /* read */ 1222 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1223 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1224 #define PMC_DEBUG_MIN_STA 11 /* start */ 1225 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1226 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1227 1228 /* CPU */ 1229 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1230 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1231 1232 /* LOG */ 1233 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1234 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1235 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1236 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1237 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1238 1239 #else 1240 #define __pmcdbg_used __unused 1241 #define PMCDBG0(M, N, L, F) /* nothing */ 1242 #define PMCDBG1(M, N, L, F, p1) 1243 #define PMCDBG2(M, N, L, F, p1, p2) 1244 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1245 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1246 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1247 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1248 #endif 1249 1250 /* declare a dedicated memory pool */ 1251 MALLOC_DECLARE(M_PMC); 1252 1253 /* 1254 * Functions 1255 */ 1256 1257 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1258 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1259 int pmc_getrowdisp(int _ri); 1260 int pmc_process_interrupt_mp(int _ring, struct pmc *_pm, 1261 struct trapframe *_tf, struct pmc_multipart *mp); 1262 int pmc_process_interrupt(int _ring, struct pmc *_pm, 1263 struct trapframe *_tf); 1264 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1265 struct trapframe *_tf); 1266 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1267 struct trapframe *_tf); 1268 void pmc_restore_cpu_binding(struct pmc_binding *pb); 1269 void pmc_save_cpu_binding(struct pmc_binding *pb); 1270 void pmc_select_cpu(int cpu); 1271 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1272 void pmc_mdep_free(struct pmc_mdep *md); 1273 uint64_t pmc_rdtsc(void); 1274 #endif /* _KERNEL */ 1275 #endif /* _SYS_PMC_H_ */ 1276