1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1991 Regents of the University of California.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and William Jolitz of UUNET Technologies Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * Derived from hp300 version by Mike Hibler, this version by William
37 * Jolitz uses a recursive map [a pde points to the page directory] to
38 * map the page tables using the pagetables themselves. This is done to
39 * reduce the impact on kernel virtual memory for lots of sparse address
40 * space, and to reduce the cost of memory to each process.
41 */
42
43 #ifdef __i386__
44 #include <i386/pmap.h>
45 #else /* !__i386__ */
46
47 #ifndef _MACHINE_PMAP_H_
48 #define _MACHINE_PMAP_H_
49
50 #include <machine/pte.h>
51
52 /*
53 * Define the PG_xx macros in terms of the bits on x86 PTEs.
54 */
55 #define PG_V X86_PG_V
56 #define PG_RW X86_PG_RW
57 #define PG_U X86_PG_U
58 #define PG_NC_PWT X86_PG_NC_PWT
59 #define PG_NC_PCD X86_PG_NC_PCD
60 #define PG_A X86_PG_A
61 #define PG_M X86_PG_M
62 #define PG_PS X86_PG_PS
63 #define PG_PTE_PAT X86_PG_PTE_PAT
64 #define PG_G X86_PG_G
65 #define PG_AVAIL1 X86_PG_AVAIL1
66 #define PG_AVAIL2 X86_PG_AVAIL2
67 #define PG_AVAIL3 X86_PG_AVAIL3
68 #define PG_PDE_PAT X86_PG_PDE_PAT
69 #define PG_NX X86_PG_NX
70 #define PG_PDE_CACHE X86_PG_PDE_CACHE
71 #define PG_PTE_CACHE X86_PG_PTE_CACHE
72
73 /* Our various interpretations of the above */
74 #define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */
75 #define PG_MANAGED X86_PG_AVAIL2
76 #define EPT_PG_EMUL_V X86_PG_AVAIL(52)
77 #define EPT_PG_EMUL_RW X86_PG_AVAIL(53)
78 #define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */
79
80 /*
81 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
82 * (PTE) page mappings have identical settings for the following fields:
83 */
84 #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \
85 PG_M | PG_U | PG_RW | PG_V | PG_PKU_MASK)
86
87 /*
88 * undef the PG_xx macros that define bits in the regular x86 PTEs that
89 * have a different position in nested PTEs. This is done when compiling
90 * code that needs to be aware of the differences between regular x86 and
91 * nested PTEs.
92 *
93 * The appropriate bitmask will be calculated at runtime based on the pmap
94 * type.
95 */
96 #ifdef AMD64_NPT_AWARE
97 #undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */
98 #undef PG_G
99 #undef PG_A
100 #undef PG_M
101 #undef PG_PDE_PAT
102 #undef PG_PDE_CACHE
103 #undef PG_PTE_PAT
104 #undef PG_PTE_CACHE
105 #undef PG_RW
106 #undef PG_V
107 #endif
108
109 /*
110 * Pte related macros. This is complicated by having to deal with
111 * the sign extension of the 48th bit.
112 */
113 #define KV4ADDR(l4, l3, l2, l1) ( \
114 ((unsigned long)-1 << 47) | \
115 ((unsigned long)(l4) << PML4SHIFT) | \
116 ((unsigned long)(l3) << PDPSHIFT) | \
117 ((unsigned long)(l2) << PDRSHIFT) | \
118 ((unsigned long)(l1) << PAGE_SHIFT))
119 #define KV5ADDR(l5, l4, l3, l2, l1) ( \
120 ((unsigned long)-1 << 56) | \
121 ((unsigned long)(l5) << PML5SHIFT) | \
122 ((unsigned long)(l4) << PML4SHIFT) | \
123 ((unsigned long)(l3) << PDPSHIFT) | \
124 ((unsigned long)(l2) << PDRSHIFT) | \
125 ((unsigned long)(l1) << PAGE_SHIFT))
126
127 #define UVADDR(l5, l4, l3, l2, l1) ( \
128 ((unsigned long)(l5) << PML5SHIFT) | \
129 ((unsigned long)(l4) << PML4SHIFT) | \
130 ((unsigned long)(l3) << PDPSHIFT) | \
131 ((unsigned long)(l2) << PDRSHIFT) | \
132 ((unsigned long)(l1) << PAGE_SHIFT))
133
134 /*
135 * Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so,
136 * but setting it larger than NDMPML4E makes no sense.
137 *
138 * Each slot provides .5 TB of kernel virtual space.
139 */
140 #define NKPML4E 4
141
142 /*
143 * Number of PML4 slots for the KASAN shadow map. It requires 1 byte of memory
144 * for every 8 bytes of the kernel address space.
145 */
146 #define NKASANPML4E ((NKPML4E + 7) / 8)
147
148 /*
149 * Number of PML4 slots for the KMSAN shadow and origin maps. These are
150 * one-to-one with the kernel map.
151 */
152 #define NKMSANSHADPML4E NKPML4E
153 #define NKMSANORIGPML4E NKPML4E
154
155 /*
156 * We use the same numbering of the page table pages for 5-level and
157 * 4-level paging structures.
158 */
159 #define NUPML5E (NPML5EPG / 2) /* number of userland PML5
160 pages */
161 #define NUPML4E (NUPML5E * NPML4EPG) /* number of userland PML4
162 pages */
163 #define NUPDPE (NUPML4E * NPDPEPG) /* number of userland PDP
164 pages */
165 #define NUPDE (NUPDPE * NPDEPG) /* number of userland PD
166 entries */
167 #define NUP4ML4E (NPML4EPG / 2)
168
169 /*
170 * NDMPML4E is the maximum number of PML4 entries that will be
171 * used to implement the direct map. It must be a power of two,
172 * and should generally exceed NKPML4E. The maximum possible
173 * value is 64; using 128 will make the direct map intrude into
174 * the recursive page table map.
175 */
176 #define NDMPML4E 8
177
178 /*
179 * These values control the layout of virtual memory. The starting address
180 * of the direct map, which is controlled by DMPML4I, must be a multiple of
181 * its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.)
182 *
183 * Note: KPML4I is the index of the (single) level 4 page that maps
184 * the KVA that holds KERNBASE, while KPML4BASE is the index of the
185 * first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E
186 * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra
187 * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to
188 * KERNBASE.
189 *
190 * (KPML4I combines with KPDPI to choose where KERNBASE starts.
191 * Or, in other words, KPML4I provides bits 39..47 of KERNBASE,
192 * and KPDPI provides bits 30..38.)
193 */
194 #define PML4PML4I (NPML4EPG / 2) /* Index of recursive pml4 mapping */
195 #define PML5PML5I (NPML5EPG / 2) /* Index of recursive pml5 mapping */
196
197 #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */
198 #define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */
199
200 #define KPML4I (NPML4EPG-1)
201 #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */
202
203 #define KASANPML4I (DMPML4I - NKASANPML4E) /* Below the direct map */
204
205 #define KMSANSHADPML4I (KPML4BASE - NKMSANSHADPML4E)
206 #define KMSANORIGPML4I (DMPML4I - NKMSANORIGPML4E)
207
208 /* Large map: index of the first and max last pml4 entry */
209 #define LMSPML4I (PML4PML4I + 1)
210 #define LMEPML4I (KASANPML4I - 1)
211
212 /*
213 * XXX doesn't really belong here I guess...
214 */
215 #define ISA_HOLE_START 0xa0000
216 #define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
217
218 #define PMAP_PCID_NONE 0xffffffff
219 #define PMAP_PCID_KERN 0
220 #define PMAP_PCID_OVERMAX 0x1000
221 #define PMAP_PCID_OVERMAX_KERN 0x800
222 #define PMAP_PCID_USER_PT 0x800
223
224 #define PMAP_NO_CR3 0xffffffffffffffff
225 #define PMAP_UCR3_NOMASK 0xffffffffffffffff
226
227 #ifndef LOCORE
228
229 #include <sys/kassert.h>
230 #include <sys/queue.h>
231 #include <sys/_cpuset.h>
232 #include <sys/_lock.h>
233 #include <sys/_mutex.h>
234 #include <sys/_pctrie.h>
235 #include <machine/_pmap.h>
236 #include <sys/_pv_entry.h>
237 #include <sys/_rangeset.h>
238 #include <sys/_smr.h>
239
240 #include <vm/_vm_radix.h>
241
242 typedef u_int64_t pd_entry_t;
243 typedef u_int64_t pt_entry_t;
244 typedef u_int64_t pdp_entry_t;
245 typedef u_int64_t pml4_entry_t;
246 typedef u_int64_t pml5_entry_t;
247
248 /*
249 * Address of current address space page table maps and directories.
250 */
251 #ifdef _KERNEL
252 #define addr_P4Tmap (KV4ADDR(PML4PML4I, 0, 0, 0))
253 #define addr_P4Dmap (KV4ADDR(PML4PML4I, PML4PML4I, 0, 0))
254 #define addr_P4DPmap (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0))
255 #define addr_P4ML4map (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I))
256 #define addr_P4ML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t)))
257 #define P4Tmap ((pt_entry_t *)(addr_P4Tmap))
258 #define P4Dmap ((pd_entry_t *)(addr_P4Dmap))
259
260 #define addr_P5Tmap (KV5ADDR(PML5PML5I, 0, 0, 0, 0))
261 #define addr_P5Dmap (KV5ADDR(PML5PML5I, PML5PML5I, 0, 0, 0))
262 #define addr_P5DPmap (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, 0, 0))
263 #define addr_P5ML4map (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, 0))
264 #define addr_P5ML5map \
265 (KVADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I))
266 #define addr_P5ML5pml5e (addr_P5ML5map + (PML5PML5I * sizeof(pml5_entry_t)))
267 #define P5Tmap ((pt_entry_t *)(addr_P5Tmap))
268 #define P5Dmap ((pd_entry_t *)(addr_P5Dmap))
269
270 extern int nkpt; /* Initial number of kernel page tables */
271 extern u_int64_t KPML4phys; /* physical address of kernel level 4 */
272 extern u_int64_t KPML5phys; /* physical address of kernel level 5 */
273
274 /*
275 * virtual address to page table entry and
276 * to physical address.
277 * Note: these work recursively, thus vtopte of a pte will give
278 * the corresponding pde that in turn maps it.
279 */
280 pt_entry_t *vtopte(vm_offset_t);
281 #define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
282
283 #define pte_load_store(ptep, pte) atomic_swap_long(ptep, pte)
284 #define pte_load_clear(ptep) atomic_swap_long(ptep, 0)
285 #define pte_store(ptep, pte) do { \
286 *(u_long *)(ptep) = (u_long)(pte); \
287 } while (0)
288 #define pte_clear(ptep) pte_store(ptep, 0)
289
290 #define pde_store(pdep, pde) pte_store(pdep, pde)
291
292 extern pt_entry_t pg_nx;
293
294 #endif /* _KERNEL */
295
296 /*
297 * Pmap stuff
298 */
299
300 /*
301 * Locks
302 * (p) PV list lock
303 */
304 struct md_page {
305 TAILQ_HEAD(, pv_entry) pv_list; /* (p) */
306 int pv_gen; /* (p) */
307 int pat_mode;
308 };
309
310 enum pmap_type {
311 PT_X86, /* regular x86 page tables */
312 PT_EPT, /* Intel's nested page tables */
313 PT_RVI, /* AMD's nested page tables */
314 };
315
316 /*
317 * The kernel virtual address (KVA) of the level 4 page table page is always
318 * within the direct map (DMAP) region.
319 */
320 struct pmap {
321 struct mtx pm_mtx;
322 pml4_entry_t *pm_pmltop; /* KVA of top level page table */
323 pml4_entry_t *pm_pmltopu; /* KVA of user top page table */
324 uint64_t pm_cr3;
325 uint64_t pm_ucr3;
326 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
327 cpuset_t pm_active; /* active on cpus */
328 enum pmap_type pm_type; /* regular or nested tables */
329 struct pmap_statistics pm_stats; /* pmap statistics */
330 struct vm_radix pm_root; /* spare page table pages */
331 long pm_eptgen; /* EPT pmap generation id */
332 smr_t pm_eptsmr;
333 int pm_flags;
334 struct pmap_pcid *pm_pcidp;
335 struct rangeset pm_pkru;
336 };
337
338 /* flags */
339 #define PMAP_NESTED_IPIMASK 0xff
340 #define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */
341 #define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */
342 #define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */
343
344 typedef struct pmap *pmap_t;
345
346 #ifdef _KERNEL
347 extern struct pmap kernel_pmap_store;
348 #define kernel_pmap (&kernel_pmap_store)
349
350 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
351 #define PMAP_LOCK_ASSERT(pmap, type) \
352 mtx_assert(&(pmap)->pm_mtx, (type))
353 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
354 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
355 NULL, MTX_DEF | MTX_DUPOK)
356 #define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
357 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
358 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
359 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
360
361 int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags);
362 int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype);
363
364 extern caddr_t CADDR1;
365 extern pt_entry_t *CMAP1;
366 extern vm_offset_t virtual_avail;
367 extern vm_offset_t virtual_end;
368 extern vm_paddr_t dmaplimit;
369 extern int pmap_pcid_enabled;
370 extern int invpcid_works;
371 extern int invlpgb_works;
372 extern int invlpgb_maxcnt;
373 extern int pmap_pcid_invlpg_workaround;
374 extern int pmap_pcid_invlpg_workaround_uena;
375
376 #define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
377 #define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0)
378 #define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz))
379
380 #define pmap_vm_page_alloc_check(m) \
381 KASSERT(m->phys_addr < kernphys || \
382 m->phys_addr >= kernphys + (vm_offset_t)&_end - KERNSTART, \
383 ("allocating kernel page %p pa %#lx kernphys %#lx end %p", \
384 m, m->phys_addr, kernphys, &_end));
385
386 struct thread;
387
388 void pmap_activate_boot(pmap_t pmap);
389 void pmap_activate_sw(struct thread *);
390 void pmap_allow_2m_x_ept_recalculate(void);
391 void pmap_bootstrap(vm_paddr_t *);
392 int pmap_cache_bits(pmap_t pmap, int mode, bool is_pde);
393 int pmap_change_attr(vm_offset_t, vm_size_t, int);
394 int pmap_change_prot(vm_offset_t, vm_size_t, vm_prot_t);
395 void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, bool invalidate);
396 void pmap_flush_cache_range(vm_offset_t, vm_offset_t);
397 void pmap_flush_cache_phys_range(vm_paddr_t, vm_paddr_t, vm_memattr_t);
398 void pmap_init_pat(void);
399 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
400 void *pmap_kenter_temporary(vm_paddr_t pa, int i);
401 vm_paddr_t pmap_kextract(vm_offset_t);
402 void pmap_kremove(vm_offset_t);
403 int pmap_large_map(vm_paddr_t, vm_size_t, void **, vm_memattr_t);
404 void pmap_large_map_wb(void *sva, vm_size_t len);
405 void pmap_large_unmap(void *sva, vm_size_t len);
406 void *pmap_mapbios(vm_paddr_t, vm_size_t);
407 void *pmap_mapdev(vm_paddr_t, vm_size_t);
408 void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
409 void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size);
410 bool pmap_not_in_di(void);
411 bool pmap_page_is_mapped(vm_page_t m);
412 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
413 void pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma);
414 void pmap_pinit_pml4(vm_page_t);
415 void pmap_pinit_pml5(vm_page_t);
416 bool pmap_ps_enabled(pmap_t pmap);
417 void pmap_unmapdev(void *, vm_size_t);
418 void pmap_invalidate_page(pmap_t, vm_offset_t);
419 void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
420 void pmap_invalidate_all(pmap_t);
421 void pmap_invalidate_cache(void);
422 void pmap_invalidate_cache_pages(vm_page_t *pages, int count);
423 void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
424 void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
425 void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num);
426 bool pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, bool);
427 void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, bool);
428 void pmap_map_delete(pmap_t, vm_offset_t, vm_offset_t);
429 void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec);
430 void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva);
431 void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3);
432 void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va);
433 void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva,
434 vm_offset_t eva);
435 int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
436 int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
437 u_int keyidx, int flags);
438 void pmap_thread_init_invl_gen(struct thread *td);
439 int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap);
440 void pmap_page_array_startup(long count);
441 vm_page_t pmap_page_alloc_below_4g(bool zeroed);
442
443 #if defined(KASAN) || defined(KMSAN)
444 void pmap_san_enter(vm_offset_t);
445 #endif
446
447 /*
448 * Returns a pointer to a set of CPUs on which the pmap is currently active.
449 * Note that the set can be modified without any mutual exclusion, so a copy
450 * must be made if a stable value is required.
451 */
452 static __inline volatile cpuset_t *
pmap_invalidate_cpu_mask(pmap_t pmap)453 pmap_invalidate_cpu_mask(pmap_t pmap)
454 {
455 return (&pmap->pm_active);
456 }
457
458 #if defined(_SYS_PCPU_H_) && defined(_MACHINE_CPUFUNC_H_)
459 /*
460 * It seems that AlderLake+ small cores have some microarchitectural
461 * bug, which results in the INVLPG instruction failing to flush all
462 * global TLB entries when PCID is enabled. Work around it for now,
463 * by doing global invalidation on small cores instead of INVLPG.
464 */
465 static __inline void
pmap_invlpg(pmap_t pmap,vm_offset_t va)466 pmap_invlpg(pmap_t pmap, vm_offset_t va)
467 {
468 if (pmap == kernel_pmap && PCPU_GET(pcid_invlpg_workaround)) {
469 struct invpcid_descr d = { 0 };
470
471 invpcid(&d, INVPCID_CTXGLOB);
472 } else {
473 invlpg(va);
474 }
475 }
476 #endif /* sys/pcpu.h && machine/cpufunc.h */
477
478 #if defined(_SYS_PCPU_H_)
479 /* Return pcid for the pmap pmap on current cpu */
480 static __inline uint32_t
pmap_get_pcid(pmap_t pmap)481 pmap_get_pcid(pmap_t pmap)
482 {
483 struct pmap_pcid *pcidp;
484
485 MPASS(pmap_pcid_enabled);
486 pcidp = zpcpu_get(pmap->pm_pcidp);
487 return (pcidp->pm_pcid);
488 }
489 #endif /* sys/pcpu.h */
490
491 /*
492 * Invalidation request. PCPU pc_smp_tlb_op uses u_int instead of the
493 * enum to avoid both namespace and ABI issues (with enums).
494 */
495 enum invl_op_codes {
496 INVL_OP_TLB = 1,
497 INVL_OP_TLB_INVPCID = 2,
498 INVL_OP_TLB_INVPCID_PTI = 3,
499 INVL_OP_TLB_PCID = 4,
500 INVL_OP_PGRNG = 5,
501 INVL_OP_PGRNG_INVPCID = 6,
502 INVL_OP_PGRNG_PCID = 7,
503 INVL_OP_PG = 8,
504 INVL_OP_PG_INVPCID = 9,
505 INVL_OP_PG_PCID = 10,
506 INVL_OP_CACHE = 11,
507 };
508
509 typedef void (*smp_invl_local_cb_t)(struct pmap *, vm_offset_t addr1,
510 vm_offset_t addr2);
511 typedef void (*smp_targeted_tlb_shootdown_t)(pmap_t, vm_offset_t, vm_offset_t,
512 smp_invl_local_cb_t, enum invl_op_codes);
513
514 void smp_targeted_tlb_shootdown_native(pmap_t, vm_offset_t, vm_offset_t,
515 smp_invl_local_cb_t, enum invl_op_codes);
516 extern smp_targeted_tlb_shootdown_t smp_targeted_tlb_shootdown;
517
518 #endif /* _KERNEL */
519
520 /* Return various clipped indexes for a given VA */
521 static __inline vm_pindex_t
pmap_pte_index(vm_offset_t va)522 pmap_pte_index(vm_offset_t va)
523 {
524
525 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
526 }
527
528 static __inline vm_pindex_t
pmap_pde_index(vm_offset_t va)529 pmap_pde_index(vm_offset_t va)
530 {
531
532 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
533 }
534
535 static __inline vm_pindex_t
pmap_pdpe_index(vm_offset_t va)536 pmap_pdpe_index(vm_offset_t va)
537 {
538
539 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
540 }
541
542 static __inline vm_pindex_t
pmap_pml4e_index(vm_offset_t va)543 pmap_pml4e_index(vm_offset_t va)
544 {
545
546 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
547 }
548
549 static __inline vm_pindex_t
pmap_pml5e_index(vm_offset_t va)550 pmap_pml5e_index(vm_offset_t va)
551 {
552
553 return ((va >> PML5SHIFT) & ((1ul << NPML5EPGSHIFT) - 1));
554 }
555
556 #endif /* !LOCORE */
557
558 #endif /* !_MACHINE_PMAP_H_ */
559
560 #endif /* __i386__ */
561