xref: /illumos-gate/usr/src/uts/sun4u/fjlite/os/fjlite.c (revision 7c478bd95313f5f23a4c958a745db2134aa03244)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/sunddi.h>
32 #include <sys/esunddi.h>
33 #include <sys/ddi.h>
34 
35 #include <sys/platform_module.h>
36 #include <sys/errno.h>
37 
38 void
startup_platform(void)39 startup_platform(void)
40 {
41 }
42 
43 int
set_platform_tsb_spares()44 set_platform_tsb_spares()
45 {
46 	return (0);
47 }
48 
49 void
set_platform_defaults(void)50 set_platform_defaults(void)
51 {
52 }
53 
54 
55 /*
56  * Definitions for accessing the pci config space of the isa node
57  * of Southbridge.
58  */
59 #define	PLATFORM_ISA_PATHNAME	"/pci@1f,0/isa@7"
60 #define	PLATFORM_ISA_PATHNAME_WITH_SIMBA	"/pci@1f,0/pci@1,1/isa@7"
61 static ddi_acc_handle_t platform_isa_handle;	/* handle for isa pci space */
62 
63 void
load_platform_drivers(void)64 load_platform_drivers(void)
65 {
66 	dev_info_t 		*dip;		/* dip of the isa driver */
67 	int			simba_present = 0;
68 	dev_info_t		*root_child_node;
69 
70 
71 	/*
72 	 * Install Isa driver. This is required for the southbridge IDE
73 	 * workaround - to reset the IDE channel during IDE bus reset.
74 	 * Panic the system in case ISA driver could not be loaded or
75 	 * any problem in accessing its pci config space. Since the register
76 	 * to reset the channel for IDE is in ISA config space!.
77 	 */
78 	root_child_node = ddi_get_child(ddi_root_node());
79 
80 	while (root_child_node != NULL) {
81 		if (strcmp(ddi_node_name(root_child_node), "pci") == 0) {
82 			root_child_node = ddi_get_child(root_child_node);
83 			if (strcmp(ddi_node_name(root_child_node), "pci") == 0)
84 				simba_present = 1;
85 			break;
86 		}
87 		root_child_node = ddi_get_next_sibling(root_child_node);
88 	}
89 
90 
91 	if (simba_present)
92 	    dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME_WITH_SIMBA, 0);
93 	else
94 	    dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME, 0);
95 
96 	if (dip == NULL) {
97 		cmn_err(CE_PANIC, "Could not install the isa driver\n");
98 		return;
99 	}
100 
101 	if (pci_config_setup(dip, &platform_isa_handle) != DDI_SUCCESS) {
102 		cmn_err(CE_PANIC, "Could not get the config space of isa\n");
103 		return;
104 	}
105 }
106 
107 /*
108  * This routine provides a workaround for a bug in the SB chip which
109  * can cause data corruption. Will be invoked from the IDE HBA driver for
110  * Acer SouthBridge at the time of IDE bus reset.
111  */
112 /*ARGSUSED*/
113 int
plat_ide_chipreset(dev_info_t * dip,int chno)114 plat_ide_chipreset(dev_info_t *dip, int chno)
115 {
116 	uint8_t	val;
117 	int	ret = DDI_SUCCESS;
118 
119 	val = pci_config_get8(platform_isa_handle, 0x58);
120 	/*
121 	 * The dip passed as the argument is not used for platform.
122 	 * This will be needed for platforms which have multiple on-board SB,
123 	 * The dip passed will be used to match the corresponding ISA node.
124 	 */
125 	switch (chno) {
126 		case 0:
127 			/*
128 			 * First disable the primary channel then re-enable it.
129 			 * As per ALI no wait should be required in between have
130 			 * given 1ms delay in between to be on safer side.
131 			 * bit 2 of register 0x58 when 0 disable the channel 0.
132 			 * bit 2 of register 0x58 when 1 enables the channel 0.
133 			 */
134 			pci_config_put8(platform_isa_handle, 0x58, val & 0xFB);
135 			drv_usecwait(1000);
136 			pci_config_put8(platform_isa_handle, 0x58, val);
137 			break;
138 		case 1:
139 			/*
140 			 * bit 3 of register 0x58 when 0 disable the channel 1.
141 			 * bit 3 of register 0x58 when 1 enables the channel 1.
142 			 */
143 			pci_config_put8(platform_isa_handle, 0x58, val & 0xF7);
144 			drv_usecwait(1000);
145 			pci_config_put8(platform_isa_handle, 0x58, val);
146 			break;
147 		default:
148 			/*
149 			 * Unknown channel number passed. Return failure.
150 			 */
151 			ret = DDI_FAILURE;
152 	}
153 
154 	return (ret);
155 }
156 
157 
158 
159 /*ARGSUSED*/
160 int
plat_cpu_poweron(struct cpu * cp)161 plat_cpu_poweron(struct cpu *cp)
162 {
163 	return (ENOTSUP);	/* not supported on this platform */
164 }
165 
166 /*ARGSUSED*/
167 int
plat_cpu_poweroff(struct cpu * cp)168 plat_cpu_poweroff(struct cpu *cp)
169 {
170 	return (ENOTSUP);	/* not supported on this platform */
171 }
172 
173 /*ARGSUSED*/
174 void
plat_freelist_process(int mnode)175 plat_freelist_process(int mnode)
176 {
177 }
178 
179 char *platform_module_list[] = {
180 	(char *)0
181 };
182 
183 /*ARGSUSED*/
184 void
plat_tod_fault(enum tod_fault_type tod_bad)185 plat_tod_fault(enum tod_fault_type tod_bad)
186 {
187 }
188