1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH11K_CORE_H
8 #define ATH11K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/rhashtable.h>
17 #include <linux/average.h>
18 #if defined(__FreeBSD__)
19 #include <linux/wait.h>
20 #endif
21 #include <linux/firmware.h>
22 #include <linux/suspend.h>
23 #if defined(CONFIG_OF)
24 #include <linux/of.h>
25 #endif
26
27 #include "qmi.h"
28 #include "htc.h"
29 #include "wmi.h"
30 #include "hal.h"
31 #include "dp.h"
32 #include "ce.h"
33 #include "mac.h"
34 #include "hw.h"
35 #include "hal_rx.h"
36 #include "reg.h"
37 #include "thermal.h"
38 #include "dbring.h"
39 #include "spectral.h"
40 #include "wow.h"
41 #include "fw.h"
42 #include "coredump.h"
43
44 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
45
46 #define ATH11K_TX_MGMT_NUM_PENDING_MAX 512
47
48 #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
49
50 /* Pending management packets threshold for dropping probe responses */
51 #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
52
53 #define ATH11K_INVALID_HW_MAC_ID 0xFF
54 #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ)
55
56 /* SMBIOS type containing Board Data File Name Extension */
57 #define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8
58
59 /* SMBIOS type structure length (excluding strings-set) */
60 #define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9
61
62 /* The magic used by QCA spec */
63 #define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_"
64
65 extern unsigned int ath11k_frame_mode;
66 extern bool ath11k_ftm_mode;
67
68 #define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
69
70 #define ATH11K_MON_TIMER_INTERVAL 10
71 #define ATH11K_RESET_TIMEOUT_HZ (20 * HZ)
72 #define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3
73 #define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5
74 #define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
75 #define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
76 #define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
77
78 enum ath11k_supported_bw {
79 ATH11K_BW_20 = 0,
80 ATH11K_BW_40 = 1,
81 ATH11K_BW_80 = 2,
82 ATH11K_BW_160 = 3,
83 };
84
85 enum ath11k_bdf_search {
86 ATH11K_BDF_SEARCH_DEFAULT,
87 ATH11K_BDF_SEARCH_BUS_AND_BOARD,
88 };
89
90 #if defined(__FreeBSD__)
91 #ifdef WME_AC_BE
92 #undef WME_AC_BE
93 #endif
94 #ifdef WME_AC_BK
95 #undef WME_AC_BK
96 #endif
97 #ifdef WME_AC_VI
98 #undef WME_AC_VI
99 #endif
100 #ifdef WME_AC_VO
101 #undef WME_AC_VO
102 #endif
103 #ifdef WME_NUM_AC
104 #undef WME_NUM_AC
105 #endif
106 #endif
107
108 enum wme_ac {
109 WME_AC_BE,
110 WME_AC_BK,
111 WME_AC_VI,
112 WME_AC_VO,
113 WME_NUM_AC
114 };
115
116 #define ATH11K_HT_MCS_MAX 7
117 #define ATH11K_VHT_MCS_MAX 9
118 #define ATH11K_HE_MCS_MAX 11
119
120 enum ath11k_crypt_mode {
121 /* Only use hardware crypto engine */
122 ATH11K_CRYPT_MODE_HW,
123 /* Only use software crypto */
124 ATH11K_CRYPT_MODE_SW,
125 };
126
ath11k_tid_to_ac(u32 tid)127 static inline enum wme_ac ath11k_tid_to_ac(u32 tid)
128 {
129 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
130 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
131 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
132 WME_AC_VO);
133 }
134
135 enum ath11k_skb_flags {
136 ATH11K_SKB_HW_80211_ENCAP = BIT(0),
137 ATH11K_SKB_CIPHER_SET = BIT(1),
138 };
139
140 struct ath11k_skb_cb {
141 dma_addr_t paddr;
142 u8 eid;
143 u8 flags;
144 u32 cipher;
145 struct ath11k *ar;
146 struct ieee80211_vif *vif;
147 } __packed;
148
149 struct ath11k_skb_rxcb {
150 dma_addr_t paddr;
151 bool is_first_msdu;
152 bool is_last_msdu;
153 bool is_continuation;
154 bool is_mcbc;
155 bool is_eapol;
156 struct hal_rx_desc *rx_desc;
157 u8 err_rel_src;
158 u8 err_code;
159 u8 mac_id;
160 u8 unmapped;
161 u8 is_frag;
162 u8 tid;
163 u16 peer_id;
164 u16 seq_no;
165 };
166
167 enum ath11k_hw_rev {
168 ATH11K_HW_IPQ8074,
169 ATH11K_HW_QCA6390_HW20,
170 ATH11K_HW_IPQ6018_HW10,
171 ATH11K_HW_QCN9074_HW10,
172 ATH11K_HW_WCN6855_HW20,
173 ATH11K_HW_WCN6855_HW21,
174 ATH11K_HW_WCN6750_HW10,
175 ATH11K_HW_IPQ5018_HW10,
176 ATH11K_HW_QCA2066_HW21,
177 ATH11K_HW_QCA6698AQ_HW21,
178 };
179
180 enum ath11k_firmware_mode {
181 /* the default mode, standard 802.11 functionality */
182 ATH11K_FIRMWARE_MODE_NORMAL,
183
184 /* factory tests etc */
185 ATH11K_FIRMWARE_MODE_FTM,
186
187 /* Cold boot calibration */
188 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7,
189 };
190
191 extern bool ath11k_cold_boot_cal;
192
193 #define ATH11K_IRQ_NUM_MAX 52
194 #define ATH11K_EXT_IRQ_NUM_MAX 16
195
196 struct ath11k_ext_irq_grp {
197 struct ath11k_base *ab;
198 u32 irqs[ATH11K_EXT_IRQ_NUM_MAX];
199 u32 num_irq;
200 u32 grp_id;
201 u64 timestamp;
202 bool napi_enabled;
203 struct napi_struct napi;
204 struct net_device *napi_ndev;
205 };
206
207 enum ath11k_smbios_cc_type {
208 /* disable country code setting from SMBIOS */
209 ATH11K_SMBIOS_CC_DISABLE = 0,
210
211 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
212 ATH11K_SMBIOS_CC_ISO = 1,
213
214 /* worldwide regdomain */
215 ATH11K_SMBIOS_CC_WW = 2,
216 };
217
218 struct ath11k_smbios_bdf {
219 struct dmi_header hdr;
220
221 u8 features_disabled;
222
223 /* enum ath11k_smbios_cc_type */
224 u8 country_code_flag;
225
226 /* To set specific country, you need to set country code
227 * flag=ATH11K_SMBIOS_CC_ISO first, then if country is United
228 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
229 * 0x53). To set country to INDONESIA, then country code value =
230 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
231 * ATH11K_SMBIOS_CC_WW, then you can use worldwide regulatory
232 * setting.
233 */
234 u16 cc_code;
235
236 u8 bdf_enabled;
237 u8 bdf_ext[];
238 } __packed;
239
240 #define HEHANDLE_CAP_PHYINFO_SIZE 3
241 #define HECAP_PHYINFO_SIZE 9
242 #define HECAP_MACINFO_SIZE 5
243 #define HECAP_TXRX_MCS_NSS_SIZE 2
244 #define HECAP_PPET16_PPET8_MAX_SIZE 25
245
246 #define HE_PPET16_PPET8_SIZE 8
247
248 /* 802.11ax PPE (PPDU packet Extension) threshold */
249 struct he_ppe_threshold {
250 u32 numss_m1;
251 u32 ru_mask;
252 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
253 };
254
255 struct ath11k_he {
256 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
257 u32 hecap_rxmcsnssmap;
258 u32 hecap_txmcsnssmap;
259 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
260 struct he_ppe_threshold hecap_ppet;
261 u32 heop_param;
262 };
263
264 #define MAX_RADIOS 3
265
266 /* ipq5018 hw param macros */
267 #define MAX_RADIOS_5018 1
268 #define CE_CNT_5018 6
269 #define TARGET_CE_CNT_5018 9
270 #define SVC_CE_MAP_LEN_5018 17
271 #define RXDMA_PER_PDEV_5018 1
272
273 enum {
274 WMI_HOST_TP_SCALE_MAX = 0,
275 WMI_HOST_TP_SCALE_50 = 1,
276 WMI_HOST_TP_SCALE_25 = 2,
277 WMI_HOST_TP_SCALE_12 = 3,
278 WMI_HOST_TP_SCALE_MIN = 4,
279 WMI_HOST_TP_SCALE_SIZE = 5,
280 };
281
282 enum ath11k_scan_state {
283 ATH11K_SCAN_IDLE,
284 ATH11K_SCAN_STARTING,
285 ATH11K_SCAN_RUNNING,
286 ATH11K_SCAN_ABORTING,
287 };
288
289 enum ath11k_11d_state {
290 ATH11K_11D_IDLE,
291 ATH11K_11D_PREPARING,
292 ATH11K_11D_RUNNING,
293 };
294
295 enum ath11k_dev_flags {
296 ATH11K_CAC_RUNNING,
297 ATH11K_FLAG_CORE_REGISTERED,
298 ATH11K_FLAG_CRASH_FLUSH,
299 ATH11K_FLAG_RAW_MODE,
300 ATH11K_FLAG_HW_CRYPTO_DISABLED,
301 ATH11K_FLAG_BTCOEX,
302 ATH11K_FLAG_RECOVERY,
303 ATH11K_FLAG_UNREGISTERING,
304 ATH11K_FLAG_REGISTERED,
305 ATH11K_FLAG_QMI_FAIL,
306 ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
307 ATH11K_FLAG_CE_IRQ_ENABLED,
308 ATH11K_FLAG_EXT_IRQ_ENABLED,
309 ATH11K_FLAG_FIXED_MEM_RGN,
310 ATH11K_FLAG_DEVICE_INIT_DONE,
311 ATH11K_FLAG_MULTI_MSI_VECTORS,
312 ATH11K_FLAG_FTM_SEGMENTED,
313 };
314
315 enum ath11k_monitor_flags {
316 ATH11K_FLAG_MONITOR_CONF_ENABLED,
317 ATH11K_FLAG_MONITOR_STARTED,
318 ATH11K_FLAG_MONITOR_VDEV_CREATED,
319 };
320
321 #define ATH11K_IPV6_UC_TYPE 0
322 #define ATH11K_IPV6_AC_TYPE 1
323
324 #define ATH11K_IPV6_MAX_COUNT 16
325 #define ATH11K_IPV4_MAX_COUNT 2
326
327 struct ath11k_arp_ns_offload {
328 u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4];
329 u32 ipv4_count;
330 u32 ipv6_count;
331 u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
332 u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
333 u8 ipv6_type[ATH11K_IPV6_MAX_COUNT];
334 bool ipv6_valid[ATH11K_IPV6_MAX_COUNT];
335 u8 mac_addr[ETH_ALEN];
336 };
337
338 struct ath11k_rekey_data {
339 u8 kck[NL80211_KCK_LEN];
340 u8 kek[NL80211_KCK_LEN];
341 u64 replay_ctr;
342 bool enable_offload;
343 };
344
345 /**
346 * struct ath11k_chan_power_info - TPE containing power info per channel chunk
347 * @chan_cfreq: channel center freq (MHz)
348 * e.g.
349 * channel 37/20 MHz, it is 6135
350 * channel 37/40 MHz, it is 6125
351 * channel 37/80 MHz, it is 6145
352 * channel 37/160 MHz, it is 6185
353 * @tx_power: transmit power (dBm)
354 */
355 struct ath11k_chan_power_info {
356 u16 chan_cfreq;
357 s8 tx_power;
358 };
359
360 /* ath11k only deals with 160 MHz, so 8 subchannels */
361 #define ATH11K_NUM_PWR_LEVELS 8
362
363 /**
364 * struct ath11k_reg_tpc_power_info - regulatory TPC power info
365 * @is_psd_power: is PSD power or not
366 * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD
367 * @ap_power_type: type of power (SP/LPI/VLP)
368 * @num_pwr_levels: number of power levels
369 * @reg_max: Array of maximum TX power (dBm) per PSD value
370 * @tpe: TPE values processed from TPE IE
371 * @chan_power_info: power info to send to firmware
372 */
373 struct ath11k_reg_tpc_power_info {
374 bool is_psd_power;
375 u8 eirp_power;
376 enum wmi_reg_6ghz_ap_type ap_power_type;
377 u8 num_pwr_levels;
378 u8 reg_max[ATH11K_NUM_PWR_LEVELS];
379 s8 tpe[ATH11K_NUM_PWR_LEVELS];
380 struct ath11k_chan_power_info chan_power_info[ATH11K_NUM_PWR_LEVELS];
381 };
382
383 struct ath11k_vif {
384 u32 vdev_id;
385 enum wmi_vdev_type vdev_type;
386 enum wmi_vdev_subtype vdev_subtype;
387 u32 beacon_interval;
388 u32 dtim_period;
389 u16 ast_hash;
390 u16 ast_idx;
391 u16 tcl_metadata;
392 u8 hal_addr_search_flags;
393 u8 search_type;
394
395 struct ath11k *ar;
396 struct ieee80211_vif *vif;
397
398 struct wmi_wmm_params_all_arg wmm_params;
399 struct wmi_wmm_params_all_arg muedca_params;
400 struct list_head list;
401 union {
402 struct {
403 u32 uapsd;
404 } sta;
405 struct {
406 /* 127 stations; wmi limit */
407 u8 tim_bitmap[16];
408 u8 tim_len;
409 u32 ssid_len;
410 u8 ssid[IEEE80211_MAX_SSID_LEN];
411 bool hidden_ssid;
412 /* P2P_IE with NoA attribute for P2P_GO case */
413 u32 noa_len;
414 u8 *noa_data;
415 } ap;
416 } u;
417
418 bool is_started;
419 bool is_up;
420 bool ftm_responder;
421 bool spectral_enabled;
422 bool ps;
423 u32 aid;
424 u8 bssid[ETH_ALEN];
425 struct cfg80211_bitrate_mask bitrate_mask;
426 struct delayed_work connection_loss_work;
427 struct work_struct bcn_tx_work;
428 int num_legacy_stations;
429 int rtscts_prot_mode;
430 int txpower;
431 bool rsnie_present;
432 bool wpaie_present;
433 bool bcca_zero_sent;
434 bool do_not_send_tmpl;
435 struct ath11k_arp_ns_offload arp_ns_offload;
436 struct ath11k_rekey_data rekey_data;
437 u32 num_stations;
438 bool reinstall_group_keys;
439
440 struct ath11k_reg_tpc_power_info reg_tpc_info;
441
442 /* Must be last - ends in a flexible-array member.
443 *
444 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
445 * especially because it has a flexible array. Find a better way.
446 */
447 struct ieee80211_chanctx_conf chanctx;
448 };
449
450 struct ath11k_vif_iter {
451 u32 vdev_id;
452 struct ath11k_vif *arvif;
453 };
454
455 struct ath11k_rx_peer_stats {
456 u64 num_msdu;
457 u64 num_mpdu_fcs_ok;
458 u64 num_mpdu_fcs_err;
459 u64 tcp_msdu_count;
460 u64 udp_msdu_count;
461 u64 other_msdu_count;
462 u64 ampdu_msdu_count;
463 u64 non_ampdu_msdu_count;
464 u64 stbc_count;
465 u64 beamformed_count;
466 u64 mcs_count[HAL_RX_MAX_MCS + 1];
467 u64 nss_count[HAL_RX_MAX_NSS];
468 u64 bw_count[HAL_RX_BW_MAX];
469 u64 gi_count[HAL_RX_GI_MAX];
470 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
471 u64 tid_count[IEEE80211_NUM_TIDS + 1];
472 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
473 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
474 u64 rx_duration;
475 u64 dcm_count;
476 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
477 };
478
479 #define ATH11K_HE_MCS_NUM 12
480 #define ATH11K_VHT_MCS_NUM 10
481 #define ATH11K_BW_NUM 4
482 #define ATH11K_NSS_NUM 4
483 #define ATH11K_LEGACY_NUM 12
484 #define ATH11K_GI_NUM 4
485 #define ATH11K_HT_MCS_NUM 32
486
487 enum ath11k_pkt_rx_err {
488 ATH11K_PKT_RX_ERR_FCS,
489 ATH11K_PKT_RX_ERR_TKIP,
490 ATH11K_PKT_RX_ERR_CRYPT,
491 ATH11K_PKT_RX_ERR_PEER_IDX_INVAL,
492 ATH11K_PKT_RX_ERR_MAX,
493 };
494
495 enum ath11k_ampdu_subfrm_num {
496 ATH11K_AMPDU_SUBFRM_NUM_10,
497 ATH11K_AMPDU_SUBFRM_NUM_20,
498 ATH11K_AMPDU_SUBFRM_NUM_30,
499 ATH11K_AMPDU_SUBFRM_NUM_40,
500 ATH11K_AMPDU_SUBFRM_NUM_50,
501 ATH11K_AMPDU_SUBFRM_NUM_60,
502 ATH11K_AMPDU_SUBFRM_NUM_MORE,
503 ATH11K_AMPDU_SUBFRM_NUM_MAX,
504 };
505
506 enum ath11k_amsdu_subfrm_num {
507 ATH11K_AMSDU_SUBFRM_NUM_1,
508 ATH11K_AMSDU_SUBFRM_NUM_2,
509 ATH11K_AMSDU_SUBFRM_NUM_3,
510 ATH11K_AMSDU_SUBFRM_NUM_4,
511 ATH11K_AMSDU_SUBFRM_NUM_MORE,
512 ATH11K_AMSDU_SUBFRM_NUM_MAX,
513 };
514
515 enum ath11k_counter_type {
516 ATH11K_COUNTER_TYPE_BYTES,
517 ATH11K_COUNTER_TYPE_PKTS,
518 ATH11K_COUNTER_TYPE_MAX,
519 };
520
521 enum ath11k_stats_type {
522 ATH11K_STATS_TYPE_SUCC,
523 ATH11K_STATS_TYPE_FAIL,
524 ATH11K_STATS_TYPE_RETRY,
525 ATH11K_STATS_TYPE_AMPDU,
526 ATH11K_STATS_TYPE_MAX,
527 };
528
529 struct ath11k_htt_data_stats {
530 u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM];
531 u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM];
532 u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM];
533 u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM];
534 u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM];
535 u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM];
536 u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM];
537 };
538
539 struct ath11k_htt_tx_stats {
540 struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX];
541 u64 tx_duration;
542 u64 ba_fails;
543 u64 ack_fails;
544 };
545
546 struct ath11k_per_ppdu_tx_stats {
547 u16 succ_pkts;
548 u16 failed_pkts;
549 u16 retry_pkts;
550 u32 succ_bytes;
551 u32 failed_bytes;
552 u32 retry_bytes;
553 };
554
555 DECLARE_EWMA(avg_rssi, 10, 8)
556
557 struct ath11k_sta {
558 struct ath11k_vif *arvif;
559
560 /* the following are protected by ar->data_lock */
561 u32 changed; /* IEEE80211_RC_* */
562 u32 bw;
563 u32 nss;
564 u32 smps;
565 enum hal_pn_type pn_type;
566
567 struct work_struct update_wk;
568 struct work_struct set_4addr_wk;
569 struct rate_info txrate;
570 u32 peer_nss;
571 struct rate_info last_txrate;
572 u64 rx_duration;
573 u64 tx_duration;
574 u8 rssi_comb;
575 struct ewma_avg_rssi avg_rssi;
576 s8 rssi_beacon;
577 s8 chain_signal[IEEE80211_MAX_CHAINS];
578 struct ath11k_htt_tx_stats *tx_stats;
579 struct ath11k_rx_peer_stats *rx_stats;
580
581 #ifdef CONFIG_MAC80211_DEBUGFS
582 /* protected by conf_mutex */
583 bool aggr_mode;
584 #endif
585
586 bool use_4addr_set;
587 u16 tcl_metadata;
588
589 /* Protected with ar->data_lock */
590 enum ath11k_wmi_peer_ps_state peer_ps_state;
591 u64 ps_start_time;
592 u64 ps_start_jiffies;
593 u64 ps_total_duration;
594 bool peer_current_ps_valid;
595
596 u32 bw_prev;
597 };
598
599 #define ATH11K_MIN_5G_FREQ 4150
600 #define ATH11K_MIN_6G_FREQ 5925
601 #define ATH11K_MAX_6G_FREQ 7115
602 #define ATH11K_NUM_CHANS 102
603 #define ATH11K_MAX_5G_CHAN 177
604
605 enum ath11k_state {
606 ATH11K_STATE_OFF,
607 ATH11K_STATE_ON,
608 ATH11K_STATE_RESTARTING,
609 ATH11K_STATE_RESTARTED,
610 ATH11K_STATE_WEDGED,
611 ATH11K_STATE_FTM,
612 /* Add other states as required */
613 };
614
615 /* Antenna noise floor */
616 #define ATH11K_DEFAULT_NOISE_FLOOR -95
617
618 #define ATH11K_INVALID_RSSI_FULL -1
619
620 #define ATH11K_INVALID_RSSI_EMPTY -128
621
622 struct ath11k_fw_stats {
623 struct dentry *debugfs_fwstats;
624 u32 pdev_id;
625 u32 stats_id;
626 struct list_head pdevs;
627 struct list_head vdevs;
628 struct list_head bcn;
629 u32 num_vdev_recvd;
630 u32 num_bcn_recvd;
631 };
632
633 struct ath11k_dbg_htt_stats {
634 u8 type;
635 u8 reset;
636 struct debug_htt_stats_req *stats_req;
637 /* protects shared stats req buffer */
638 spinlock_t lock;
639 };
640
641 #define MAX_MODULE_ID_BITMAP_WORDS 16
642
643 struct ath11k_debug {
644 struct dentry *debugfs_pdev;
645 struct ath11k_dbg_htt_stats htt_stats;
646 u32 extd_tx_stats;
647 u32 extd_rx_stats;
648 u32 pktlog_filter;
649 u32 pktlog_mode;
650 u32 pktlog_peer_valid;
651 u8 pktlog_peer_addr[ETH_ALEN];
652 u32 rx_filter;
653 u32 mem_offset;
654 u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS];
655 struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX];
656 };
657
658 struct ath11k_per_peer_tx_stats {
659 u32 succ_bytes;
660 u32 retry_bytes;
661 u32 failed_bytes;
662 u16 succ_pkts;
663 u16 retry_pkts;
664 u16 failed_pkts;
665 u32 duration;
666 u8 ba_fails;
667 bool is_ampdu;
668 };
669
670 #define ATH11K_FLUSH_TIMEOUT (5 * HZ)
671 #define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
672
673 struct ath11k {
674 struct ath11k_base *ab;
675 struct ath11k_pdev *pdev;
676 struct ieee80211_hw *hw;
677 struct ath11k_pdev_wmi *wmi;
678 struct ath11k_pdev_dp dp;
679 u8 mac_addr[ETH_ALEN];
680 struct ath11k_he ar_he;
681 enum ath11k_state state;
682 bool supports_6ghz;
683 struct {
684 struct completion started;
685 struct completion completed;
686 struct completion on_channel;
687 struct delayed_work timeout;
688 enum ath11k_scan_state state;
689 bool is_roc;
690 int vdev_id;
691 int roc_freq;
692 bool roc_notify;
693 } scan;
694
695 struct {
696 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
697 struct ieee80211_sband_iftype_data
698 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
699 } mac;
700
701 unsigned long dev_flags;
702 unsigned int filter_flags;
703 unsigned long monitor_flags;
704 u32 min_tx_power;
705 u32 max_tx_power;
706 u32 txpower_limit_2g;
707 u32 txpower_limit_5g;
708 u32 txpower_scale;
709 u32 power_scale;
710 u32 chan_tx_pwr;
711 u32 num_stations;
712 u32 max_num_stations;
713 /* To synchronize concurrent synchronous mac80211 callback operations,
714 * concurrent debugfs configuration and concurrent FW statistics events.
715 */
716 struct mutex conf_mutex;
717 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
718 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info,
719 * channel context data, survey info, test mode data, channel_update_queue.
720 */
721 spinlock_t data_lock;
722
723 struct list_head arvifs;
724 /* should never be NULL; needed for regular htt rx */
725 struct ieee80211_channel *rx_channel;
726
727 /* valid during scan; needed for mgmt rx during scan */
728 struct ieee80211_channel *scan_channel;
729
730 u8 cfg_tx_chainmask;
731 u8 cfg_rx_chainmask;
732 u8 num_rx_chains;
733 u8 num_tx_chains;
734 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
735 u8 pdev_idx;
736 u8 lmac_id;
737
738 struct completion peer_assoc_done;
739 struct completion peer_delete_done;
740
741 int install_key_status;
742 struct completion install_key_done;
743
744 int last_wmi_vdev_start_status;
745 struct completion vdev_setup_done;
746 struct completion vdev_delete_done;
747
748 int num_peers;
749 int max_num_peers;
750 u32 num_started_vdevs;
751 u32 num_created_vdevs;
752 unsigned long long allocated_vdev_map;
753
754 struct idr txmgmt_idr;
755 /* protects txmgmt_idr data */
756 spinlock_t txmgmt_idr_lock;
757 atomic_t num_pending_mgmt_tx;
758 wait_queue_head_t txmgmt_empty_waitq;
759
760 /* cycle count is reported twice for each visited channel during scan.
761 * access protected by data_lock
762 */
763 u32 survey_last_rx_clear_count;
764 u32 survey_last_cycle_count;
765
766 /* Channel info events are expected to come in pairs without and with
767 * COMPLETE flag set respectively for each channel visit during scan.
768 *
769 * However there are deviations from this rule. This flag is used to
770 * avoid reporting garbage data.
771 */
772 bool ch_info_can_report_survey;
773 struct survey_info survey[ATH11K_NUM_CHANS];
774 struct completion bss_survey_done;
775
776 struct work_struct regd_update_work;
777 struct work_struct channel_update_work;
778 /* protected with data_lock */
779 struct list_head channel_update_queue;
780
781 struct work_struct wmi_mgmt_tx_work;
782 struct sk_buff_head wmi_mgmt_tx_queue;
783
784 struct ath11k_wow wow;
785 struct completion target_suspend;
786 bool target_suspend_ack;
787 struct ath11k_per_peer_tx_stats peer_tx_stats;
788 struct list_head ppdu_stats_info;
789 u32 ppdu_stat_list_depth;
790
791 struct ath11k_per_peer_tx_stats cached_stats;
792 u32 last_ppdu_id;
793 u32 cached_ppdu_id;
794 int monitor_vdev_id;
795 struct completion fw_mode_reset;
796 u8 ftm_msgref;
797 #ifdef CONFIG_ATH11K_DEBUGFS
798 struct ath11k_debug debug;
799 #endif
800 #ifdef CONFIG_ATH11K_SPECTRAL
801 struct ath11k_spectral spectral;
802 #endif
803 bool dfs_block_radar_events;
804 struct ath11k_thermal thermal;
805 u32 vdev_id_11d_scan;
806 struct completion completed_11d_scan;
807 enum ath11k_11d_state state_11d;
808 bool regdom_set_by_user;
809 int hw_rate_code;
810 u8 twt_enabled;
811 bool nlo_enabled;
812 u8 alpha2[REG_ALPHA2_LEN + 1];
813 struct ath11k_fw_stats fw_stats;
814 struct completion fw_stats_complete;
815 struct completion fw_stats_done;
816
817 /* protected by conf_mutex */
818 bool ps_state_enable;
819 bool ps_timekeeper_enable;
820 s8 max_allowed_tx_power;
821 };
822
823 struct ath11k_band_cap {
824 u32 phy_id;
825 u32 max_bw_supported;
826 u32 ht_cap_info;
827 u32 he_cap_info[2];
828 u32 he_mcs;
829 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
830 struct ath11k_ppe_threshold he_ppet;
831 u16 he_6ghz_capa;
832 };
833
834 struct ath11k_pdev_cap {
835 u32 supported_bands;
836 u32 ampdu_density;
837 u32 vht_cap;
838 u32 vht_mcs;
839 u32 he_mcs;
840 u32 tx_chain_mask;
841 u32 rx_chain_mask;
842 u32 tx_chain_mask_shift;
843 u32 rx_chain_mask_shift;
844 struct ath11k_band_cap band[NUM_NL80211_BANDS];
845 bool nss_ratio_enabled;
846 u8 nss_ratio_info;
847 };
848
849 struct ath11k_pdev {
850 struct ath11k *ar;
851 u32 pdev_id;
852 struct ath11k_pdev_cap cap;
853 u8 mac_addr[ETH_ALEN];
854 };
855
856 struct ath11k_board_data {
857 const struct firmware *fw;
858 const void *data;
859 size_t len;
860 };
861
862 struct ath11k_pci_ops {
863 int (*wakeup)(struct ath11k_base *ab);
864 void (*release)(struct ath11k_base *ab);
865 int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
866 void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
867 u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
868 };
869
870 /* IPQ8074 HW channel counters frequency value in hertz */
871 #define IPQ8074_CC_FREQ_HERTZ 320000
872
873 struct ath11k_bp_stats {
874 /* Head Pointer reported by the last HTT Backpressure event for the ring */
875 u16 hp;
876
877 /* Tail Pointer reported by the last HTT Backpressure event for the ring */
878 u16 tp;
879
880 /* Number of Backpressure events received for the ring */
881 u32 count;
882
883 /* Last recorded event timestamp */
884 unsigned long jiffies;
885 };
886
887 struct ath11k_dp_ring_bp_stats {
888 struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX];
889 struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS];
890 };
891
892 struct ath11k_soc_dp_tx_err_stats {
893 /* TCL Ring Descriptor unavailable */
894 u32 desc_na[DP_TCL_NUM_RING_MAX];
895 /* Other failures during dp_tx due to mem allocation failure
896 * idr unavailable etc.
897 */
898 atomic_t misc_fail;
899 };
900
901 struct ath11k_soc_dp_stats {
902 u32 err_ring_pkts;
903 u32 invalid_rbm;
904 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
905 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
906 u32 hal_reo_error[DP_REO_DST_RING_MAX];
907 struct ath11k_soc_dp_tx_err_stats tx_err;
908 struct ath11k_dp_ring_bp_stats bp_stats;
909 };
910
911 struct ath11k_msi_user {
912 char *name;
913 int num_vectors;
914 u32 base_vector;
915 };
916
917 struct ath11k_msi_config {
918 int total_vectors;
919 int total_users;
920 struct ath11k_msi_user *users;
921 u16 hw_rev;
922 };
923
924 enum ath11k_pm_policy {
925 ATH11K_PM_DEFAULT,
926 ATH11K_PM_WOW,
927 };
928
929 /* Master structure to hold the hw data which may be used in core module */
930 struct ath11k_base {
931 enum ath11k_hw_rev hw_rev;
932 enum ath11k_firmware_mode fw_mode;
933 struct platform_device *pdev;
934 struct device *dev;
935 struct ath11k_qmi qmi;
936 struct ath11k_wmi_base wmi_ab;
937 struct completion fw_ready;
938 int num_radios;
939 /* HW channel counters frequency value in hertz common to all MACs */
940 u32 cc_freq_hz;
941
942 struct ath11k_dump_file_data *dump_data;
943 size_t ath11k_coredump_len;
944 struct work_struct dump_work;
945
946 struct ath11k_htc htc;
947
948 struct ath11k_dp dp;
949
950 void __iomem *mem;
951 void __iomem *mem_ce;
952 unsigned long mem_len;
953
954 struct {
955 enum ath11k_bus bus;
956 const struct ath11k_hif_ops *ops;
957 } hif;
958
959 struct {
960 struct completion wakeup_completed;
961 } wow;
962
963 struct ath11k_ce ce;
964 struct timer_list rx_replenish_retry;
965 struct ath11k_hal hal;
966 /* To synchronize core_start/core_stop */
967 struct mutex core_lock;
968 /* Protects data like peers */
969 spinlock_t base_lock;
970 struct ath11k_pdev pdevs[MAX_RADIOS];
971 struct {
972 enum WMI_HOST_WLAN_BAND supported_bands;
973 u32 pdev_id;
974 } target_pdev_ids[MAX_RADIOS];
975 u8 target_pdev_count;
976 struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
977 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
978 unsigned long long free_vdev_map;
979
980 /* To synchronize rhash tbl write operation */
981 struct mutex tbl_mtx_lock;
982
983 /* The rhashtable containing struct ath11k_peer keyed by mac addr */
984 struct rhashtable *rhead_peer_addr;
985 struct rhashtable_params rhash_peer_addr_param;
986
987 /* The rhashtable containing struct ath11k_peer keyed by id */
988 struct rhashtable *rhead_peer_id;
989 struct rhashtable_params rhash_peer_id_param;
990
991 struct list_head peers;
992 wait_queue_head_t peer_mapping_wq;
993 u8 mac_addr[ETH_ALEN];
994 int irq_num[ATH11K_IRQ_NUM_MAX];
995 struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
996 struct ath11k_targ_cap target_caps;
997 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
998 bool pdevs_macaddr_valid;
999
1000 struct ath11k_hw_params hw_params;
1001
1002 const struct firmware *cal_file;
1003
1004 /* Below regd's are protected by ab->data_lock */
1005 /* This is the regd set for every radio
1006 * by the firmware during initialization
1007 */
1008 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1009 /* This regd is set during dynamic country setting
1010 * This may or may not be used during the runtime
1011 */
1012 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1013 struct cur_regulatory_info *reg_info_store;
1014
1015 /* Current DFS Regulatory */
1016 enum ath11k_dfs_region dfs_region;
1017 #ifdef CONFIG_ATH11K_DEBUGFS
1018 struct dentry *debugfs_soc;
1019 #endif
1020 struct ath11k_soc_dp_stats soc_stats;
1021
1022 unsigned long dev_flags;
1023 struct completion driver_recovery;
1024 struct workqueue_struct *workqueue;
1025 struct work_struct restart_work;
1026 struct work_struct update_11d_work;
1027 u8 new_alpha2[3];
1028 struct workqueue_struct *workqueue_aux;
1029 struct work_struct reset_work;
1030 atomic_t reset_count;
1031 atomic_t recovery_count;
1032 atomic_t recovery_start_count;
1033 bool is_reset;
1034 struct completion reset_complete;
1035 struct completion reconfigure_complete;
1036 struct completion recovery_start;
1037 /* continuous recovery fail count */
1038 atomic_t fail_cont_count;
1039 unsigned long reset_fail_timeout;
1040 struct {
1041 /* protected by data_lock */
1042 u32 fw_crash_counter;
1043 } stats;
1044 u32 pktlog_defs_checksum;
1045
1046 struct ath11k_dbring_cap *db_caps;
1047 u32 num_db_cap;
1048
1049 /* To synchronize 11d scan vdev id */
1050 struct mutex vdev_id_11d_lock;
1051 struct timer_list mon_reap_timer;
1052
1053 struct completion htc_suspend;
1054
1055 struct {
1056 enum ath11k_bdf_search bdf_search;
1057 u32 vendor;
1058 u32 device;
1059 u32 subsystem_vendor;
1060 u32 subsystem_device;
1061 } id;
1062
1063 struct {
1064 struct {
1065 const struct ath11k_msi_config *config;
1066 u32 ep_base_data;
1067 u32 irqs[32];
1068 u32 addr_lo;
1069 u32 addr_hi;
1070 } msi;
1071
1072 const struct ath11k_pci_ops *ops;
1073 } pci;
1074
1075 struct {
1076 u32 api_version;
1077
1078 const struct firmware *fw;
1079 const u8 *amss_data;
1080 size_t amss_len;
1081 const u8 *m3_data;
1082 size_t m3_len;
1083
1084 DECLARE_BITMAP(fw_features, ATH11K_FW_FEATURE_COUNT);
1085 } fw;
1086
1087 struct completion restart_completed;
1088
1089 #ifdef CONFIG_NL80211_TESTMODE
1090 struct {
1091 u32 data_pos;
1092 u32 expected_seq;
1093 u8 *eventdata;
1094 } testmode;
1095 #endif
1096
1097 enum ath11k_pm_policy pm_policy;
1098 enum ath11k_pm_policy actual_pm_policy;
1099 struct notifier_block pm_nb;
1100
1101 /* must be last */
1102 u8 drv_priv[] __aligned(sizeof(void *));
1103 };
1104
1105 struct ath11k_fw_stats_pdev {
1106 struct list_head list;
1107
1108 /* PDEV stats */
1109 s32 ch_noise_floor;
1110 /* Cycles spent transmitting frames */
1111 u32 tx_frame_count;
1112 /* Cycles spent receiving frames */
1113 u32 rx_frame_count;
1114 /* Total channel busy time, evidently */
1115 u32 rx_clear_count;
1116 /* Total on-channel time */
1117 u32 cycle_count;
1118 u32 phy_err_count;
1119 u32 chan_tx_power;
1120 u32 ack_rx_bad;
1121 u32 rts_bad;
1122 u32 rts_good;
1123 u32 fcs_bad;
1124 u32 no_beacons;
1125 u32 mib_int_count;
1126
1127 /* PDEV TX stats */
1128 /* Num HTT cookies queued to dispatch list */
1129 s32 comp_queued;
1130 /* Num HTT cookies dispatched */
1131 s32 comp_delivered;
1132 /* Num MSDU queued to WAL */
1133 s32 msdu_enqued;
1134 /* Num MPDU queue to WAL */
1135 s32 mpdu_enqued;
1136 /* Num MSDUs dropped by WMM limit */
1137 s32 wmm_drop;
1138 /* Num Local frames queued */
1139 s32 local_enqued;
1140 /* Num Local frames done */
1141 s32 local_freed;
1142 /* Num queued to HW */
1143 s32 hw_queued;
1144 /* Num PPDU reaped from HW */
1145 s32 hw_reaped;
1146 /* Num underruns */
1147 s32 underrun;
1148 /* Num hw paused */
1149 u32 hw_paused;
1150 /* Num PPDUs cleaned up in TX abort */
1151 s32 tx_abort;
1152 /* Num MPDUs requeued by SW */
1153 s32 mpdus_requeued;
1154 /* excessive retries */
1155 u32 tx_ko;
1156 u32 tx_xretry;
1157 /* data hw rate code */
1158 u32 data_rc;
1159 /* Scheduler self triggers */
1160 u32 self_triggers;
1161 /* frames dropped due to excessive sw retries */
1162 u32 sw_retry_failure;
1163 /* illegal rate phy errors */
1164 u32 illgl_rate_phy_err;
1165 /* wal pdev continuous xretry */
1166 u32 pdev_cont_xretry;
1167 /* wal pdev tx timeouts */
1168 u32 pdev_tx_timeout;
1169 /* wal pdev resets */
1170 u32 pdev_resets;
1171 /* frames dropped due to non-availability of stateless TIDs */
1172 u32 stateless_tid_alloc_failure;
1173 /* PhY/BB underrun */
1174 u32 phy_underrun;
1175 /* MPDU is more than txop limit */
1176 u32 txop_ovf;
1177 /* Num sequences posted */
1178 u32 seq_posted;
1179 /* Num sequences failed in queueing */
1180 u32 seq_failed_queueing;
1181 /* Num sequences completed */
1182 u32 seq_completed;
1183 /* Num sequences restarted */
1184 u32 seq_restarted;
1185 /* Num of MU sequences posted */
1186 u32 mu_seq_posted;
1187 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
1188 * (Reset,channel change)
1189 */
1190 s32 mpdus_sw_flush;
1191 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */
1192 s32 mpdus_hw_filter;
1193 /* Num MPDUs truncated by PDG (TXOP, TBTT,
1194 * PPDU_duration based on rate, dyn_bw)
1195 */
1196 s32 mpdus_truncated;
1197 /* Num MPDUs that was tried but didn't receive ACK or BA */
1198 s32 mpdus_ack_failed;
1199 /* Num MPDUs that was dropped du to expiry. */
1200 s32 mpdus_expired;
1201
1202 /* PDEV RX stats */
1203 /* Cnts any change in ring routing mid-ppdu */
1204 s32 mid_ppdu_route_change;
1205 /* Total number of statuses processed */
1206 s32 status_rcvd;
1207 /* Extra frags on rings 0-3 */
1208 s32 r0_frags;
1209 s32 r1_frags;
1210 s32 r2_frags;
1211 s32 r3_frags;
1212 /* MSDUs / MPDUs delivered to HTT */
1213 s32 htt_msdus;
1214 s32 htt_mpdus;
1215 /* MSDUs / MPDUs delivered to local stack */
1216 s32 loc_msdus;
1217 s32 loc_mpdus;
1218 /* AMSDUs that have more MSDUs than the status ring size */
1219 s32 oversize_amsdu;
1220 /* Number of PHY errors */
1221 s32 phy_errs;
1222 /* Number of PHY errors drops */
1223 s32 phy_err_drop;
1224 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1225 s32 mpdu_errs;
1226 /* Num overflow errors */
1227 s32 rx_ovfl_errs;
1228 };
1229
1230 struct ath11k_fw_stats_vdev {
1231 struct list_head list;
1232
1233 u32 vdev_id;
1234 u32 beacon_snr;
1235 u32 data_snr;
1236 u32 num_tx_frames[WLAN_MAX_AC];
1237 u32 num_rx_frames;
1238 u32 num_tx_frames_retries[WLAN_MAX_AC];
1239 u32 num_tx_frames_failures[WLAN_MAX_AC];
1240 u32 num_rts_fail;
1241 u32 num_rts_success;
1242 u32 num_rx_err;
1243 u32 num_rx_discard;
1244 u32 num_tx_not_acked;
1245 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1246 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1247 };
1248
1249 struct ath11k_fw_stats_bcn {
1250 struct list_head list;
1251
1252 u32 vdev_id;
1253 u32 tx_bcn_succ_cnt;
1254 u32 tx_bcn_outage_cnt;
1255 };
1256
1257 void ath11k_fw_stats_init(struct ath11k *ar);
1258 void ath11k_fw_stats_pdevs_free(struct list_head *head);
1259 void ath11k_fw_stats_vdevs_free(struct list_head *head);
1260 void ath11k_fw_stats_bcn_free(struct list_head *head);
1261 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats);
1262
1263 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[];
1264 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[];
1265 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[];
1266
1267 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[];
1268 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[];
1269
1270 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[];
1271 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[];
1272
1273 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[];
1274 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[];
1275 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
1276 int ath11k_core_pre_init(struct ath11k_base *ab);
1277 int ath11k_core_init(struct ath11k_base *ath11k);
1278 void ath11k_core_deinit(struct ath11k_base *ath11k);
1279 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
1280 enum ath11k_bus bus);
1281 void ath11k_core_free(struct ath11k_base *ath11k);
1282 int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
1283 struct ath11k_board_data *bd);
1284 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd);
1285 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1286 struct ath11k_board_data *bd,
1287 const char *name);
1288 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
1289 int ath11k_core_check_dt(struct ath11k_base *ath11k);
1290 int ath11k_core_check_smbios(struct ath11k_base *ab);
1291 void ath11k_core_halt(struct ath11k *ar);
1292 int ath11k_core_resume_early(struct ath11k_base *ab);
1293 int ath11k_core_resume(struct ath11k_base *ab);
1294 int ath11k_core_suspend(struct ath11k_base *ab);
1295 int ath11k_core_suspend_late(struct ath11k_base *ab);
1296 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab);
1297 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab);
1298
1299 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1300 const char *filename);
1301
ath11k_scan_state_str(enum ath11k_scan_state state)1302 static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state)
1303 {
1304 switch (state) {
1305 case ATH11K_SCAN_IDLE:
1306 return "idle";
1307 case ATH11K_SCAN_STARTING:
1308 return "starting";
1309 case ATH11K_SCAN_RUNNING:
1310 return "running";
1311 case ATH11K_SCAN_ABORTING:
1312 return "aborting";
1313 }
1314
1315 return "unknown";
1316 }
1317
ATH11K_SKB_CB(struct sk_buff * skb)1318 static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb)
1319 {
1320 BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) >
1321 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1322 return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1323 }
1324
ATH11K_SKB_RXCB(struct sk_buff * skb)1325 static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb)
1326 {
1327 BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb));
1328 return (struct ath11k_skb_rxcb *)skb->cb;
1329 }
1330
ath11k_vif_to_arvif(struct ieee80211_vif * vif)1331 static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif)
1332 {
1333 return (struct ath11k_vif *)vif->drv_priv;
1334 }
1335
ath11k_sta_to_arsta(struct ieee80211_sta * sta)1336 static inline struct ath11k_sta *ath11k_sta_to_arsta(struct ieee80211_sta *sta)
1337 {
1338 return (struct ath11k_sta *)sta->drv_priv;
1339 }
1340
ath11k_ab_to_ar(struct ath11k_base * ab,int mac_id)1341 static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab,
1342 int mac_id)
1343 {
1344 return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
1345 }
1346
ath11k_core_create_firmware_path(struct ath11k_base * ab,const char * filename,void * buf,size_t buf_len)1347 static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab,
1348 const char *filename,
1349 void *buf, size_t buf_len)
1350 {
1351 const char *fw_name = NULL;
1352
1353 #if defined(CONFIG_OF)
1354 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1355 #endif
1356
1357 if (fw_name && strncmp(filename, "board", 5))
1358 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH11K_FW_DIR,
1359 ab->hw_params.fw.dir, fw_name, filename);
1360 else
1361 snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR,
1362 ab->hw_params.fw.dir, filename);
1363 }
1364
ath11k_bus_str(enum ath11k_bus bus)1365 static inline const char *ath11k_bus_str(enum ath11k_bus bus)
1366 {
1367 switch (bus) {
1368 case ATH11K_BUS_PCI:
1369 return "pci";
1370 case ATH11K_BUS_AHB:
1371 return "ahb";
1372 }
1373
1374 return "unknown";
1375 }
1376
1377 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab);
1378
1379 #endif /* _CORE_H_ */
1380