1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/ctype.h>
13 #include <linux/stringify.h>
14 #include <linux/ethtool.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/linkmode.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/etherdevice.h>
20 #include <linux/crc32.h>
21 #include <linux/firmware.h>
22 #include <linux/utsname.h>
23 #include <linux/time.h>
24 #include <linux/ptp_clock_kernel.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/timecounter.h>
27 #include <net/netdev_queues.h>
28 #include <net/netlink.h>
29 #include "bnxt_hsi.h"
30 #include "bnxt.h"
31 #include "bnxt_hwrm.h"
32 #include "bnxt_ulp.h"
33 #include "bnxt_xdp.h"
34 #include "bnxt_ptp.h"
35 #include "bnxt_ethtool.h"
36 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
37 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
38 #include "bnxt_coredump.h"
39
40 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \
41 do { \
42 if (extack) \
43 NL_SET_ERR_MSG_MOD(extack, msg); \
44 netdev_err(dev, "%s\n", msg); \
45 } while (0)
46
bnxt_get_msglevel(struct net_device * dev)47 static u32 bnxt_get_msglevel(struct net_device *dev)
48 {
49 struct bnxt *bp = netdev_priv(dev);
50
51 return bp->msg_enable;
52 }
53
bnxt_set_msglevel(struct net_device * dev,u32 value)54 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
55 {
56 struct bnxt *bp = netdev_priv(dev);
57
58 bp->msg_enable = value;
59 }
60
bnxt_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)61 static int bnxt_get_coalesce(struct net_device *dev,
62 struct ethtool_coalesce *coal,
63 struct kernel_ethtool_coalesce *kernel_coal,
64 struct netlink_ext_ack *extack)
65 {
66 struct bnxt *bp = netdev_priv(dev);
67 struct bnxt_coal *hw_coal;
68 u16 mult;
69
70 memset(coal, 0, sizeof(*coal));
71
72 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
73
74 hw_coal = &bp->rx_coal;
75 mult = hw_coal->bufs_per_record;
76 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
77 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
78 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
79 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
80 if (hw_coal->flags &
81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
82 kernel_coal->use_cqe_mode_rx = true;
83
84 hw_coal = &bp->tx_coal;
85 mult = hw_coal->bufs_per_record;
86 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
87 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
88 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
89 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
90 if (hw_coal->flags &
91 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
92 kernel_coal->use_cqe_mode_tx = true;
93
94 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
95
96 return 0;
97 }
98
bnxt_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)99 static int bnxt_set_coalesce(struct net_device *dev,
100 struct ethtool_coalesce *coal,
101 struct kernel_ethtool_coalesce *kernel_coal,
102 struct netlink_ext_ack *extack)
103 {
104 struct bnxt *bp = netdev_priv(dev);
105 bool update_stats = false;
106 struct bnxt_coal *hw_coal;
107 int rc = 0;
108 u16 mult;
109
110 if (coal->use_adaptive_rx_coalesce) {
111 bp->flags |= BNXT_FLAG_DIM;
112 } else {
113 if (bp->flags & BNXT_FLAG_DIM) {
114 bp->flags &= ~(BNXT_FLAG_DIM);
115 goto reset_coalesce;
116 }
117 }
118
119 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
120 !(bp->coal_cap.cmpl_params &
121 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
122 return -EOPNOTSUPP;
123
124 hw_coal = &bp->rx_coal;
125 mult = hw_coal->bufs_per_record;
126 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
127 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
128 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
129 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
130 hw_coal->flags &=
131 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
132 if (kernel_coal->use_cqe_mode_rx)
133 hw_coal->flags |=
134 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
135
136 hw_coal = &bp->tx_coal;
137 mult = hw_coal->bufs_per_record;
138 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
139 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
140 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
141 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
142 hw_coal->flags &=
143 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
144 if (kernel_coal->use_cqe_mode_tx)
145 hw_coal->flags |=
146 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
147
148 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
149 u32 stats_ticks = coal->stats_block_coalesce_usecs;
150
151 /* Allow 0, which means disable. */
152 if (stats_ticks)
153 stats_ticks = clamp_t(u32, stats_ticks,
154 BNXT_MIN_STATS_COAL_TICKS,
155 BNXT_MAX_STATS_COAL_TICKS);
156 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
157 bp->stats_coal_ticks = stats_ticks;
158 if (bp->stats_coal_ticks)
159 bp->current_interval =
160 bp->stats_coal_ticks * HZ / 1000000;
161 else
162 bp->current_interval = BNXT_TIMER_INTERVAL;
163 update_stats = true;
164 }
165
166 reset_coalesce:
167 if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
168 if (update_stats) {
169 bnxt_close_nic(bp, true, false);
170 rc = bnxt_open_nic(bp, true, false);
171 } else {
172 rc = bnxt_hwrm_set_coal(bp);
173 }
174 }
175
176 return rc;
177 }
178
179 static const char * const bnxt_ring_rx_stats_str[] = {
180 "rx_ucast_packets",
181 "rx_mcast_packets",
182 "rx_bcast_packets",
183 "rx_discards",
184 "rx_errors",
185 "rx_ucast_bytes",
186 "rx_mcast_bytes",
187 "rx_bcast_bytes",
188 };
189
190 static const char * const bnxt_ring_tx_stats_str[] = {
191 "tx_ucast_packets",
192 "tx_mcast_packets",
193 "tx_bcast_packets",
194 "tx_errors",
195 "tx_discards",
196 "tx_ucast_bytes",
197 "tx_mcast_bytes",
198 "tx_bcast_bytes",
199 };
200
201 static const char * const bnxt_ring_tpa_stats_str[] = {
202 "tpa_packets",
203 "tpa_bytes",
204 "tpa_events",
205 "tpa_aborts",
206 };
207
208 static const char * const bnxt_ring_tpa2_stats_str[] = {
209 "rx_tpa_eligible_pkt",
210 "rx_tpa_eligible_bytes",
211 "rx_tpa_pkt",
212 "rx_tpa_bytes",
213 "rx_tpa_errors",
214 "rx_tpa_events",
215 };
216
217 static const char * const bnxt_rx_sw_stats_str[] = {
218 "rx_l4_csum_errors",
219 "rx_resets",
220 "rx_buf_errors",
221 };
222
223 static const char * const bnxt_cmn_sw_stats_str[] = {
224 "missed_irqs",
225 };
226
227 #define BNXT_RX_STATS_ENTRY(counter) \
228 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
229
230 #define BNXT_TX_STATS_ENTRY(counter) \
231 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
232
233 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
234 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
235
236 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
237 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
238
239 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
242
243 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
246
247 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
248 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
249 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
250 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
251 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
252 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
253 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
254 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
255 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
256
257 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
258 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
259 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
260 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
261 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
262 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
263 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
264 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
265 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
266
267 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
268 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
269 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
270
271 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
272 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
273 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
274
275 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
276 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
277 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
278 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
279 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
280 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
281 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
282 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
283 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
284
285 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
286 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
287 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
288 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
289 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
290 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
291 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
292 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
293 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
294
295 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
298
299 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
308
309 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
310 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
311 __stringify(counter##_pri##n) }
312
313 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
314 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
315 __stringify(counter##_pri##n) }
316
317 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
318 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
319 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
320 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
321 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
322 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
323 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
324 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
325 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
326
327 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
328 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
329 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
330 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
331 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
332 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
333 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
334 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
335 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
336
337 enum {
338 RX_TOTAL_DISCARDS,
339 TX_TOTAL_DISCARDS,
340 RX_NETPOLL_DISCARDS,
341 };
342
343 static const char *const bnxt_ring_err_stats_arr[] = {
344 "rx_total_l4_csum_errors",
345 "rx_total_resets",
346 "rx_total_buf_errors",
347 "rx_total_oom_discards",
348 "rx_total_netpoll_discards",
349 "rx_total_ring_discards",
350 "tx_total_resets",
351 "tx_total_ring_discards",
352 "total_missed_irqs",
353 };
354
355 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
356 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
357 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
358 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
359
360 static const struct {
361 long offset;
362 char string[ETH_GSTRING_LEN];
363 } bnxt_port_stats_arr[] = {
364 BNXT_RX_STATS_ENTRY(rx_64b_frames),
365 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
366 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
367 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
368 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
369 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
370 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
371 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
372 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
373 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
374 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
375 BNXT_RX_STATS_ENTRY(rx_total_frames),
376 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
377 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
378 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
379 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
380 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
381 BNXT_RX_STATS_ENTRY(rx_pause_frames),
382 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
383 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
384 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
385 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
386 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
387 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
388 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
389 BNXT_RX_STATS_ENTRY(rx_good_frames),
390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
398 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
401 BNXT_RX_STATS_ENTRY(rx_bytes),
402 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
403 BNXT_RX_STATS_ENTRY(rx_runt_frames),
404 BNXT_RX_STATS_ENTRY(rx_stat_discard),
405 BNXT_RX_STATS_ENTRY(rx_stat_err),
406
407 BNXT_TX_STATS_ENTRY(tx_64b_frames),
408 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
409 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
410 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
411 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
412 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
413 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
414 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
415 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
416 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
417 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
418 BNXT_TX_STATS_ENTRY(tx_good_frames),
419 BNXT_TX_STATS_ENTRY(tx_total_frames),
420 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
421 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
422 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
423 BNXT_TX_STATS_ENTRY(tx_pause_frames),
424 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
425 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
426 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
427 BNXT_TX_STATS_ENTRY(tx_err),
428 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
439 BNXT_TX_STATS_ENTRY(tx_total_collisions),
440 BNXT_TX_STATS_ENTRY(tx_bytes),
441 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
442 BNXT_TX_STATS_ENTRY(tx_stat_discard),
443 BNXT_TX_STATS_ENTRY(tx_stat_error),
444 };
445
446 static const struct {
447 long offset;
448 char string[ETH_GSTRING_LEN];
449 } bnxt_port_stats_ext_arr[] = {
450 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
451 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
452 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
453 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
454 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
455 BNXT_RX_STATS_EXT_COS_ENTRIES,
456 BNXT_RX_STATS_EXT_PFC_ENTRIES,
457 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
458 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
459 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
460 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
461 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
464 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss),
465 };
466
467 static const struct {
468 long offset;
469 char string[ETH_GSTRING_LEN];
470 } bnxt_tx_port_stats_ext_arr[] = {
471 BNXT_TX_STATS_EXT_COS_ENTRIES,
472 BNXT_TX_STATS_EXT_PFC_ENTRIES,
473 };
474
475 static const struct {
476 long base_off;
477 char string[ETH_GSTRING_LEN];
478 } bnxt_rx_bytes_pri_arr[] = {
479 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
480 };
481
482 static const struct {
483 long base_off;
484 char string[ETH_GSTRING_LEN];
485 } bnxt_rx_pkts_pri_arr[] = {
486 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
487 };
488
489 static const struct {
490 long base_off;
491 char string[ETH_GSTRING_LEN];
492 } bnxt_tx_bytes_pri_arr[] = {
493 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
494 };
495
496 static const struct {
497 long base_off;
498 char string[ETH_GSTRING_LEN];
499 } bnxt_tx_pkts_pri_arr[] = {
500 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
501 };
502
503 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr)
504 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
505 #define BNXT_NUM_STATS_PRI \
506 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
507 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
508 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
509 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
510
bnxt_get_num_tpa_ring_stats(struct bnxt * bp)511 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
512 {
513 if (BNXT_SUPPORTS_TPA(bp)) {
514 if (bp->max_tpa_v2) {
515 if (BNXT_CHIP_P5(bp))
516 return BNXT_NUM_TPA_RING_STATS_P5;
517 return BNXT_NUM_TPA_RING_STATS_P7;
518 }
519 return BNXT_NUM_TPA_RING_STATS;
520 }
521 return 0;
522 }
523
bnxt_get_num_ring_stats(struct bnxt * bp)524 static int bnxt_get_num_ring_stats(struct bnxt *bp)
525 {
526 int rx, tx, cmn;
527
528 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
529 bnxt_get_num_tpa_ring_stats(bp);
530 tx = NUM_RING_TX_HW_STATS;
531 cmn = NUM_RING_CMN_SW_STATS;
532 return rx * bp->rx_nr_rings +
533 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) +
534 cmn * bp->cp_nr_rings;
535 }
536
bnxt_get_num_stats(struct bnxt * bp)537 static int bnxt_get_num_stats(struct bnxt *bp)
538 {
539 int num_stats = bnxt_get_num_ring_stats(bp);
540 int len;
541
542 num_stats += BNXT_NUM_RING_ERR_STATS;
543
544 if (bp->flags & BNXT_FLAG_PORT_STATS)
545 num_stats += BNXT_NUM_PORT_STATS;
546
547 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
548 len = min_t(int, bp->fw_rx_stats_ext_size,
549 ARRAY_SIZE(bnxt_port_stats_ext_arr));
550 num_stats += len;
551 len = min_t(int, bp->fw_tx_stats_ext_size,
552 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
553 num_stats += len;
554 if (bp->pri2cos_valid)
555 num_stats += BNXT_NUM_STATS_PRI;
556 }
557
558 return num_stats;
559 }
560
bnxt_get_sset_count(struct net_device * dev,int sset)561 static int bnxt_get_sset_count(struct net_device *dev, int sset)
562 {
563 struct bnxt *bp = netdev_priv(dev);
564
565 switch (sset) {
566 case ETH_SS_STATS:
567 return bnxt_get_num_stats(bp);
568 case ETH_SS_TEST:
569 if (!bp->num_tests)
570 return -EOPNOTSUPP;
571 return bp->num_tests;
572 default:
573 return -EOPNOTSUPP;
574 }
575 }
576
is_rx_ring(struct bnxt * bp,int ring_num)577 static bool is_rx_ring(struct bnxt *bp, int ring_num)
578 {
579 return ring_num < bp->rx_nr_rings;
580 }
581
is_tx_ring(struct bnxt * bp,int ring_num)582 static bool is_tx_ring(struct bnxt *bp, int ring_num)
583 {
584 int tx_base = 0;
585
586 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
587 tx_base = bp->rx_nr_rings;
588
589 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
590 return true;
591 return false;
592 }
593
bnxt_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * buf)594 static void bnxt_get_ethtool_stats(struct net_device *dev,
595 struct ethtool_stats *stats, u64 *buf)
596 {
597 struct bnxt_total_ring_err_stats ring_err_stats = {0};
598 struct bnxt *bp = netdev_priv(dev);
599 u64 *curr, *prev;
600 u32 tpa_stats;
601 u32 i, j = 0;
602
603 if (!bp->bnapi) {
604 j += bnxt_get_num_ring_stats(bp);
605 goto skip_ring_stats;
606 }
607
608 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
609 for (i = 0; i < bp->cp_nr_rings; i++) {
610 struct bnxt_napi *bnapi = bp->bnapi[i];
611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
612 u64 *sw_stats = cpr->stats.sw_stats;
613 u64 *sw;
614 int k;
615
616 if (is_rx_ring(bp, i)) {
617 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
618 buf[j] = sw_stats[k];
619 }
620 if (is_tx_ring(bp, i)) {
621 k = NUM_RING_RX_HW_STATS;
622 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
623 j++, k++)
624 buf[j] = sw_stats[k];
625 }
626 if (!tpa_stats || !is_rx_ring(bp, i))
627 goto skip_tpa_ring_stats;
628
629 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
630 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
631 tpa_stats; j++, k++)
632 buf[j] = sw_stats[k];
633
634 skip_tpa_ring_stats:
635 sw = (u64 *)&cpr->sw_stats->rx;
636 if (is_rx_ring(bp, i)) {
637 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
638 buf[j] = sw[k];
639 }
640
641 sw = (u64 *)&cpr->sw_stats->cmn;
642 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
643 buf[j] = sw[k];
644 }
645
646 bnxt_get_ring_err_stats(bp, &ring_err_stats);
647
648 skip_ring_stats:
649 curr = &ring_err_stats.rx_total_l4_csum_errors;
650 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors;
651 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++)
652 buf[j] = *curr + *prev;
653
654 if (bp->flags & BNXT_FLAG_PORT_STATS) {
655 u64 *port_stats = bp->port_stats.sw_stats;
656
657 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
658 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
659 }
660 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
661 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
662 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
663 u32 len;
664
665 len = min_t(u32, bp->fw_rx_stats_ext_size,
666 ARRAY_SIZE(bnxt_port_stats_ext_arr));
667 for (i = 0; i < len; i++, j++) {
668 buf[j] = *(rx_port_stats_ext +
669 bnxt_port_stats_ext_arr[i].offset);
670 }
671 len = min_t(u32, bp->fw_tx_stats_ext_size,
672 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
673 for (i = 0; i < len; i++, j++) {
674 buf[j] = *(tx_port_stats_ext +
675 bnxt_tx_port_stats_ext_arr[i].offset);
676 }
677 if (bp->pri2cos_valid) {
678 for (i = 0; i < 8; i++, j++) {
679 long n = bnxt_rx_bytes_pri_arr[i].base_off +
680 bp->pri2cos_idx[i];
681
682 buf[j] = *(rx_port_stats_ext + n);
683 }
684 for (i = 0; i < 8; i++, j++) {
685 long n = bnxt_rx_pkts_pri_arr[i].base_off +
686 bp->pri2cos_idx[i];
687
688 buf[j] = *(rx_port_stats_ext + n);
689 }
690 for (i = 0; i < 8; i++, j++) {
691 long n = bnxt_tx_bytes_pri_arr[i].base_off +
692 bp->pri2cos_idx[i];
693
694 buf[j] = *(tx_port_stats_ext + n);
695 }
696 for (i = 0; i < 8; i++, j++) {
697 long n = bnxt_tx_pkts_pri_arr[i].base_off +
698 bp->pri2cos_idx[i];
699
700 buf[j] = *(tx_port_stats_ext + n);
701 }
702 }
703 }
704 }
705
bnxt_get_strings(struct net_device * dev,u32 stringset,u8 * buf)706 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
707 {
708 struct bnxt *bp = netdev_priv(dev);
709 u32 i, j, num_str;
710 const char *str;
711
712 switch (stringset) {
713 case ETH_SS_STATS:
714 for (i = 0; i < bp->cp_nr_rings; i++) {
715 if (is_rx_ring(bp, i))
716 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) {
717 str = bnxt_ring_rx_stats_str[j];
718 ethtool_sprintf(&buf, "[%d]: %s", i,
719 str);
720 }
721 if (is_tx_ring(bp, i))
722 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) {
723 str = bnxt_ring_tx_stats_str[j];
724 ethtool_sprintf(&buf, "[%d]: %s", i,
725 str);
726 }
727 num_str = bnxt_get_num_tpa_ring_stats(bp);
728 if (!num_str || !is_rx_ring(bp, i))
729 goto skip_tpa_stats;
730
731 if (bp->max_tpa_v2)
732 for (j = 0; j < num_str; j++) {
733 str = bnxt_ring_tpa2_stats_str[j];
734 ethtool_sprintf(&buf, "[%d]: %s", i,
735 str);
736 }
737 else
738 for (j = 0; j < num_str; j++) {
739 str = bnxt_ring_tpa_stats_str[j];
740 ethtool_sprintf(&buf, "[%d]: %s", i,
741 str);
742 }
743 skip_tpa_stats:
744 if (is_rx_ring(bp, i))
745 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) {
746 str = bnxt_rx_sw_stats_str[j];
747 ethtool_sprintf(&buf, "[%d]: %s", i,
748 str);
749 }
750 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) {
751 str = bnxt_cmn_sw_stats_str[j];
752 ethtool_sprintf(&buf, "[%d]: %s", i, str);
753 }
754 }
755 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++)
756 ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]);
757
758 if (bp->flags & BNXT_FLAG_PORT_STATS)
759 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
760 str = bnxt_port_stats_arr[i].string;
761 ethtool_puts(&buf, str);
762 }
763
764 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
765 u32 len;
766
767 len = min_t(u32, bp->fw_rx_stats_ext_size,
768 ARRAY_SIZE(bnxt_port_stats_ext_arr));
769 for (i = 0; i < len; i++) {
770 str = bnxt_port_stats_ext_arr[i].string;
771 ethtool_puts(&buf, str);
772 }
773
774 len = min_t(u32, bp->fw_tx_stats_ext_size,
775 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
776 for (i = 0; i < len; i++) {
777 str = bnxt_tx_port_stats_ext_arr[i].string;
778 ethtool_puts(&buf, str);
779 }
780
781 if (bp->pri2cos_valid) {
782 for (i = 0; i < 8; i++) {
783 str = bnxt_rx_bytes_pri_arr[i].string;
784 ethtool_puts(&buf, str);
785 }
786
787 for (i = 0; i < 8; i++) {
788 str = bnxt_rx_pkts_pri_arr[i].string;
789 ethtool_puts(&buf, str);
790 }
791
792 for (i = 0; i < 8; i++) {
793 str = bnxt_tx_bytes_pri_arr[i].string;
794 ethtool_puts(&buf, str);
795 }
796
797 for (i = 0; i < 8; i++) {
798 str = bnxt_tx_pkts_pri_arr[i].string;
799 ethtool_puts(&buf, str);
800 }
801 }
802 }
803 break;
804 case ETH_SS_TEST:
805 if (bp->num_tests)
806 for (i = 0; i < bp->num_tests; i++)
807 ethtool_puts(&buf, bp->test_info->string[i]);
808 break;
809 default:
810 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
811 stringset);
812 break;
813 }
814 }
815
bnxt_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)816 static void bnxt_get_ringparam(struct net_device *dev,
817 struct ethtool_ringparam *ering,
818 struct kernel_ethtool_ringparam *kernel_ering,
819 struct netlink_ext_ack *extack)
820 {
821 struct bnxt *bp = netdev_priv(dev);
822
823 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
824 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
825 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
826 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
827 } else {
828 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
829 ering->rx_jumbo_max_pending = 0;
830 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
831 }
832 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
833
834 ering->rx_pending = bp->rx_ring_size;
835 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
836 ering->tx_pending = bp->tx_ring_size;
837
838 kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX;
839 }
840
bnxt_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)841 static int bnxt_set_ringparam(struct net_device *dev,
842 struct ethtool_ringparam *ering,
843 struct kernel_ethtool_ringparam *kernel_ering,
844 struct netlink_ext_ack *extack)
845 {
846 u8 tcp_data_split = kernel_ering->tcp_data_split;
847 struct bnxt *bp = netdev_priv(dev);
848 u8 hds_config_mod;
849
850 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
851 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
852 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
853 return -EINVAL;
854
855 hds_config_mod = tcp_data_split != dev->cfg->hds_config;
856 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod)
857 return -EINVAL;
858
859 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED &&
860 hds_config_mod && BNXT_RX_PAGE_MODE(bp)) {
861 NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached");
862 return -EINVAL;
863 }
864
865 if (netif_running(dev))
866 bnxt_close_nic(bp, false, false);
867
868 if (hds_config_mod) {
869 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED)
870 bp->flags |= BNXT_FLAG_HDS;
871 else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN)
872 bp->flags &= ~BNXT_FLAG_HDS;
873 }
874
875 bp->rx_ring_size = ering->rx_pending;
876 bp->tx_ring_size = ering->tx_pending;
877 bnxt_set_ring_params(bp);
878
879 if (netif_running(dev))
880 return bnxt_open_nic(bp, false, false);
881
882 return 0;
883 }
884
bnxt_get_channels(struct net_device * dev,struct ethtool_channels * channel)885 static void bnxt_get_channels(struct net_device *dev,
886 struct ethtool_channels *channel)
887 {
888 struct bnxt *bp = netdev_priv(dev);
889 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
890 int max_rx_rings, max_tx_rings, tcs;
891 int max_tx_sch_inputs, tx_grps;
892
893 /* Get the most up-to-date max_tx_sch_inputs. */
894 if (netif_running(dev) && BNXT_NEW_RM(bp))
895 bnxt_hwrm_func_resc_qcaps(bp, false);
896 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
897
898 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
899 if (max_tx_sch_inputs)
900 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
901
902 tcs = bp->num_tc;
903 tx_grps = max(tcs, 1);
904 if (bp->tx_nr_rings_xdp)
905 tx_grps++;
906 max_tx_rings /= tx_grps;
907 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
908
909 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
910 max_rx_rings = 0;
911 max_tx_rings = 0;
912 }
913 if (max_tx_sch_inputs)
914 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
915
916 if (tcs > 1)
917 max_tx_rings /= tcs;
918
919 channel->max_rx = max_rx_rings;
920 channel->max_tx = max_tx_rings;
921 channel->max_other = 0;
922 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
923 channel->combined_count = bp->rx_nr_rings;
924 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
925 channel->combined_count--;
926 } else {
927 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
928 channel->rx_count = bp->rx_nr_rings;
929 channel->tx_count = bp->tx_nr_rings_per_tc;
930 }
931 }
932 }
933
bnxt_set_channels(struct net_device * dev,struct ethtool_channels * channel)934 static int bnxt_set_channels(struct net_device *dev,
935 struct ethtool_channels *channel)
936 {
937 struct bnxt *bp = netdev_priv(dev);
938 int req_tx_rings, req_rx_rings, tcs;
939 bool sh = false;
940 int tx_xdp = 0;
941 int rc = 0;
942 int tx_cp;
943
944 if (channel->other_count)
945 return -EINVAL;
946
947 if (!channel->combined_count &&
948 (!channel->rx_count || !channel->tx_count))
949 return -EINVAL;
950
951 if (channel->combined_count &&
952 (channel->rx_count || channel->tx_count))
953 return -EINVAL;
954
955 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
956 channel->tx_count))
957 return -EINVAL;
958
959 if (channel->combined_count)
960 sh = true;
961
962 tcs = bp->num_tc;
963
964 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
965 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
966 if (bp->tx_nr_rings_xdp) {
967 if (!sh) {
968 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
969 return -EINVAL;
970 }
971 tx_xdp = req_rx_rings;
972 }
973
974 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
975 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
976 netif_is_rxfh_configured(dev)) {
977 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
978 return -EINVAL;
979 }
980
981 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
982 if (rc) {
983 netdev_warn(dev, "Unable to allocate the requested rings\n");
984 return rc;
985 }
986
987 if (netif_running(dev)) {
988 if (BNXT_PF(bp)) {
989 /* TODO CHIMP_FW: Send message to all VF's
990 * before PF unload
991 */
992 }
993 bnxt_close_nic(bp, true, false);
994 }
995
996 if (sh) {
997 bp->flags |= BNXT_FLAG_SHARED_RINGS;
998 bp->rx_nr_rings = channel->combined_count;
999 bp->tx_nr_rings_per_tc = channel->combined_count;
1000 } else {
1001 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
1002 bp->rx_nr_rings = channel->rx_count;
1003 bp->tx_nr_rings_per_tc = channel->tx_count;
1004 }
1005 bp->tx_nr_rings_xdp = tx_xdp;
1006 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
1007 if (tcs > 1)
1008 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
1009
1010 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings);
1011 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) :
1012 tx_cp + bp->rx_nr_rings;
1013
1014 /* After changing number of rx channels, update NTUPLE feature. */
1015 netdev_update_features(dev);
1016 if (netif_running(dev)) {
1017 rc = bnxt_open_nic(bp, true, false);
1018 if ((!rc) && BNXT_PF(bp)) {
1019 /* TODO CHIMP_FW: Send message to all VF's
1020 * to renable
1021 */
1022 }
1023 } else {
1024 rc = bnxt_reserve_rings(bp, true);
1025 }
1026
1027 return rc;
1028 }
1029
bnxt_get_all_fltr_ids_rcu(struct bnxt * bp,struct hlist_head tbl[],int tbl_size,u32 * ids,u32 start,u32 id_cnt)1030 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[],
1031 int tbl_size, u32 *ids, u32 start,
1032 u32 id_cnt)
1033 {
1034 int i, j = start;
1035
1036 if (j >= id_cnt)
1037 return j;
1038 for (i = 0; i < tbl_size; i++) {
1039 struct hlist_head *head;
1040 struct bnxt_filter_base *fltr;
1041
1042 head = &tbl[i];
1043 hlist_for_each_entry_rcu(fltr, head, hash) {
1044 if (!fltr->flags ||
1045 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state))
1046 continue;
1047 ids[j++] = fltr->sw_id;
1048 if (j == id_cnt)
1049 return j;
1050 }
1051 }
1052 return j;
1053 }
1054
bnxt_get_one_fltr_rcu(struct bnxt * bp,struct hlist_head tbl[],int tbl_size,u32 id)1055 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp,
1056 struct hlist_head tbl[],
1057 int tbl_size, u32 id)
1058 {
1059 int i;
1060
1061 for (i = 0; i < tbl_size; i++) {
1062 struct hlist_head *head;
1063 struct bnxt_filter_base *fltr;
1064
1065 head = &tbl[i];
1066 hlist_for_each_entry_rcu(fltr, head, hash) {
1067 if (fltr->flags && fltr->sw_id == id)
1068 return fltr;
1069 }
1070 }
1071 return NULL;
1072 }
1073
bnxt_grxclsrlall(struct bnxt * bp,struct ethtool_rxnfc * cmd,u32 * rule_locs)1074 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
1075 u32 *rule_locs)
1076 {
1077 u32 count;
1078
1079 cmd->data = bp->ntp_fltr_count;
1080 rcu_read_lock();
1081 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl,
1082 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0,
1083 cmd->rule_cnt);
1084 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl,
1085 BNXT_NTP_FLTR_HASH_SIZE,
1086 rule_locs, count,
1087 cmd->rule_cnt);
1088 rcu_read_unlock();
1089
1090 return 0;
1091 }
1092
bnxt_grxclsrule(struct bnxt * bp,struct ethtool_rxnfc * cmd)1093 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1094 {
1095 struct ethtool_rx_flow_spec *fs =
1096 (struct ethtool_rx_flow_spec *)&cmd->fs;
1097 struct bnxt_filter_base *fltr_base;
1098 struct bnxt_ntuple_filter *fltr;
1099 struct bnxt_flow_masks *fmasks;
1100 struct flow_keys *fkeys;
1101 int rc = -EINVAL;
1102
1103 if (fs->location >= bp->max_fltr)
1104 return rc;
1105
1106 rcu_read_lock();
1107 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1108 BNXT_L2_FLTR_HASH_SIZE,
1109 fs->location);
1110 if (fltr_base) {
1111 struct ethhdr *h_ether = &fs->h_u.ether_spec;
1112 struct ethhdr *m_ether = &fs->m_u.ether_spec;
1113 struct bnxt_l2_filter *l2_fltr;
1114 struct bnxt_l2_key *l2_key;
1115
1116 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1117 l2_key = &l2_fltr->l2_key;
1118 fs->flow_type = ETHER_FLOW;
1119 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr);
1120 eth_broadcast_addr(m_ether->h_dest);
1121 if (l2_key->vlan) {
1122 struct ethtool_flow_ext *m_ext = &fs->m_ext;
1123 struct ethtool_flow_ext *h_ext = &fs->h_ext;
1124
1125 fs->flow_type |= FLOW_EXT;
1126 m_ext->vlan_tci = htons(0xfff);
1127 h_ext->vlan_tci = htons(l2_key->vlan);
1128 }
1129 if (fltr_base->flags & BNXT_ACT_RING_DST)
1130 fs->ring_cookie = fltr_base->rxq;
1131 if (fltr_base->flags & BNXT_ACT_FUNC_DST)
1132 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) <<
1133 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
1134 rcu_read_unlock();
1135 return 0;
1136 }
1137 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1138 BNXT_NTP_FLTR_HASH_SIZE,
1139 fs->location);
1140 if (!fltr_base) {
1141 rcu_read_unlock();
1142 return rc;
1143 }
1144 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1145
1146 fkeys = &fltr->fkeys;
1147 fmasks = &fltr->fmasks;
1148 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1149 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) {
1150 fs->flow_type = IP_USER_FLOW;
1151 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1152 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD;
1153 fs->m_u.usr_ip4_spec.proto = 0;
1154 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) {
1155 fs->flow_type = IP_USER_FLOW;
1156 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1157 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP;
1158 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK;
1159 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1160 fs->flow_type = TCP_V4_FLOW;
1161 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1162 fs->flow_type = UDP_V4_FLOW;
1163 } else {
1164 goto fltr_err;
1165 }
1166
1167 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1168 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src;
1169 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1170 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst;
1171 if (fs->flow_type == TCP_V4_FLOW ||
1172 fs->flow_type == UDP_V4_FLOW) {
1173 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1174 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src;
1175 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1176 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst;
1177 }
1178 } else {
1179 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) {
1180 fs->flow_type = IPV6_USER_FLOW;
1181 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD;
1182 fs->m_u.usr_ip6_spec.l4_proto = 0;
1183 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) {
1184 fs->flow_type = IPV6_USER_FLOW;
1185 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6;
1186 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK;
1187 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1188 fs->flow_type = TCP_V6_FLOW;
1189 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1190 fs->flow_type = UDP_V6_FLOW;
1191 } else {
1192 goto fltr_err;
1193 }
1194
1195 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1196 fkeys->addrs.v6addrs.src;
1197 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] =
1198 fmasks->addrs.v6addrs.src;
1199 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1200 fkeys->addrs.v6addrs.dst;
1201 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] =
1202 fmasks->addrs.v6addrs.dst;
1203 if (fs->flow_type == TCP_V6_FLOW ||
1204 fs->flow_type == UDP_V6_FLOW) {
1205 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1206 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src;
1207 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1208 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst;
1209 }
1210 }
1211
1212 if (fltr->base.flags & BNXT_ACT_DROP) {
1213 fs->ring_cookie = RX_CLS_FLOW_DISC;
1214 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) {
1215 fs->flow_type |= FLOW_RSS;
1216 cmd->rss_context = fltr->base.fw_vnic_id;
1217 } else {
1218 fs->ring_cookie = fltr->base.rxq;
1219 }
1220 rc = 0;
1221
1222 fltr_err:
1223 rcu_read_unlock();
1224
1225 return rc;
1226 }
1227
bnxt_get_rss_ctx_from_index(struct bnxt * bp,u32 index)1228 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp,
1229 u32 index)
1230 {
1231 struct ethtool_rxfh_context *ctx;
1232
1233 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index);
1234 if (!ctx)
1235 return NULL;
1236 return ethtool_rxfh_context_priv(ctx);
1237 }
1238
bnxt_alloc_vnic_rss_table(struct bnxt * bp,struct bnxt_vnic_info * vnic)1239 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp,
1240 struct bnxt_vnic_info *vnic)
1241 {
1242 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
1243
1244 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
1245 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev,
1246 vnic->rss_table_size,
1247 &vnic->rss_table_dma_addr,
1248 GFP_KERNEL);
1249 if (!vnic->rss_table)
1250 return -ENOMEM;
1251
1252 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
1253 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
1254 return 0;
1255 }
1256
bnxt_add_l2_cls_rule(struct bnxt * bp,struct ethtool_rx_flow_spec * fs)1257 static int bnxt_add_l2_cls_rule(struct bnxt *bp,
1258 struct ethtool_rx_flow_spec *fs)
1259 {
1260 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1261 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1262 struct ethhdr *h_ether = &fs->h_u.ether_spec;
1263 struct ethhdr *m_ether = &fs->m_u.ether_spec;
1264 struct bnxt_l2_filter *fltr;
1265 struct bnxt_l2_key key;
1266 u16 vnic_id;
1267 u8 flags;
1268 int rc;
1269
1270 if (BNXT_CHIP_P5_PLUS(bp))
1271 return -EOPNOTSUPP;
1272
1273 if (!is_broadcast_ether_addr(m_ether->h_dest))
1274 return -EINVAL;
1275 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest);
1276 key.vlan = 0;
1277 if (fs->flow_type & FLOW_EXT) {
1278 struct ethtool_flow_ext *m_ext = &fs->m_ext;
1279 struct ethtool_flow_ext *h_ext = &fs->h_ext;
1280
1281 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci)
1282 return -EINVAL;
1283 key.vlan = ntohs(h_ext->vlan_tci);
1284 }
1285
1286 if (vf) {
1287 flags = BNXT_ACT_FUNC_DST;
1288 vnic_id = 0xffff;
1289 vf--;
1290 } else {
1291 flags = BNXT_ACT_RING_DST;
1292 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id;
1293 }
1294 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags);
1295 if (IS_ERR(fltr))
1296 return PTR_ERR(fltr);
1297
1298 fltr->base.fw_vnic_id = vnic_id;
1299 fltr->base.rxq = ring;
1300 fltr->base.vf_idx = vf;
1301 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr);
1302 if (rc)
1303 bnxt_del_l2_filter(bp, fltr);
1304 else
1305 fs->location = fltr->base.sw_id;
1306 return rc;
1307 }
1308
bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec * ip_spec,struct ethtool_usrip4_spec * ip_mask)1309 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec,
1310 struct ethtool_usrip4_spec *ip_mask)
1311 {
1312 u8 mproto = ip_mask->proto;
1313 u8 sproto = ip_spec->proto;
1314
1315 if (ip_mask->l4_4_bytes || ip_mask->tos ||
1316 ip_spec->ip_ver != ETH_RX_NFC_IP4 ||
1317 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP)))
1318 return false;
1319 return true;
1320 }
1321
bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec * ip_spec,struct ethtool_usrip6_spec * ip_mask)1322 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec,
1323 struct ethtool_usrip6_spec *ip_mask)
1324 {
1325 u8 mproto = ip_mask->l4_proto;
1326 u8 sproto = ip_spec->l4_proto;
1327
1328 if (ip_mask->l4_4_bytes || ip_mask->tclass ||
1329 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6)))
1330 return false;
1331 return true;
1332 }
1333
bnxt_add_ntuple_cls_rule(struct bnxt * bp,struct ethtool_rxnfc * cmd)1334 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp,
1335 struct ethtool_rxnfc *cmd)
1336 {
1337 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1338 struct bnxt_ntuple_filter *new_fltr, *fltr;
1339 u32 flow_type = fs->flow_type & 0xff;
1340 struct bnxt_l2_filter *l2_fltr;
1341 struct bnxt_flow_masks *fmasks;
1342 struct flow_keys *fkeys;
1343 u32 idx, ring;
1344 int rc;
1345 u8 vf;
1346
1347 if (!bp->vnic_info)
1348 return -EAGAIN;
1349
1350 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1351 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1352 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf)
1353 return -EOPNOTSUPP;
1354
1355 if (flow_type == IP_USER_FLOW) {
1356 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec,
1357 &fs->m_u.usr_ip4_spec))
1358 return -EOPNOTSUPP;
1359 }
1360
1361 if (flow_type == IPV6_USER_FLOW) {
1362 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec,
1363 &fs->m_u.usr_ip6_spec))
1364 return -EOPNOTSUPP;
1365 }
1366
1367 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL);
1368 if (!new_fltr)
1369 return -ENOMEM;
1370
1371 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
1372 atomic_inc(&l2_fltr->refcnt);
1373 new_fltr->l2_fltr = l2_fltr;
1374 fmasks = &new_fltr->fmasks;
1375 fkeys = &new_fltr->fkeys;
1376
1377 rc = -EOPNOTSUPP;
1378 switch (flow_type) {
1379 case IP_USER_FLOW: {
1380 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec;
1381 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec;
1382
1383 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto
1384 : BNXT_IP_PROTO_WILDCARD;
1385 fkeys->basic.n_proto = htons(ETH_P_IP);
1386 fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1387 fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1388 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1389 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1390 break;
1391 }
1392 case TCP_V4_FLOW:
1393 case UDP_V4_FLOW: {
1394 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec;
1395 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec;
1396
1397 fkeys->basic.ip_proto = IPPROTO_TCP;
1398 if (flow_type == UDP_V4_FLOW)
1399 fkeys->basic.ip_proto = IPPROTO_UDP;
1400 fkeys->basic.n_proto = htons(ETH_P_IP);
1401 fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1402 fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1403 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1404 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1405 fkeys->ports.src = ip_spec->psrc;
1406 fmasks->ports.src = ip_mask->psrc;
1407 fkeys->ports.dst = ip_spec->pdst;
1408 fmasks->ports.dst = ip_mask->pdst;
1409 break;
1410 }
1411 case IPV6_USER_FLOW: {
1412 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec;
1413 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec;
1414
1415 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto
1416 : BNXT_IP_PROTO_WILDCARD;
1417 fkeys->basic.n_proto = htons(ETH_P_IPV6);
1418 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1419 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1420 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1421 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1422 break;
1423 }
1424 case TCP_V6_FLOW:
1425 case UDP_V6_FLOW: {
1426 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec;
1427 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec;
1428
1429 fkeys->basic.ip_proto = IPPROTO_TCP;
1430 if (flow_type == UDP_V6_FLOW)
1431 fkeys->basic.ip_proto = IPPROTO_UDP;
1432 fkeys->basic.n_proto = htons(ETH_P_IPV6);
1433
1434 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1435 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1436 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1437 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1438 fkeys->ports.src = ip_spec->psrc;
1439 fmasks->ports.src = ip_mask->psrc;
1440 fkeys->ports.dst = ip_spec->pdst;
1441 fmasks->ports.dst = ip_mask->pdst;
1442 break;
1443 }
1444 default:
1445 rc = -EOPNOTSUPP;
1446 goto ntuple_err;
1447 }
1448 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks)))
1449 goto ntuple_err;
1450
1451 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL);
1452 rcu_read_lock();
1453 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);
1454 if (fltr) {
1455 rcu_read_unlock();
1456 rc = -EEXIST;
1457 goto ntuple_err;
1458 }
1459 rcu_read_unlock();
1460
1461 new_fltr->base.flags = BNXT_ACT_NO_AGING;
1462 if (fs->flow_type & FLOW_RSS) {
1463 struct bnxt_rss_ctx *rss_ctx;
1464
1465 new_fltr->base.fw_vnic_id = 0;
1466 new_fltr->base.flags |= BNXT_ACT_RSS_CTX;
1467 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context);
1468 if (rss_ctx) {
1469 new_fltr->base.fw_vnic_id = rss_ctx->index;
1470 } else {
1471 rc = -EINVAL;
1472 goto ntuple_err;
1473 }
1474 }
1475 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1476 new_fltr->base.flags |= BNXT_ACT_DROP;
1477 else
1478 new_fltr->base.rxq = ring;
1479 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state);
1480 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);
1481 if (!rc) {
1482 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr);
1483 if (rc) {
1484 bnxt_del_ntp_filter(bp, new_fltr);
1485 return rc;
1486 }
1487 fs->location = new_fltr->base.sw_id;
1488 return 0;
1489 }
1490
1491 ntuple_err:
1492 atomic_dec(&l2_fltr->refcnt);
1493 kfree(new_fltr);
1494 return rc;
1495 }
1496
bnxt_srxclsrlins(struct bnxt * bp,struct ethtool_rxnfc * cmd)1497 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1498 {
1499 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1500 u32 ring, flow_type;
1501 int rc;
1502 u8 vf;
1503
1504 if (!netif_running(bp->dev))
1505 return -EAGAIN;
1506 if (!(bp->flags & BNXT_FLAG_RFS))
1507 return -EPERM;
1508 if (fs->location != RX_CLS_LOC_ANY)
1509 return -EINVAL;
1510
1511 flow_type = fs->flow_type;
1512 if ((flow_type == IP_USER_FLOW ||
1513 flow_type == IPV6_USER_FLOW) &&
1514 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO))
1515 return -EOPNOTSUPP;
1516 if (flow_type & FLOW_MAC_EXT)
1517 return -EINVAL;
1518 flow_type &= ~FLOW_EXT;
1519
1520 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW)
1521 return bnxt_add_ntuple_cls_rule(bp, cmd);
1522
1523 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1524 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1525 if (BNXT_VF(bp) && vf)
1526 return -EINVAL;
1527 if (BNXT_PF(bp) && vf > bp->pf.active_vfs)
1528 return -EINVAL;
1529 if (!vf && ring >= bp->rx_nr_rings)
1530 return -EINVAL;
1531
1532 if (flow_type == ETHER_FLOW)
1533 rc = bnxt_add_l2_cls_rule(bp, fs);
1534 else
1535 rc = bnxt_add_ntuple_cls_rule(bp, cmd);
1536 return rc;
1537 }
1538
bnxt_srxclsrldel(struct bnxt * bp,struct ethtool_rxnfc * cmd)1539 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1540 {
1541 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1542 struct bnxt_filter_base *fltr_base;
1543 struct bnxt_ntuple_filter *fltr;
1544 u32 id = fs->location;
1545
1546 rcu_read_lock();
1547 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1548 BNXT_L2_FLTR_HASH_SIZE, id);
1549 if (fltr_base) {
1550 struct bnxt_l2_filter *l2_fltr;
1551
1552 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1553 rcu_read_unlock();
1554 bnxt_hwrm_l2_filter_free(bp, l2_fltr);
1555 bnxt_del_l2_filter(bp, l2_fltr);
1556 return 0;
1557 }
1558 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1559 BNXT_NTP_FLTR_HASH_SIZE, id);
1560 if (!fltr_base) {
1561 rcu_read_unlock();
1562 return -ENOENT;
1563 }
1564
1565 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1566 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) {
1567 rcu_read_unlock();
1568 return -EINVAL;
1569 }
1570 rcu_read_unlock();
1571 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr);
1572 bnxt_del_ntp_filter(bp, fltr);
1573 return 0;
1574 }
1575
get_ethtool_ipv4_rss(struct bnxt * bp)1576 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1577 {
1578 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1579 return RXH_IP_SRC | RXH_IP_DST;
1580 return 0;
1581 }
1582
get_ethtool_ipv6_rss(struct bnxt * bp)1583 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1584 {
1585 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1586 return RXH_IP_SRC | RXH_IP_DST;
1587 return 0;
1588 }
1589
bnxt_grxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1590 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1591 {
1592 cmd->data = 0;
1593 switch (cmd->flow_type) {
1594 case TCP_V4_FLOW:
1595 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1596 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1597 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1598 cmd->data |= get_ethtool_ipv4_rss(bp);
1599 break;
1600 case UDP_V4_FLOW:
1601 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1602 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1603 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1604 fallthrough;
1605 case AH_ESP_V4_FLOW:
1606 if (bp->rss_hash_cfg &
1607 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1608 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4))
1609 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1610 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1611 fallthrough;
1612 case SCTP_V4_FLOW:
1613 case AH_V4_FLOW:
1614 case ESP_V4_FLOW:
1615 case IPV4_FLOW:
1616 cmd->data |= get_ethtool_ipv4_rss(bp);
1617 break;
1618
1619 case TCP_V6_FLOW:
1620 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1621 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1622 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1623 cmd->data |= get_ethtool_ipv6_rss(bp);
1624 break;
1625 case UDP_V6_FLOW:
1626 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1627 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1628 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1629 fallthrough;
1630 case AH_ESP_V6_FLOW:
1631 if (bp->rss_hash_cfg &
1632 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1633 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6))
1634 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1635 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1636 fallthrough;
1637 case SCTP_V6_FLOW:
1638 case AH_V6_FLOW:
1639 case ESP_V6_FLOW:
1640 case IPV6_FLOW:
1641 cmd->data |= get_ethtool_ipv6_rss(bp);
1642 break;
1643 }
1644 return 0;
1645 }
1646
1647 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1648 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1649
bnxt_srxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1650 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1651 {
1652 u32 rss_hash_cfg = bp->rss_hash_cfg;
1653 int tuple, rc = 0;
1654
1655 if (cmd->data == RXH_4TUPLE)
1656 tuple = 4;
1657 else if (cmd->data == RXH_2TUPLE)
1658 tuple = 2;
1659 else if (!cmd->data)
1660 tuple = 0;
1661 else
1662 return -EINVAL;
1663
1664 if (cmd->flow_type == TCP_V4_FLOW) {
1665 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1666 if (tuple == 4)
1667 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1668 } else if (cmd->flow_type == UDP_V4_FLOW) {
1669 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1670 return -EINVAL;
1671 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1672 if (tuple == 4)
1673 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1674 } else if (cmd->flow_type == TCP_V6_FLOW) {
1675 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1676 if (tuple == 4)
1677 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1678 } else if (cmd->flow_type == UDP_V6_FLOW) {
1679 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1680 return -EINVAL;
1681 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1682 if (tuple == 4)
1683 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1684 } else if (cmd->flow_type == AH_ESP_V4_FLOW) {
1685 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) ||
1686 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP)))
1687 return -EINVAL;
1688 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1689 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4);
1690 if (tuple == 4)
1691 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1692 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4;
1693 } else if (cmd->flow_type == AH_ESP_V6_FLOW) {
1694 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) ||
1695 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP)))
1696 return -EINVAL;
1697 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1698 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6);
1699 if (tuple == 4)
1700 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1701 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6;
1702 } else if (tuple == 4) {
1703 return -EINVAL;
1704 }
1705
1706 switch (cmd->flow_type) {
1707 case TCP_V4_FLOW:
1708 case UDP_V4_FLOW:
1709 case SCTP_V4_FLOW:
1710 case AH_ESP_V4_FLOW:
1711 case AH_V4_FLOW:
1712 case ESP_V4_FLOW:
1713 case IPV4_FLOW:
1714 if (tuple == 2)
1715 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1716 else if (!tuple)
1717 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1718 break;
1719
1720 case TCP_V6_FLOW:
1721 case UDP_V6_FLOW:
1722 case SCTP_V6_FLOW:
1723 case AH_ESP_V6_FLOW:
1724 case AH_V6_FLOW:
1725 case ESP_V6_FLOW:
1726 case IPV6_FLOW:
1727 if (tuple == 2)
1728 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1729 else if (!tuple)
1730 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1731 break;
1732 }
1733
1734 if (bp->rss_hash_cfg == rss_hash_cfg)
1735 return 0;
1736
1737 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
1738 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
1739 bp->rss_hash_cfg = rss_hash_cfg;
1740 if (netif_running(bp->dev)) {
1741 bnxt_close_nic(bp, false, false);
1742 rc = bnxt_open_nic(bp, false, false);
1743 }
1744 return rc;
1745 }
1746
bnxt_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1747 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1748 u32 *rule_locs)
1749 {
1750 struct bnxt *bp = netdev_priv(dev);
1751 int rc = 0;
1752
1753 switch (cmd->cmd) {
1754 case ETHTOOL_GRXRINGS:
1755 cmd->data = bp->rx_nr_rings;
1756 break;
1757
1758 case ETHTOOL_GRXCLSRLCNT:
1759 cmd->rule_cnt = bp->ntp_fltr_count;
1760 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL;
1761 break;
1762
1763 case ETHTOOL_GRXCLSRLALL:
1764 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1765 break;
1766
1767 case ETHTOOL_GRXCLSRULE:
1768 rc = bnxt_grxclsrule(bp, cmd);
1769 break;
1770
1771 case ETHTOOL_GRXFH:
1772 rc = bnxt_grxfh(bp, cmd);
1773 break;
1774
1775 default:
1776 rc = -EOPNOTSUPP;
1777 break;
1778 }
1779
1780 return rc;
1781 }
1782
bnxt_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1783 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1784 {
1785 struct bnxt *bp = netdev_priv(dev);
1786 int rc;
1787
1788 switch (cmd->cmd) {
1789 case ETHTOOL_SRXFH:
1790 rc = bnxt_srxfh(bp, cmd);
1791 break;
1792
1793 case ETHTOOL_SRXCLSRLINS:
1794 rc = bnxt_srxclsrlins(bp, cmd);
1795 break;
1796
1797 case ETHTOOL_SRXCLSRLDEL:
1798 rc = bnxt_srxclsrldel(bp, cmd);
1799 break;
1800
1801 default:
1802 rc = -EOPNOTSUPP;
1803 break;
1804 }
1805 return rc;
1806 }
1807
bnxt_get_rxfh_indir_size(struct net_device * dev)1808 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1809 {
1810 struct bnxt *bp = netdev_priv(dev);
1811
1812 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1813 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) *
1814 BNXT_RSS_TABLE_ENTRIES_P5;
1815 return HW_HASH_INDEX_SIZE;
1816 }
1817
bnxt_get_rxfh_key_size(struct net_device * dev)1818 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1819 {
1820 return HW_HASH_KEY_SIZE;
1821 }
1822
bnxt_get_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh)1823 static int bnxt_get_rxfh(struct net_device *dev,
1824 struct ethtool_rxfh_param *rxfh)
1825 {
1826 struct bnxt_rss_ctx *rss_ctx = NULL;
1827 struct bnxt *bp = netdev_priv(dev);
1828 u32 *indir_tbl = bp->rss_indir_tbl;
1829 struct bnxt_vnic_info *vnic;
1830 u32 i, tbl_size;
1831
1832 rxfh->hfunc = ETH_RSS_HASH_TOP;
1833
1834 if (!bp->vnic_info)
1835 return 0;
1836
1837 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
1838 if (rxfh->rss_context) {
1839 struct ethtool_rxfh_context *ctx;
1840
1841 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context);
1842 if (!ctx)
1843 return -EINVAL;
1844 indir_tbl = ethtool_rxfh_context_indir(ctx);
1845 rss_ctx = ethtool_rxfh_context_priv(ctx);
1846 vnic = &rss_ctx->vnic;
1847 }
1848
1849 if (rxfh->indir && indir_tbl) {
1850 tbl_size = bnxt_get_rxfh_indir_size(dev);
1851 for (i = 0; i < tbl_size; i++)
1852 rxfh->indir[i] = indir_tbl[i];
1853 }
1854
1855 if (rxfh->key && vnic->rss_hash_key)
1856 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1857
1858 return 0;
1859 }
1860
bnxt_modify_rss(struct bnxt * bp,struct ethtool_rxfh_context * ctx,struct bnxt_rss_ctx * rss_ctx,const struct ethtool_rxfh_param * rxfh)1861 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx,
1862 struct bnxt_rss_ctx *rss_ctx,
1863 const struct ethtool_rxfh_param *rxfh)
1864 {
1865 if (rxfh->key) {
1866 if (rss_ctx) {
1867 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key,
1868 HW_HASH_KEY_SIZE);
1869 } else {
1870 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE);
1871 bp->rss_hash_key_updated = true;
1872 }
1873 }
1874 if (rxfh->indir) {
1875 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
1876 u32 *indir_tbl = bp->rss_indir_tbl;
1877
1878 if (rss_ctx)
1879 indir_tbl = ethtool_rxfh_context_indir(ctx);
1880 for (i = 0; i < tbl_size; i++)
1881 indir_tbl[i] = rxfh->indir[i];
1882 pad = bp->rss_indir_tbl_entries - tbl_size;
1883 if (pad)
1884 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl));
1885 }
1886 }
1887
bnxt_rxfh_context_check(struct bnxt * bp,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1888 static int bnxt_rxfh_context_check(struct bnxt *bp,
1889 const struct ethtool_rxfh_param *rxfh,
1890 struct netlink_ext_ack *extack)
1891 {
1892 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) {
1893 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported");
1894 return -EOPNOTSUPP;
1895 }
1896
1897 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) {
1898 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported");
1899 return -EOPNOTSUPP;
1900 }
1901
1902 if (!netif_running(bp->dev)) {
1903 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down");
1904 return -EAGAIN;
1905 }
1906
1907 return 0;
1908 }
1909
bnxt_create_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1910 static int bnxt_create_rxfh_context(struct net_device *dev,
1911 struct ethtool_rxfh_context *ctx,
1912 const struct ethtool_rxfh_param *rxfh,
1913 struct netlink_ext_ack *extack)
1914 {
1915 struct bnxt *bp = netdev_priv(dev);
1916 struct bnxt_rss_ctx *rss_ctx;
1917 struct bnxt_vnic_info *vnic;
1918 int rc;
1919
1920 rc = bnxt_rxfh_context_check(bp, rxfh, extack);
1921 if (rc)
1922 return rc;
1923
1924 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) {
1925 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u",
1926 BNXT_MAX_ETH_RSS_CTX);
1927 return -EINVAL;
1928 }
1929
1930 if (!bnxt_rfs_capable(bp, true)) {
1931 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources");
1932 return -ENOMEM;
1933 }
1934
1935 rss_ctx = ethtool_rxfh_context_priv(ctx);
1936
1937 bp->num_rss_ctx++;
1938
1939 vnic = &rss_ctx->vnic;
1940 vnic->rss_ctx = ctx;
1941 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG;
1942 vnic->vnic_id = BNXT_VNIC_ID_INVALID;
1943 rc = bnxt_alloc_vnic_rss_table(bp, vnic);
1944 if (rc)
1945 goto out;
1946
1947 /* Populate defaults in the context */
1948 bnxt_set_dflt_rss_indir_tbl(bp, ctx);
1949 ctx->hfunc = ETH_RSS_HASH_TOP;
1950 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE);
1951 memcpy(ethtool_rxfh_context_key(ctx),
1952 bp->rss_hash_key, HW_HASH_KEY_SIZE);
1953
1954 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings);
1955 if (rc) {
1956 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC");
1957 goto out;
1958 }
1959
1960 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA);
1961 if (rc) {
1962 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
1963 goto out;
1964 }
1965 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh);
1966
1967 rc = __bnxt_setup_vnic_p5(bp, vnic);
1968 if (rc) {
1969 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
1970 goto out;
1971 }
1972
1973 rss_ctx->index = rxfh->rss_context;
1974 return 0;
1975 out:
1976 bnxt_del_one_rss_ctx(bp, rss_ctx, true);
1977 return rc;
1978 }
1979
bnxt_modify_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1980 static int bnxt_modify_rxfh_context(struct net_device *dev,
1981 struct ethtool_rxfh_context *ctx,
1982 const struct ethtool_rxfh_param *rxfh,
1983 struct netlink_ext_ack *extack)
1984 {
1985 struct bnxt *bp = netdev_priv(dev);
1986 struct bnxt_rss_ctx *rss_ctx;
1987 int rc;
1988
1989 rc = bnxt_rxfh_context_check(bp, rxfh, extack);
1990 if (rc)
1991 return rc;
1992
1993 rss_ctx = ethtool_rxfh_context_priv(ctx);
1994
1995 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh);
1996
1997 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic);
1998 }
1999
bnxt_remove_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,u32 rss_context,struct netlink_ext_ack * extack)2000 static int bnxt_remove_rxfh_context(struct net_device *dev,
2001 struct ethtool_rxfh_context *ctx,
2002 u32 rss_context,
2003 struct netlink_ext_ack *extack)
2004 {
2005 struct bnxt *bp = netdev_priv(dev);
2006 struct bnxt_rss_ctx *rss_ctx;
2007
2008 rss_ctx = ethtool_rxfh_context_priv(ctx);
2009
2010 bnxt_del_one_rss_ctx(bp, rss_ctx, true);
2011 return 0;
2012 }
2013
bnxt_set_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)2014 static int bnxt_set_rxfh(struct net_device *dev,
2015 struct ethtool_rxfh_param *rxfh,
2016 struct netlink_ext_ack *extack)
2017 {
2018 struct bnxt *bp = netdev_priv(dev);
2019 int rc = 0;
2020
2021 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP)
2022 return -EOPNOTSUPP;
2023
2024 bnxt_modify_rss(bp, NULL, NULL, rxfh);
2025
2026 if (netif_running(bp->dev)) {
2027 bnxt_close_nic(bp, false, false);
2028 rc = bnxt_open_nic(bp, false, false);
2029 }
2030 return rc;
2031 }
2032
bnxt_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2033 static void bnxt_get_drvinfo(struct net_device *dev,
2034 struct ethtool_drvinfo *info)
2035 {
2036 struct bnxt *bp = netdev_priv(dev);
2037
2038 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
2039 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
2040 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
2041 info->n_stats = bnxt_get_num_stats(bp);
2042 info->testinfo_len = bp->num_tests;
2043 /* TODO CHIMP_FW: eeprom dump details */
2044 info->eedump_len = 0;
2045 /* TODO CHIMP FW: reg dump details */
2046 info->regdump_len = 0;
2047 }
2048
bnxt_get_regs_len(struct net_device * dev)2049 static int bnxt_get_regs_len(struct net_device *dev)
2050 {
2051 struct bnxt *bp = netdev_priv(dev);
2052 int reg_len;
2053
2054 if (!BNXT_PF(bp))
2055 return -EOPNOTSUPP;
2056
2057 reg_len = BNXT_PXP_REG_LEN;
2058
2059 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
2060 reg_len += sizeof(struct pcie_ctx_hw_stats);
2061
2062 return reg_len;
2063 }
2064
bnxt_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * _p)2065 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2066 void *_p)
2067 {
2068 struct pcie_ctx_hw_stats *hw_pcie_stats;
2069 struct hwrm_pcie_qstats_input *req;
2070 struct bnxt *bp = netdev_priv(dev);
2071 dma_addr_t hw_pcie_stats_addr;
2072 int rc;
2073
2074 regs->version = 0;
2075 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED))
2076 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
2077
2078 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
2079 return;
2080
2081 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
2082 return;
2083
2084 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
2085 &hw_pcie_stats_addr);
2086 if (!hw_pcie_stats) {
2087 hwrm_req_drop(bp, req);
2088 return;
2089 }
2090
2091 regs->version = 1;
2092 hwrm_req_hold(bp, req); /* hold on to slice */
2093 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
2094 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
2095 rc = hwrm_req_send(bp, req);
2096 if (!rc) {
2097 __le64 *src = (__le64 *)hw_pcie_stats;
2098 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
2099 int i;
2100
2101 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
2102 dst[i] = le64_to_cpu(src[i]);
2103 }
2104 hwrm_req_drop(bp, req);
2105 }
2106
bnxt_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)2107 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2108 {
2109 struct bnxt *bp = netdev_priv(dev);
2110
2111 wol->supported = 0;
2112 wol->wolopts = 0;
2113 memset(&wol->sopass, 0, sizeof(wol->sopass));
2114 if (bp->flags & BNXT_FLAG_WOL_CAP) {
2115 wol->supported = WAKE_MAGIC;
2116 if (bp->wol)
2117 wol->wolopts = WAKE_MAGIC;
2118 }
2119 }
2120
bnxt_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)2121 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2122 {
2123 struct bnxt *bp = netdev_priv(dev);
2124
2125 if (wol->wolopts & ~WAKE_MAGIC)
2126 return -EINVAL;
2127
2128 if (wol->wolopts & WAKE_MAGIC) {
2129 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
2130 return -EINVAL;
2131 if (!bp->wol) {
2132 if (bnxt_hwrm_alloc_wol_fltr(bp))
2133 return -EBUSY;
2134 bp->wol = 1;
2135 }
2136 } else {
2137 if (bp->wol) {
2138 if (bnxt_hwrm_free_wol_fltr(bp))
2139 return -EBUSY;
2140 bp->wol = 0;
2141 }
2142 }
2143 return 0;
2144 }
2145
2146 /* TODO: support 25GB, 40GB, 50GB with different cable type */
_bnxt_fw_to_linkmode(unsigned long * mode,u16 fw_speeds)2147 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds)
2148 {
2149 linkmode_zero(mode);
2150
2151 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
2152 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode);
2153 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
2154 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode);
2155 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
2156 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode);
2157 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
2158 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode);
2159 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
2160 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode);
2161 }
2162
2163 enum bnxt_media_type {
2164 BNXT_MEDIA_UNKNOWN = 0,
2165 BNXT_MEDIA_TP,
2166 BNXT_MEDIA_CR,
2167 BNXT_MEDIA_SR,
2168 BNXT_MEDIA_LR_ER_FR,
2169 BNXT_MEDIA_KR,
2170 BNXT_MEDIA_KX,
2171 BNXT_MEDIA_X,
2172 __BNXT_MEDIA_END,
2173 };
2174
2175 static const enum bnxt_media_type bnxt_phy_types[] = {
2176 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR,
2177 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR,
2178 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR,
2179 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR,
2180 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR,
2181 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX,
2182 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR,
2183 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP,
2184 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP,
2185 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR,
2186 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR,
2187 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR,
2188 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR,
2189 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR,
2190 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR,
2191 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2192 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2193 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR,
2194 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR,
2195 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR,
2196 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2197 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2198 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR,
2199 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP,
2200 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X,
2201 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X,
2202 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR,
2203 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR,
2204 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2205 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2206 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR,
2207 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR,
2208 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2209 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2210 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR,
2211 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR,
2212 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2213 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2214 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR,
2215 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR,
2216 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2217 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2218 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR,
2219 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR,
2220 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2221 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2222 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR,
2223 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR,
2224 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR,
2225 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR,
2226 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR,
2227 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR,
2228 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2229 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2230 };
2231
2232 static enum bnxt_media_type
bnxt_get_media(struct bnxt_link_info * link_info)2233 bnxt_get_media(struct bnxt_link_info *link_info)
2234 {
2235 switch (link_info->media_type) {
2236 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP:
2237 return BNXT_MEDIA_TP;
2238 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC:
2239 return BNXT_MEDIA_CR;
2240 default:
2241 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types))
2242 return bnxt_phy_types[link_info->phy_type];
2243 return BNXT_MEDIA_UNKNOWN;
2244 }
2245 }
2246
2247 enum bnxt_link_speed_indices {
2248 BNXT_LINK_SPEED_UNKNOWN = 0,
2249 BNXT_LINK_SPEED_100MB_IDX,
2250 BNXT_LINK_SPEED_1GB_IDX,
2251 BNXT_LINK_SPEED_10GB_IDX,
2252 BNXT_LINK_SPEED_25GB_IDX,
2253 BNXT_LINK_SPEED_40GB_IDX,
2254 BNXT_LINK_SPEED_50GB_IDX,
2255 BNXT_LINK_SPEED_100GB_IDX,
2256 BNXT_LINK_SPEED_200GB_IDX,
2257 BNXT_LINK_SPEED_400GB_IDX,
2258 __BNXT_LINK_SPEED_END
2259 };
2260
bnxt_fw_speed_idx(u16 speed)2261 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed)
2262 {
2263 switch (speed) {
2264 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX;
2265 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX;
2266 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX;
2267 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX;
2268 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX;
2269 case BNXT_LINK_SPEED_50GB:
2270 case BNXT_LINK_SPEED_50GB_PAM4:
2271 return BNXT_LINK_SPEED_50GB_IDX;
2272 case BNXT_LINK_SPEED_100GB:
2273 case BNXT_LINK_SPEED_100GB_PAM4:
2274 case BNXT_LINK_SPEED_100GB_PAM4_112:
2275 return BNXT_LINK_SPEED_100GB_IDX;
2276 case BNXT_LINK_SPEED_200GB:
2277 case BNXT_LINK_SPEED_200GB_PAM4:
2278 case BNXT_LINK_SPEED_200GB_PAM4_112:
2279 return BNXT_LINK_SPEED_200GB_IDX;
2280 case BNXT_LINK_SPEED_400GB:
2281 case BNXT_LINK_SPEED_400GB_PAM4:
2282 case BNXT_LINK_SPEED_400GB_PAM4_112:
2283 return BNXT_LINK_SPEED_400GB_IDX;
2284 default: return BNXT_LINK_SPEED_UNKNOWN;
2285 }
2286 }
2287
2288 static const enum ethtool_link_mode_bit_indices
2289 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {
2290 [BNXT_LINK_SPEED_100MB_IDX] = {
2291 {
2292 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2293 },
2294 },
2295 [BNXT_LINK_SPEED_1GB_IDX] = {
2296 {
2297 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2298 /* historically baseT, but DAC is more correctly baseX */
2299 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2300 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2301 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2302 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2303 },
2304 },
2305 [BNXT_LINK_SPEED_10GB_IDX] = {
2306 {
2307 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2308 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2309 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2310 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2311 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2312 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2313 },
2314 },
2315 [BNXT_LINK_SPEED_25GB_IDX] = {
2316 {
2317 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2318 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2319 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2320 },
2321 },
2322 [BNXT_LINK_SPEED_40GB_IDX] = {
2323 {
2324 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2325 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2326 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2327 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2328 },
2329 },
2330 [BNXT_LINK_SPEED_50GB_IDX] = {
2331 [BNXT_SIG_MODE_NRZ] = {
2332 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2333 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2334 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2335 },
2336 [BNXT_SIG_MODE_PAM4] = {
2337 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2338 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2339 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2340 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2341 },
2342 },
2343 [BNXT_LINK_SPEED_100GB_IDX] = {
2344 [BNXT_SIG_MODE_NRZ] = {
2345 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2346 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2347 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2348 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2349 },
2350 [BNXT_SIG_MODE_PAM4] = {
2351 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2352 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2353 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2354 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2355 },
2356 [BNXT_SIG_MODE_PAM4_112] = {
2357 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,
2358 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
2359 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
2360 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
2361 },
2362 },
2363 [BNXT_LINK_SPEED_200GB_IDX] = {
2364 [BNXT_SIG_MODE_PAM4] = {
2365 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2366 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2367 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2368 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2369 },
2370 [BNXT_SIG_MODE_PAM4_112] = {
2371 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,
2372 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
2373 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
2374 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
2375 },
2376 },
2377 [BNXT_LINK_SPEED_400GB_IDX] = {
2378 [BNXT_SIG_MODE_PAM4] = {
2379 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
2380 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
2381 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2382 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2383 },
2384 [BNXT_SIG_MODE_PAM4_112] = {
2385 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,
2386 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
2387 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
2388 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
2389 },
2390 },
2391 };
2392
2393 #define BNXT_LINK_MODE_UNKNOWN -1
2394
2395 static enum ethtool_link_mode_bit_indices
bnxt_get_link_mode(struct bnxt_link_info * link_info)2396 bnxt_get_link_mode(struct bnxt_link_info *link_info)
2397 {
2398 enum ethtool_link_mode_bit_indices link_mode;
2399 enum bnxt_link_speed_indices speed;
2400 enum bnxt_media_type media;
2401 u8 sig_mode;
2402
2403 if (link_info->phy_link_status != BNXT_LINK_LINK)
2404 return BNXT_LINK_MODE_UNKNOWN;
2405
2406 media = bnxt_get_media(link_info);
2407 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
2408 speed = bnxt_fw_speed_idx(link_info->link_speed);
2409 sig_mode = link_info->active_fec_sig_mode &
2410 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
2411 } else {
2412 speed = bnxt_fw_speed_idx(link_info->req_link_speed);
2413 sig_mode = link_info->req_signal_mode;
2414 }
2415 if (sig_mode >= BNXT_SIG_MODE_MAX)
2416 return BNXT_LINK_MODE_UNKNOWN;
2417
2418 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux
2419 * link mode, but since no such devices exist, the zeroes in the
2420 * map can be conveniently used to represent unknown link modes.
2421 */
2422 link_mode = bnxt_link_modes[speed][sig_mode][media];
2423 if (!link_mode)
2424 return BNXT_LINK_MODE_UNKNOWN;
2425
2426 switch (link_mode) {
2427 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
2428 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2429 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT;
2430 break;
2431 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
2432 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2433 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT;
2434 break;
2435 default:
2436 break;
2437 }
2438
2439 return link_mode;
2440 }
2441
bnxt_get_ethtool_modes(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)2442 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info,
2443 struct ethtool_link_ksettings *lk_ksettings)
2444 {
2445 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2446
2447 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
2448 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2449 lk_ksettings->link_modes.supported);
2450 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2451 lk_ksettings->link_modes.supported);
2452 }
2453
2454 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 ||
2455 link_info->support_pam4_auto_speeds)
2456 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2457 lk_ksettings->link_modes.supported);
2458
2459 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2460 return;
2461
2462 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX)
2463 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2464 lk_ksettings->link_modes.advertising);
2465 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1)
2466 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2467 lk_ksettings->link_modes.advertising);
2468 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX)
2469 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2470 lk_ksettings->link_modes.lp_advertising);
2471 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1)
2472 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2473 lk_ksettings->link_modes.lp_advertising);
2474 }
2475
2476 static const u16 bnxt_nrz_speed_masks[] = {
2477 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB,
2478 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB,
2479 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB,
2480 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB,
2481 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB,
2482 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB,
2483 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB,
2484 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2485 };
2486
2487 static const u16 bnxt_pam4_speed_masks[] = {
2488 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB,
2489 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB,
2490 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB,
2491 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2492 };
2493
2494 static const u16 bnxt_nrz_speeds2_masks[] = {
2495 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB,
2496 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB,
2497 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB,
2498 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB,
2499 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB,
2500 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB,
2501 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2502 };
2503
2504 static const u16 bnxt_pam4_speeds2_masks[] = {
2505 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4,
2506 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4,
2507 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4,
2508 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4,
2509 };
2510
2511 static const u16 bnxt_pam4_112_speeds2_masks[] = {
2512 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112,
2513 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112,
2514 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112,
2515 };
2516
2517 static enum bnxt_link_speed_indices
bnxt_encoding_speed_idx(u8 sig_mode,u16 phy_flags,u16 speed_msk)2518 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk)
2519 {
2520 const u16 *speeds;
2521 int idx, len;
2522
2523 switch (sig_mode) {
2524 case BNXT_SIG_MODE_NRZ:
2525 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2526 speeds = bnxt_nrz_speeds2_masks;
2527 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks);
2528 } else {
2529 speeds = bnxt_nrz_speed_masks;
2530 len = ARRAY_SIZE(bnxt_nrz_speed_masks);
2531 }
2532 break;
2533 case BNXT_SIG_MODE_PAM4:
2534 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2535 speeds = bnxt_pam4_speeds2_masks;
2536 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks);
2537 } else {
2538 speeds = bnxt_pam4_speed_masks;
2539 len = ARRAY_SIZE(bnxt_pam4_speed_masks);
2540 }
2541 break;
2542 case BNXT_SIG_MODE_PAM4_112:
2543 speeds = bnxt_pam4_112_speeds2_masks;
2544 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks);
2545 break;
2546 default:
2547 return BNXT_LINK_SPEED_UNKNOWN;
2548 }
2549
2550 for (idx = 0; idx < len; idx++) {
2551 if (speeds[idx] == speed_msk)
2552 return idx;
2553 }
2554
2555 return BNXT_LINK_SPEED_UNKNOWN;
2556 }
2557
2558 #define BNXT_FW_SPEED_MSK_BITS 16
2559
2560 static void
__bnxt_get_ethtool_speeds(unsigned long fw_mask,enum bnxt_media_type media,u8 sig_mode,u16 phy_flags,unsigned long * et_mask)2561 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2562 u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2563 {
2564 enum ethtool_link_mode_bit_indices link_mode;
2565 enum bnxt_link_speed_indices speed;
2566 u8 bit;
2567
2568 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) {
2569 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit);
2570 if (!speed)
2571 continue;
2572
2573 link_mode = bnxt_link_modes[speed][sig_mode][media];
2574 if (!link_mode)
2575 continue;
2576
2577 linkmode_set_bit(link_mode, et_mask);
2578 }
2579 }
2580
2581 static void
bnxt_get_ethtool_speeds(unsigned long fw_mask,enum bnxt_media_type media,u8 sig_mode,u16 phy_flags,unsigned long * et_mask)2582 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2583 u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2584 {
2585 if (media) {
2586 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2587 et_mask);
2588 return;
2589 }
2590
2591 /* list speeds for all media if unknown */
2592 for (media = 1; media < __BNXT_MEDIA_END; media++)
2593 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2594 et_mask);
2595 }
2596
2597 static void
bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info * link_info,enum bnxt_media_type media,struct ethtool_link_ksettings * lk_ksettings)2598 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info,
2599 enum bnxt_media_type media,
2600 struct ethtool_link_ksettings *lk_ksettings)
2601 {
2602 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2603 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2604 u16 phy_flags = bp->phy_flags;
2605
2606 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2607 sp_nrz = link_info->support_speeds2;
2608 sp_pam4 = link_info->support_speeds2;
2609 sp_pam4_112 = link_info->support_speeds2;
2610 } else {
2611 sp_nrz = link_info->support_speeds;
2612 sp_pam4 = link_info->support_pam4_speeds;
2613 }
2614 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2615 lk_ksettings->link_modes.supported);
2616 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2617 lk_ksettings->link_modes.supported);
2618 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2619 phy_flags, lk_ksettings->link_modes.supported);
2620 }
2621
2622 static void
bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info * link_info,enum bnxt_media_type media,struct ethtool_link_ksettings * lk_ksettings)2623 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info,
2624 enum bnxt_media_type media,
2625 struct ethtool_link_ksettings *lk_ksettings)
2626 {
2627 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2628 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2629 u16 phy_flags = bp->phy_flags;
2630
2631 sp_nrz = link_info->advertising;
2632 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2633 sp_pam4 = link_info->advertising;
2634 sp_pam4_112 = link_info->advertising;
2635 } else {
2636 sp_pam4 = link_info->advertising_pam4;
2637 }
2638 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2639 lk_ksettings->link_modes.advertising);
2640 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2641 lk_ksettings->link_modes.advertising);
2642 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2643 phy_flags, lk_ksettings->link_modes.advertising);
2644 }
2645
2646 static void
bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info * link_info,enum bnxt_media_type media,struct ethtool_link_ksettings * lk_ksettings)2647 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info,
2648 enum bnxt_media_type media,
2649 struct ethtool_link_ksettings *lk_ksettings)
2650 {
2651 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2652 u16 phy_flags = bp->phy_flags;
2653
2654 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media,
2655 BNXT_SIG_MODE_NRZ, phy_flags,
2656 lk_ksettings->link_modes.lp_advertising);
2657 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media,
2658 BNXT_SIG_MODE_PAM4, phy_flags,
2659 lk_ksettings->link_modes.lp_advertising);
2660 }
2661
bnxt_update_speed(u32 * delta,bool installed_media,u16 * speeds,u16 speed_msk,const unsigned long * et_mask,enum ethtool_link_mode_bit_indices mode)2662 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,
2663 u16 speed_msk, const unsigned long *et_mask,
2664 enum ethtool_link_mode_bit_indices mode)
2665 {
2666 bool mode_desired = linkmode_test_bit(mode, et_mask);
2667
2668 if (!mode)
2669 return;
2670
2671 /* enabled speeds for installed media should override */
2672 if (installed_media && mode_desired) {
2673 *speeds |= speed_msk;
2674 *delta |= speed_msk;
2675 return;
2676 }
2677
2678 /* many to one mapping, only allow one change per fw_speed bit */
2679 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) {
2680 *speeds ^= speed_msk;
2681 *delta |= speed_msk;
2682 }
2683 }
2684
bnxt_set_ethtool_speeds(struct bnxt_link_info * link_info,const unsigned long * et_mask)2685 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info,
2686 const unsigned long *et_mask)
2687 {
2688 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2689 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks;
2690 enum bnxt_media_type media = bnxt_get_media(link_info);
2691 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL;
2692 u32 delta_pam4_112 = 0;
2693 u32 delta_pam4 = 0;
2694 u32 delta_nrz = 0;
2695 int i, m;
2696
2697 adv = &link_info->advertising;
2698 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2699 adv_pam4 = &link_info->advertising;
2700 adv_pam4_112 = &link_info->advertising;
2701 sp_msks = bnxt_nrz_speeds2_masks;
2702 sp_pam4_msks = bnxt_pam4_speeds2_masks;
2703 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks;
2704 } else {
2705 adv_pam4 = &link_info->advertising_pam4;
2706 sp_msks = bnxt_nrz_speed_masks;
2707 sp_pam4_msks = bnxt_pam4_speed_masks;
2708 }
2709 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) {
2710 /* accept any legal media from user */
2711 for (m = 1; m < __BNXT_MEDIA_END; m++) {
2712 bnxt_update_speed(&delta_nrz, m == media,
2713 adv, sp_msks[i], et_mask,
2714 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]);
2715 bnxt_update_speed(&delta_pam4, m == media,
2716 adv_pam4, sp_pam4_msks[i], et_mask,
2717 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]);
2718 if (!adv_pam4_112)
2719 continue;
2720
2721 bnxt_update_speed(&delta_pam4_112, m == media,
2722 adv_pam4_112, sp_pam4_112_msks[i], et_mask,
2723 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]);
2724 }
2725 }
2726 }
2727
bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)2728 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
2729 struct ethtool_link_ksettings *lk_ksettings)
2730 {
2731 u16 fec_cfg = link_info->fec_cfg;
2732
2733 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
2734 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2735 lk_ksettings->link_modes.advertising);
2736 return;
2737 }
2738 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
2739 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2740 lk_ksettings->link_modes.advertising);
2741 if (fec_cfg & BNXT_FEC_ENC_RS)
2742 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2743 lk_ksettings->link_modes.advertising);
2744 if (fec_cfg & BNXT_FEC_ENC_LLRS)
2745 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2746 lk_ksettings->link_modes.advertising);
2747 }
2748
bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)2749 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
2750 struct ethtool_link_ksettings *lk_ksettings)
2751 {
2752 u16 fec_cfg = link_info->fec_cfg;
2753
2754 if (fec_cfg & BNXT_FEC_NONE) {
2755 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2756 lk_ksettings->link_modes.supported);
2757 return;
2758 }
2759 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
2760 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2761 lk_ksettings->link_modes.supported);
2762 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
2763 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2764 lk_ksettings->link_modes.supported);
2765 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
2766 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2767 lk_ksettings->link_modes.supported);
2768 }
2769
bnxt_fw_to_ethtool_speed(u16 fw_link_speed)2770 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
2771 {
2772 switch (fw_link_speed) {
2773 case BNXT_LINK_SPEED_100MB:
2774 return SPEED_100;
2775 case BNXT_LINK_SPEED_1GB:
2776 return SPEED_1000;
2777 case BNXT_LINK_SPEED_2_5GB:
2778 return SPEED_2500;
2779 case BNXT_LINK_SPEED_10GB:
2780 return SPEED_10000;
2781 case BNXT_LINK_SPEED_20GB:
2782 return SPEED_20000;
2783 case BNXT_LINK_SPEED_25GB:
2784 return SPEED_25000;
2785 case BNXT_LINK_SPEED_40GB:
2786 return SPEED_40000;
2787 case BNXT_LINK_SPEED_50GB:
2788 case BNXT_LINK_SPEED_50GB_PAM4:
2789 return SPEED_50000;
2790 case BNXT_LINK_SPEED_100GB:
2791 case BNXT_LINK_SPEED_100GB_PAM4:
2792 case BNXT_LINK_SPEED_100GB_PAM4_112:
2793 return SPEED_100000;
2794 case BNXT_LINK_SPEED_200GB:
2795 case BNXT_LINK_SPEED_200GB_PAM4:
2796 case BNXT_LINK_SPEED_200GB_PAM4_112:
2797 return SPEED_200000;
2798 case BNXT_LINK_SPEED_400GB:
2799 case BNXT_LINK_SPEED_400GB_PAM4:
2800 case BNXT_LINK_SPEED_400GB_PAM4_112:
2801 return SPEED_400000;
2802 default:
2803 return SPEED_UNKNOWN;
2804 }
2805 }
2806
bnxt_get_default_speeds(struct ethtool_link_ksettings * lk_ksettings,struct bnxt_link_info * link_info)2807 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings,
2808 struct bnxt_link_info *link_info)
2809 {
2810 struct ethtool_link_settings *base = &lk_ksettings->base;
2811
2812 if (link_info->link_state == BNXT_LINK_STATE_UP) {
2813 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
2814 base->duplex = DUPLEX_HALF;
2815 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2816 base->duplex = DUPLEX_FULL;
2817 lk_ksettings->lanes = link_info->active_lanes;
2818 } else if (!link_info->autoneg) {
2819 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
2820 base->duplex = DUPLEX_HALF;
2821 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
2822 base->duplex = DUPLEX_FULL;
2823 }
2824 }
2825
bnxt_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * lk_ksettings)2826 static int bnxt_get_link_ksettings(struct net_device *dev,
2827 struct ethtool_link_ksettings *lk_ksettings)
2828 {
2829 struct ethtool_link_settings *base = &lk_ksettings->base;
2830 enum ethtool_link_mode_bit_indices link_mode;
2831 struct bnxt *bp = netdev_priv(dev);
2832 struct bnxt_link_info *link_info;
2833 enum bnxt_media_type media;
2834
2835 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising);
2836 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
2837 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
2838 base->duplex = DUPLEX_UNKNOWN;
2839 base->speed = SPEED_UNKNOWN;
2840 link_info = &bp->link_info;
2841
2842 mutex_lock(&bp->link_lock);
2843 bnxt_get_ethtool_modes(link_info, lk_ksettings);
2844 media = bnxt_get_media(link_info);
2845 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings);
2846 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
2847 link_mode = bnxt_get_link_mode(link_info);
2848 if (link_mode != BNXT_LINK_MODE_UNKNOWN)
2849 ethtool_params_from_link_mode(lk_ksettings, link_mode);
2850 else
2851 bnxt_get_default_speeds(lk_ksettings, link_info);
2852
2853 if (link_info->autoneg) {
2854 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
2855 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2856 lk_ksettings->link_modes.advertising);
2857 base->autoneg = AUTONEG_ENABLE;
2858 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings);
2859 if (link_info->phy_link_status == BNXT_LINK_LINK)
2860 bnxt_get_all_ethtool_lp_speeds(link_info, media,
2861 lk_ksettings);
2862 } else {
2863 base->autoneg = AUTONEG_DISABLE;
2864 }
2865
2866 base->port = PORT_NONE;
2867 if (media == BNXT_MEDIA_TP) {
2868 base->port = PORT_TP;
2869 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2870 lk_ksettings->link_modes.supported);
2871 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2872 lk_ksettings->link_modes.advertising);
2873 } else if (media == BNXT_MEDIA_KR) {
2874 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT,
2875 lk_ksettings->link_modes.supported);
2876 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT,
2877 lk_ksettings->link_modes.advertising);
2878 } else {
2879 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2880 lk_ksettings->link_modes.supported);
2881 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2882 lk_ksettings->link_modes.advertising);
2883
2884 if (media == BNXT_MEDIA_CR)
2885 base->port = PORT_DA;
2886 else
2887 base->port = PORT_FIBRE;
2888 }
2889 base->phy_address = link_info->phy_addr;
2890 mutex_unlock(&bp->link_lock);
2891
2892 return 0;
2893 }
2894
2895 static int
bnxt_force_link_speed(struct net_device * dev,u32 ethtool_speed,u32 lanes)2896 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)
2897 {
2898 struct bnxt *bp = netdev_priv(dev);
2899 struct bnxt_link_info *link_info = &bp->link_info;
2900 u16 support_pam4_spds = link_info->support_pam4_speeds;
2901 u16 support_spds2 = link_info->support_speeds2;
2902 u16 support_spds = link_info->support_speeds;
2903 u8 sig_mode = BNXT_SIG_MODE_NRZ;
2904 u32 lanes_needed = 1;
2905 u16 fw_speed = 0;
2906
2907 switch (ethtool_speed) {
2908 case SPEED_100:
2909 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
2910 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
2911 break;
2912 case SPEED_1000:
2913 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) ||
2914 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB))
2915 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
2916 break;
2917 case SPEED_2500:
2918 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
2919 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
2920 break;
2921 case SPEED_10000:
2922 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) ||
2923 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB))
2924 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
2925 break;
2926 case SPEED_20000:
2927 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) {
2928 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
2929 lanes_needed = 2;
2930 }
2931 break;
2932 case SPEED_25000:
2933 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) ||
2934 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB))
2935 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
2936 break;
2937 case SPEED_40000:
2938 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) ||
2939 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) {
2940 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
2941 lanes_needed = 4;
2942 }
2943 break;
2944 case SPEED_50000:
2945 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) ||
2946 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) &&
2947 lanes != 1) {
2948 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
2949 lanes_needed = 2;
2950 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
2951 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
2952 sig_mode = BNXT_SIG_MODE_PAM4;
2953 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) {
2954 fw_speed = BNXT_LINK_SPEED_50GB_PAM4;
2955 sig_mode = BNXT_SIG_MODE_PAM4;
2956 }
2957 break;
2958 case SPEED_100000:
2959 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) ||
2960 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) &&
2961 lanes != 2 && lanes != 1) {
2962 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
2963 lanes_needed = 4;
2964 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
2965 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
2966 sig_mode = BNXT_SIG_MODE_PAM4;
2967 lanes_needed = 2;
2968 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) &&
2969 lanes != 1) {
2970 fw_speed = BNXT_LINK_SPEED_100GB_PAM4;
2971 sig_mode = BNXT_SIG_MODE_PAM4;
2972 lanes_needed = 2;
2973 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) {
2974 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112;
2975 sig_mode = BNXT_SIG_MODE_PAM4_112;
2976 }
2977 break;
2978 case SPEED_200000:
2979 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
2980 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
2981 sig_mode = BNXT_SIG_MODE_PAM4;
2982 lanes_needed = 4;
2983 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) &&
2984 lanes != 2) {
2985 fw_speed = BNXT_LINK_SPEED_200GB_PAM4;
2986 sig_mode = BNXT_SIG_MODE_PAM4;
2987 lanes_needed = 4;
2988 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) {
2989 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112;
2990 sig_mode = BNXT_SIG_MODE_PAM4_112;
2991 lanes_needed = 2;
2992 }
2993 break;
2994 case SPEED_400000:
2995 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) &&
2996 lanes != 4) {
2997 fw_speed = BNXT_LINK_SPEED_400GB_PAM4;
2998 sig_mode = BNXT_SIG_MODE_PAM4;
2999 lanes_needed = 8;
3000 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) {
3001 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112;
3002 sig_mode = BNXT_SIG_MODE_PAM4_112;
3003 lanes_needed = 4;
3004 }
3005 break;
3006 }
3007
3008 if (!fw_speed) {
3009 netdev_err(dev, "unsupported speed!\n");
3010 return -EINVAL;
3011 }
3012
3013 if (lanes && lanes != lanes_needed) {
3014 netdev_err(dev, "unsupported number of lanes for speed\n");
3015 return -EINVAL;
3016 }
3017
3018 if (link_info->req_link_speed == fw_speed &&
3019 link_info->req_signal_mode == sig_mode &&
3020 link_info->autoneg == 0)
3021 return -EALREADY;
3022
3023 link_info->req_link_speed = fw_speed;
3024 link_info->req_signal_mode = sig_mode;
3025 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
3026 link_info->autoneg = 0;
3027 link_info->advertising = 0;
3028 link_info->advertising_pam4 = 0;
3029
3030 return 0;
3031 }
3032
bnxt_get_fw_auto_link_speeds(const unsigned long * mode)3033 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode)
3034 {
3035 u16 fw_speed_mask = 0;
3036
3037 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) ||
3038 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode))
3039 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
3040
3041 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) ||
3042 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode))
3043 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
3044
3045 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode))
3046 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
3047
3048 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode))
3049 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
3050
3051 return fw_speed_mask;
3052 }
3053
bnxt_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * lk_ksettings)3054 static int bnxt_set_link_ksettings(struct net_device *dev,
3055 const struct ethtool_link_ksettings *lk_ksettings)
3056 {
3057 struct bnxt *bp = netdev_priv(dev);
3058 struct bnxt_link_info *link_info = &bp->link_info;
3059 const struct ethtool_link_settings *base = &lk_ksettings->base;
3060 bool set_pause = false;
3061 u32 speed, lanes = 0;
3062 int rc = 0;
3063
3064 if (!BNXT_PHY_CFG_ABLE(bp))
3065 return -EOPNOTSUPP;
3066
3067 mutex_lock(&bp->link_lock);
3068 if (base->autoneg == AUTONEG_ENABLE) {
3069 bnxt_set_ethtool_speeds(link_info,
3070 lk_ksettings->link_modes.advertising);
3071 link_info->autoneg |= BNXT_AUTONEG_SPEED;
3072 if (!link_info->advertising && !link_info->advertising_pam4) {
3073 link_info->advertising = link_info->support_auto_speeds;
3074 link_info->advertising_pam4 =
3075 link_info->support_pam4_auto_speeds;
3076 }
3077 /* any change to autoneg will cause link change, therefore the
3078 * driver should put back the original pause setting in autoneg
3079 */
3080 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3081 set_pause = true;
3082 } else {
3083 u8 phy_type = link_info->phy_type;
3084
3085 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
3086 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
3087 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
3088 netdev_err(dev, "10GBase-T devices must autoneg\n");
3089 rc = -EINVAL;
3090 goto set_setting_exit;
3091 }
3092 if (base->duplex == DUPLEX_HALF) {
3093 netdev_err(dev, "HALF DUPLEX is not supported!\n");
3094 rc = -EINVAL;
3095 goto set_setting_exit;
3096 }
3097 speed = base->speed;
3098 lanes = lk_ksettings->lanes;
3099 rc = bnxt_force_link_speed(dev, speed, lanes);
3100 if (rc) {
3101 if (rc == -EALREADY)
3102 rc = 0;
3103 goto set_setting_exit;
3104 }
3105 }
3106
3107 if (netif_running(dev))
3108 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
3109
3110 set_setting_exit:
3111 mutex_unlock(&bp->link_lock);
3112 return rc;
3113 }
3114
bnxt_get_fecparam(struct net_device * dev,struct ethtool_fecparam * fec)3115 static int bnxt_get_fecparam(struct net_device *dev,
3116 struct ethtool_fecparam *fec)
3117 {
3118 struct bnxt *bp = netdev_priv(dev);
3119 struct bnxt_link_info *link_info;
3120 u8 active_fec;
3121 u16 fec_cfg;
3122
3123 link_info = &bp->link_info;
3124 fec_cfg = link_info->fec_cfg;
3125 active_fec = link_info->active_fec_sig_mode &
3126 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
3127 if (fec_cfg & BNXT_FEC_NONE) {
3128 fec->fec = ETHTOOL_FEC_NONE;
3129 fec->active_fec = ETHTOOL_FEC_NONE;
3130 return 0;
3131 }
3132 if (fec_cfg & BNXT_FEC_AUTONEG)
3133 fec->fec |= ETHTOOL_FEC_AUTO;
3134 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
3135 fec->fec |= ETHTOOL_FEC_BASER;
3136 if (fec_cfg & BNXT_FEC_ENC_RS)
3137 fec->fec |= ETHTOOL_FEC_RS;
3138 if (fec_cfg & BNXT_FEC_ENC_LLRS)
3139 fec->fec |= ETHTOOL_FEC_LLRS;
3140
3141 switch (active_fec) {
3142 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
3143 fec->active_fec |= ETHTOOL_FEC_BASER;
3144 break;
3145 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
3146 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
3147 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
3148 fec->active_fec |= ETHTOOL_FEC_RS;
3149 break;
3150 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
3151 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
3152 fec->active_fec |= ETHTOOL_FEC_LLRS;
3153 break;
3154 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
3155 fec->active_fec |= ETHTOOL_FEC_OFF;
3156 break;
3157 }
3158 return 0;
3159 }
3160
bnxt_get_fec_stats(struct net_device * dev,struct ethtool_fec_stats * fec_stats)3161 static void bnxt_get_fec_stats(struct net_device *dev,
3162 struct ethtool_fec_stats *fec_stats)
3163 {
3164 struct bnxt *bp = netdev_priv(dev);
3165 u64 *rx;
3166
3167 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
3168 return;
3169
3170 rx = bp->rx_port_stats_ext.sw_stats;
3171 fec_stats->corrected_bits.total =
3172 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
3173
3174 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY)
3175 return;
3176
3177 fec_stats->corrected_blocks.total =
3178 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks));
3179 fec_stats->uncorrectable_blocks.total =
3180 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks));
3181 }
3182
bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info * link_info,u32 fec)3183 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
3184 u32 fec)
3185 {
3186 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
3187
3188 if (fec & ETHTOOL_FEC_BASER)
3189 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
3190 else if (fec & ETHTOOL_FEC_RS)
3191 fw_fec |= BNXT_FEC_RS_ON(link_info);
3192 else if (fec & ETHTOOL_FEC_LLRS)
3193 fw_fec |= BNXT_FEC_LLRS_ON;
3194 return fw_fec;
3195 }
3196
bnxt_set_fecparam(struct net_device * dev,struct ethtool_fecparam * fecparam)3197 static int bnxt_set_fecparam(struct net_device *dev,
3198 struct ethtool_fecparam *fecparam)
3199 {
3200 struct hwrm_port_phy_cfg_input *req;
3201 struct bnxt *bp = netdev_priv(dev);
3202 struct bnxt_link_info *link_info;
3203 u32 new_cfg, fec = fecparam->fec;
3204 u16 fec_cfg;
3205 int rc;
3206
3207 link_info = &bp->link_info;
3208 fec_cfg = link_info->fec_cfg;
3209 if (fec_cfg & BNXT_FEC_NONE)
3210 return -EOPNOTSUPP;
3211
3212 if (fec & ETHTOOL_FEC_OFF) {
3213 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
3214 BNXT_FEC_ALL_OFF(link_info);
3215 goto apply_fec;
3216 }
3217 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
3218 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
3219 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
3220 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
3221 return -EINVAL;
3222
3223 if (fec & ETHTOOL_FEC_AUTO) {
3224 if (!link_info->autoneg)
3225 return -EINVAL;
3226 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
3227 } else {
3228 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
3229 }
3230
3231 apply_fec:
3232 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3233 if (rc)
3234 return rc;
3235 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3236 rc = hwrm_req_send(bp, req);
3237 /* update current settings */
3238 if (!rc) {
3239 mutex_lock(&bp->link_lock);
3240 bnxt_update_link(bp, false);
3241 mutex_unlock(&bp->link_lock);
3242 }
3243 return rc;
3244 }
3245
bnxt_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)3246 static void bnxt_get_pauseparam(struct net_device *dev,
3247 struct ethtool_pauseparam *epause)
3248 {
3249 struct bnxt *bp = netdev_priv(dev);
3250 struct bnxt_link_info *link_info = &bp->link_info;
3251
3252 if (BNXT_VF(bp))
3253 return;
3254 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
3255 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
3256 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
3257 }
3258
bnxt_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * epstat)3259 static void bnxt_get_pause_stats(struct net_device *dev,
3260 struct ethtool_pause_stats *epstat)
3261 {
3262 struct bnxt *bp = netdev_priv(dev);
3263 u64 *rx, *tx;
3264
3265 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3266 return;
3267
3268 rx = bp->port_stats.sw_stats;
3269 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3270
3271 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
3272 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
3273 }
3274
bnxt_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)3275 static int bnxt_set_pauseparam(struct net_device *dev,
3276 struct ethtool_pauseparam *epause)
3277 {
3278 int rc = 0;
3279 struct bnxt *bp = netdev_priv(dev);
3280 struct bnxt_link_info *link_info = &bp->link_info;
3281
3282 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3283 return -EOPNOTSUPP;
3284
3285 mutex_lock(&bp->link_lock);
3286 if (epause->autoneg) {
3287 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3288 rc = -EINVAL;
3289 goto pause_exit;
3290 }
3291
3292 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
3293 link_info->req_flow_ctrl = 0;
3294 } else {
3295 /* when transition from auto pause to force pause,
3296 * force a link change
3297 */
3298 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
3299 link_info->force_link_chng = true;
3300 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
3301 link_info->req_flow_ctrl = 0;
3302 }
3303 if (epause->rx_pause)
3304 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
3305
3306 if (epause->tx_pause)
3307 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
3308
3309 if (netif_running(dev))
3310 rc = bnxt_hwrm_set_pause(bp);
3311
3312 pause_exit:
3313 mutex_unlock(&bp->link_lock);
3314 return rc;
3315 }
3316
bnxt_get_link(struct net_device * dev)3317 static u32 bnxt_get_link(struct net_device *dev)
3318 {
3319 struct bnxt *bp = netdev_priv(dev);
3320
3321 /* TODO: handle MF, VF, driver close case */
3322 return BNXT_LINK_IS_UP(bp);
3323 }
3324
bnxt_hwrm_nvm_get_dev_info(struct bnxt * bp,struct hwrm_nvm_get_dev_info_output * nvm_dev_info)3325 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
3326 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
3327 {
3328 struct hwrm_nvm_get_dev_info_output *resp;
3329 struct hwrm_nvm_get_dev_info_input *req;
3330 int rc;
3331
3332 if (BNXT_VF(bp))
3333 return -EOPNOTSUPP;
3334
3335 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
3336 if (rc)
3337 return rc;
3338
3339 resp = hwrm_req_hold(bp, req);
3340 rc = hwrm_req_send(bp, req);
3341 if (!rc)
3342 memcpy(nvm_dev_info, resp, sizeof(*resp));
3343 hwrm_req_drop(bp, req);
3344 return rc;
3345 }
3346
bnxt_print_admin_err(struct bnxt * bp)3347 static void bnxt_print_admin_err(struct bnxt *bp)
3348 {
3349 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
3350 }
3351
3352 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
3353 u16 ext, u16 *index, u32 *item_length,
3354 u32 *data_length);
3355
bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,u32 dir_item_len,const u8 * data,size_t data_len)3356 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
3357 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
3358 u32 dir_item_len, const u8 *data,
3359 size_t data_len)
3360 {
3361 struct bnxt *bp = netdev_priv(dev);
3362 struct hwrm_nvm_write_input *req;
3363 int rc;
3364
3365 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
3366 if (rc)
3367 return rc;
3368
3369 if (data_len && data) {
3370 dma_addr_t dma_handle;
3371 u8 *kmem;
3372
3373 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
3374 if (!kmem) {
3375 hwrm_req_drop(bp, req);
3376 return -ENOMEM;
3377 }
3378
3379 req->dir_data_length = cpu_to_le32(data_len);
3380
3381 memcpy(kmem, data, data_len);
3382 req->host_src_addr = cpu_to_le64(dma_handle);
3383 }
3384
3385 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
3386 req->dir_type = cpu_to_le16(dir_type);
3387 req->dir_ordinal = cpu_to_le16(dir_ordinal);
3388 req->dir_ext = cpu_to_le16(dir_ext);
3389 req->dir_attr = cpu_to_le16(dir_attr);
3390 req->dir_item_length = cpu_to_le32(dir_item_len);
3391 rc = hwrm_req_send(bp, req);
3392
3393 if (rc == -EACCES)
3394 bnxt_print_admin_err(bp);
3395 return rc;
3396 }
3397
bnxt_hwrm_firmware_reset(struct net_device * dev,u8 proc_type,u8 self_reset,u8 flags)3398 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
3399 u8 self_reset, u8 flags)
3400 {
3401 struct bnxt *bp = netdev_priv(dev);
3402 struct hwrm_fw_reset_input *req;
3403 int rc;
3404
3405 if (!bnxt_hwrm_reset_permitted(bp)) {
3406 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
3407 return -EPERM;
3408 }
3409
3410 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
3411 if (rc)
3412 return rc;
3413
3414 req->embedded_proc_type = proc_type;
3415 req->selfrst_status = self_reset;
3416 req->flags = flags;
3417
3418 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
3419 rc = hwrm_req_send_silent(bp, req);
3420 } else {
3421 rc = hwrm_req_send(bp, req);
3422 if (rc == -EACCES)
3423 bnxt_print_admin_err(bp);
3424 }
3425 return rc;
3426 }
3427
bnxt_firmware_reset(struct net_device * dev,enum bnxt_nvm_directory_type dir_type)3428 static int bnxt_firmware_reset(struct net_device *dev,
3429 enum bnxt_nvm_directory_type dir_type)
3430 {
3431 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
3432 u8 proc_type, flags = 0;
3433
3434 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
3435 /* (e.g. when firmware isn't already running) */
3436 switch (dir_type) {
3437 case BNX_DIR_TYPE_CHIMP_PATCH:
3438 case BNX_DIR_TYPE_BOOTCODE:
3439 case BNX_DIR_TYPE_BOOTCODE_2:
3440 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
3441 /* Self-reset ChiMP upon next PCIe reset: */
3442 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3443 break;
3444 case BNX_DIR_TYPE_APE_FW:
3445 case BNX_DIR_TYPE_APE_PATCH:
3446 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
3447 /* Self-reset APE upon next PCIe reset: */
3448 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3449 break;
3450 case BNX_DIR_TYPE_KONG_FW:
3451 case BNX_DIR_TYPE_KONG_PATCH:
3452 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
3453 break;
3454 case BNX_DIR_TYPE_BONO_FW:
3455 case BNX_DIR_TYPE_BONO_PATCH:
3456 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
3457 break;
3458 default:
3459 return -EINVAL;
3460 }
3461
3462 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
3463 }
3464
bnxt_firmware_reset_chip(struct net_device * dev)3465 static int bnxt_firmware_reset_chip(struct net_device *dev)
3466 {
3467 struct bnxt *bp = netdev_priv(dev);
3468 u8 flags = 0;
3469
3470 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
3471 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
3472
3473 return bnxt_hwrm_firmware_reset(dev,
3474 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
3475 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
3476 flags);
3477 }
3478
bnxt_firmware_reset_ap(struct net_device * dev)3479 static int bnxt_firmware_reset_ap(struct net_device *dev)
3480 {
3481 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
3482 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
3483 0);
3484 }
3485
bnxt_flash_firmware(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)3486 static int bnxt_flash_firmware(struct net_device *dev,
3487 u16 dir_type,
3488 const u8 *fw_data,
3489 size_t fw_size)
3490 {
3491 int rc = 0;
3492 u16 code_type;
3493 u32 stored_crc;
3494 u32 calculated_crc;
3495 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
3496
3497 switch (dir_type) {
3498 case BNX_DIR_TYPE_BOOTCODE:
3499 case BNX_DIR_TYPE_BOOTCODE_2:
3500 code_type = CODE_BOOT;
3501 break;
3502 case BNX_DIR_TYPE_CHIMP_PATCH:
3503 code_type = CODE_CHIMP_PATCH;
3504 break;
3505 case BNX_DIR_TYPE_APE_FW:
3506 code_type = CODE_MCTP_PASSTHRU;
3507 break;
3508 case BNX_DIR_TYPE_APE_PATCH:
3509 code_type = CODE_APE_PATCH;
3510 break;
3511 case BNX_DIR_TYPE_KONG_FW:
3512 code_type = CODE_KONG_FW;
3513 break;
3514 case BNX_DIR_TYPE_KONG_PATCH:
3515 code_type = CODE_KONG_PATCH;
3516 break;
3517 case BNX_DIR_TYPE_BONO_FW:
3518 code_type = CODE_BONO_FW;
3519 break;
3520 case BNX_DIR_TYPE_BONO_PATCH:
3521 code_type = CODE_BONO_PATCH;
3522 break;
3523 default:
3524 netdev_err(dev, "Unsupported directory entry type: %u\n",
3525 dir_type);
3526 return -EINVAL;
3527 }
3528 if (fw_size < sizeof(struct bnxt_fw_header)) {
3529 netdev_err(dev, "Invalid firmware file size: %u\n",
3530 (unsigned int)fw_size);
3531 return -EINVAL;
3532 }
3533 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
3534 netdev_err(dev, "Invalid firmware signature: %08X\n",
3535 le32_to_cpu(header->signature));
3536 return -EINVAL;
3537 }
3538 if (header->code_type != code_type) {
3539 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
3540 code_type, header->code_type);
3541 return -EINVAL;
3542 }
3543 if (header->device != DEVICE_CUMULUS_FAMILY) {
3544 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
3545 DEVICE_CUMULUS_FAMILY, header->device);
3546 return -EINVAL;
3547 }
3548 /* Confirm the CRC32 checksum of the file: */
3549 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3550 sizeof(stored_crc)));
3551 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3552 if (calculated_crc != stored_crc) {
3553 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
3554 (unsigned long)stored_crc,
3555 (unsigned long)calculated_crc);
3556 return -EINVAL;
3557 }
3558 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3559 0, 0, 0, fw_data, fw_size);
3560 if (rc == 0) /* Firmware update successful */
3561 rc = bnxt_firmware_reset(dev, dir_type);
3562
3563 return rc;
3564 }
3565
bnxt_flash_microcode(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)3566 static int bnxt_flash_microcode(struct net_device *dev,
3567 u16 dir_type,
3568 const u8 *fw_data,
3569 size_t fw_size)
3570 {
3571 struct bnxt_ucode_trailer *trailer;
3572 u32 calculated_crc;
3573 u32 stored_crc;
3574 int rc = 0;
3575
3576 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
3577 netdev_err(dev, "Invalid microcode file size: %u\n",
3578 (unsigned int)fw_size);
3579 return -EINVAL;
3580 }
3581 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
3582 sizeof(*trailer)));
3583 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
3584 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
3585 le32_to_cpu(trailer->sig));
3586 return -EINVAL;
3587 }
3588 if (le16_to_cpu(trailer->dir_type) != dir_type) {
3589 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
3590 dir_type, le16_to_cpu(trailer->dir_type));
3591 return -EINVAL;
3592 }
3593 if (le16_to_cpu(trailer->trailer_length) <
3594 sizeof(struct bnxt_ucode_trailer)) {
3595 netdev_err(dev, "Invalid microcode trailer length: %d\n",
3596 le16_to_cpu(trailer->trailer_length));
3597 return -EINVAL;
3598 }
3599
3600 /* Confirm the CRC32 checksum of the file: */
3601 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3602 sizeof(stored_crc)));
3603 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3604 if (calculated_crc != stored_crc) {
3605 netdev_err(dev,
3606 "CRC32 (%08lX) does not match calculated: %08lX\n",
3607 (unsigned long)stored_crc,
3608 (unsigned long)calculated_crc);
3609 return -EINVAL;
3610 }
3611 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3612 0, 0, 0, fw_data, fw_size);
3613
3614 return rc;
3615 }
3616
bnxt_dir_type_is_ape_bin_format(u16 dir_type)3617 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
3618 {
3619 switch (dir_type) {
3620 case BNX_DIR_TYPE_CHIMP_PATCH:
3621 case BNX_DIR_TYPE_BOOTCODE:
3622 case BNX_DIR_TYPE_BOOTCODE_2:
3623 case BNX_DIR_TYPE_APE_FW:
3624 case BNX_DIR_TYPE_APE_PATCH:
3625 case BNX_DIR_TYPE_KONG_FW:
3626 case BNX_DIR_TYPE_KONG_PATCH:
3627 case BNX_DIR_TYPE_BONO_FW:
3628 case BNX_DIR_TYPE_BONO_PATCH:
3629 return true;
3630 }
3631
3632 return false;
3633 }
3634
bnxt_dir_type_is_other_exec_format(u16 dir_type)3635 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
3636 {
3637 switch (dir_type) {
3638 case BNX_DIR_TYPE_AVS:
3639 case BNX_DIR_TYPE_EXP_ROM_MBA:
3640 case BNX_DIR_TYPE_PCIE:
3641 case BNX_DIR_TYPE_TSCF_UCODE:
3642 case BNX_DIR_TYPE_EXT_PHY:
3643 case BNX_DIR_TYPE_CCM:
3644 case BNX_DIR_TYPE_ISCSI_BOOT:
3645 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3646 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3647 return true;
3648 }
3649
3650 return false;
3651 }
3652
bnxt_dir_type_is_executable(u16 dir_type)3653 static bool bnxt_dir_type_is_executable(u16 dir_type)
3654 {
3655 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3656 bnxt_dir_type_is_other_exec_format(dir_type);
3657 }
3658
bnxt_flash_firmware_from_file(struct net_device * dev,u16 dir_type,const char * filename)3659 static int bnxt_flash_firmware_from_file(struct net_device *dev,
3660 u16 dir_type,
3661 const char *filename)
3662 {
3663 const struct firmware *fw;
3664 int rc;
3665
3666 rc = request_firmware(&fw, filename, &dev->dev);
3667 if (rc != 0) {
3668 netdev_err(dev, "Error %d requesting firmware file: %s\n",
3669 rc, filename);
3670 return rc;
3671 }
3672 if (bnxt_dir_type_is_ape_bin_format(dir_type))
3673 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
3674 else if (bnxt_dir_type_is_other_exec_format(dir_type))
3675 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
3676 else
3677 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3678 0, 0, 0, fw->data, fw->size);
3679 release_firmware(fw);
3680 return rc;
3681 }
3682
3683 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
3684 #define MSG_INVALID_PKG "PKG install error : Invalid package"
3685 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
3686 #define MSG_INVALID_DEV "PKG install error : Invalid device"
3687 #define MSG_INTERNAL_ERR "PKG install error : Internal error"
3688 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
3689 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
3690 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error"
3691 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
3692 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
3693
nvm_update_err_to_stderr(struct net_device * dev,u8 result,struct netlink_ext_ack * extack)3694 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
3695 struct netlink_ext_ack *extack)
3696 {
3697 switch (result) {
3698 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
3699 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
3700 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
3701 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
3702 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
3703 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
3704 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
3705 return -EINVAL;
3706 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
3707 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
3708 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
3709 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
3710 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
3711 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
3712 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
3713 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
3714 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
3715 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
3716 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
3717 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
3718 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
3719 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
3720 return -ENOPKG;
3721 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
3722 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
3723 return -EPERM;
3724 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
3725 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
3726 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
3727 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
3728 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
3729 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
3730 return -EOPNOTSUPP;
3731 default:
3732 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
3733 return -EIO;
3734 }
3735 }
3736
3737 #define BNXT_PKG_DMA_SIZE 0x40000
3738 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
3739 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
3740
bnxt_resize_update_entry(struct net_device * dev,size_t fw_size,struct netlink_ext_ack * extack)3741 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size,
3742 struct netlink_ext_ack *extack)
3743 {
3744 u32 item_len;
3745 int rc;
3746
3747 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3748 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL,
3749 &item_len, NULL);
3750 if (rc) {
3751 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3752 return rc;
3753 }
3754
3755 if (fw_size > item_len) {
3756 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE,
3757 BNX_DIR_ORDINAL_FIRST, 0, 1,
3758 round_up(fw_size, 4096), NULL, 0);
3759 if (rc) {
3760 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR);
3761 return rc;
3762 }
3763 }
3764 return 0;
3765 }
3766
bnxt_flash_package_from_fw_obj(struct net_device * dev,const struct firmware * fw,u32 install_type,struct netlink_ext_ack * extack)3767 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
3768 u32 install_type, struct netlink_ext_ack *extack)
3769 {
3770 struct hwrm_nvm_install_update_input *install;
3771 struct hwrm_nvm_install_update_output *resp;
3772 struct hwrm_nvm_modify_input *modify;
3773 struct bnxt *bp = netdev_priv(dev);
3774 bool defrag_attempted = false;
3775 dma_addr_t dma_handle;
3776 u8 *kmem = NULL;
3777 u32 modify_len;
3778 u32 item_len;
3779 u8 cmd_err;
3780 u16 index;
3781 int rc;
3782
3783 /* resize before flashing larger image than available space */
3784 rc = bnxt_resize_update_entry(dev, fw->size, extack);
3785 if (rc)
3786 return rc;
3787
3788 bnxt_hwrm_fw_set_time(bp);
3789
3790 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
3791 if (rc)
3792 return rc;
3793
3794 /* Try allocating a large DMA buffer first. Older fw will
3795 * cause excessive NVRAM erases when using small blocks.
3796 */
3797 modify_len = roundup_pow_of_two(fw->size);
3798 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
3799 while (1) {
3800 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
3801 if (!kmem && modify_len > PAGE_SIZE)
3802 modify_len /= 2;
3803 else
3804 break;
3805 }
3806 if (!kmem) {
3807 hwrm_req_drop(bp, modify);
3808 return -ENOMEM;
3809 }
3810
3811 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
3812 if (rc) {
3813 hwrm_req_drop(bp, modify);
3814 return rc;
3815 }
3816
3817 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
3818 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
3819
3820 hwrm_req_hold(bp, modify);
3821 modify->host_src_addr = cpu_to_le64(dma_handle);
3822
3823 resp = hwrm_req_hold(bp, install);
3824 if ((install_type & 0xffff) == 0)
3825 install_type >>= 16;
3826 install->install_type = cpu_to_le32(install_type);
3827
3828 do {
3829 u32 copied = 0, len = modify_len;
3830
3831 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3832 BNX_DIR_ORDINAL_FIRST,
3833 BNX_DIR_EXT_NONE,
3834 &index, &item_len, NULL);
3835 if (rc) {
3836 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3837 break;
3838 }
3839 if (fw->size > item_len) {
3840 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
3841 rc = -EFBIG;
3842 break;
3843 }
3844
3845 modify->dir_idx = cpu_to_le16(index);
3846
3847 if (fw->size > modify_len)
3848 modify->flags = BNXT_NVM_MORE_FLAG;
3849 while (copied < fw->size) {
3850 u32 balance = fw->size - copied;
3851
3852 if (balance <= modify_len) {
3853 len = balance;
3854 if (copied)
3855 modify->flags |= BNXT_NVM_LAST_FLAG;
3856 }
3857 memcpy(kmem, fw->data + copied, len);
3858 modify->len = cpu_to_le32(len);
3859 modify->offset = cpu_to_le32(copied);
3860 rc = hwrm_req_send(bp, modify);
3861 if (rc)
3862 goto pkg_abort;
3863 copied += len;
3864 }
3865
3866 rc = hwrm_req_send_silent(bp, install);
3867 if (!rc)
3868 break;
3869
3870 if (defrag_attempted) {
3871 /* We have tried to defragment already in the previous
3872 * iteration. Return with the result for INSTALL_UPDATE
3873 */
3874 break;
3875 }
3876
3877 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3878
3879 switch (cmd_err) {
3880 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
3881 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
3882 rc = -EALREADY;
3883 break;
3884 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
3885 install->flags =
3886 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
3887
3888 rc = hwrm_req_send_silent(bp, install);
3889 if (!rc)
3890 break;
3891
3892 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3893
3894 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
3895 /* FW has cleared NVM area, driver will create
3896 * UPDATE directory and try the flash again
3897 */
3898 defrag_attempted = true;
3899 install->flags = 0;
3900 rc = bnxt_flash_nvram(bp->dev,
3901 BNX_DIR_TYPE_UPDATE,
3902 BNX_DIR_ORDINAL_FIRST,
3903 0, 0, item_len, NULL, 0);
3904 if (!rc)
3905 break;
3906 }
3907 fallthrough;
3908 default:
3909 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
3910 }
3911 } while (defrag_attempted && !rc);
3912
3913 pkg_abort:
3914 hwrm_req_drop(bp, modify);
3915 hwrm_req_drop(bp, install);
3916
3917 if (resp->result) {
3918 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
3919 (s8)resp->result, (int)resp->problem_item);
3920 rc = nvm_update_err_to_stderr(dev, resp->result, extack);
3921 }
3922 if (rc == -EACCES)
3923 bnxt_print_admin_err(bp);
3924 return rc;
3925 }
3926
bnxt_flash_package_from_file(struct net_device * dev,const char * filename,u32 install_type,struct netlink_ext_ack * extack)3927 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
3928 u32 install_type, struct netlink_ext_ack *extack)
3929 {
3930 const struct firmware *fw;
3931 int rc;
3932
3933 rc = request_firmware(&fw, filename, &dev->dev);
3934 if (rc != 0) {
3935 netdev_err(dev, "PKG error %d requesting file: %s\n",
3936 rc, filename);
3937 return rc;
3938 }
3939
3940 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
3941
3942 release_firmware(fw);
3943
3944 return rc;
3945 }
3946
bnxt_flash_device(struct net_device * dev,struct ethtool_flash * flash)3947 static int bnxt_flash_device(struct net_device *dev,
3948 struct ethtool_flash *flash)
3949 {
3950 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
3951 netdev_err(dev, "flashdev not supported from a virtual function\n");
3952 return -EINVAL;
3953 }
3954
3955 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
3956 flash->region > 0xffff)
3957 return bnxt_flash_package_from_file(dev, flash->data,
3958 flash->region, NULL);
3959
3960 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
3961 }
3962
nvm_get_dir_info(struct net_device * dev,u32 * entries,u32 * length)3963 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
3964 {
3965 struct hwrm_nvm_get_dir_info_output *output;
3966 struct hwrm_nvm_get_dir_info_input *req;
3967 struct bnxt *bp = netdev_priv(dev);
3968 int rc;
3969
3970 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
3971 if (rc)
3972 return rc;
3973
3974 output = hwrm_req_hold(bp, req);
3975 rc = hwrm_req_send(bp, req);
3976 if (!rc) {
3977 *entries = le32_to_cpu(output->entries);
3978 *length = le32_to_cpu(output->entry_length);
3979 }
3980 hwrm_req_drop(bp, req);
3981 return rc;
3982 }
3983
bnxt_get_eeprom_len(struct net_device * dev)3984 static int bnxt_get_eeprom_len(struct net_device *dev)
3985 {
3986 struct bnxt *bp = netdev_priv(dev);
3987
3988 if (BNXT_VF(bp))
3989 return 0;
3990
3991 /* The -1 return value allows the entire 32-bit range of offsets to be
3992 * passed via the ethtool command-line utility.
3993 */
3994 return -1;
3995 }
3996
bnxt_get_nvram_directory(struct net_device * dev,u32 len,u8 * data)3997 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
3998 {
3999 struct bnxt *bp = netdev_priv(dev);
4000 int rc;
4001 u32 dir_entries;
4002 u32 entry_length;
4003 u8 *buf;
4004 size_t buflen;
4005 dma_addr_t dma_handle;
4006 struct hwrm_nvm_get_dir_entries_input *req;
4007
4008 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
4009 if (rc != 0)
4010 return rc;
4011
4012 if (!dir_entries || !entry_length)
4013 return -EIO;
4014
4015 /* Insert 2 bytes of directory info (count and size of entries) */
4016 if (len < 2)
4017 return -EINVAL;
4018
4019 *data++ = dir_entries;
4020 *data++ = entry_length;
4021 len -= 2;
4022 memset(data, 0xff, len);
4023
4024 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
4025 if (rc)
4026 return rc;
4027
4028 buflen = mul_u32_u32(dir_entries, entry_length);
4029 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
4030 if (!buf) {
4031 hwrm_req_drop(bp, req);
4032 return -ENOMEM;
4033 }
4034 req->host_dest_addr = cpu_to_le64(dma_handle);
4035
4036 hwrm_req_hold(bp, req); /* hold the slice */
4037 rc = hwrm_req_send(bp, req);
4038 if (rc == 0)
4039 memcpy(data, buf, len > buflen ? buflen : len);
4040 hwrm_req_drop(bp, req);
4041 return rc;
4042 }
4043
bnxt_get_nvram_item(struct net_device * dev,u32 index,u32 offset,u32 length,u8 * data)4044 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
4045 u32 length, u8 *data)
4046 {
4047 struct bnxt *bp = netdev_priv(dev);
4048 int rc;
4049 u8 *buf;
4050 dma_addr_t dma_handle;
4051 struct hwrm_nvm_read_input *req;
4052
4053 if (!length)
4054 return -EINVAL;
4055
4056 rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
4057 if (rc)
4058 return rc;
4059
4060 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
4061 if (!buf) {
4062 hwrm_req_drop(bp, req);
4063 return -ENOMEM;
4064 }
4065
4066 req->host_dest_addr = cpu_to_le64(dma_handle);
4067 req->dir_idx = cpu_to_le16(index);
4068 req->offset = cpu_to_le32(offset);
4069 req->len = cpu_to_le32(length);
4070
4071 hwrm_req_hold(bp, req); /* hold the slice */
4072 rc = hwrm_req_send(bp, req);
4073 if (rc == 0)
4074 memcpy(data, buf, length);
4075 hwrm_req_drop(bp, req);
4076 return rc;
4077 }
4078
bnxt_find_nvram_item(struct net_device * dev,u16 type,u16 ordinal,u16 ext,u16 * index,u32 * item_length,u32 * data_length)4079 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
4080 u16 ext, u16 *index, u32 *item_length,
4081 u32 *data_length)
4082 {
4083 struct hwrm_nvm_find_dir_entry_output *output;
4084 struct hwrm_nvm_find_dir_entry_input *req;
4085 struct bnxt *bp = netdev_priv(dev);
4086 int rc;
4087
4088 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
4089 if (rc)
4090 return rc;
4091
4092 req->enables = 0;
4093 req->dir_idx = 0;
4094 req->dir_type = cpu_to_le16(type);
4095 req->dir_ordinal = cpu_to_le16(ordinal);
4096 req->dir_ext = cpu_to_le16(ext);
4097 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
4098 output = hwrm_req_hold(bp, req);
4099 rc = hwrm_req_send_silent(bp, req);
4100 if (rc == 0) {
4101 if (index)
4102 *index = le16_to_cpu(output->dir_idx);
4103 if (item_length)
4104 *item_length = le32_to_cpu(output->dir_item_length);
4105 if (data_length)
4106 *data_length = le32_to_cpu(output->dir_data_length);
4107 }
4108 hwrm_req_drop(bp, req);
4109 return rc;
4110 }
4111
bnxt_parse_pkglog(int desired_field,u8 * data,size_t datalen)4112 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
4113 {
4114 char *retval = NULL;
4115 char *p;
4116 char *value;
4117 int field = 0;
4118
4119 if (datalen < 1)
4120 return NULL;
4121 /* null-terminate the log data (removing last '\n'): */
4122 data[datalen - 1] = 0;
4123 for (p = data; *p != 0; p++) {
4124 field = 0;
4125 retval = NULL;
4126 while (*p != 0 && *p != '\n') {
4127 value = p;
4128 while (*p != 0 && *p != '\t' && *p != '\n')
4129 p++;
4130 if (field == desired_field)
4131 retval = value;
4132 if (*p != '\t')
4133 break;
4134 *p = 0;
4135 field++;
4136 p++;
4137 }
4138 if (*p == 0)
4139 break;
4140 *p = 0;
4141 }
4142 return retval;
4143 }
4144
bnxt_get_pkginfo(struct net_device * dev,char * ver,int size)4145 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
4146 {
4147 struct bnxt *bp = netdev_priv(dev);
4148 u16 index = 0;
4149 char *pkgver;
4150 u32 pkglen;
4151 u8 *pkgbuf;
4152 int rc;
4153
4154 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
4155 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
4156 &index, NULL, &pkglen);
4157 if (rc)
4158 return rc;
4159
4160 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
4161 if (!pkgbuf) {
4162 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
4163 pkglen);
4164 return -ENOMEM;
4165 }
4166
4167 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
4168 if (rc)
4169 goto err;
4170
4171 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
4172 pkglen);
4173 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
4174 strscpy(ver, pkgver, size);
4175 else
4176 rc = -ENOENT;
4177
4178 err:
4179 kfree(pkgbuf);
4180
4181 return rc;
4182 }
4183
bnxt_get_pkgver(struct net_device * dev)4184 static void bnxt_get_pkgver(struct net_device *dev)
4185 {
4186 struct bnxt *bp = netdev_priv(dev);
4187 char buf[FW_VER_STR_LEN - 5];
4188 int len;
4189
4190 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
4191 len = strlen(bp->fw_ver_str);
4192 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len,
4193 "/pkg %s", buf);
4194 }
4195 }
4196
bnxt_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)4197 static int bnxt_get_eeprom(struct net_device *dev,
4198 struct ethtool_eeprom *eeprom,
4199 u8 *data)
4200 {
4201 u32 index;
4202 u32 offset;
4203
4204 if (eeprom->offset == 0) /* special offset value to get directory */
4205 return bnxt_get_nvram_directory(dev, eeprom->len, data);
4206
4207 index = eeprom->offset >> 24;
4208 offset = eeprom->offset & 0xffffff;
4209
4210 if (index == 0) {
4211 netdev_err(dev, "unsupported index value: %d\n", index);
4212 return -EINVAL;
4213 }
4214
4215 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
4216 }
4217
bnxt_erase_nvram_directory(struct net_device * dev,u8 index)4218 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
4219 {
4220 struct hwrm_nvm_erase_dir_entry_input *req;
4221 struct bnxt *bp = netdev_priv(dev);
4222 int rc;
4223
4224 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
4225 if (rc)
4226 return rc;
4227
4228 req->dir_idx = cpu_to_le16(index);
4229 return hwrm_req_send(bp, req);
4230 }
4231
bnxt_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)4232 static int bnxt_set_eeprom(struct net_device *dev,
4233 struct ethtool_eeprom *eeprom,
4234 u8 *data)
4235 {
4236 struct bnxt *bp = netdev_priv(dev);
4237 u8 index, dir_op;
4238 u16 type, ext, ordinal, attr;
4239
4240 if (!BNXT_PF(bp)) {
4241 netdev_err(dev, "NVM write not supported from a virtual function\n");
4242 return -EINVAL;
4243 }
4244
4245 type = eeprom->magic >> 16;
4246
4247 if (type == 0xffff) { /* special value for directory operations */
4248 index = eeprom->magic & 0xff;
4249 dir_op = eeprom->magic >> 8;
4250 if (index == 0)
4251 return -EINVAL;
4252 switch (dir_op) {
4253 case 0x0e: /* erase */
4254 if (eeprom->offset != ~eeprom->magic)
4255 return -EINVAL;
4256 return bnxt_erase_nvram_directory(dev, index - 1);
4257 default:
4258 return -EINVAL;
4259 }
4260 }
4261
4262 /* Create or re-write an NVM item: */
4263 if (bnxt_dir_type_is_executable(type))
4264 return -EOPNOTSUPP;
4265 ext = eeprom->magic & 0xffff;
4266 ordinal = eeprom->offset >> 16;
4267 attr = eeprom->offset & 0xffff;
4268
4269 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
4270 eeprom->len);
4271 }
4272
bnxt_set_eee(struct net_device * dev,struct ethtool_keee * edata)4273 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata)
4274 {
4275 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
4276 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp);
4277 struct bnxt *bp = netdev_priv(dev);
4278 struct ethtool_keee *eee = &bp->eee;
4279 struct bnxt_link_info *link_info = &bp->link_info;
4280 int rc = 0;
4281
4282 if (!BNXT_PHY_CFG_ABLE(bp))
4283 return -EOPNOTSUPP;
4284
4285 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4286 return -EOPNOTSUPP;
4287
4288 mutex_lock(&bp->link_lock);
4289 _bnxt_fw_to_linkmode(advertising, link_info->advertising);
4290 if (!edata->eee_enabled)
4291 goto eee_ok;
4292
4293 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4294 netdev_warn(dev, "EEE requires autoneg\n");
4295 rc = -EINVAL;
4296 goto eee_exit;
4297 }
4298 if (edata->tx_lpi_enabled) {
4299 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
4300 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
4301 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
4302 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
4303 rc = -EINVAL;
4304 goto eee_exit;
4305 } else if (!bp->lpi_tmr_hi) {
4306 edata->tx_lpi_timer = eee->tx_lpi_timer;
4307 }
4308 }
4309 if (linkmode_empty(edata->advertised)) {
4310 linkmode_and(edata->advertised, advertising, eee->supported);
4311 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) {
4312 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n");
4313 rc = -EINVAL;
4314 goto eee_exit;
4315 }
4316
4317 linkmode_copy(eee->advertised, edata->advertised);
4318 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
4319 eee->tx_lpi_timer = edata->tx_lpi_timer;
4320 eee_ok:
4321 eee->eee_enabled = edata->eee_enabled;
4322
4323 if (netif_running(dev))
4324 rc = bnxt_hwrm_set_link_setting(bp, false, true);
4325
4326 eee_exit:
4327 mutex_unlock(&bp->link_lock);
4328 return rc;
4329 }
4330
bnxt_get_eee(struct net_device * dev,struct ethtool_keee * edata)4331 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata)
4332 {
4333 struct bnxt *bp = netdev_priv(dev);
4334
4335 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4336 return -EOPNOTSUPP;
4337
4338 *edata = bp->eee;
4339 if (!bp->eee.eee_enabled) {
4340 /* Preserve tx_lpi_timer so that the last value will be used
4341 * by default when it is re-enabled.
4342 */
4343 linkmode_zero(edata->advertised);
4344 edata->tx_lpi_enabled = 0;
4345 }
4346
4347 if (!bp->eee.eee_active)
4348 linkmode_zero(edata->lp_advertised);
4349
4350 return 0;
4351 }
4352
bnxt_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)4353 static int bnxt_set_tunable(struct net_device *dev,
4354 const struct ethtool_tunable *tuna,
4355 const void *data)
4356 {
4357 struct bnxt *bp = netdev_priv(dev);
4358 u32 rx_copybreak;
4359
4360 switch (tuna->id) {
4361 case ETHTOOL_RX_COPYBREAK:
4362 rx_copybreak = *(u32 *)data;
4363 if (rx_copybreak > BNXT_MAX_RX_COPYBREAK)
4364 return -ERANGE;
4365 if (rx_copybreak != bp->rx_copybreak) {
4366 if (netif_running(dev))
4367 return -EBUSY;
4368 bp->rx_copybreak = rx_copybreak;
4369 }
4370 return 0;
4371 default:
4372 return -EOPNOTSUPP;
4373 }
4374 }
4375
bnxt_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)4376 static int bnxt_get_tunable(struct net_device *dev,
4377 const struct ethtool_tunable *tuna, void *data)
4378 {
4379 struct bnxt *bp = netdev_priv(dev);
4380
4381 switch (tuna->id) {
4382 case ETHTOOL_RX_COPYBREAK:
4383 *(u32 *)data = bp->rx_copybreak;
4384 break;
4385 default:
4386 return -EOPNOTSUPP;
4387 }
4388
4389 return 0;
4390 }
4391
bnxt_read_sfp_module_eeprom_info(struct bnxt * bp,u16 i2c_addr,u16 page_number,u8 bank,u16 start_addr,u16 data_length,u8 * buf)4392 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
4393 u16 page_number, u8 bank,
4394 u16 start_addr, u16 data_length,
4395 u8 *buf)
4396 {
4397 struct hwrm_port_phy_i2c_read_output *output;
4398 struct hwrm_port_phy_i2c_read_input *req;
4399 int rc, byte_offset = 0;
4400
4401 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
4402 if (rc)
4403 return rc;
4404
4405 output = hwrm_req_hold(bp, req);
4406 req->i2c_slave_addr = i2c_addr;
4407 req->page_number = cpu_to_le16(page_number);
4408 req->port_id = cpu_to_le16(bp->pf.port_id);
4409 do {
4410 u16 xfer_size;
4411
4412 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
4413 data_length -= xfer_size;
4414 req->page_offset = cpu_to_le16(start_addr + byte_offset);
4415 req->data_length = xfer_size;
4416 req->enables =
4417 cpu_to_le32((start_addr + byte_offset ?
4418 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET :
4419 0) |
4420 (bank ?
4421 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER :
4422 0));
4423 rc = hwrm_req_send(bp, req);
4424 if (!rc)
4425 memcpy(buf + byte_offset, output->data, xfer_size);
4426 byte_offset += xfer_size;
4427 } while (!rc && data_length > 0);
4428 hwrm_req_drop(bp, req);
4429
4430 return rc;
4431 }
4432
bnxt_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)4433 static int bnxt_get_module_info(struct net_device *dev,
4434 struct ethtool_modinfo *modinfo)
4435 {
4436 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
4437 struct bnxt *bp = netdev_priv(dev);
4438 int rc;
4439
4440 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4441 return -EPERM;
4442
4443 /* No point in going further if phy status indicates
4444 * module is not inserted or if it is powered down or
4445 * if it is of type 10GBase-T
4446 */
4447 if (bp->link_info.module_status >
4448 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4449 return -EOPNOTSUPP;
4450
4451 /* This feature is not supported in older firmware versions */
4452 if (bp->hwrm_spec_code < 0x10202)
4453 return -EOPNOTSUPP;
4454
4455 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0,
4456 SFF_DIAG_SUPPORT_OFFSET + 1,
4457 data);
4458 if (!rc) {
4459 u8 module_id = data[0];
4460 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
4461
4462 switch (module_id) {
4463 case SFF_MODULE_ID_SFP:
4464 modinfo->type = ETH_MODULE_SFF_8472;
4465 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
4466 if (!diag_supported)
4467 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4468 break;
4469 case SFF_MODULE_ID_QSFP:
4470 case SFF_MODULE_ID_QSFP_PLUS:
4471 modinfo->type = ETH_MODULE_SFF_8436;
4472 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4473 break;
4474 case SFF_MODULE_ID_QSFP28:
4475 modinfo->type = ETH_MODULE_SFF_8636;
4476 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
4477 break;
4478 default:
4479 rc = -EOPNOTSUPP;
4480 break;
4481 }
4482 }
4483 return rc;
4484 }
4485
bnxt_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)4486 static int bnxt_get_module_eeprom(struct net_device *dev,
4487 struct ethtool_eeprom *eeprom,
4488 u8 *data)
4489 {
4490 struct bnxt *bp = netdev_priv(dev);
4491 u16 start = eeprom->offset, length = eeprom->len;
4492 int rc = 0;
4493
4494 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4495 return -EPERM;
4496
4497 memset(data, 0, eeprom->len);
4498
4499 /* Read A0 portion of the EEPROM */
4500 if (start < ETH_MODULE_SFF_8436_LEN) {
4501 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
4502 length = ETH_MODULE_SFF_8436_LEN - start;
4503 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
4504 start, length, data);
4505 if (rc)
4506 return rc;
4507 start += length;
4508 data += length;
4509 length = eeprom->len - length;
4510 }
4511
4512 /* Read A2 portion of the EEPROM */
4513 if (length) {
4514 start -= ETH_MODULE_SFF_8436_LEN;
4515 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0,
4516 start, length, data);
4517 }
4518 return rc;
4519 }
4520
bnxt_get_module_status(struct bnxt * bp,struct netlink_ext_ack * extack)4521 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack)
4522 {
4523 if (bp->link_info.module_status <=
4524 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4525 return 0;
4526
4527 switch (bp->link_info.module_status) {
4528 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4529 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down");
4530 break;
4531 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED:
4532 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted");
4533 break;
4534 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT:
4535 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault");
4536 break;
4537 default:
4538 NL_SET_ERR_MSG_MOD(extack, "Unknown error");
4539 break;
4540 }
4541 return -EINVAL;
4542 }
4543
bnxt_get_module_eeprom_by_page(struct net_device * dev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)4544 static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4545 const struct ethtool_module_eeprom *page_data,
4546 struct netlink_ext_ack *extack)
4547 {
4548 struct bnxt *bp = netdev_priv(dev);
4549 int rc;
4550
4551 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
4552 NL_SET_ERR_MSG_MOD(extack,
4553 "Module read not permitted on untrusted VF");
4554 return -EPERM;
4555 }
4556
4557 rc = bnxt_get_module_status(bp, extack);
4558 if (rc)
4559 return rc;
4560
4561 if (bp->hwrm_spec_code < 0x10202) {
4562 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old");
4563 return -EINVAL;
4564 }
4565
4566 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {
4567 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
4568 return -EINVAL;
4569 }
4570
4571 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
4572 page_data->page, page_data->bank,
4573 page_data->offset,
4574 page_data->length,
4575 page_data->data);
4576 if (rc) {
4577 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
4578 return rc;
4579 }
4580 return page_data->length;
4581 }
4582
bnxt_nway_reset(struct net_device * dev)4583 static int bnxt_nway_reset(struct net_device *dev)
4584 {
4585 int rc = 0;
4586
4587 struct bnxt *bp = netdev_priv(dev);
4588 struct bnxt_link_info *link_info = &bp->link_info;
4589
4590 if (!BNXT_PHY_CFG_ABLE(bp))
4591 return -EOPNOTSUPP;
4592
4593 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
4594 return -EINVAL;
4595
4596 if (netif_running(dev))
4597 rc = bnxt_hwrm_set_link_setting(bp, true, false);
4598
4599 return rc;
4600 }
4601
bnxt_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)4602 static int bnxt_set_phys_id(struct net_device *dev,
4603 enum ethtool_phys_id_state state)
4604 {
4605 struct hwrm_port_led_cfg_input *req;
4606 struct bnxt *bp = netdev_priv(dev);
4607 struct bnxt_pf_info *pf = &bp->pf;
4608 struct bnxt_led_cfg *led_cfg;
4609 u8 led_state;
4610 __le16 duration;
4611 int rc, i;
4612
4613 if (!bp->num_leds || BNXT_VF(bp))
4614 return -EOPNOTSUPP;
4615
4616 if (state == ETHTOOL_ID_ACTIVE) {
4617 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
4618 duration = cpu_to_le16(500);
4619 } else if (state == ETHTOOL_ID_INACTIVE) {
4620 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
4621 duration = cpu_to_le16(0);
4622 } else {
4623 return -EINVAL;
4624 }
4625 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
4626 if (rc)
4627 return rc;
4628
4629 req->port_id = cpu_to_le16(pf->port_id);
4630 req->num_leds = bp->num_leds;
4631 led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
4632 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
4633 req->enables |= BNXT_LED_DFLT_ENABLES(i);
4634 led_cfg->led_id = bp->leds[i].led_id;
4635 led_cfg->led_state = led_state;
4636 led_cfg->led_blink_on = duration;
4637 led_cfg->led_blink_off = duration;
4638 led_cfg->led_group_id = bp->leds[i].led_group_id;
4639 }
4640 return hwrm_req_send(bp, req);
4641 }
4642
bnxt_hwrm_selftest_irq(struct bnxt * bp,u16 cmpl_ring)4643 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
4644 {
4645 struct hwrm_selftest_irq_input *req;
4646 int rc;
4647
4648 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
4649 if (rc)
4650 return rc;
4651
4652 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4653 return hwrm_req_send(bp, req);
4654 }
4655
bnxt_test_irq(struct bnxt * bp)4656 static int bnxt_test_irq(struct bnxt *bp)
4657 {
4658 int i;
4659
4660 for (i = 0; i < bp->cp_nr_rings; i++) {
4661 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
4662 int rc;
4663
4664 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
4665 if (rc)
4666 return rc;
4667 }
4668 return 0;
4669 }
4670
bnxt_hwrm_mac_loopback(struct bnxt * bp,bool enable)4671 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
4672 {
4673 struct hwrm_port_mac_cfg_input *req;
4674 int rc;
4675
4676 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
4677 if (rc)
4678 return rc;
4679
4680 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
4681 if (enable)
4682 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
4683 else
4684 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
4685 return hwrm_req_send(bp, req);
4686 }
4687
bnxt_query_force_speeds(struct bnxt * bp,u16 * force_speeds)4688 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
4689 {
4690 struct hwrm_port_phy_qcaps_output *resp;
4691 struct hwrm_port_phy_qcaps_input *req;
4692 int rc;
4693
4694 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
4695 if (rc)
4696 return rc;
4697
4698 resp = hwrm_req_hold(bp, req);
4699 rc = hwrm_req_send(bp, req);
4700 if (!rc)
4701 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
4702
4703 hwrm_req_drop(bp, req);
4704 return rc;
4705 }
4706
bnxt_disable_an_for_lpbk(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)4707 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
4708 struct hwrm_port_phy_cfg_input *req)
4709 {
4710 struct bnxt_link_info *link_info = &bp->link_info;
4711 u16 fw_advertising;
4712 u16 fw_speed;
4713 int rc;
4714
4715 if (!link_info->autoneg ||
4716 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
4717 return 0;
4718
4719 rc = bnxt_query_force_speeds(bp, &fw_advertising);
4720 if (rc)
4721 return rc;
4722
4723 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
4724 if (BNXT_LINK_IS_UP(bp))
4725 fw_speed = bp->link_info.link_speed;
4726 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
4727 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
4728 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
4729 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
4730 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
4731 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
4732 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
4733 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
4734
4735 req->force_link_speed = cpu_to_le16(fw_speed);
4736 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
4737 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4738 rc = hwrm_req_send(bp, req);
4739 req->flags = 0;
4740 req->force_link_speed = cpu_to_le16(0);
4741 return rc;
4742 }
4743
bnxt_hwrm_phy_loopback(struct bnxt * bp,bool enable,bool ext)4744 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
4745 {
4746 struct hwrm_port_phy_cfg_input *req;
4747 int rc;
4748
4749 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
4750 if (rc)
4751 return rc;
4752
4753 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */
4754 hwrm_req_hold(bp, req);
4755
4756 if (enable) {
4757 bnxt_disable_an_for_lpbk(bp, req);
4758 if (ext)
4759 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
4760 else
4761 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
4762 } else {
4763 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
4764 }
4765 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
4766 rc = hwrm_req_send(bp, req);
4767 hwrm_req_drop(bp, req);
4768 return rc;
4769 }
4770
bnxt_rx_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u32 raw_cons,int pkt_size)4771 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4772 u32 raw_cons, int pkt_size)
4773 {
4774 struct bnxt_napi *bnapi = cpr->bnapi;
4775 struct bnxt_rx_ring_info *rxr;
4776 struct bnxt_sw_rx_bd *rx_buf;
4777 struct rx_cmp *rxcmp;
4778 u16 cp_cons, cons;
4779 u8 *data;
4780 u32 len;
4781 int i;
4782
4783 rxr = bnapi->rx_ring;
4784 cp_cons = RING_CMP(raw_cons);
4785 rxcmp = (struct rx_cmp *)
4786 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
4787 cons = rxcmp->rx_cmp_opaque;
4788 rx_buf = &rxr->rx_buf_ring[cons];
4789 data = rx_buf->data_ptr;
4790 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
4791 if (len != pkt_size)
4792 return -EIO;
4793 i = ETH_ALEN;
4794 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
4795 return -EIO;
4796 i += ETH_ALEN;
4797 for ( ; i < pkt_size; i++) {
4798 if (data[i] != (u8)(i & 0xff))
4799 return -EIO;
4800 }
4801 return 0;
4802 }
4803
bnxt_poll_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,int pkt_size)4804 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4805 int pkt_size)
4806 {
4807 struct tx_cmp *txcmp;
4808 int rc = -EIO;
4809 u32 raw_cons;
4810 u32 cons;
4811 int i;
4812
4813 raw_cons = cpr->cp_raw_cons;
4814 for (i = 0; i < 200; i++) {
4815 cons = RING_CMP(raw_cons);
4816 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
4817
4818 if (!TX_CMP_VALID(txcmp, raw_cons)) {
4819 udelay(5);
4820 continue;
4821 }
4822
4823 /* The valid test of the entry must be done first before
4824 * reading any further.
4825 */
4826 dma_rmb();
4827 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP ||
4828 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) {
4829 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
4830 raw_cons = NEXT_RAW_CMP(raw_cons);
4831 raw_cons = NEXT_RAW_CMP(raw_cons);
4832 break;
4833 }
4834 raw_cons = NEXT_RAW_CMP(raw_cons);
4835 }
4836 cpr->cp_raw_cons = raw_cons;
4837 return rc;
4838 }
4839
bnxt_run_loopback(struct bnxt * bp)4840 static int bnxt_run_loopback(struct bnxt *bp)
4841 {
4842 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
4843 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4844 struct bnxt_cp_ring_info *cpr;
4845 int pkt_size, i = 0;
4846 struct sk_buff *skb;
4847 dma_addr_t map;
4848 u8 *data;
4849 int rc;
4850
4851 cpr = &rxr->bnapi->cp_ring;
4852 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
4853 cpr = rxr->rx_cpr;
4854 pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_DEFAULT_RX_COPYBREAK,
4855 bp->rx_copybreak));
4856 skb = netdev_alloc_skb(bp->dev, pkt_size);
4857 if (!skb)
4858 return -ENOMEM;
4859 data = skb_put(skb, pkt_size);
4860 ether_addr_copy(&data[i], bp->dev->dev_addr);
4861 i += ETH_ALEN;
4862 ether_addr_copy(&data[i], bp->dev->dev_addr);
4863 i += ETH_ALEN;
4864 for ( ; i < pkt_size; i++)
4865 data[i] = (u8)(i & 0xff);
4866
4867 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
4868 DMA_TO_DEVICE);
4869 if (dma_mapping_error(&bp->pdev->dev, map)) {
4870 dev_kfree_skb(skb);
4871 return -EIO;
4872 }
4873 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
4874
4875 /* Sync BD data before updating doorbell */
4876 wmb();
4877
4878 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
4879 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
4880
4881 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
4882 dev_kfree_skb(skb);
4883 return rc;
4884 }
4885
bnxt_run_fw_tests(struct bnxt * bp,u8 test_mask,u8 * test_results)4886 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
4887 {
4888 struct hwrm_selftest_exec_output *resp;
4889 struct hwrm_selftest_exec_input *req;
4890 int rc;
4891
4892 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
4893 if (rc)
4894 return rc;
4895
4896 hwrm_req_timeout(bp, req, bp->test_info->timeout);
4897 req->flags = test_mask;
4898
4899 resp = hwrm_req_hold(bp, req);
4900 rc = hwrm_req_send(bp, req);
4901 *test_results = resp->test_success;
4902 hwrm_req_drop(bp, req);
4903 return rc;
4904 }
4905
4906 #define BNXT_DRV_TESTS 4
4907 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
4908 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
4909 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
4910 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
4911
bnxt_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)4912 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
4913 u64 *buf)
4914 {
4915 struct bnxt *bp = netdev_priv(dev);
4916 bool do_ext_lpbk = false;
4917 bool offline = false;
4918 u8 test_results = 0;
4919 u8 test_mask = 0;
4920 int rc = 0, i;
4921
4922 if (!bp->num_tests || !BNXT_PF(bp))
4923 return;
4924
4925 if (etest->flags & ETH_TEST_FL_OFFLINE &&
4926 bnxt_ulp_registered(bp->edev)) {
4927 etest->flags |= ETH_TEST_FL_FAILED;
4928 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n");
4929 return;
4930 }
4931
4932 memset(buf, 0, sizeof(u64) * bp->num_tests);
4933 if (!netif_running(dev)) {
4934 etest->flags |= ETH_TEST_FL_FAILED;
4935 return;
4936 }
4937
4938 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
4939 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
4940 do_ext_lpbk = true;
4941
4942 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4943 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
4944 etest->flags |= ETH_TEST_FL_FAILED;
4945 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
4946 return;
4947 }
4948 offline = true;
4949 }
4950
4951 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
4952 u8 bit_val = 1 << i;
4953
4954 if (!(bp->test_info->offline_mask & bit_val))
4955 test_mask |= bit_val;
4956 else if (offline)
4957 test_mask |= bit_val;
4958 }
4959 if (!offline) {
4960 bnxt_run_fw_tests(bp, test_mask, &test_results);
4961 } else {
4962 bnxt_close_nic(bp, true, false);
4963 bnxt_run_fw_tests(bp, test_mask, &test_results);
4964
4965 rc = bnxt_half_open_nic(bp);
4966 if (rc) {
4967 etest->flags |= ETH_TEST_FL_FAILED;
4968 return;
4969 }
4970 buf[BNXT_MACLPBK_TEST_IDX] = 1;
4971 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK)
4972 goto skip_mac_loopback;
4973
4974 bnxt_hwrm_mac_loopback(bp, true);
4975 msleep(250);
4976 if (bnxt_run_loopback(bp))
4977 etest->flags |= ETH_TEST_FL_FAILED;
4978 else
4979 buf[BNXT_MACLPBK_TEST_IDX] = 0;
4980
4981 bnxt_hwrm_mac_loopback(bp, false);
4982 skip_mac_loopback:
4983 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
4984 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK)
4985 goto skip_phy_loopback;
4986
4987 bnxt_hwrm_phy_loopback(bp, true, false);
4988 msleep(1000);
4989 if (bnxt_run_loopback(bp))
4990 etest->flags |= ETH_TEST_FL_FAILED;
4991 else
4992 buf[BNXT_PHYLPBK_TEST_IDX] = 0;
4993 skip_phy_loopback:
4994 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
4995 if (do_ext_lpbk) {
4996 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
4997 bnxt_hwrm_phy_loopback(bp, true, true);
4998 msleep(1000);
4999 if (bnxt_run_loopback(bp))
5000 etest->flags |= ETH_TEST_FL_FAILED;
5001 else
5002 buf[BNXT_EXTLPBK_TEST_IDX] = 0;
5003 }
5004 bnxt_hwrm_phy_loopback(bp, false, false);
5005 bnxt_half_close_nic(bp);
5006 rc = bnxt_open_nic(bp, true, true);
5007 }
5008 if (rc || bnxt_test_irq(bp)) {
5009 buf[BNXT_IRQ_TEST_IDX] = 1;
5010 etest->flags |= ETH_TEST_FL_FAILED;
5011 }
5012 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
5013 u8 bit_val = 1 << i;
5014
5015 if ((test_mask & bit_val) && !(test_results & bit_val)) {
5016 buf[i] = 1;
5017 etest->flags |= ETH_TEST_FL_FAILED;
5018 }
5019 }
5020 }
5021
bnxt_reset(struct net_device * dev,u32 * flags)5022 static int bnxt_reset(struct net_device *dev, u32 *flags)
5023 {
5024 struct bnxt *bp = netdev_priv(dev);
5025 bool reload = false;
5026 u32 req = *flags;
5027
5028 if (!req)
5029 return -EINVAL;
5030
5031 if (!BNXT_PF(bp)) {
5032 netdev_err(dev, "Reset is not supported from a VF\n");
5033 return -EOPNOTSUPP;
5034 }
5035
5036 if (pci_vfs_assigned(bp->pdev) &&
5037 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
5038 netdev_err(dev,
5039 "Reset not allowed when VFs are assigned to VMs\n");
5040 return -EBUSY;
5041 }
5042
5043 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
5044 /* This feature is not supported in older firmware versions */
5045 if (bp->hwrm_spec_code >= 0x10803) {
5046 if (!bnxt_firmware_reset_chip(dev)) {
5047 netdev_info(dev, "Firmware reset request successful.\n");
5048 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
5049 reload = true;
5050 *flags &= ~BNXT_FW_RESET_CHIP;
5051 }
5052 } else if (req == BNXT_FW_RESET_CHIP) {
5053 return -EOPNOTSUPP; /* only request, fail hard */
5054 }
5055 }
5056
5057 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
5058 /* This feature is not supported in older firmware versions */
5059 if (bp->hwrm_spec_code >= 0x10803) {
5060 if (!bnxt_firmware_reset_ap(dev)) {
5061 netdev_info(dev, "Reset application processor successful.\n");
5062 reload = true;
5063 *flags &= ~BNXT_FW_RESET_AP;
5064 }
5065 } else if (req == BNXT_FW_RESET_AP) {
5066 return -EOPNOTSUPP; /* only request, fail hard */
5067 }
5068 }
5069
5070 if (reload)
5071 netdev_info(dev, "Reload driver to complete reset\n");
5072
5073 return 0;
5074 }
5075
bnxt_set_dump(struct net_device * dev,struct ethtool_dump * dump)5076 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
5077 {
5078 struct bnxt *bp = netdev_priv(dev);
5079
5080 if (dump->flag > BNXT_DUMP_DRIVER) {
5081 netdev_info(dev, "Supports only Live(0), Crash(1), Driver(2) dumps.\n");
5082 return -EINVAL;
5083 }
5084
5085 if (dump->flag == BNXT_DUMP_CRASH) {
5086 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR &&
5087 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) {
5088 netdev_info(dev,
5089 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
5090 return -EOPNOTSUPP;
5091 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) {
5092 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n");
5093 return -EOPNOTSUPP;
5094 }
5095 }
5096
5097 bp->dump_flag = dump->flag;
5098 return 0;
5099 }
5100
bnxt_get_dump_flag(struct net_device * dev,struct ethtool_dump * dump)5101 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
5102 {
5103 struct bnxt *bp = netdev_priv(dev);
5104
5105 if (bp->hwrm_spec_code < 0x10801)
5106 return -EOPNOTSUPP;
5107
5108 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
5109 bp->ver_resp.hwrm_fw_min_8b << 16 |
5110 bp->ver_resp.hwrm_fw_bld_8b << 8 |
5111 bp->ver_resp.hwrm_fw_rsvd_8b;
5112
5113 dump->flag = bp->dump_flag;
5114 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
5115 return 0;
5116 }
5117
bnxt_get_dump_data(struct net_device * dev,struct ethtool_dump * dump,void * buf)5118 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
5119 void *buf)
5120 {
5121 struct bnxt *bp = netdev_priv(dev);
5122
5123 if (bp->hwrm_spec_code < 0x10801)
5124 return -EOPNOTSUPP;
5125
5126 memset(buf, 0, dump->len);
5127
5128 dump->flag = bp->dump_flag;
5129 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
5130 }
5131
bnxt_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)5132 static int bnxt_get_ts_info(struct net_device *dev,
5133 struct kernel_ethtool_ts_info *info)
5134 {
5135 struct bnxt *bp = netdev_priv(dev);
5136 struct bnxt_ptp_cfg *ptp;
5137
5138 ptp = bp->ptp_cfg;
5139 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
5140
5141 if (!ptp)
5142 return 0;
5143
5144 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
5145 SOF_TIMESTAMPING_RX_HARDWARE |
5146 SOF_TIMESTAMPING_RAW_HARDWARE;
5147 if (ptp->ptp_clock)
5148 info->phc_index = ptp_clock_index(ptp->ptp_clock);
5149
5150 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
5151
5152 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
5153 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
5154 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
5155
5156 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
5157 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
5158 return 0;
5159 }
5160
bnxt_ethtool_init(struct bnxt * bp)5161 void bnxt_ethtool_init(struct bnxt *bp)
5162 {
5163 struct hwrm_selftest_qlist_output *resp;
5164 struct hwrm_selftest_qlist_input *req;
5165 struct bnxt_test_info *test_info;
5166 struct net_device *dev = bp->dev;
5167 int i, rc;
5168
5169 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
5170 bnxt_get_pkgver(dev);
5171
5172 bp->num_tests = 0;
5173 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
5174 return;
5175
5176 test_info = bp->test_info;
5177 if (!test_info) {
5178 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
5179 if (!test_info)
5180 return;
5181 bp->test_info = test_info;
5182 }
5183
5184 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
5185 return;
5186
5187 resp = hwrm_req_hold(bp, req);
5188 rc = hwrm_req_send_silent(bp, req);
5189 if (rc)
5190 goto ethtool_init_exit;
5191
5192 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
5193 if (bp->num_tests > BNXT_MAX_TEST)
5194 bp->num_tests = BNXT_MAX_TEST;
5195
5196 test_info->offline_mask = resp->offline_tests;
5197 test_info->timeout = le16_to_cpu(resp->test_timeout);
5198 if (!test_info->timeout)
5199 test_info->timeout = HWRM_CMD_TIMEOUT;
5200 for (i = 0; i < bp->num_tests; i++) {
5201 char *str = test_info->string[i];
5202 char *fw_str = resp->test_name[i];
5203
5204 if (i == BNXT_MACLPBK_TEST_IDX) {
5205 strcpy(str, "Mac loopback test (offline)");
5206 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
5207 strcpy(str, "Phy loopback test (offline)");
5208 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
5209 strcpy(str, "Ext loopback test (offline)");
5210 } else if (i == BNXT_IRQ_TEST_IDX) {
5211 strcpy(str, "Interrupt_test (offline)");
5212 } else {
5213 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
5214 fw_str, test_info->offline_mask & (1 << i) ?
5215 "offline" : "online");
5216 }
5217 }
5218
5219 ethtool_init_exit:
5220 hwrm_req_drop(bp, req);
5221 }
5222
bnxt_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)5223 static void bnxt_get_eth_phy_stats(struct net_device *dev,
5224 struct ethtool_eth_phy_stats *phy_stats)
5225 {
5226 struct bnxt *bp = netdev_priv(dev);
5227 u64 *rx;
5228
5229 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5230 return;
5231
5232 rx = bp->rx_port_stats_ext.sw_stats;
5233 phy_stats->SymbolErrorDuringCarrier =
5234 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
5235 }
5236
bnxt_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)5237 static void bnxt_get_eth_mac_stats(struct net_device *dev,
5238 struct ethtool_eth_mac_stats *mac_stats)
5239 {
5240 struct bnxt *bp = netdev_priv(dev);
5241 u64 *rx, *tx;
5242
5243 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5244 return;
5245
5246 rx = bp->port_stats.sw_stats;
5247 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5248
5249 mac_stats->FramesReceivedOK =
5250 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
5251 mac_stats->FramesTransmittedOK =
5252 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
5253 mac_stats->FrameCheckSequenceErrors =
5254 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
5255 mac_stats->AlignmentErrors =
5256 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
5257 mac_stats->OutOfRangeLengthField =
5258 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
5259 }
5260
bnxt_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)5261 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
5262 struct ethtool_eth_ctrl_stats *ctrl_stats)
5263 {
5264 struct bnxt *bp = netdev_priv(dev);
5265 u64 *rx;
5266
5267 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5268 return;
5269
5270 rx = bp->port_stats.sw_stats;
5271 ctrl_stats->MACControlFramesReceived =
5272 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
5273 }
5274
5275 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
5276 { 0, 64 },
5277 { 65, 127 },
5278 { 128, 255 },
5279 { 256, 511 },
5280 { 512, 1023 },
5281 { 1024, 1518 },
5282 { 1519, 2047 },
5283 { 2048, 4095 },
5284 { 4096, 9216 },
5285 { 9217, 16383 },
5286 {}
5287 };
5288
bnxt_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)5289 static void bnxt_get_rmon_stats(struct net_device *dev,
5290 struct ethtool_rmon_stats *rmon_stats,
5291 const struct ethtool_rmon_hist_range **ranges)
5292 {
5293 struct bnxt *bp = netdev_priv(dev);
5294 u64 *rx, *tx;
5295
5296 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5297 return;
5298
5299 rx = bp->port_stats.sw_stats;
5300 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5301
5302 rmon_stats->jabbers =
5303 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
5304 rmon_stats->oversize_pkts =
5305 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
5306 rmon_stats->undersize_pkts =
5307 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
5308
5309 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
5310 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
5311 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
5312 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
5313 rmon_stats->hist[4] =
5314 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
5315 rmon_stats->hist[5] =
5316 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
5317 rmon_stats->hist[6] =
5318 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
5319 rmon_stats->hist[7] =
5320 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
5321 rmon_stats->hist[8] =
5322 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
5323 rmon_stats->hist[9] =
5324 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
5325
5326 rmon_stats->hist_tx[0] =
5327 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
5328 rmon_stats->hist_tx[1] =
5329 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
5330 rmon_stats->hist_tx[2] =
5331 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
5332 rmon_stats->hist_tx[3] =
5333 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
5334 rmon_stats->hist_tx[4] =
5335 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
5336 rmon_stats->hist_tx[5] =
5337 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
5338 rmon_stats->hist_tx[6] =
5339 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
5340 rmon_stats->hist_tx[7] =
5341 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
5342 rmon_stats->hist_tx[8] =
5343 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
5344 rmon_stats->hist_tx[9] =
5345 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
5346
5347 *ranges = bnxt_rmon_ranges;
5348 }
5349
bnxt_get_ptp_stats(struct net_device * dev,struct ethtool_ts_stats * ts_stats)5350 static void bnxt_get_ptp_stats(struct net_device *dev,
5351 struct ethtool_ts_stats *ts_stats)
5352 {
5353 struct bnxt *bp = netdev_priv(dev);
5354 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5355
5356 if (ptp) {
5357 ts_stats->pkts = ptp->stats.ts_pkts;
5358 ts_stats->lost = ptp->stats.ts_lost;
5359 ts_stats->err = atomic64_read(&ptp->stats.ts_err);
5360 }
5361 }
5362
bnxt_get_link_ext_stats(struct net_device * dev,struct ethtool_link_ext_stats * stats)5363 static void bnxt_get_link_ext_stats(struct net_device *dev,
5364 struct ethtool_link_ext_stats *stats)
5365 {
5366 struct bnxt *bp = netdev_priv(dev);
5367 u64 *rx;
5368
5369 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5370 return;
5371
5372 rx = bp->rx_port_stats_ext.sw_stats;
5373 stats->link_down_events =
5374 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events));
5375 }
5376
bnxt_ethtool_free(struct bnxt * bp)5377 void bnxt_ethtool_free(struct bnxt *bp)
5378 {
5379 kfree(bp->test_info);
5380 bp->test_info = NULL;
5381 }
5382
5383 const struct ethtool_ops bnxt_ethtool_ops = {
5384 .cap_link_lanes_supported = 1,
5385 .rxfh_per_ctx_key = 1,
5386 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1,
5387 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5,
5388 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx),
5389 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5390 ETHTOOL_COALESCE_MAX_FRAMES |
5391 ETHTOOL_COALESCE_USECS_IRQ |
5392 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
5393 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
5394 ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
5395 ETHTOOL_COALESCE_USE_CQE,
5396 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT |
5397 ETHTOOL_RING_USE_HDS_THRS,
5398 .get_link_ksettings = bnxt_get_link_ksettings,
5399 .set_link_ksettings = bnxt_set_link_ksettings,
5400 .get_fec_stats = bnxt_get_fec_stats,
5401 .get_fecparam = bnxt_get_fecparam,
5402 .set_fecparam = bnxt_set_fecparam,
5403 .get_pause_stats = bnxt_get_pause_stats,
5404 .get_pauseparam = bnxt_get_pauseparam,
5405 .set_pauseparam = bnxt_set_pauseparam,
5406 .get_drvinfo = bnxt_get_drvinfo,
5407 .get_regs_len = bnxt_get_regs_len,
5408 .get_regs = bnxt_get_regs,
5409 .get_wol = bnxt_get_wol,
5410 .set_wol = bnxt_set_wol,
5411 .get_coalesce = bnxt_get_coalesce,
5412 .set_coalesce = bnxt_set_coalesce,
5413 .get_msglevel = bnxt_get_msglevel,
5414 .set_msglevel = bnxt_set_msglevel,
5415 .get_sset_count = bnxt_get_sset_count,
5416 .get_strings = bnxt_get_strings,
5417 .get_ethtool_stats = bnxt_get_ethtool_stats,
5418 .set_ringparam = bnxt_set_ringparam,
5419 .get_ringparam = bnxt_get_ringparam,
5420 .get_channels = bnxt_get_channels,
5421 .set_channels = bnxt_set_channels,
5422 .get_rxnfc = bnxt_get_rxnfc,
5423 .set_rxnfc = bnxt_set_rxnfc,
5424 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
5425 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
5426 .get_rxfh = bnxt_get_rxfh,
5427 .set_rxfh = bnxt_set_rxfh,
5428 .create_rxfh_context = bnxt_create_rxfh_context,
5429 .modify_rxfh_context = bnxt_modify_rxfh_context,
5430 .remove_rxfh_context = bnxt_remove_rxfh_context,
5431 .flash_device = bnxt_flash_device,
5432 .get_eeprom_len = bnxt_get_eeprom_len,
5433 .get_eeprom = bnxt_get_eeprom,
5434 .set_eeprom = bnxt_set_eeprom,
5435 .get_link = bnxt_get_link,
5436 .get_link_ext_stats = bnxt_get_link_ext_stats,
5437 .get_eee = bnxt_get_eee,
5438 .set_eee = bnxt_set_eee,
5439 .get_tunable = bnxt_get_tunable,
5440 .set_tunable = bnxt_set_tunable,
5441 .get_module_info = bnxt_get_module_info,
5442 .get_module_eeprom = bnxt_get_module_eeprom,
5443 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
5444 .nway_reset = bnxt_nway_reset,
5445 .set_phys_id = bnxt_set_phys_id,
5446 .self_test = bnxt_self_test,
5447 .get_ts_info = bnxt_get_ts_info,
5448 .reset = bnxt_reset,
5449 .set_dump = bnxt_set_dump,
5450 .get_dump_flag = bnxt_get_dump_flag,
5451 .get_dump_data = bnxt_get_dump_data,
5452 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
5453 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
5454 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
5455 .get_rmon_stats = bnxt_get_rmon_stats,
5456 .get_ts_stats = bnxt_get_ptp_stats,
5457 };
5458