1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
26
27 #include "phy-qcom-qmp-common.h"
28
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38 #include "phy-qcom-qmp-pcs-v6_30.h"
39 #include "phy-qcom-qmp-pcie-qhp.h"
40
41 #define PHY_INIT_COMPLETE_TIMEOUT 10000
42
43 /* set of registers with offsets different per-PHY */
44 enum qphy_reg_layout {
45 /* PCS registers */
46 QPHY_SW_RESET,
47 QPHY_START_CTRL,
48 QPHY_PCS_STATUS,
49 QPHY_PCS_POWER_DOWN_CONTROL,
50 /* Keep last to ensure regs_layout arrays are properly initialized */
51 QPHY_LAYOUT_SIZE
52 };
53
54 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
55 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
56 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
57 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
59 };
60
61 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
65 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
66 };
67
68 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
69 [QPHY_SW_RESET] = 0x00,
70 [QPHY_START_CTRL] = 0x08,
71 [QPHY_PCS_STATUS] = 0x2ac,
72 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
73 };
74
75 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
76 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
77 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
78 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
79 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
80 };
81
82 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
83 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
84 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
85 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
86 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
87 };
88
89 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
90 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
91 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
92 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
93 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
94 };
95
96 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
139 };
140
141 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
142 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
143 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
144 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
145 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
146 };
147
148 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
161 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
163 };
164
165 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
176 };
177
178 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
179 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
180 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
181 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
182 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
183 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
184 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
185 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
186 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
187 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
188 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
189 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
190 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
191 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
192 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
193 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
194 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
195 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
196 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
197 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
198 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
199 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
200 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
201 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
202 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
203 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
204 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
205 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
206 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
207 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
208 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
209 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
210 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
211 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
212 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
213 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
214 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
215 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
216 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
217 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
218 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
219 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
220 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
221 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
222 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
223 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
224 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
225 };
226
227 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
228 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
229 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
230 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
231 };
232
233 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
264 };
265
266 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
269 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
270 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
271 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
272 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
273 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
274 };
275
276 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
286 };
287
288 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
289 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
290 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
291 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
292 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
293 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
294 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
295 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
296 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
297 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
298 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
299 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
300 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
301 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
302 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
303 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
304 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
305 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
306 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
307 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
308 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
309 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
310 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
311 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
312 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
313 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
314 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
315 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
316 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
317 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
318 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
319 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
320 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
321 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
322 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
323 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
324 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
325 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
326 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
329 };
330
331 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
332 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
333 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
334 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
335 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
336 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
337 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
338 };
339
340 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
341 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
342 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
343 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
344 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
345 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
346 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
347 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
348 };
349
350 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
351 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
352 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
353 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
354 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
355 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
356 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
361 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
362 };
363
364 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
365 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
366 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
367 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
368 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
369 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
370 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
371 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
372 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
373 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
374 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
375 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
376 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
377 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
378 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
379 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
380 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
381 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
382 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
383 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
384 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
385 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
386 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
387 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
388 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
389 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
390 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
391 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
393 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
394 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
395 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
396 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
397 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
398 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
399 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
400 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
401 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
402 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
403 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
404 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
405 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
406 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
407 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
409 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
410 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
411 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
412 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
413 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
414 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
415 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
416 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
417 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
418 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
419 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
420 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
421 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
422 };
423
424 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
425 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
426 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
427 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
428 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
429 };
430
431 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
462 };
463
464 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
465 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
466 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
467 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
468 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
469 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
470 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
471 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
472 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
473 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
474 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
475 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
476 };
477
478 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
492 };
493
494 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
495 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
496 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
497 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
498 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
499 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
500 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
501 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
502 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
503 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
504 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
505 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
506 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
507 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
508 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
509 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
510 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
511 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
512 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
513 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
514 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
515 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
516 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
517 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
518 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
519 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
520 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
521 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
522 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
523 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
524 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
525 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
526 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
527 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
528 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
529 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
530 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
531 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
532 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
533 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
534 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
535 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
536 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
537 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
538 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
539 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
540 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
541 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
542 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
543 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
544 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
545 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
546 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
547 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
548 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
549 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
550 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
551 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
552 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
553 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
554 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
555 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
556 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
557 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
558 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
559 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
560 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
561 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
562 };
563
564 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
565 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
566 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
567 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
568 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
569 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
570 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
571 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
572 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
573 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
574 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
575 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
576 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
577 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
578 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
579 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
580 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
581 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
582 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
583 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
584 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
585 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
586 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
587 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
588 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
589 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
590 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
591 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
592 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
593 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
594 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
595 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
596 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
597 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
598 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
599 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
600 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
601 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
602 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
603 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
604 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
605 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
606 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
607 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
608 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
609 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
610 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
611 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
612 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
613 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
614 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
615 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
616 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
617 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
618 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
619 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
620 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
621 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
622 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
623 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
624 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
625 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
626 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
627 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
628 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
629 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
630 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
631 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
632 };
633
634 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {
635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),
647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),
648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),
654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),
660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
665 };
666
667 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {
668 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
669 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
670 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
671 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
672 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
673 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
674 };
675
676 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {
677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),
684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),
685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),
686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),
694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
696 };
697
698 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {
699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
705 };
706
707 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
708 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
709 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
710 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
711 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
712 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
713 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
714 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
715 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
716 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
717 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
718 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
719 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
720 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
729 };
730
731 static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = {
732 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
733 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
734 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
735 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
736 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
737 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
738 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
739 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
740 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
741 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
742 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
743 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
744 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
745 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
746 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9),
747 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4),
748 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
749 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
750 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
751 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
752 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
753 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd),
754 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04),
755 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35),
756 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
757 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
758 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4),
759 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
760 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30),
761 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
762 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
763 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
764 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
765 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
766 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
767 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
768 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
769 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
770 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
771 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
772 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
773 };
774
775 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = {
776 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
777 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
778 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
779 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
780 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
781 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
782 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
783 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
784 };
785
786 static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = {
787 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
788 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
789 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
790 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
791 };
792
793 static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = {
794 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
795 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
796 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
797 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
798 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
799 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
800 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
801 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
802 QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7),
803 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
804 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
805 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
806 };
807
808 static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = {
809 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
810 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
811 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
812 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
813 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
814 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
815 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
816 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
817 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
818 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
819 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
820 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
821 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
822 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
823 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
824 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
825 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
826 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
827 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
828 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
829 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
830 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
831 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
832 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
833 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
834 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
835 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
836 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
837 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
838 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
839 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
840 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
841 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
842 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
843 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
844 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
845 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
846 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
847 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
848 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
849 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
850 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
851 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
852 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
853 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
854 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
855 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
856 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
857 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
858 };
859
860 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
861 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
862 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
863 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
864 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
865 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
866 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
867 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
868 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
869 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
870 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
871 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
872 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
873 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
874 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
875 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
876 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
877 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
878 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
879 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
880 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
881 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
882 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
883 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
884 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
885 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
886 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
887 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
888 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
889 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
890 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
891 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
892 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
893 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
894 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
895 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
896 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
897 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
898 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
899 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
900 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
901 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
902 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
903 };
904
905 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
906 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
907 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
908 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
909 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
910 };
911
912 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
913 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
914 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
915 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
916 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
917 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
918 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
919 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
920 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
921 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
922 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
923 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
924 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
925 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
926 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
927 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
928 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
929 };
930
931 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
932 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
933
934 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
935 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
936 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
937 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
938 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
939
940 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
941 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
942 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
943 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
944 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
945 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
946 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
947
948 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
949 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
950 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
951
952 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
953 };
954
955 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
956 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
957 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
958 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
959 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
960 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
961 };
962
963 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
964 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
965 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
966 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
967 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
968 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
969 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
970 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
971 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
972 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
973 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
974 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
975 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
976 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
977 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
978 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
1009 };
1010
1011 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
1016 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
1017 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
1018 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
1019 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
1020 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
1021 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
1022 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
1023 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
1024 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
1025 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
1026 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
1027 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
1028 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
1029 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
1030 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
1031 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
1032 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
1033 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
1034 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
1035 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
1036 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
1037 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
1038 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
1039 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
1040 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
1041 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
1042 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
1043 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
1044 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1045 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1046 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1047 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1048 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1049 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1050 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1051 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1052 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1053 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1054 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1055 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1056 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1057 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1058 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1059 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1060 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1061 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1062 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1063 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1064 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1065 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1066 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1067 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1068 };
1069
1070 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1071 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1072 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1073 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1074 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1075 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1076 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1077 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1078 };
1079
1080 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
1081 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1082 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1083 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1084 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1085 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1086 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1087 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1088 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1089 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1090 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1091 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1092 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1093 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1094 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1095 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1096 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1097 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1098 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1099 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1100 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1101 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1102 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1103 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1104 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1105 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1106 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1107 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1108 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1109 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1110 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1111 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1112 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1113 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1114 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1115 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1116 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1117 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1118 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1119 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1120 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1121 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1122 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1123 };
1124
1125 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
1126 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1127 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
1128 };
1129
1130 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
1131 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1132 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1133 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1134 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
1135 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
1136 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
1137 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
1138 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1139 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1140 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1141 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1142 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1143 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
1144 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1145 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1146 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1147 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
1148 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1149 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1150 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1151 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1152 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
1153 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1154 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1155 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
1156 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1157 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
1158 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
1159 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1160 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1161 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1162 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
1163 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1164 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
1165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1167 };
1168
1169 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
1170 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1171 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1172 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1173 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1174 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
1175 };
1176
1177 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
1178 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1179 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1180 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1181 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1182 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1183 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1184 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1185 };
1186
1187 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1229 };
1230
1231 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1233 };
1234
1235 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1237 };
1238
1239 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
1241 };
1242
1243 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
1244 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1245 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1246 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1247 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1248 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1249 };
1250
1251 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
1252 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1253 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1254 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1255 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1256 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1257 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1258 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1259 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1260 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1261 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1262 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1263 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1264 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1265 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1269 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1270 };
1271
1272 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
1273 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1274 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1275 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1276 };
1277
1278 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1279 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1280 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1281 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1282 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1283 };
1284
1285 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
1286 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1287 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1288 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1289 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1290 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1291 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1292 };
1293
1294 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
1295 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1296 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1297 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1298 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1299 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1300 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1301 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1302 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1303 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1304 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1305 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1306 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1307 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1308 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1309 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1310 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1311 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1312 };
1313
1314 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
1315 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1316 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
1317 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1318 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
1319 };
1320
1321 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1322 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1323 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1324 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1325 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1326 };
1327
1328 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {
1329 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1330 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1331 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1332 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1333 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1334 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1335 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1336 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1337 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1338 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1339 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1340 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1341 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1374 };
1375
1376 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = {
1377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
1378 };
1379
1380 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1381 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1382 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1383 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1384 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1385 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
1386 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1387 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1388 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1389 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),
1390 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1391 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1392 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1393 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1394 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1395 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1396 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1397 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1398 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1399 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1400 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1401 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1402 };
1403
1404 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
1405 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1406 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1407 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1408 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1409 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1410 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1411 };
1412
1413 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
1414 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1415 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1416 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1417 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1418 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1419 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1420 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1421 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1422 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
1423 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
1424 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1425 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),
1426 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),
1427 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
1428 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1429 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1430 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1431 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1432 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),
1433 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),
1434 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1435 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1436 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1437 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1438 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1439 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1440 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1441 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1442 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4),
1443 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4),
1444 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1445 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1446 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
1447 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1448 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1449 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1450 };
1451
1452 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
1453 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1454 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
1455 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1456 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1457 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1458 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1459 };
1460
1461 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1462 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1463 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1464 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1465 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1466 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1467 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1468 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1469 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
1470 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
1471 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1472 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1473 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),
1474 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1475 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
1476 };
1477
1478 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = {
1479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1481 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1482 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1483 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1484 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08),
1485 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04),
1486 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d),
1487 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1488 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1489 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1490 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1491 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1492 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1493 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1494 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1495 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1496 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1497 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1498 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1499 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1500 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1501 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1502 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1503 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1504 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1505 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1506 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1507 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1508 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1509 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1510 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
1511 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1512 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1513 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1514 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1515 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1516 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1517 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1518 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1519 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
1520 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1521 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1522 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1523 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1524 };
1525
1526 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = {
1527 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1528 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1529 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1530 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1531 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1532 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1533 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1534 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1535 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1536 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1537 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1538 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1539 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1540 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1541 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1542 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1543 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1544 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1545 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1546 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1547 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1548 };
1549
1550 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = {
1551 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1552 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05),
1553 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1554 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1555 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1556 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1557 };
1558
1559 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = {
1560 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1561 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1562 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1563 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1564 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1565 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1566 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1567 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1568 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1569 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c),
1570 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
1571 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1572 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1573 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1574 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1575 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1576 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1577 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4),
1578 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23),
1579 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1580 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1581 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38),
1582 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1583 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1584 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c),
1585 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4),
1586 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1587 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1588 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69),
1589 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1590 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1591 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1592 };
1593
1594 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = {
1595 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)),
1596 };
1597
1598 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = {
1599 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00),
1600 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e),
1601 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99),
1602 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00),
1603 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00),
1604 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22),
1605 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04),
1606 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02),
1607 };
1608
1609 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = {
1610 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1611 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00),
1612 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16),
1613 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02),
1614 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e),
1615 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03),
1616 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28),
1617 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18),
1618 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1619 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
1620 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27),
1621 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27),
1622 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0),
1623 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d),
1624 };
1625
1626 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
1627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1667 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1668 };
1669
1670 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1671 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1672 };
1673
1674 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1675 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1676 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1677 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1678 };
1679
1680 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1711 };
1712
1713 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1720 };
1721
1722 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1726 };
1727
1728 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1729 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1730 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1731 };
1732
1733 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1734 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1735 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1736 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1737 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1738 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1739 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1740 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1741 };
1742
1743 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1744 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1745 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1746 };
1747
1748 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1749 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1750 };
1751
1752 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1757 };
1758
1759 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1762 };
1763
1764 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1765 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1766 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1767 };
1768
1769 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1784 };
1785
1786 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
1787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
1791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
1792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
1796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
1797 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1798 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1799 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1800 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
1805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
1806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
1807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
1808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
1809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
1810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
1811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
1812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
1813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
1814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
1818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
1819 };
1820
1821 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
1822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
1827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
1828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
1834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
1835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
1836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
1837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
1838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1847 };
1848
1849 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
1850 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
1851 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
1852 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
1853 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
1854 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
1855 };
1856
1857 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
1858 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
1859 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
1860 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
1861 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
1862 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
1863 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
1864 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
1865 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1866 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
1867 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
1868 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
1869 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
1870 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
1871 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
1872 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
1873 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
1874 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
1875 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
1876 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
1877 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
1878 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
1879 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
1880 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
1881 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1882 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
1883 };
1884
1885 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
1886 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
1887 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
1888 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
1889 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
1890 };
1891
1892 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
1893 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
1894 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
1895 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1896 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1897 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1898 };
1899
1900 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
1901 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1902 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1903 };
1904
1905 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = {
1906 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1907 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1908 };
1909
1910 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {
1911 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1912 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1913 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1914 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1915 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1916 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1917 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1918 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1919 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1920 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1921 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1922 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1923 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1927 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1928 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1929 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1939 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1940 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),
1944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1945 };
1946
1947 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {
1948 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1949 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1950 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),
1951 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),
1952 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),
1953 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1954 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1955 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),
1956 };
1957
1958 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {
1959 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1960 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),
1961 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),
1962 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
1963 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
1964 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1965 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1966 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),
1967 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),
1968 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),
1969 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),
1970 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
1971 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1972 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),
1973 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1974 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),
1975 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),
1976 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1977 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),
1978 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1979 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1980 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1981 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),
1982 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1983 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1984 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1985 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),
1986 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1987 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1988 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1989 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1990 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1991 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1992 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1993 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1994 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1995 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1996 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1997 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1998 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1999 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2000 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
2001 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2002 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),
2003 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2004 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
2005 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2006 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
2007 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),
2008 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
2009 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
2010 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),
2011 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
2012 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2013 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),
2014 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),
2015 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
2016 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
2017 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
2018 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
2019 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
2020 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),
2021 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2022 };
2023
2024 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {
2025 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2026 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),
2027 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),
2028 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2029 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2030 };
2031
2032 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
2033 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2034 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2035 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
2036 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
2037 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2038 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2039 };
2040
2041 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = {
2042 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2043 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2044 };
2045
2046 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
2047 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2048 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2049 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
2050 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2051 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2052 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
2053 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
2054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
2055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2061 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
2064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
2065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
2066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
2067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
2070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
2081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2088 };
2089
2090 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
2091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
2092 };
2093
2094 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
2095 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
2096 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
2097 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2098 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2099 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
2100 };
2101
2102 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
2103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
2104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
2105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
2106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
2107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
2108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
2109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
2110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
2111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
2112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
2117 };
2118
2119 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
2120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
2121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
2122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
2123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
2124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
2125 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
2126 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
2127 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2128 };
2129
2130 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
2131 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
2132 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
2133 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
2134 };
2135
2136 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2137 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2138 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2139 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
2140 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2141 };
2142
2143 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
2144 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
2145 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
2146 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2147 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2148 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
2149 };
2150
2151 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
2152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
2153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
2154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
2155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
2156 };
2157
2158 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
2159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
2160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
2161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2162 };
2163
2164 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
2165 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
2166 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
2167 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
2168 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2169 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2170 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
2171 };
2172
2173 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
2174 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
2175 };
2176
2177 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
2178 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
2179 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2180 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2181 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2182 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2183 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2184 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2185 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2191 };
2192
2193 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
2194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
2222 };
2223
2224 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
2225 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
2226 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
2227 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
2228 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
2229 };
2230
2231 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
2232 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2233 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2234 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
2235 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
2236 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
2237 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
2238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
2239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
2240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
2241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
2242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
2243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
2244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
2245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
2246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
2247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
2248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
2249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
2250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
2251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
2252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
2253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2256
2257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
2258
2259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2260
2261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2269
2270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
2272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2273 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2276 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
2277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2279 };
2280
2281 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
2282 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2283 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2284 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2285 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),
2286 };
2287
2288 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
2289 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2290 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2291 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2292 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2293 };
2294
2295 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
2296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),
2299 };
2300
2301 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
2302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
2303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
2304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
2305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
2306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
2307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
2308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
2309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
2310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
2311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
2313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
2314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
2315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
2316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
2317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2322 };
2323
2324 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
2325 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
2326 };
2327
2328 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
2329 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2330 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
2331 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
2332 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2333 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2334 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
2335 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
2336 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2337 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2338 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2339 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
2340 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
2341 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
2347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
2349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
2350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
2351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
2352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
2353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
2354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
2356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
2357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
2358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
2359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
2360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
2366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2367 };
2368
2369 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
2370 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
2371 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
2372 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
2373 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
2374 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
2375 };
2376
2377 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
2378 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2379 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
2380 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
2381 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
2382 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
2383 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
2384 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
2385 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
2386 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
2387 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
2388 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
2389 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
2390 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
2391 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
2392 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
2393 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
2394 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),
2395 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
2396 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
2397 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
2398 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
2399 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
2400 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
2401 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
2402 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
2403 };
2404
2405 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
2406 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
2407 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
2408 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
2409 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
2410 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
2411 };
2412
2413 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2414 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
2415 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
2416 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2417 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2418 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2419 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2420 };
2421
2422 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
2423 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
2424 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
2425 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
2426 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
2430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
2431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
2432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
2433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
2434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
2435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
2436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
2439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
2442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
2443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
2444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
2445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
2447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
2448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
2449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
2450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
2452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
2453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
2454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
2455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
2458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
2460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
2461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
2465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
2466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
2467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
2468 };
2469
2470 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
2471 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
2472 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
2473 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
2474 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
2475 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
2476 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
2477 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
2478 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
2479 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
2480 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
2481 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
2482 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2483 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2484 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2485 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2486 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2487 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2488 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2489 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2490 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2491 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
2492 };
2493
2494 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
2495 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2496 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
2497 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
2498 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
2499 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
2500 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
2501 };
2502
2503 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
2504 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
2505 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
2506 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
2507 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
2508 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
2509 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
2510 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
2511 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
2512 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
2513 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2514 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
2515 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2516 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
2517 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
2518 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2519 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2520 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
2521 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
2522 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
2523 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
2524 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
2525 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
2526 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
2527 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
2528 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
2529 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
2530 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
2531 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
2532 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
2533 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
2534 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
2535 };
2536
2537 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
2538 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2539 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
2540 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
2541 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
2542 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
2543 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
2544 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
2545 };
2546
2547 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
2548 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
2549 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
2550 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
2551 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
2552 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
2553 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
2554 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
2555 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
2556 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
2557 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
2558 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
2559 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
2560 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
2561 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
2562 };
2563
2564 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {
2565 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
2566 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
2567 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
2568 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
2569 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82),
2570 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
2571 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2572 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
2573 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2574 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
2575 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
2576 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2577 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3),
2578 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3),
2579 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00),
2580 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
2581 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06),
2582 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
2583 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
2584 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23),
2585 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b),
2586 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
2587 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
2588 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43),
2589 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
2590 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
2591 };
2592
2593 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {
2594 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
2595 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2596 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2597 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2598 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2599 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2600 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2601 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2602 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2603 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2604 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2605 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2606 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2607 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2608 };
2609
2610 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = {
2611 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2612 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2613 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2614 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2615 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2616 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2617 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2618 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2628 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2629 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2630 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2631 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2632 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2633 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2634 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2635 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2636 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2637 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2638 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2639 };
2640
2641 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
2642 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2643 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2644 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a),
2645 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2646 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2647 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2648 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2649 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99),
2650 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
2651 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2652 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
2653 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2654 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
2655 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2656 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2657 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2658 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2659 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
2660 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
2661 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
2662 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2663 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
2664 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
2665 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2666 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2667 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2668 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2669 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2670 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2671 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2672 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2673 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2674 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2675 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2676 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2677 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2678 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2679 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2680 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2681 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2682 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2683 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2684 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2685 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2686 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2687 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2688 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2689 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2690 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2691 };
2692
2693 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {
2694 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
2695 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
2696 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
2697 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
2698 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f),
2699 };
2700
2701 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
2702 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2703 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2704 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2705 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2706 };
2707
2708 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
2709 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2710 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2711 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2712 };
2713
2714 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
2715 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2716 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2717 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2718 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2719 };
2720
2721 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
2722 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2723 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2724 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2725 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2726 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2727 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2728 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2729 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2730 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2731 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2732 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2733 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2734 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2735 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2736 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2737 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2738 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2739 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2740 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2741 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2742 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99),
2743 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2744 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2745 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2746 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2747 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2748 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2749 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2750 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
2751 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2752 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
2753 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2754 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2755 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2756 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2757 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
2758 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee),
2759 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2),
2760 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2761 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9),
2762 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d),
2763 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2764 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2765 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2766 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2767 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2768 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2769 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2770 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2771 };
2772
2773 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
2774 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2775 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2776 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2777 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2778 };
2779
2780 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
2781 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
2782 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2783 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2784 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2785 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2786 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2787 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2788 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2789 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2790 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2791 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2792 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2793 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2794 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2795 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2796 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2797 };
2798
2799
2800 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = {
2801 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2802 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2803 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2804 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2805 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2806 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2807 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2808 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2809 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2810 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2811 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2812 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2813 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2814 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2815 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2816 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2817 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2818 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2819 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2820 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2821 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2822 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2823 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2824 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2825 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2826 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2827 };
2828
2829 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {
2830 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
2831 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
2832 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
2833 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
2834 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
2835 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
2836 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
2837 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
2838 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
2839 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2840 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2841 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2842 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2843 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2844 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
2846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
2847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
2848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
2849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
2850 };
2851
2852 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {
2853 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00),
2854 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),
2855 };
2856
2857 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
2858 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2859 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
2860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
2861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff),
2862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
2863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2865 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2866 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2867 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2868 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
2869 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
2870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2872 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
2876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
2878 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
2879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14),
2880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34),
2881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
2882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
2883 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2884 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
2885 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
2886 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
2887 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
2888 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
2889 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2890 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2891 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2892 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2893 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2894 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
2895 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2896 };
2897
2898 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = {
2899 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01),
2900 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01),
2901 };
2902
2903 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = {
2904 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2),
2905 };
2906
2907 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
2908 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2909 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e),
2910 };
2911
2912 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = {
2913 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00),
2914 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06),
2915 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07),
2916 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28),
2918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28),
2919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d),
2920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d),
2921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00),
2922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00),
2923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
2925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
2926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff),
2927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09),
2928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19),
2929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14),
2930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03),
2932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03),
2934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
2939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2940 };
2941
2942 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = {
2943 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2944 };
2945
2946 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = {
2947 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
2948 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14),
2949 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2950 };
2951
2952 struct qmp_pcie_offsets {
2953 u16 serdes;
2954 u16 pcs;
2955 u16 pcs_misc;
2956 u16 pcs_lane1;
2957 u16 tx;
2958 u16 rx;
2959 u16 tx2;
2960 u16 rx2;
2961 u16 txz;
2962 u16 rxz;
2963 u16 ln_shrd;
2964 };
2965
2966 struct qmp_phy_cfg_tbls {
2967 const struct qmp_phy_init_tbl *serdes;
2968 int serdes_num;
2969 const struct qmp_phy_init_tbl *tx;
2970 int tx_num;
2971 const struct qmp_phy_init_tbl *rx;
2972 int rx_num;
2973 const struct qmp_phy_init_tbl *txz;
2974 int txz_num;
2975 const struct qmp_phy_init_tbl *rxz;
2976 int rxz_num;
2977 const struct qmp_phy_init_tbl *pcs;
2978 int pcs_num;
2979 const struct qmp_phy_init_tbl *pcs_misc;
2980 int pcs_misc_num;
2981 const struct qmp_phy_init_tbl *pcs_lane1;
2982 int pcs_lane1_num;
2983 const struct qmp_phy_init_tbl *ln_shrd;
2984 int ln_shrd_num;
2985 };
2986
2987 /* struct qmp_phy_cfg - per-PHY initialization config */
2988 struct qmp_phy_cfg {
2989 int lanes;
2990
2991 const struct qmp_pcie_offsets *offsets;
2992
2993 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
2994 const struct qmp_phy_cfg_tbls tbls;
2995 /*
2996 * Additional init sequences for PHY blocks, providing additional
2997 * register programming. They are used for providing separate sequences
2998 * for the Root Complex and End Point use cases.
2999 *
3000 * If EP mode is not supported, both tables can be left unset.
3001 */
3002 const struct qmp_phy_cfg_tbls *tbls_rc;
3003 const struct qmp_phy_cfg_tbls *tbls_ep;
3004
3005 const struct qmp_phy_init_tbl *serdes_4ln_tbl;
3006 int serdes_4ln_num;
3007
3008 /* resets to be requested */
3009 const char * const *reset_list;
3010 int num_resets;
3011 /* regulators to be requested */
3012 const char * const *vreg_list;
3013 int num_vregs;
3014
3015 /* array of registers with different offsets */
3016 const unsigned int *regs;
3017
3018 unsigned int pwrdn_ctrl;
3019 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
3020 unsigned int phy_status;
3021
3022 bool skip_start_delay;
3023
3024 /* QMP PHY pipe clock interface rate */
3025 unsigned long pipe_clock_rate;
3026
3027 /* QMP PHY AUX clock interface rate */
3028 unsigned long aux_clock_rate;
3029 };
3030
3031 struct qmp_pcie {
3032 struct device *dev;
3033
3034 const struct qmp_phy_cfg *cfg;
3035 bool tcsr_4ln_config;
3036 bool skip_init;
3037
3038 void __iomem *serdes;
3039 void __iomem *pcs;
3040 void __iomem *pcs_misc;
3041 void __iomem *pcs_lane1;
3042 void __iomem *tx;
3043 void __iomem *rx;
3044 void __iomem *tx2;
3045 void __iomem *rx2;
3046 void __iomem *txz;
3047 void __iomem *rxz;
3048 void __iomem *ln_shrd;
3049
3050 void __iomem *port_b;
3051
3052 struct clk_bulk_data *clks;
3053 struct clk_bulk_data pipe_clks[2];
3054 int num_pipe_clks;
3055
3056 struct reset_control_bulk_data *resets;
3057 struct reset_control *nocsr_reset;
3058 struct regulator_bulk_data *vregs;
3059
3060 struct phy *phy;
3061 int mode;
3062
3063 struct clk_fixed_rate pipe_clk_fixed;
3064 struct clk_fixed_rate aux_clk_fixed;
3065 };
3066
qphy_setbits(void __iomem * base,u32 offset,u32 val)3067 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
3068 {
3069 u32 reg;
3070
3071 reg = readl(base + offset);
3072 reg |= val;
3073 writel(reg, base + offset);
3074
3075 /* ensure that above write is through */
3076 readl(base + offset);
3077 }
3078
qphy_clrbits(void __iomem * base,u32 offset,u32 val)3079 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
3080 {
3081 u32 reg;
3082
3083 reg = readl(base + offset);
3084 reg &= ~val;
3085 writel(reg, base + offset);
3086
3087 /* ensure that above write is through */
3088 readl(base + offset);
3089 }
3090
3091 /* list of clocks required by phy */
3092 static const char * const qmp_pciephy_clk_l[] = {
3093 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
3094 };
3095
3096 /* list of regulators */
3097 static const char * const qmp_phy_vreg_l[] = {
3098 "vdda-phy", "vdda-pll",
3099 };
3100
3101 static const char * const sm8550_qmp_phy_vreg_l[] = {
3102 "vdda-phy", "vdda-pll", "vdda-qref",
3103 };
3104
3105 /* list of resets */
3106 static const char * const ipq8074_pciephy_reset_l[] = {
3107 "phy", "common",
3108 };
3109
3110 static const char * const sdm845_pciephy_reset_l[] = {
3111 "phy",
3112 };
3113
3114 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
3115 .serdes = 0,
3116 .pcs = 0x1800,
3117 .tx = 0x0800,
3118 /* no .rx for QHP */
3119 };
3120
3121 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
3122 .serdes = 0,
3123 .pcs = 0x0800,
3124 .tx = 0x0200,
3125 .rx = 0x0400,
3126 };
3127
3128 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
3129 .serdes = 0,
3130 .pcs = 0x0800,
3131 .pcs_misc = 0x0600,
3132 .tx = 0x0200,
3133 .rx = 0x0400,
3134 };
3135
3136 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
3137 .serdes = 0,
3138 .pcs = 0x0800,
3139 .pcs_misc = 0x0c00,
3140 .tx = 0x0200,
3141 .rx = 0x0400,
3142 };
3143
3144 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
3145 .serdes = 0,
3146 .pcs = 0x0a00,
3147 .pcs_misc = 0x0e00,
3148 .tx = 0x0200,
3149 .rx = 0x0400,
3150 .tx2 = 0x0600,
3151 .rx2 = 0x0800,
3152 };
3153
3154 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
3155 .serdes = 0x1000,
3156 .pcs = 0x1200,
3157 .pcs_misc = 0x1600,
3158 .pcs_lane1 = 0x1e00,
3159 .tx = 0x0000,
3160 .rx = 0x0200,
3161 .tx2 = 0x0800,
3162 .rx2 = 0x0a00,
3163 };
3164
3165 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
3166 .serdes = 0,
3167 .pcs = 0x0200,
3168 .pcs_misc = 0x0600,
3169 .tx = 0x0e00,
3170 .rx = 0x1000,
3171 .tx2 = 0x1600,
3172 .rx2 = 0x1800,
3173 };
3174
3175 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
3176 .serdes = 0,
3177 .pcs = 0x1000,
3178 .pcs_misc = 0x1400,
3179 .tx = 0x0200,
3180 .rx = 0x0400,
3181 .tx2 = 0x0600,
3182 .rx2 = 0x0800,
3183 };
3184
3185 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
3186 .serdes = 0x1000,
3187 .pcs = 0x1200,
3188 .pcs_misc = 0x1400,
3189 .pcs_lane1 = 0x1e00,
3190 .tx = 0x0000,
3191 .rx = 0x0200,
3192 .tx2 = 0x0800,
3193 .rx2 = 0x0a00,
3194 };
3195
3196 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
3197 .serdes = 0x2000,
3198 .pcs = 0x2200,
3199 .pcs_misc = 0x2400,
3200 .tx = 0x0,
3201 .rx = 0x0200,
3202 .tx2 = 0x3800,
3203 .rx2 = 0x3a00,
3204 };
3205
3206 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
3207 .serdes = 0x1000,
3208 .pcs = 0x1200,
3209 .pcs_misc = 0x1400,
3210 .tx = 0x0000,
3211 .rx = 0x0200,
3212 .tx2 = 0x0800,
3213 .rx2 = 0x0a00,
3214 .ln_shrd = 0x0e00,
3215 };
3216
3217 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
3218 .serdes = 0x8800,
3219 .pcs = 0x9000,
3220 .pcs_misc = 0x9800,
3221 .tx = 0x0000,
3222 .rx = 0x0200,
3223 .txz = 0xe000,
3224 .rxz = 0xe200,
3225 .ln_shrd = 0x8000,
3226 };
3227
3228 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3229 .lanes = 1,
3230
3231 .offsets = &qmp_pcie_offsets_v2,
3232
3233 .tbls = {
3234 .serdes = ipq8074_pcie_serdes_tbl,
3235 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3236 .tx = ipq8074_pcie_tx_tbl,
3237 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3238 .rx = ipq8074_pcie_rx_tbl,
3239 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3240 .pcs = ipq8074_pcie_pcs_tbl,
3241 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
3242 },
3243 .reset_list = ipq8074_pciephy_reset_l,
3244 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3245 .vreg_list = NULL,
3246 .num_vregs = 0,
3247 .regs = pciephy_v2_regs_layout,
3248
3249 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3250 .phy_status = PHYSTATUS,
3251 };
3252
3253 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
3254 .lanes = 1,
3255
3256 .offsets = &qmp_pcie_offsets_v4x1,
3257
3258 .tbls = {
3259 .serdes = ipq8074_pcie_gen3_serdes_tbl,
3260 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
3261 .tx = ipq8074_pcie_gen3_tx_tbl,
3262 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
3263 .rx = ipq8074_pcie_gen3_rx_tbl,
3264 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
3265 .pcs = ipq8074_pcie_gen3_pcs_tbl,
3266 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
3267 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl,
3268 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
3269 },
3270 .reset_list = ipq8074_pciephy_reset_l,
3271 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3272 .vreg_list = NULL,
3273 .num_vregs = 0,
3274 .regs = pciephy_v4_regs_layout,
3275
3276 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3277 .phy_status = PHYSTATUS,
3278
3279 .pipe_clock_rate = 250000000,
3280 };
3281
3282 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3283 .lanes = 1,
3284
3285 .offsets = &qmp_pcie_offsets_v4x1,
3286
3287 .tbls = {
3288 .serdes = ipq6018_pcie_serdes_tbl,
3289 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3290 .tx = ipq6018_pcie_tx_tbl,
3291 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3292 .rx = ipq6018_pcie_rx_tbl,
3293 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3294 .pcs = ipq6018_pcie_pcs_tbl,
3295 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3296 .pcs_misc = ipq6018_pcie_pcs_misc_tbl,
3297 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
3298 },
3299 .reset_list = ipq8074_pciephy_reset_l,
3300 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3301 .vreg_list = NULL,
3302 .num_vregs = 0,
3303 .regs = pciephy_v4_regs_layout,
3304
3305 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3306 .phy_status = PHYSTATUS,
3307 };
3308
3309 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
3310 .lanes = 1,
3311
3312 .offsets = &qmp_pcie_offsets_v4x1,
3313
3314 .tbls = {
3315 .serdes = ipq9574_gen3x1_pcie_serdes_tbl,
3316 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
3317 .tx = ipq8074_pcie_gen3_tx_tbl,
3318 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
3319 .rx = ipq9574_pcie_rx_tbl,
3320 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
3321 .pcs = ipq9574_gen3x1_pcie_pcs_tbl,
3322 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
3323 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl,
3324 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
3325 },
3326 .reset_list = ipq8074_pciephy_reset_l,
3327 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3328 .vreg_list = NULL,
3329 .num_vregs = 0,
3330 .regs = pciephy_v4_regs_layout,
3331
3332 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3333 .phy_status = PHYSTATUS,
3334 .pipe_clock_rate = 250000000,
3335 };
3336
3337 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
3338 .lanes = 2,
3339
3340 .offsets = &qmp_pcie_offsets_ipq9574,
3341
3342 .tbls = {
3343 .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
3344 .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
3345 .tx = ipq8074_pcie_gen3_tx_tbl,
3346 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
3347 .rx = ipq9574_pcie_rx_tbl,
3348 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
3349 .pcs = ipq9574_gen3x2_pcie_pcs_tbl,
3350 .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),
3351 .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
3352 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
3353 },
3354 .reset_list = ipq8074_pciephy_reset_l,
3355 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3356 .vreg_list = NULL,
3357 .num_vregs = 0,
3358 .regs = pciephy_v5_regs_layout,
3359
3360 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3361 .phy_status = PHYSTATUS,
3362 .pipe_clock_rate = 250000000,
3363 };
3364
3365 static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
3366 .lanes = 1,
3367
3368 .offsets = &qmp_pcie_offsets_v2,
3369
3370 .tbls = {
3371 .serdes = qcs615_pcie_serdes_tbl,
3372 .serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl),
3373 .tx = qcs615_pcie_tx_tbl,
3374 .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl),
3375 .rx = qcs615_pcie_rx_tbl,
3376 .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl),
3377 .pcs = qcs615_pcie_pcs_tbl,
3378 .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl),
3379 },
3380 .reset_list = sdm845_pciephy_reset_l,
3381 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3382 .vreg_list = qmp_phy_vreg_l,
3383 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3384 .regs = pciephy_v2_regs_layout,
3385
3386 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3387 .phy_status = PHYSTATUS,
3388 };
3389
3390 static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
3391 .lanes = 2,
3392 .offsets = &qmp_pcie_offsets_v5_20,
3393
3394 .tbls = {
3395 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
3396 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
3397 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3398 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3399 .rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
3400 .rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
3401 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3402 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
3403 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3404 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3405 },
3406
3407 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3408 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
3409 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
3410 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3411 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3412 },
3413
3414 .reset_list = sdm845_pciephy_reset_l,
3415 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3416 .vreg_list = qmp_phy_vreg_l,
3417 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3418 .regs = pciephy_v5_regs_layout,
3419
3420 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3421 .phy_status = PHYSTATUS_4_20,
3422 };
3423
3424 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3425 .lanes = 1,
3426
3427 .offsets = &qmp_pcie_offsets_v3,
3428
3429 .tbls = {
3430 .serdes = sdm845_qmp_pcie_serdes_tbl,
3431 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3432 .tx = sdm845_qmp_pcie_tx_tbl,
3433 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3434 .rx = sdm845_qmp_pcie_rx_tbl,
3435 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3436 .pcs = sdm845_qmp_pcie_pcs_tbl,
3437 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3438 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl,
3439 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3440 },
3441 .reset_list = sdm845_pciephy_reset_l,
3442 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3443 .vreg_list = qmp_phy_vreg_l,
3444 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3445 .regs = pciephy_v3_regs_layout,
3446
3447 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3448 .phy_status = PHYSTATUS,
3449 };
3450
3451 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3452 .lanes = 1,
3453
3454 .offsets = &qmp_pcie_offsets_qhp,
3455
3456 .tbls = {
3457 .serdes = sdm845_qhp_pcie_serdes_tbl,
3458 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3459 .tx = sdm845_qhp_pcie_tx_tbl,
3460 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3461 .pcs = sdm845_qhp_pcie_pcs_tbl,
3462 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3463 },
3464 .reset_list = sdm845_pciephy_reset_l,
3465 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3466 .vreg_list = qmp_phy_vreg_l,
3467 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3468 .regs = sdm845_qhp_pciephy_regs_layout,
3469
3470 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3471 .phy_status = PHYSTATUS,
3472 };
3473
3474 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3475 .lanes = 1,
3476
3477 .offsets = &qmp_pcie_offsets_v4x1,
3478
3479 .tbls = {
3480 .serdes = sm8250_qmp_pcie_serdes_tbl,
3481 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3482 .tx = sm8250_qmp_pcie_tx_tbl,
3483 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3484 .rx = sm8250_qmp_pcie_rx_tbl,
3485 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3486 .pcs = sm8250_qmp_pcie_pcs_tbl,
3487 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3488 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
3489 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3490 },
3491 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3492 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3493 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3494 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl,
3495 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3496 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3497 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3498 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3499 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3500 },
3501 .reset_list = sdm845_pciephy_reset_l,
3502 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3503 .vreg_list = qmp_phy_vreg_l,
3504 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3505 .regs = pciephy_v4_regs_layout,
3506
3507 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3508 .phy_status = PHYSTATUS,
3509 };
3510
3511 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3512 .lanes = 2,
3513
3514 .offsets = &qmp_pcie_offsets_v4x2,
3515
3516 .tbls = {
3517 .serdes = sm8250_qmp_pcie_serdes_tbl,
3518 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3519 .tx = sm8250_qmp_pcie_tx_tbl,
3520 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3521 .rx = sm8250_qmp_pcie_rx_tbl,
3522 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3523 .pcs = sm8250_qmp_pcie_pcs_tbl,
3524 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3525 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
3526 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3527 },
3528 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3529 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
3530 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3531 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl,
3532 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3533 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3534 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3535 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3536 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3537 },
3538 .reset_list = sdm845_pciephy_reset_l,
3539 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3540 .vreg_list = qmp_phy_vreg_l,
3541 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3542 .regs = pciephy_v4_regs_layout,
3543
3544 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3545 .phy_status = PHYSTATUS,
3546 };
3547
3548 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3549 .lanes = 1,
3550
3551 .offsets = &qmp_pcie_offsets_v3,
3552
3553 .tbls = {
3554 .serdes = msm8998_pcie_serdes_tbl,
3555 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3556 .tx = msm8998_pcie_tx_tbl,
3557 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3558 .rx = msm8998_pcie_rx_tbl,
3559 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3560 .pcs = msm8998_pcie_pcs_tbl,
3561 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3562 },
3563 .reset_list = ipq8074_pciephy_reset_l,
3564 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3565 .vreg_list = qmp_phy_vreg_l,
3566 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3567 .regs = pciephy_v3_regs_layout,
3568
3569 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3570 .phy_status = PHYSTATUS,
3571
3572 .skip_start_delay = true,
3573 };
3574
3575 static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = {
3576 .lanes = 2,
3577
3578 .offsets = &qmp_pcie_offsets_v5,
3579
3580 .tbls = {
3581 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
3582 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
3583 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
3584 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
3585 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3586 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
3587 .pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl,
3588 .pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl),
3589 },
3590 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3591 .serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl,
3592 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl),
3593 .tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl,
3594 .tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl),
3595 .pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl,
3596 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl),
3597 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
3598 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
3599 },
3600 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3601 .serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl,
3602 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl),
3603 .pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl,
3604 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl),
3605 .pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl,
3606 .pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl),
3607 },
3608 .reset_list = sdm845_pciephy_reset_l,
3609 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3610 .vreg_list = qmp_phy_vreg_l,
3611 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3612 .regs = pciephy_v5_regs_layout,
3613
3614 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3615 .phy_status = PHYSTATUS,
3616 };
3617
3618 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3619 .lanes = 2,
3620
3621 .offsets = &qmp_pcie_offsets_v4x2,
3622
3623 .tbls = {
3624 .serdes = sc8180x_qmp_pcie_serdes_tbl,
3625 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
3626 .tx = sc8180x_qmp_pcie_tx_tbl,
3627 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3628 .rx = sc8180x_qmp_pcie_rx_tbl,
3629 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3630 .pcs = sc8180x_qmp_pcie_pcs_tbl,
3631 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3632 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl,
3633 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3634 },
3635 .reset_list = sdm845_pciephy_reset_l,
3636 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3637 .vreg_list = qmp_phy_vreg_l,
3638 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3639 .regs = pciephy_v4_regs_layout,
3640
3641 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3642 .phy_status = PHYSTATUS,
3643 };
3644
3645 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
3646 .lanes = 1,
3647
3648 .offsets = &qmp_pcie_offsets_v5,
3649
3650 .tbls = {
3651 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
3652 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3653 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
3654 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
3655 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
3656 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
3657 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
3658 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
3659 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
3660 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
3661 },
3662
3663 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3664 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
3665 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
3666 },
3667
3668 .reset_list = sdm845_pciephy_reset_l,
3669 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3670 .vreg_list = qmp_phy_vreg_l,
3671 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3672 .regs = pciephy_v5_regs_layout,
3673
3674 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3675 .phy_status = PHYSTATUS,
3676 };
3677
3678 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
3679 .lanes = 2,
3680
3681 .offsets = &qmp_pcie_offsets_v5,
3682
3683 .tbls = {
3684 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
3685 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3686 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3687 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
3688 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
3689 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
3690 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3691 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
3692 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3693 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3694 },
3695
3696 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3697 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
3698 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
3699 },
3700
3701 .reset_list = sdm845_pciephy_reset_l,
3702 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3703 .vreg_list = qmp_phy_vreg_l,
3704 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3705 .regs = pciephy_v5_regs_layout,
3706
3707 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3708 .phy_status = PHYSTATUS,
3709 };
3710
3711 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
3712 .lanes = 4,
3713
3714 .offsets = &qmp_pcie_offsets_v5,
3715
3716 .tbls = {
3717 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
3718 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3719 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3720 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
3721 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
3722 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
3723 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3724 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
3725 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3726 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3727 },
3728
3729 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3730 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
3731 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
3732 },
3733
3734 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
3735 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
3736
3737 .reset_list = sdm845_pciephy_reset_l,
3738 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3739 .vreg_list = qmp_phy_vreg_l,
3740 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3741 .regs = pciephy_v5_regs_layout,
3742
3743 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3744 .phy_status = PHYSTATUS,
3745 };
3746
3747 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3748 .lanes = 2,
3749
3750 .offsets = &qmp_pcie_offsets_v4_20,
3751
3752 .tbls = {
3753 .serdes = sdx55_qmp_pcie_serdes_tbl,
3754 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3755 .tx = sdx55_qmp_pcie_tx_tbl,
3756 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3757 .rx = sdx55_qmp_pcie_rx_tbl,
3758 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3759 .pcs = sdx55_qmp_pcie_pcs_tbl,
3760 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3761 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl,
3762 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3763 },
3764
3765 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3766 .serdes = sdx55_qmp_pcie_rc_serdes_tbl,
3767 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
3768 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
3769 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
3770 },
3771
3772 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3773 .serdes = sdx55_qmp_pcie_ep_serdes_tbl,
3774 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
3775 .pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl,
3776 .pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl),
3777 },
3778
3779 .reset_list = sdm845_pciephy_reset_l,
3780 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3781 .vreg_list = qmp_phy_vreg_l,
3782 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3783 .regs = pciephy_v4_regs_layout,
3784
3785 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3786 .phy_status = PHYSTATUS_4_20,
3787 };
3788
3789 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
3790 .lanes = 1,
3791
3792 .offsets = &qmp_pcie_offsets_v5,
3793
3794 .tbls = {
3795 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
3796 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3797 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
3798 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
3799 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
3800 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3801 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3802 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3803 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
3804 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
3805 },
3806
3807 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3808 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
3809 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
3810 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
3811 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
3812 },
3813
3814 .reset_list = sdm845_pciephy_reset_l,
3815 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3816 .vreg_list = qmp_phy_vreg_l,
3817 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3818 .regs = pciephy_v5_regs_layout,
3819
3820 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3821 .phy_status = PHYSTATUS,
3822 };
3823
3824 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
3825 .lanes = 2,
3826
3827 .offsets = &qmp_pcie_offsets_v5,
3828
3829 .tbls = {
3830 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
3831 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3832 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
3833 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
3834 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
3835 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3836 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3837 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3838 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3839 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3840 },
3841
3842 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3843 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
3844 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
3845 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
3846 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
3847 },
3848
3849 .reset_list = sdm845_pciephy_reset_l,
3850 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3851 .vreg_list = qmp_phy_vreg_l,
3852 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3853 .regs = pciephy_v5_regs_layout,
3854
3855 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3856 .phy_status = PHYSTATUS,
3857 };
3858
3859 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
3860 .lanes = 2,
3861
3862 .offsets = &qmp_pcie_offsets_v6_20,
3863
3864 .tbls = {
3865 .serdes = sdx65_qmp_pcie_serdes_tbl,
3866 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),
3867 .tx = sdx65_qmp_pcie_tx_tbl,
3868 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),
3869 .rx = sdx65_qmp_pcie_rx_tbl,
3870 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),
3871 .pcs = sdx65_qmp_pcie_pcs_tbl,
3872 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
3873 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
3874 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
3875 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
3876 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
3877 },
3878 .reset_list = sdm845_pciephy_reset_l,
3879 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3880 .vreg_list = qmp_phy_vreg_l,
3881 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3882 .regs = pciephy_v6_regs_layout,
3883
3884 .pwrdn_ctrl = SW_PWRDN,
3885 .phy_status = PHYSTATUS_4_20,
3886 };
3887
3888 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
3889 .lanes = 1,
3890
3891 .offsets = &qmp_pcie_offsets_v5,
3892
3893 .tbls = {
3894 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
3895 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3896 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
3897 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
3898 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
3899 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3900 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3901 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3902 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
3903 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
3904 },
3905
3906 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3907 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
3908 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
3909 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
3910 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
3911 },
3912
3913 .reset_list = sdm845_pciephy_reset_l,
3914 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3915 .vreg_list = qmp_phy_vreg_l,
3916 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3917 .regs = pciephy_v5_regs_layout,
3918
3919 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3920 .phy_status = PHYSTATUS,
3921 };
3922
3923 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
3924 .lanes = 2,
3925
3926 .offsets = &qmp_pcie_offsets_v5_20,
3927
3928 .tbls = {
3929 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl,
3930 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
3931 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
3932 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
3933 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl,
3934 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
3935 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
3936 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
3937 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
3938 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
3939 },
3940
3941 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3942 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
3943 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
3944 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
3945 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
3946 },
3947
3948 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3949 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
3950 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
3951 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
3952 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
3953 },
3954
3955 .reset_list = sdm845_pciephy_reset_l,
3956 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3957 .vreg_list = qmp_phy_vreg_l,
3958 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3959 .regs = pciephy_v5_regs_layout,
3960
3961 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3962 .phy_status = PHYSTATUS_4_20,
3963
3964 /* 20MHz PHY AUX Clock */
3965 .aux_clock_rate = 20000000,
3966 };
3967
3968 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
3969 .lanes = 2,
3970
3971 .offsets = &qmp_pcie_offsets_v5,
3972
3973 .tbls = {
3974 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
3975 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
3976 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
3977 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
3978 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
3979 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
3980 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3981 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
3982 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
3983 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
3984 },
3985 .reset_list = sdm845_pciephy_reset_l,
3986 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3987 .vreg_list = qmp_phy_vreg_l,
3988 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3989 .regs = pciephy_v5_regs_layout,
3990
3991 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3992 .phy_status = PHYSTATUS,
3993 };
3994
3995 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
3996 .lanes = 2,
3997
3998 .offsets = &qmp_pcie_offsets_v6_20,
3999
4000 .tbls = {
4001 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
4002 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
4003 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
4004 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
4005 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
4006 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
4007 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
4008 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
4009 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
4010 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
4011 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
4012 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
4013 },
4014 .reset_list = sdm845_pciephy_reset_l,
4015 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4016 .vreg_list = sm8550_qmp_phy_vreg_l,
4017 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
4018 .regs = pciephy_v6_regs_layout,
4019
4020 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4021 .phy_status = PHYSTATUS_4_20,
4022
4023 /* 20MHz PHY AUX Clock */
4024 .aux_clock_rate = 20000000,
4025 };
4026
4027 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
4028 .lanes = 2,
4029
4030 .offsets = &qmp_pcie_offsets_v6_20,
4031
4032 .tbls = {
4033 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
4034 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
4035 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
4036 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
4037 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl,
4038 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl),
4039 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
4040 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
4041 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
4042 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
4043 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
4044 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
4045 },
4046 .reset_list = sdm845_pciephy_reset_l,
4047 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4048 .vreg_list = sm8550_qmp_phy_vreg_l,
4049 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
4050 .regs = pciephy_v6_regs_layout,
4051
4052 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4053 .phy_status = PHYSTATUS_4_20,
4054
4055 /* 20MHz PHY AUX Clock */
4056 .aux_clock_rate = 20000000,
4057 };
4058
4059 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
4060 .lanes = 2,
4061 .offsets = &qmp_pcie_offsets_v5_20,
4062
4063 .tbls = {
4064 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
4065 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
4066 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
4067 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
4068 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
4069 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
4070 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
4071 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
4072 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4073 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
4074 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
4075 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
4076 },
4077
4078 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
4079 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
4080 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
4081 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
4082 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
4083 },
4084
4085 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
4086 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
4087 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
4088 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
4089 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
4090 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
4091 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),
4092 },
4093
4094 .reset_list = sdm845_pciephy_reset_l,
4095 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4096 .vreg_list = qmp_phy_vreg_l,
4097 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4098 .regs = pciephy_v5_regs_layout,
4099
4100 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4101 .phy_status = PHYSTATUS_4_20,
4102 };
4103
4104 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
4105 .lanes = 4,
4106 .offsets = &qmp_pcie_offsets_v5_30,
4107
4108 .tbls = {
4109 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl,
4110 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl),
4111 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
4112 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
4113 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
4114 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
4115 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
4116 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl),
4117 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4118 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
4119 },
4120
4121 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
4122 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl,
4123 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl),
4124 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
4125 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
4126 },
4127
4128 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
4129 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
4130 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
4131 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
4132 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
4133 },
4134
4135 .reset_list = sdm845_pciephy_reset_l,
4136 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4137 .vreg_list = qmp_phy_vreg_l,
4138 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4139 .regs = pciephy_v5_regs_layout,
4140
4141 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4142 .phy_status = PHYSTATUS_4_20,
4143 };
4144
4145 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
4146 .lanes = 2,
4147
4148 .offsets = &qmp_pcie_offsets_v6_20,
4149
4150 .tbls = {
4151 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
4152 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
4153 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
4154 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
4155 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
4156 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
4157 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
4158 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
4159 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
4160 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
4161 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
4162 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
4163 },
4164
4165 .reset_list = sdm845_pciephy_reset_l,
4166 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4167 .vreg_list = qmp_phy_vreg_l,
4168 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4169 .regs = pciephy_v6_regs_layout,
4170
4171 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4172 .phy_status = PHYSTATUS_4_20,
4173 };
4174
4175 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
4176 .lanes = 4,
4177
4178 .offsets = &qmp_pcie_offsets_v6_20,
4179
4180 .tbls = {
4181 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
4182 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
4183 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
4184 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
4185 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
4186 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
4187 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
4188 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
4189 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
4190 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
4191 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
4192 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
4193 },
4194
4195 .serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl,
4196 .serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl),
4197
4198 .reset_list = sdm845_pciephy_reset_l,
4199 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4200 .vreg_list = qmp_phy_vreg_l,
4201 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4202 .regs = pciephy_v6_regs_layout,
4203
4204 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4205 .phy_status = PHYSTATUS_4_20,
4206 };
4207
4208 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
4209 .lanes = 8,
4210
4211 .offsets = &qmp_pcie_offsets_v6_30,
4212 .tbls = {
4213 .serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl,
4214 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl),
4215 .rx = x1e80100_qmp_gen4x8_pcie_rx_tbl,
4216 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl),
4217 .txz = x1e80100_qmp_gen4x8_pcie_txz_tbl,
4218 .txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl),
4219 .rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl,
4220 .rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl),
4221 .pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl,
4222 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl),
4223 .pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl,
4224 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl),
4225 .ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl,
4226 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl),
4227 },
4228
4229 .reset_list = sdm845_pciephy_reset_l,
4230 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4231 .vreg_list = qmp_phy_vreg_l,
4232 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4233 .regs = pciephy_v6_regs_layout,
4234
4235 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4236 .phy_status = PHYSTATUS_4_20,
4237 };
4238
4239 static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
4240 .lanes = 4,
4241
4242 .offsets = &qmp_pcie_offsets_v6_20,
4243
4244 .reset_list = sdm845_pciephy_reset_l,
4245 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4246 .vreg_list = qmp_phy_vreg_l,
4247 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4248 .regs = pciephy_v6_regs_layout,
4249
4250 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4251 .phy_status = PHYSTATUS_4_20,
4252 };
4253
qmp_pcie_init_port_b(struct qmp_pcie * qmp,const struct qmp_phy_cfg_tbls * tbls)4254 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
4255 {
4256 const struct qmp_phy_cfg *cfg = qmp->cfg;
4257 const struct qmp_pcie_offsets *offs = cfg->offsets;
4258 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd;
4259
4260 serdes = qmp->port_b + offs->serdes;
4261 tx3 = qmp->port_b + offs->tx;
4262 rx3 = qmp->port_b + offs->rx;
4263 tx4 = qmp->port_b + offs->tx2;
4264 rx4 = qmp->port_b + offs->rx2;
4265 pcs = qmp->port_b + offs->pcs;
4266 pcs_misc = qmp->port_b + offs->pcs_misc;
4267 ln_shrd = qmp->port_b + offs->ln_shrd;
4268
4269 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
4270 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
4271
4272 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1);
4273 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1);
4274
4275 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2);
4276 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2);
4277
4278 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
4279 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
4280
4281 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
4282 }
4283
qmp_pcie_init_registers(struct qmp_pcie * qmp,const struct qmp_phy_cfg_tbls * tbls)4284 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
4285 {
4286 const struct qmp_phy_cfg *cfg = qmp->cfg;
4287 void __iomem *serdes = qmp->serdes;
4288 void __iomem *tx = qmp->tx;
4289 void __iomem *rx = qmp->rx;
4290 void __iomem *tx2 = qmp->tx2;
4291 void __iomem *rx2 = qmp->rx2;
4292 void __iomem *pcs = qmp->pcs;
4293 void __iomem *pcs_misc = qmp->pcs_misc;
4294 void __iomem *pcs_lane1 = qmp->pcs_lane1;
4295 void __iomem *ln_shrd = qmp->ln_shrd;
4296
4297 if (!tbls)
4298 return;
4299
4300 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
4301
4302 /*
4303 * Tx/Rx registers that require different settings than
4304 * txz/rxz must be programmed after txz/rxz.
4305 */
4306 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num);
4307 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num);
4308
4309 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
4310 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
4311
4312 if (cfg->lanes >= 2) {
4313 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2);
4314 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2);
4315 }
4316
4317 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
4318 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
4319 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);
4320
4321 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
4322 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,
4323 cfg->serdes_4ln_num);
4324 qmp_pcie_init_port_b(qmp, tbls);
4325 }
4326
4327 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
4328 }
4329
qmp_pcie_init(struct phy * phy)4330 static int qmp_pcie_init(struct phy *phy)
4331 {
4332 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4333 const struct qmp_phy_cfg *cfg = qmp->cfg;
4334 void __iomem *pcs = qmp->pcs;
4335 bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
4336 int ret;
4337
4338 qmp->skip_init = qmp->nocsr_reset && phy_initialized;
4339 /*
4340 * We need to check the existence of init sequences in two cases:
4341 * 1. The PHY doesn't support no_csr reset.
4342 * 2. The PHY supports no_csr reset but isn't initialized by bootloader.
4343 * As we can't skip init in these two cases.
4344 */
4345 if (!qmp->skip_init && !cfg->tbls.serdes_num) {
4346 dev_err(qmp->dev, "Init sequence not available\n");
4347 return -ENODATA;
4348 }
4349
4350 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
4351 if (ret) {
4352 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
4353 return ret;
4354 }
4355
4356 /*
4357 * Toggle BCR reset for PHY that doesn't support no_csr reset or has not
4358 * been initialized.
4359 */
4360 if (!qmp->skip_init) {
4361 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
4362 if (ret) {
4363 dev_err(qmp->dev, "reset assert failed\n");
4364 goto err_disable_regulators;
4365 }
4366 }
4367
4368 ret = reset_control_assert(qmp->nocsr_reset);
4369 if (ret) {
4370 dev_err(qmp->dev, "no-csr reset assert failed\n");
4371 goto err_assert_reset;
4372 }
4373
4374 usleep_range(200, 300);
4375
4376 if (!qmp->skip_init) {
4377 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
4378 if (ret) {
4379 dev_err(qmp->dev, "reset deassert failed\n");
4380 goto err_assert_reset;
4381 }
4382 }
4383
4384 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
4385 if (ret)
4386 goto err_assert_reset;
4387
4388 return 0;
4389
4390 err_assert_reset:
4391 if (!qmp->skip_init)
4392 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
4393 err_disable_regulators:
4394 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4395
4396 return ret;
4397 }
4398
qmp_pcie_exit(struct phy * phy)4399 static int qmp_pcie_exit(struct phy *phy)
4400 {
4401 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4402 const struct qmp_phy_cfg *cfg = qmp->cfg;
4403
4404 if (qmp->nocsr_reset)
4405 reset_control_assert(qmp->nocsr_reset);
4406 else
4407 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
4408
4409 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
4410
4411 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4412
4413 return 0;
4414 }
4415
qmp_pcie_power_on(struct phy * phy)4416 static int qmp_pcie_power_on(struct phy *phy)
4417 {
4418 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4419 const struct qmp_phy_cfg *cfg = qmp->cfg;
4420 const struct qmp_phy_cfg_tbls *mode_tbls;
4421 void __iomem *pcs = qmp->pcs;
4422 void __iomem *status;
4423 unsigned int mask, val;
4424 int ret;
4425
4426 /*
4427 * Write CSR register for PHY that doesn't support no_csr reset or has not
4428 * been initialized.
4429 */
4430 if (qmp->skip_init)
4431 goto skip_tbls_init;
4432
4433 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4434 cfg->pwrdn_ctrl);
4435
4436 if (qmp->mode == PHY_MODE_PCIE_RC)
4437 mode_tbls = cfg->tbls_rc;
4438 else
4439 mode_tbls = cfg->tbls_ep;
4440
4441 qmp_pcie_init_registers(qmp, &cfg->tbls);
4442 qmp_pcie_init_registers(qmp, mode_tbls);
4443
4444 skip_tbls_init:
4445 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
4446 if (ret)
4447 return ret;
4448
4449 ret = reset_control_deassert(qmp->nocsr_reset);
4450 if (ret) {
4451 dev_err(qmp->dev, "no-csr reset deassert failed\n");
4452 goto err_disable_pipe_clk;
4453 }
4454
4455 if (qmp->skip_init)
4456 goto skip_serdes_start;
4457
4458 /* Pull PHY out of reset state */
4459 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4460
4461 /* start SerDes and Phy-Coding-Sublayer */
4462 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
4463
4464 if (!cfg->skip_start_delay)
4465 usleep_range(1000, 1200);
4466
4467 skip_serdes_start:
4468 status = pcs + cfg->regs[QPHY_PCS_STATUS];
4469 mask = cfg->phy_status;
4470 ret = readl_poll_timeout(status, val, !(val & mask), 200,
4471 PHY_INIT_COMPLETE_TIMEOUT);
4472 if (ret) {
4473 dev_err(qmp->dev, "phy initialization timed-out\n");
4474 goto err_disable_pipe_clk;
4475 }
4476
4477 return 0;
4478
4479 err_disable_pipe_clk:
4480 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
4481
4482 return ret;
4483 }
4484
qmp_pcie_power_off(struct phy * phy)4485 static int qmp_pcie_power_off(struct phy *phy)
4486 {
4487 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4488 const struct qmp_phy_cfg *cfg = qmp->cfg;
4489
4490 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
4491
4492 /*
4493 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In
4494 * this way, no matter whether the PHY settings were initially programmed by
4495 * bootloader or PHY driver itself, we can reuse them when PHY is powered on
4496 * next time.
4497 */
4498 if (qmp->nocsr_reset)
4499 goto skip_phy_deinit;
4500
4501 /* PHY reset */
4502 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4503
4504 /* stop SerDes and Phy-Coding-Sublayer */
4505 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
4506 SERDES_START | PCS_START);
4507
4508 /* Put PHY into POWER DOWN state: active low */
4509 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4510 cfg->pwrdn_ctrl);
4511
4512 skip_phy_deinit:
4513 return 0;
4514 }
4515
qmp_pcie_enable(struct phy * phy)4516 static int qmp_pcie_enable(struct phy *phy)
4517 {
4518 int ret;
4519
4520 ret = qmp_pcie_init(phy);
4521 if (ret)
4522 return ret;
4523
4524 ret = qmp_pcie_power_on(phy);
4525 if (ret)
4526 qmp_pcie_exit(phy);
4527
4528 return ret;
4529 }
4530
qmp_pcie_disable(struct phy * phy)4531 static int qmp_pcie_disable(struct phy *phy)
4532 {
4533 int ret;
4534
4535 ret = qmp_pcie_power_off(phy);
4536 if (ret)
4537 return ret;
4538
4539 return qmp_pcie_exit(phy);
4540 }
4541
qmp_pcie_set_mode(struct phy * phy,enum phy_mode mode,int submode)4542 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
4543 {
4544 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4545
4546 switch (submode) {
4547 case PHY_MODE_PCIE_RC:
4548 case PHY_MODE_PCIE_EP:
4549 qmp->mode = submode;
4550 break;
4551 default:
4552 dev_err(&phy->dev, "Unsupported submode %d\n", submode);
4553 return -EINVAL;
4554 }
4555
4556 return 0;
4557 }
4558
4559 static const struct phy_ops qmp_pcie_phy_ops = {
4560 .power_on = qmp_pcie_enable,
4561 .power_off = qmp_pcie_disable,
4562 .set_mode = qmp_pcie_set_mode,
4563 .owner = THIS_MODULE,
4564 };
4565
qmp_pcie_vreg_init(struct qmp_pcie * qmp)4566 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
4567 {
4568 const struct qmp_phy_cfg *cfg = qmp->cfg;
4569 struct device *dev = qmp->dev;
4570 int num = cfg->num_vregs;
4571 int i;
4572
4573 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
4574 if (!qmp->vregs)
4575 return -ENOMEM;
4576
4577 for (i = 0; i < num; i++)
4578 qmp->vregs[i].supply = cfg->vreg_list[i];
4579
4580 return devm_regulator_bulk_get(dev, num, qmp->vregs);
4581 }
4582
qmp_pcie_reset_init(struct qmp_pcie * qmp)4583 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
4584 {
4585 const struct qmp_phy_cfg *cfg = qmp->cfg;
4586 struct device *dev = qmp->dev;
4587 int i;
4588 int ret;
4589
4590 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
4591 sizeof(*qmp->resets), GFP_KERNEL);
4592 if (!qmp->resets)
4593 return -ENOMEM;
4594
4595 for (i = 0; i < cfg->num_resets; i++)
4596 qmp->resets[i].id = cfg->reset_list[i];
4597
4598 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
4599 if (ret)
4600 return dev_err_probe(dev, ret, "failed to get resets\n");
4601
4602 qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");
4603 if (IS_ERR(qmp->nocsr_reset))
4604 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
4605 "failed to get no-csr reset\n");
4606
4607 return 0;
4608 }
4609
qmp_pcie_clk_init(struct qmp_pcie * qmp)4610 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
4611 {
4612 struct device *dev = qmp->dev;
4613 int num = ARRAY_SIZE(qmp_pciephy_clk_l);
4614 int i;
4615
4616 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
4617 if (!qmp->clks)
4618 return -ENOMEM;
4619
4620 for (i = 0; i < num; i++)
4621 qmp->clks[i].id = qmp_pciephy_clk_l[i];
4622
4623 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
4624 }
4625
phy_clk_release_provider(void * res)4626 static void phy_clk_release_provider(void *res)
4627 {
4628 of_clk_del_provider(res);
4629 }
4630
4631 /*
4632 * Register a fixed rate pipe clock.
4633 *
4634 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4635 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4636 * by the PHY driver for its operations.
4637 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4638 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
4639 * Below picture shows this relationship.
4640 *
4641 * +---------------+
4642 * | PHY block |<<---------------------------------------+
4643 * | | |
4644 * | +-------+ | +-----+ |
4645 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4646 * clk | +-------+ | +-----+
4647 * +---------------+
4648 */
phy_pipe_clk_register(struct qmp_pcie * qmp,struct device_node * np)4649 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
4650 {
4651 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
4652 struct clk_init_data init = { };
4653 int ret;
4654
4655 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name);
4656 if (ret) {
4657 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
4658 return ret;
4659 }
4660
4661 init.ops = &clk_fixed_rate_ops;
4662
4663 /*
4664 * Controllers using QMP PHY-s use 125MHz pipe clock interface
4665 * unless other frequency is specified in the PHY config.
4666 */
4667 if (qmp->cfg->pipe_clock_rate)
4668 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
4669 else
4670 fixed->fixed_rate = 125000000;
4671
4672 fixed->hw.init = &init;
4673
4674 return devm_clk_hw_register(qmp->dev, &fixed->hw);
4675 }
4676
4677 /*
4678 * Register a fixed rate PHY aux clock.
4679 *
4680 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
4681 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested
4682 * by the PHY driver for its operations.
4683 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care
4684 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk.
4685 * Below picture shows this relationship.
4686 *
4687 * +---------------+
4688 * | PHY block |<<---------------------------------------------+
4689 * | | |
4690 * | +-------+ | +-----+ |
4691 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4692 * clk | +-------+ | +-----+
4693 * +---------------+
4694 */
phy_aux_clk_register(struct qmp_pcie * qmp,struct device_node * np)4695 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
4696 {
4697 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
4698 struct clk_init_data init = { };
4699 char name[64];
4700
4701 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));
4702
4703 init.name = name;
4704 init.ops = &clk_fixed_rate_ops;
4705
4706 fixed->fixed_rate = qmp->cfg->aux_clock_rate;
4707 fixed->hw.init = &init;
4708
4709 return devm_clk_hw_register(qmp->dev, &fixed->hw);
4710 }
4711
qmp_pcie_clk_hw_get(struct of_phandle_args * clkspec,void * data)4712 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data)
4713 {
4714 struct qmp_pcie *qmp = data;
4715
4716 /* Support legacy bindings */
4717 if (!clkspec->args_count)
4718 return &qmp->pipe_clk_fixed.hw;
4719
4720 switch (clkspec->args[0]) {
4721 case QMP_PCIE_PIPE_CLK:
4722 return &qmp->pipe_clk_fixed.hw;
4723 case QMP_PCIE_PHY_AUX_CLK:
4724 return &qmp->aux_clk_fixed.hw;
4725 }
4726
4727 return ERR_PTR(-EINVAL);
4728 }
4729
qmp_pcie_register_clocks(struct qmp_pcie * qmp,struct device_node * np)4730 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)
4731 {
4732 int ret;
4733
4734 ret = phy_pipe_clk_register(qmp, np);
4735 if (ret)
4736 return ret;
4737
4738 if (qmp->cfg->aux_clock_rate) {
4739 ret = phy_aux_clk_register(qmp, np);
4740 if (ret)
4741 return ret;
4742
4743 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp);
4744 if (ret)
4745 return ret;
4746 } else {
4747 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);
4748 if (ret)
4749 return ret;
4750 }
4751
4752 /*
4753 * Roll a devm action because the clock provider is the child node, but
4754 * the child node is not actually a device.
4755 */
4756 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
4757 }
4758
qmp_pcie_parse_dt_legacy(struct qmp_pcie * qmp,struct device_node * np)4759 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
4760 {
4761 struct platform_device *pdev = to_platform_device(qmp->dev);
4762 const struct qmp_phy_cfg *cfg = qmp->cfg;
4763 struct device *dev = qmp->dev;
4764 struct clk *clk;
4765
4766 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
4767 if (IS_ERR(qmp->serdes))
4768 return PTR_ERR(qmp->serdes);
4769
4770 /*
4771 * Get memory resources for the PHY:
4772 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
4773 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
4774 * For single lane PHYs: pcs_misc (optional) -> 3.
4775 */
4776 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
4777 if (IS_ERR(qmp->tx))
4778 return PTR_ERR(qmp->tx);
4779
4780 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
4781 qmp->rx = qmp->tx;
4782 else
4783 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
4784 if (IS_ERR(qmp->rx))
4785 return PTR_ERR(qmp->rx);
4786
4787 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
4788 if (IS_ERR(qmp->pcs))
4789 return PTR_ERR(qmp->pcs);
4790
4791 if (cfg->lanes >= 2) {
4792 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
4793 if (IS_ERR(qmp->tx2))
4794 return PTR_ERR(qmp->tx2);
4795
4796 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
4797 if (IS_ERR(qmp->rx2))
4798 return PTR_ERR(qmp->rx2);
4799
4800 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
4801 } else {
4802 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
4803 }
4804
4805 if (IS_ERR(qmp->pcs_misc) &&
4806 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
4807 qmp->pcs_misc = qmp->pcs + 0x400;
4808
4809 if (IS_ERR(qmp->pcs_misc)) {
4810 if (cfg->tbls.pcs_misc ||
4811 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
4812 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
4813 return PTR_ERR(qmp->pcs_misc);
4814 }
4815 }
4816
4817 /*
4818 * For all platforms where legacy bindings existed, PCS_LANE1 was
4819 * mapped as a part of the PCS_MISC region.
4820 */
4821 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0)
4822 qmp->pcs_lane1 = qmp->pcs_misc +
4823 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc);
4824
4825 clk = devm_get_clk_from_child(dev, np, NULL);
4826 if (IS_ERR(clk)) {
4827 return dev_err_probe(dev, PTR_ERR(clk),
4828 "failed to get pipe clock\n");
4829 }
4830
4831 qmp->num_pipe_clks = 1;
4832 qmp->pipe_clks[0].id = "pipe";
4833 qmp->pipe_clks[0].clk = clk;
4834
4835 return 0;
4836 }
4837
qmp_pcie_get_4ln_config(struct qmp_pcie * qmp)4838 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
4839 {
4840 struct regmap *tcsr;
4841 unsigned int args[2];
4842 int ret;
4843
4844 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
4845 "qcom,4ln-config-sel",
4846 ARRAY_SIZE(args), args);
4847 if (IS_ERR(tcsr)) {
4848 ret = PTR_ERR(tcsr);
4849 if (ret == -ENOENT)
4850 return 0;
4851
4852 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
4853 return ret;
4854 }
4855
4856 ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
4857 if (ret < 0) {
4858 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
4859 return ret;
4860 }
4861
4862 qmp->tcsr_4ln_config = ret;
4863
4864 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
4865
4866 return 0;
4867 }
4868
qmp_pcie_parse_dt(struct qmp_pcie * qmp)4869 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
4870 {
4871 struct platform_device *pdev = to_platform_device(qmp->dev);
4872 const struct qmp_phy_cfg *cfg = qmp->cfg;
4873 const struct qmp_pcie_offsets *offs = cfg->offsets;
4874 struct device *dev = qmp->dev;
4875 void __iomem *base;
4876 int ret;
4877
4878 if (!offs)
4879 return -EINVAL;
4880
4881 ret = qmp_pcie_get_4ln_config(qmp);
4882 if (ret)
4883 return ret;
4884
4885 base = devm_platform_ioremap_resource(pdev, 0);
4886 if (IS_ERR(base))
4887 return PTR_ERR(base);
4888
4889 qmp->serdes = base + offs->serdes;
4890 qmp->pcs = base + offs->pcs;
4891 qmp->pcs_misc = base + offs->pcs_misc;
4892 qmp->pcs_lane1 = base + offs->pcs_lane1;
4893 qmp->tx = base + offs->tx;
4894 qmp->rx = base + offs->rx;
4895
4896 if (cfg->lanes >= 2) {
4897 qmp->tx2 = base + offs->tx2;
4898 qmp->rx2 = base + offs->rx2;
4899 }
4900
4901 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
4902 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
4903 if (IS_ERR(qmp->port_b))
4904 return PTR_ERR(qmp->port_b);
4905 }
4906
4907 qmp->txz = base + offs->txz;
4908 qmp->rxz = base + offs->rxz;
4909
4910 if (cfg->tbls.ln_shrd)
4911 qmp->ln_shrd = base + offs->ln_shrd;
4912
4913 qmp->num_pipe_clks = 2;
4914 qmp->pipe_clks[0].id = "pipe";
4915 qmp->pipe_clks[1].id = "pipediv2";
4916
4917 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
4918 if (ret)
4919 return ret;
4920
4921 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
4922 if (ret)
4923 return ret;
4924
4925 return 0;
4926 }
4927
qmp_pcie_probe(struct platform_device * pdev)4928 static int qmp_pcie_probe(struct platform_device *pdev)
4929 {
4930 struct device *dev = &pdev->dev;
4931 struct phy_provider *phy_provider;
4932 struct device_node *np;
4933 struct qmp_pcie *qmp;
4934 int ret;
4935
4936 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
4937 if (!qmp)
4938 return -ENOMEM;
4939
4940 qmp->dev = dev;
4941
4942 qmp->cfg = of_device_get_match_data(dev);
4943 if (!qmp->cfg)
4944 return -EINVAL;
4945
4946 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
4947 WARN_ON_ONCE(!qmp->cfg->phy_status);
4948
4949 ret = qmp_pcie_clk_init(qmp);
4950 if (ret)
4951 return ret;
4952
4953 ret = qmp_pcie_reset_init(qmp);
4954 if (ret)
4955 return ret;
4956
4957 ret = qmp_pcie_vreg_init(qmp);
4958 if (ret)
4959 return ret;
4960
4961 /* Check for legacy binding with child node. */
4962 np = of_get_next_available_child(dev->of_node, NULL);
4963 if (np) {
4964 ret = qmp_pcie_parse_dt_legacy(qmp, np);
4965 } else {
4966 np = of_node_get(dev->of_node);
4967 ret = qmp_pcie_parse_dt(qmp);
4968 }
4969 if (ret)
4970 goto err_node_put;
4971
4972 ret = qmp_pcie_register_clocks(qmp, np);
4973 if (ret)
4974 goto err_node_put;
4975
4976 qmp->mode = PHY_MODE_PCIE_RC;
4977
4978 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
4979 if (IS_ERR(qmp->phy)) {
4980 ret = PTR_ERR(qmp->phy);
4981 dev_err(dev, "failed to create PHY: %d\n", ret);
4982 goto err_node_put;
4983 }
4984
4985 phy_set_drvdata(qmp->phy, qmp);
4986
4987 of_node_put(np);
4988
4989 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
4990
4991 return PTR_ERR_OR_ZERO(phy_provider);
4992
4993 err_node_put:
4994 of_node_put(np);
4995 return ret;
4996 }
4997
4998 static const struct of_device_id qmp_pcie_of_match_table[] = {
4999 {
5000 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5001 .data = &ipq6018_pciephy_cfg,
5002 }, {
5003 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
5004 .data = &ipq8074_pciephy_gen3_cfg,
5005 }, {
5006 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5007 .data = &ipq8074_pciephy_cfg,
5008 }, {
5009 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
5010 .data = &ipq9574_gen3x1_pciephy_cfg,
5011 }, {
5012 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
5013 .data = &ipq9574_gen3x2_pciephy_cfg,
5014 }, {
5015 .compatible = "qcom,msm8998-qmp-pcie-phy",
5016 .data = &msm8998_pciephy_cfg,
5017 }, {
5018 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
5019 .data = &qcs615_pciephy_cfg,
5020 }, {
5021 .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
5022 .data = &qcs8300_qmp_gen4x2_pciephy_cfg,
5023 }, {
5024 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
5025 .data = &sa8775p_qmp_gen4x2_pciephy_cfg,
5026 }, {
5027 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
5028 .data = &sa8775p_qmp_gen4x4_pciephy_cfg,
5029 }, {
5030 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
5031 .data = &sar2130p_qmp_gen3x2_pciephy_cfg,
5032 }, {
5033 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5034 .data = &sc8180x_pciephy_cfg,
5035 }, {
5036 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
5037 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
5038 }, {
5039 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
5040 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
5041 }, {
5042 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
5043 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
5044 }, {
5045 .compatible = "qcom,sdm845-qhp-pcie-phy",
5046 .data = &sdm845_qhp_pciephy_cfg,
5047 }, {
5048 .compatible = "qcom,sdm845-qmp-pcie-phy",
5049 .data = &sdm845_qmp_pciephy_cfg,
5050 }, {
5051 .compatible = "qcom,sdx55-qmp-pcie-phy",
5052 .data = &sdx55_qmp_pciephy_cfg,
5053 }, {
5054 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
5055 .data = &sdx65_qmp_pciephy_cfg,
5056 }, {
5057 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
5058 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5059 }, {
5060 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
5061 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5062 }, {
5063 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5064 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5065 }, {
5066 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5067 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5068 }, {
5069 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5070 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5071 }, {
5072 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
5073 .data = &sm8350_qmp_gen3x1_pciephy_cfg,
5074 }, {
5075 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
5076 .data = &sm8350_qmp_gen3x2_pciephy_cfg,
5077 }, {
5078 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
5079 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
5080 }, {
5081 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
5082 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
5083 }, {
5084 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
5085 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
5086 }, {
5087 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
5088 .data = &sm8550_qmp_gen4x2_pciephy_cfg,
5089 }, {
5090 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
5091 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
5092 }, {
5093 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
5094 .data = &sm8650_qmp_gen4x2_pciephy_cfg,
5095 }, {
5096 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
5097 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
5098 }, {
5099 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
5100 .data = &x1e80100_qmp_gen4x2_pciephy_cfg,
5101 }, {
5102 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
5103 .data = &x1e80100_qmp_gen4x4_pciephy_cfg,
5104 }, {
5105 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
5106 .data = &x1e80100_qmp_gen4x8_pciephy_cfg,
5107 }, {
5108 .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
5109 .data = &qmp_v6_gen4x4_pciephy_cfg,
5110 },
5111 { },
5112 };
5113 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
5114
5115 static struct platform_driver qmp_pcie_driver = {
5116 .probe = qmp_pcie_probe,
5117 .driver = {
5118 .name = "qcom-qmp-pcie-phy",
5119 .of_match_table = qmp_pcie_of_match_table,
5120 },
5121 };
5122
5123 module_platform_driver(qmp_pcie_driver);
5124
5125 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
5126 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
5127 MODULE_LICENSE("GPL v2");
5128