1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale MXS I2C bus driver
4 *
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
7 *
8 * based on a (non-working) driver which was:
9 *
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
11 */
12
13 #include <linux/slab.h>
14 #include <linux/device.h>
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/err.h>
18 #include <linux/interrupt.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/jiffies.h>
22 #include <linux/io.h>
23 #include <linux/stmp_device.h>
24 #include <linux/of.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma/mxs-dma.h>
28
29 #define DRIVER_NAME "mxs-i2c"
30
31 #define MXS_I2C_CTRL0 (0x00)
32 #define MXS_I2C_CTRL0_SET (0x04)
33 #define MXS_I2C_CTRL0_CLR (0x08)
34
35 #define MXS_I2C_CTRL0_SFTRST 0x80000000
36 #define MXS_I2C_CTRL0_RUN 0x20000000
37 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
38 #define MXS_I2C_CTRL0_PIO_MODE 0x01000000
39 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
40 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
41 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
42 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
43 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
44 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
45
46 #define MXS_I2C_TIMING0 (0x10)
47 #define MXS_I2C_TIMING1 (0x20)
48 #define MXS_I2C_TIMING2 (0x30)
49
50 #define MXS_I2C_CTRL1 (0x40)
51 #define MXS_I2C_CTRL1_SET (0x44)
52 #define MXS_I2C_CTRL1_CLR (0x48)
53
54 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
55 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
56 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
57 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
58 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
59 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
60 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
61 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
62 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
63
64 #define MXS_I2C_STAT (0x50)
65 #define MXS_I2C_STAT_GOT_A_NAK 0x10000000
66 #define MXS_I2C_STAT_BUS_BUSY 0x00000800
67 #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
68
69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
70
71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
72
73 #define MXS_I2C_DEBUG0_DMAREQ 0x80000000
74
75 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
76 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
77 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
78 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
79 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
80 MXS_I2C_CTRL1_SLAVE_IRQ)
81
82
83 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
84 MXS_I2C_CTRL0_PRE_SEND_START | \
85 MXS_I2C_CTRL0_MASTER_MODE | \
86 MXS_I2C_CTRL0_DIRECTION | \
87 MXS_I2C_CTRL0_XFER_COUNT(1))
88
89 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
90 MXS_I2C_CTRL0_MASTER_MODE | \
91 MXS_I2C_CTRL0_DIRECTION)
92
93 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
94 MXS_I2C_CTRL0_MASTER_MODE)
95
96 enum mxs_i2c_devtype {
97 MXS_I2C_UNKNOWN = 0,
98 MXS_I2C_V1,
99 MXS_I2C_V2,
100 };
101
102 /**
103 * struct mxs_i2c_dev - per device, private MXS-I2C data
104 *
105 * @dev: driver model device node
106 * @dev_type: distinguish i.MX23/i.MX28 features
107 * @regs: IO registers pointer
108 * @cmd_complete: completion object for transaction wait
109 * @cmd_err: error code for last transaction
110 * @adapter: i2c subsystem adapter node
111 * @timing0: I2C TIMING0 register value
112 * @timing1: I2C TIMING1 register value
113 * @timing2: I2C TIMING2 register value
114 * @dmach: DMA channel
115 * @pio_data: PIO data for DMA
116 * @addr_data: address data for DMA
117 * @sg_io: scatterlist for I/O
118 * @dma_read: flag indicating DMA read
119 */
120 struct mxs_i2c_dev {
121 struct device *dev;
122 enum mxs_i2c_devtype dev_type;
123 void __iomem *regs;
124 struct completion cmd_complete;
125 int cmd_err;
126 struct i2c_adapter adapter;
127
128 uint32_t timing0;
129 uint32_t timing1;
130 uint32_t timing2;
131
132 /* DMA support components */
133 struct dma_chan *dmach;
134 uint32_t pio_data[2];
135 uint32_t addr_data;
136 struct scatterlist sg_io[2];
137 bool dma_read;
138 };
139
mxs_i2c_reset(struct mxs_i2c_dev * i2c)140 static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
141 {
142 int ret = stmp_reset_block(i2c->regs);
143 if (ret)
144 return ret;
145
146 /*
147 * Configure timing for the I2C block. The I2C TIMING2 register has to
148 * be programmed with this particular magic number. The rest is derived
149 * from the XTAL speed and requested I2C speed.
150 *
151 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
152 */
153 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
154 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
155 writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
156
157 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
158
159 return 0;
160 }
161
mxs_i2c_dma_finish(struct mxs_i2c_dev * i2c)162 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
163 {
164 if (i2c->dma_read) {
165 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
166 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
167 } else {
168 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
169 }
170 }
171
mxs_i2c_dma_irq_callback(void * param)172 static void mxs_i2c_dma_irq_callback(void *param)
173 {
174 struct mxs_i2c_dev *i2c = param;
175
176 complete(&i2c->cmd_complete);
177 mxs_i2c_dma_finish(i2c);
178 }
179
mxs_i2c_dma_setup_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,u8 * buf,uint32_t flags)180 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
181 struct i2c_msg *msg, u8 *buf, uint32_t flags)
182 {
183 struct dma_async_tx_descriptor *desc;
184 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
185
186 i2c->addr_data = i2c_8bit_addr_from_msg(msg);
187
188 if (msg->flags & I2C_M_RD) {
189 i2c->dma_read = true;
190
191 /*
192 * SELECT command.
193 */
194
195 /* Queue the PIO register write transfer. */
196 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
197 desc = dmaengine_prep_slave_sg(i2c->dmach,
198 (struct scatterlist *)&i2c->pio_data[0],
199 1, DMA_TRANS_NONE, 0);
200 if (!desc) {
201 dev_err(i2c->dev,
202 "Failed to get PIO reg. write descriptor.\n");
203 goto select_init_pio_fail;
204 }
205
206 /* Queue the DMA data transfer. */
207 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
208 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
209 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
210 DMA_MEM_TO_DEV,
211 DMA_PREP_INTERRUPT |
212 MXS_DMA_CTRL_WAIT4END);
213 if (!desc) {
214 dev_err(i2c->dev,
215 "Failed to get DMA data write descriptor.\n");
216 goto select_init_dma_fail;
217 }
218
219 /*
220 * READ command.
221 */
222
223 /* Queue the PIO register write transfer. */
224 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
225 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
226 desc = dmaengine_prep_slave_sg(i2c->dmach,
227 (struct scatterlist *)&i2c->pio_data[1],
228 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
229 if (!desc) {
230 dev_err(i2c->dev,
231 "Failed to get PIO reg. write descriptor.\n");
232 goto select_init_dma_fail;
233 }
234
235 /* Queue the DMA data transfer. */
236 sg_init_one(&i2c->sg_io[1], buf, msg->len);
237 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
238 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
239 DMA_DEV_TO_MEM,
240 DMA_PREP_INTERRUPT |
241 MXS_DMA_CTRL_WAIT4END);
242 if (!desc) {
243 dev_err(i2c->dev,
244 "Failed to get DMA data write descriptor.\n");
245 goto read_init_dma_fail;
246 }
247 } else {
248 i2c->dma_read = false;
249
250 /*
251 * WRITE command.
252 */
253
254 /* Queue the PIO register write transfer. */
255 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
256 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
257 desc = dmaengine_prep_slave_sg(i2c->dmach,
258 (struct scatterlist *)&i2c->pio_data[0],
259 1, DMA_TRANS_NONE, 0);
260 if (!desc) {
261 dev_err(i2c->dev,
262 "Failed to get PIO reg. write descriptor.\n");
263 goto write_init_pio_fail;
264 }
265
266 /* Queue the DMA data transfer. */
267 sg_init_table(i2c->sg_io, 2);
268 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
269 sg_set_buf(&i2c->sg_io[1], buf, msg->len);
270 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
271 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
272 DMA_MEM_TO_DEV,
273 DMA_PREP_INTERRUPT |
274 MXS_DMA_CTRL_WAIT4END);
275 if (!desc) {
276 dev_err(i2c->dev,
277 "Failed to get DMA data write descriptor.\n");
278 goto write_init_dma_fail;
279 }
280 }
281
282 /*
283 * The last descriptor must have this callback,
284 * to finish the DMA transaction.
285 */
286 desc->callback = mxs_i2c_dma_irq_callback;
287 desc->callback_param = i2c;
288
289 /* Start the transfer. */
290 dmaengine_submit(desc);
291 dma_async_issue_pending(i2c->dmach);
292 return 0;
293
294 /* Read failpath. */
295 read_init_dma_fail:
296 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
297 select_init_dma_fail:
298 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
299 select_init_pio_fail:
300 dmaengine_terminate_sync(i2c->dmach);
301 return -EINVAL;
302
303 /* Write failpath. */
304 write_init_dma_fail:
305 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
306 write_init_pio_fail:
307 dmaengine_terminate_sync(i2c->dmach);
308 return -EINVAL;
309 }
310
mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev * i2c)311 static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
312 {
313 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
314
315 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
316 if (readl(i2c->regs + MXS_I2C_CTRL1) &
317 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
318 return -ENXIO;
319 if (time_after(jiffies, timeout))
320 return -ETIMEDOUT;
321 cond_resched();
322 }
323
324 return 0;
325 }
326
mxs_i2c_pio_check_error_state(struct mxs_i2c_dev * i2c)327 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
328 {
329 u32 state;
330
331 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
332
333 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
334 i2c->cmd_err = -ENXIO;
335 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
336 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
337 MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
338 MXS_I2C_CTRL1_SLAVE_IRQ))
339 i2c->cmd_err = -EIO;
340
341 return i2c->cmd_err;
342 }
343
mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev * i2c,u32 cmd)344 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
345 {
346 u32 reg;
347
348 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
349
350 /* readback makes sure the write is latched into hardware */
351 reg = readl(i2c->regs + MXS_I2C_CTRL0);
352 reg |= MXS_I2C_CTRL0_RUN;
353 writel(reg, i2c->regs + MXS_I2C_CTRL0);
354 }
355
356 /*
357 * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
358 * CTRL0::PIO_MODE bit description clarifies the order in which the registers
359 * must be written during PIO mode operation. First, the CTRL0 register has
360 * to be programmed with all the necessary bits but the RUN bit. Then the
361 * payload has to be written into the DATA register. Finally, the transmission
362 * is executed by setting the RUN bit in CTRL0.
363 */
mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev * i2c,u32 cmd,u32 data)364 static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
365 u32 data)
366 {
367 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
368
369 if (i2c->dev_type == MXS_I2C_V1)
370 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
371
372 writel(data, i2c->regs + MXS_I2C_DATA(i2c));
373 writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
374 }
375
mxs_i2c_pio_setup_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,uint32_t flags)376 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
377 struct i2c_msg *msg, uint32_t flags)
378 {
379 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
380 uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
381 uint32_t data = 0;
382 int i, ret, xlen = 0, xmit = 0;
383 uint32_t start;
384
385 /* Mute IRQs coming from this block. */
386 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
387
388 /*
389 * MX23 idea:
390 * - Enable CTRL0::PIO_MODE (1 << 24)
391 * - Enable CTRL1::ACK_MODE (1 << 27)
392 *
393 * WARNING! The MX23 is broken in some way, even if it claims
394 * to support PIO, when we try to transfer any amount of data
395 * that is not aligned to 4 bytes, the DMA engine will have
396 * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
397 * transfer. This in turn will mess up the next transfer as
398 * the block it emit one byte write onto the bus terminated
399 * with a NAK+STOP. A possible workaround is to reset the IP
400 * block after every PIO transmission, which might just work.
401 *
402 * NOTE: The CTRL0::PIO_MODE description is important, since
403 * it outlines how the PIO mode is really supposed to work.
404 */
405 if (msg->flags & I2C_M_RD) {
406 /*
407 * PIO READ transfer:
408 *
409 * This transfer MUST be limited to 4 bytes maximum. It is not
410 * possible to transfer more than four bytes via PIO, since we
411 * can not in any way make sure we can read the data from the
412 * DATA register fast enough. Besides, the RX FIFO is only four
413 * bytes deep, thus we can only really read up to four bytes at
414 * time. Finally, there is no bit indicating us that new data
415 * arrived at the FIFO and can thus be fetched from the DATA
416 * register.
417 */
418 BUG_ON(msg->len > 4);
419
420 /* SELECT command. */
421 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
422 addr_data);
423
424 ret = mxs_i2c_pio_wait_xfer_end(i2c);
425 if (ret) {
426 dev_dbg(i2c->dev,
427 "PIO: Failed to send SELECT command!\n");
428 goto cleanup;
429 }
430
431 /* READ command. */
432 mxs_i2c_pio_trigger_cmd(i2c,
433 MXS_CMD_I2C_READ | flags |
434 MXS_I2C_CTRL0_XFER_COUNT(msg->len));
435
436 ret = mxs_i2c_pio_wait_xfer_end(i2c);
437 if (ret) {
438 dev_dbg(i2c->dev,
439 "PIO: Failed to send READ command!\n");
440 goto cleanup;
441 }
442
443 data = readl(i2c->regs + MXS_I2C_DATA(i2c));
444 for (i = 0; i < msg->len; i++) {
445 msg->buf[i] = data & 0xff;
446 data >>= 8;
447 }
448 } else {
449 /*
450 * PIO WRITE transfer:
451 *
452 * The code below implements clock stretching to circumvent
453 * the possibility of kernel not being able to supply data
454 * fast enough. It is possible to transfer arbitrary amount
455 * of data using PIO write.
456 */
457
458 /*
459 * The LSB of data buffer is the first byte blasted across
460 * the bus. Higher order bytes follow. Thus the following
461 * filling schematic.
462 */
463
464 data = addr_data << 24;
465
466 /* Start the transfer with START condition. */
467 start = MXS_I2C_CTRL0_PRE_SEND_START;
468
469 /* If the transfer is long, use clock stretching. */
470 if (msg->len > 3)
471 start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
472
473 for (i = 0; i < msg->len; i++) {
474 data >>= 8;
475 data |= (msg->buf[i] << 24);
476
477 xmit = 0;
478
479 /* This is the last transfer of the message. */
480 if (i + 1 == msg->len) {
481 /* Add optional STOP flag. */
482 start |= flags;
483 /* Remove RETAIN_CLOCK bit. */
484 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
485 xmit = 1;
486 }
487
488 /* Four bytes are ready in the "data" variable. */
489 if ((i & 3) == 2)
490 xmit = 1;
491
492 /* Nothing interesting happened, continue stuffing. */
493 if (!xmit)
494 continue;
495
496 /*
497 * Compute the size of the transfer and shift the
498 * data accordingly.
499 *
500 * i = (4k + 0) .... xlen = 2
501 * i = (4k + 1) .... xlen = 3
502 * i = (4k + 2) .... xlen = 4
503 * i = (4k + 3) .... xlen = 1
504 */
505
506 if ((i % 4) == 3)
507 xlen = 1;
508 else
509 xlen = (i % 4) + 2;
510
511 data >>= (4 - xlen) * 8;
512
513 dev_dbg(i2c->dev,
514 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
515 xlen, i, msg->len,
516 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
517 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
518 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
519
520 writel(MXS_I2C_DEBUG0_DMAREQ,
521 i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
522
523 mxs_i2c_pio_trigger_write_cmd(i2c,
524 start | MXS_I2C_CTRL0_MASTER_MODE |
525 MXS_I2C_CTRL0_DIRECTION |
526 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
527
528 /* The START condition is sent only once. */
529 start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
530
531 /* Wait for the end of the transfer. */
532 ret = mxs_i2c_pio_wait_xfer_end(i2c);
533 if (ret) {
534 dev_dbg(i2c->dev,
535 "PIO: Failed to finish WRITE cmd!\n");
536 break;
537 }
538
539 /* Check NAK here. */
540 ret = readl(i2c->regs + MXS_I2C_STAT) &
541 MXS_I2C_STAT_GOT_A_NAK;
542 if (ret) {
543 ret = -ENXIO;
544 goto cleanup;
545 }
546 }
547 }
548
549 /* make sure we capture any occurred error into cmd_err */
550 ret = mxs_i2c_pio_check_error_state(i2c);
551
552 cleanup:
553 /* Clear any dangling IRQs and re-enable interrupts. */
554 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
555 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
556
557 /* Clear the PIO_MODE on i.MX23 */
558 if (i2c->dev_type == MXS_I2C_V1)
559 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
560
561 return ret;
562 }
563
564 /*
565 * Low level master read/write transaction.
566 */
mxs_i2c_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)567 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
568 int stop)
569 {
570 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
571 int ret;
572 int flags;
573 u8 *dma_buf;
574 int use_pio = 0;
575 unsigned long time_left;
576
577 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
578
579 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
580 msg->addr, msg->len, msg->flags, stop);
581
582 /*
583 * The MX28 I2C IP block can only do PIO READ for transfer of to up
584 * 4 bytes of length. The write transfer is not limited as it can use
585 * clock stretching to avoid FIFO underruns.
586 */
587 if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
588 use_pio = 1;
589 if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
590 use_pio = 1;
591
592 i2c->cmd_err = 0;
593 if (use_pio) {
594 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
595 /* No need to reset the block if NAK was received. */
596 if (ret && (ret != -ENXIO))
597 mxs_i2c_reset(i2c);
598 } else {
599 dma_buf = i2c_get_dma_safe_msg_buf(msg, 1);
600 if (!dma_buf)
601 return -ENOMEM;
602
603 reinit_completion(&i2c->cmd_complete);
604 ret = mxs_i2c_dma_setup_xfer(adap, msg, dma_buf, flags);
605 if (ret) {
606 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
607 return ret;
608 }
609
610 time_left = wait_for_completion_timeout(&i2c->cmd_complete,
611 msecs_to_jiffies(1000));
612 i2c_put_dma_safe_msg_buf(dma_buf, msg, true);
613 if (!time_left)
614 goto timeout;
615
616 ret = i2c->cmd_err;
617 }
618
619 if (ret == -ENXIO) {
620 /*
621 * If the transfer fails with a NAK from the slave the
622 * controller halts until it gets told to return to idle state.
623 */
624 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
625 i2c->regs + MXS_I2C_CTRL1_SET);
626 }
627
628 /*
629 * WARNING!
630 * The i.MX23 is strange. After each and every operation, it's I2C IP
631 * block must be reset, otherwise the IP block will misbehave. This can
632 * be observed on the bus by the block sending out one single byte onto
633 * the bus. In case such an error happens, bit 27 will be set in the
634 * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
635 * and is marked as "TBD" instead. To reset this bit to a correct state,
636 * reset the whole block. Since the block reset does not take long, do
637 * reset the block after every transfer to play safe.
638 */
639 if (i2c->dev_type == MXS_I2C_V1)
640 mxs_i2c_reset(i2c);
641
642 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
643
644 return ret;
645
646 timeout:
647 dev_dbg(i2c->dev, "Timeout!\n");
648 mxs_i2c_dma_finish(i2c);
649 ret = mxs_i2c_reset(i2c);
650 if (ret)
651 return ret;
652
653 return -ETIMEDOUT;
654 }
655
mxs_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)656 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
657 int num)
658 {
659 int i;
660 int err;
661
662 for (i = 0; i < num; i++) {
663 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
664 if (err)
665 return err;
666 }
667
668 return num;
669 }
670
mxs_i2c_func(struct i2c_adapter * adap)671 static u32 mxs_i2c_func(struct i2c_adapter *adap)
672 {
673 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
674 }
675
mxs_i2c_isr(int this_irq,void * dev_id)676 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
677 {
678 struct mxs_i2c_dev *i2c = dev_id;
679 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
680
681 if (!stat)
682 return IRQ_NONE;
683
684 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
685 i2c->cmd_err = -ENXIO;
686 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
687 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
688 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
689 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
690 i2c->cmd_err = -EIO;
691
692 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
693
694 return IRQ_HANDLED;
695 }
696
697 static const struct i2c_algorithm mxs_i2c_algo = {
698 .xfer = mxs_i2c_xfer,
699 .functionality = mxs_i2c_func,
700 };
701
702 static const struct i2c_adapter_quirks mxs_i2c_quirks = {
703 .flags = I2C_AQ_NO_ZERO_LEN,
704 };
705
mxs_i2c_derive_timing(struct mxs_i2c_dev * i2c,uint32_t speed)706 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
707 {
708 /* The I2C block clock runs at 24MHz */
709 const uint32_t clk = 24000000;
710 uint32_t divider;
711 uint16_t high_count, low_count, rcv_count, xmit_count;
712 uint32_t bus_free, leadin;
713 struct device *dev = i2c->dev;
714
715 divider = DIV_ROUND_UP(clk, speed);
716
717 if (divider < 25) {
718 /*
719 * limit the divider, so that min(low_count, high_count)
720 * is >= 1
721 */
722 divider = 25;
723 dev_warn(dev,
724 "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
725 speed / 1000, speed % 1000,
726 clk / divider / 1000, clk / divider % 1000);
727 } else if (divider > 1897) {
728 /*
729 * limit the divider, so that max(low_count, high_count)
730 * cannot exceed 1023
731 */
732 divider = 1897;
733 dev_warn(dev,
734 "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
735 speed / 1000, speed % 1000,
736 clk / divider / 1000, clk / divider % 1000);
737 }
738
739 /*
740 * The I2C spec specifies the following timing data:
741 * standard mode fast mode Bitfield name
742 * tLOW (SCL LOW period) 4700 ns 1300 ns
743 * tHIGH (SCL HIGH period) 4000 ns 600 ns
744 * tSU;DAT (data setup time) 250 ns 100 ns
745 * tHD;STA (START hold time) 4000 ns 600 ns
746 * tBUF (bus free time) 4700 ns 1300 ns
747 *
748 * The hardware (of the i.MX28 at least) seems to add 2 additional
749 * clock cycles to the low_count and 7 cycles to the high_count.
750 * This is compensated for by subtracting the respective constants
751 * from the values written to the timing registers.
752 */
753 if (speed > I2C_MAX_STANDARD_MODE_FREQ) {
754 /* fast mode */
755 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
756 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
757 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
758 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
759 } else {
760 /* normal mode */
761 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
762 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
763 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
764 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
765 }
766 rcv_count = high_count * 3 / 8;
767 xmit_count = low_count * 3 / 8;
768
769 dev_dbg(dev,
770 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
771 speed, clk / divider, divider, low_count, high_count,
772 xmit_count, rcv_count, leadin, bus_free);
773
774 low_count -= 2;
775 high_count -= 7;
776 i2c->timing0 = (high_count << 16) | rcv_count;
777 i2c->timing1 = (low_count << 16) | xmit_count;
778 i2c->timing2 = (bus_free << 16 | leadin);
779 }
780
mxs_i2c_get_ofdata(struct mxs_i2c_dev * i2c)781 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
782 {
783 uint32_t speed;
784 struct device *dev = i2c->dev;
785 struct device_node *node = dev->of_node;
786 int ret;
787
788 ret = of_property_read_u32(node, "clock-frequency", &speed);
789 if (ret) {
790 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
791 speed = I2C_MAX_STANDARD_MODE_FREQ;
792 }
793
794 mxs_i2c_derive_timing(i2c, speed);
795
796 return 0;
797 }
798
799 static const struct of_device_id mxs_i2c_dt_ids[] = {
800 { .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, },
801 { .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, },
802 { /* sentinel */ }
803 };
804 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
805
mxs_i2c_probe(struct platform_device * pdev)806 static int mxs_i2c_probe(struct platform_device *pdev)
807 {
808 struct device *dev = &pdev->dev;
809 struct mxs_i2c_dev *i2c;
810 struct i2c_adapter *adap;
811 int err, irq;
812
813 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
814 if (!i2c)
815 return -ENOMEM;
816
817 i2c->dev_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
818
819 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
820 if (IS_ERR(i2c->regs))
821 return PTR_ERR(i2c->regs);
822
823 irq = platform_get_irq(pdev, 0);
824 if (irq < 0)
825 return irq;
826
827 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
828 if (err)
829 return err;
830
831 i2c->dev = dev;
832
833 init_completion(&i2c->cmd_complete);
834
835 if (dev->of_node) {
836 err = mxs_i2c_get_ofdata(i2c);
837 if (err)
838 return err;
839 }
840
841 /* Setup the DMA */
842 i2c->dmach = devm_dma_request_chan(dev, "rx-tx");
843 if (IS_ERR(i2c->dmach)) {
844 return dev_err_probe(dev, PTR_ERR(i2c->dmach),
845 "Failed to request dma\n");
846 }
847
848 platform_set_drvdata(pdev, i2c);
849
850 /* Do reset to enforce correct startup after pinmuxing */
851 err = mxs_i2c_reset(i2c);
852 if (err)
853 return err;
854
855 adap = &i2c->adapter;
856 strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
857 adap->owner = THIS_MODULE;
858 adap->algo = &mxs_i2c_algo;
859 adap->quirks = &mxs_i2c_quirks;
860 adap->dev.parent = dev;
861 adap->nr = pdev->id;
862 adap->dev.of_node = pdev->dev.of_node;
863 i2c_set_adapdata(adap, i2c);
864 err = i2c_add_numbered_adapter(adap);
865 if (err) {
866 writel(MXS_I2C_CTRL0_SFTRST,
867 i2c->regs + MXS_I2C_CTRL0_SET);
868 return err;
869 }
870
871 return 0;
872 }
873
mxs_i2c_remove(struct platform_device * pdev)874 static void mxs_i2c_remove(struct platform_device *pdev)
875 {
876 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
877
878 i2c_del_adapter(&i2c->adapter);
879
880 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
881 }
882
883 static struct platform_driver mxs_i2c_driver = {
884 .driver = {
885 .name = DRIVER_NAME,
886 .of_match_table = mxs_i2c_dt_ids,
887 },
888 .probe = mxs_i2c_probe,
889 .remove = mxs_i2c_remove,
890 };
891
mxs_i2c_init(void)892 static int __init mxs_i2c_init(void)
893 {
894 return platform_driver_register(&mxs_i2c_driver);
895 }
896 subsys_initcall(mxs_i2c_init);
897
mxs_i2c_exit(void)898 static void __exit mxs_i2c_exit(void)
899 {
900 platform_driver_unregister(&mxs_i2c_driver);
901 }
902 module_exit(mxs_i2c_exit);
903
904 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
905 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
906 MODULE_DESCRIPTION("MXS I2C Bus Driver");
907 MODULE_LICENSE("GPL");
908 MODULE_ALIAS("platform:" DRIVER_NAME);
909