1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23 * The full GNU General Public License is included in this distribution 24 * in the file called LICENSE.GPL. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 */ 54 #ifndef _SCIC_SDS_CONTROLLER_H_ 55 #define _SCIC_SDS_CONTROLLER_H_ 56 57 /** 58 * @file 59 * 60 * @brief This file contains the structures, constants and prototypes used for 61 * the core controller object. 62 */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif // __cplusplus 67 68 #include <dev/isci/scil/sci_pool.h> 69 #include <dev/isci/scil/sci_controller_constants.h> 70 #include <dev/isci/scil/sci_memory_descriptor_list.h> 71 #include <dev/isci/scil/sci_base_controller.h> 72 #include <dev/isci/scil/scic_config_parameters.h> 73 #include <dev/isci/scil/scic_sds_port.h> 74 #include <dev/isci/scil/scic_sds_phy.h> 75 #include <dev/isci/scil/scic_sds_remote_node_table.h> 76 #include <dev/isci/scil/scu_registers.h> 77 #include <dev/isci/scil/scu_constants.h> 78 #include <dev/isci/scil/scu_remote_node_context.h> 79 #include <dev/isci/scil/scu_task_context.h> 80 #include <dev/isci/scil/scu_unsolicited_frame.h> 81 #include <dev/isci/scil/scic_sds_unsolicited_frame_control.h> 82 #include <dev/isci/scil/scic_sds_port_configuration_agent.h> 83 #include <dev/isci/scil/scic_sds_pci.h> 84 85 struct SCIC_SDS_REMOTE_DEVICE; 86 struct SCIC_SDS_REQUEST; 87 88 89 #define SCU_COMPLETION_RAM_ALIGNMENT (64) 90 91 /** 92 * @enum SCIC_SDS_CONTROLLER_MEMORY_DESCRIPTORS 93 * 94 * This enumeration depects the types of MDEs that are going to be created for 95 * the controller object. 96 */ 97 enum SCIC_SDS_CONTROLLER_MEMORY_DESCRIPTORS 98 { 99 /** 100 * Completion queue MDE entry 101 */ 102 SCU_MDE_COMPLETION_QUEUE, 103 104 /** 105 * Remote node context MDE entry 106 */ 107 SCU_MDE_REMOTE_NODE_CONTEXT, 108 109 /** 110 * Task context MDE entry 111 */ 112 SCU_MDE_TASK_CONTEXT, 113 114 /** 115 * Unsolicited frame buffer MDE entrys this is the start of the unsolicited 116 * frame buffer entries. 117 */ 118 SCU_MDE_UF_BUFFER, 119 120 SCU_MAX_MDES 121 }; 122 123 /** 124 * @struct SCIC_POWER_CONTROL 125 * 126 * This structure defines the fields for managing power control for direct 127 * attached disk devices. 128 */ 129 typedef struct SCIC_POWER_CONTROL 130 { 131 /** 132 * This field is set when the power control timer is running and cleared when 133 * it is not. 134 */ 135 BOOL timer_started; 136 137 /** 138 * This field is the handle to the driver timer object. This timer is used to 139 * control when the directed attached disks can consume power. 140 */ 141 void *timer; 142 143 /** 144 * This field is used to keep track of how many phys are put into the 145 * requesters field. 146 */ 147 U8 phys_waiting; 148 149 /** 150 * This field is used to keep track of how many remote devices have been granted to consume power 151 */ 152 U8 remote_devices_granted_power; 153 154 /** 155 * This field is an array of phys that we are waiting on. The phys are direct 156 * mapped into requesters via SCIC_SDS_PHY_T.phy_index 157 */ 158 SCIC_SDS_PHY_T *requesters[SCI_MAX_PHYS]; 159 160 } SCIC_POWER_CONTROL_T; 161 162 /** 163 * @struct SCIC_SDS_CONTROLLER 164 * 165 * This structure represents the SCU contoller object. 166 */ 167 typedef struct SCIC_SDS_CONTROLLER 168 { 169 /** 170 * The SCI_BASE_CONTROLLER is the parent object for the SCIC_SDS_CONTROLLER 171 * object. 172 */ 173 SCI_BASE_CONTROLLER_T parent; 174 175 /** 176 * This field is the driver timer object handler used to time the controller 177 * object start and stop requests. 178 */ 179 void *timeout_timer; 180 181 /** 182 * This field is the current set of state handlers assigned to this controller 183 * object. 184 */ 185 struct SCIC_SDS_CONTROLLER_STATE_HANDLER *state_handlers; 186 187 /** 188 * This field contains the user parameters to be utilized for this 189 * core controller object. 190 */ 191 SCIC_USER_PARAMETERS_T user_parameters; 192 193 /** 194 * This field contains the OEM parameters version defining the structure 195 * layout. It comes from the version in the OEM block header. 196 */ 197 U8 oem_parameters_version; 198 199 /** 200 * This field contains the OEM parameters to be utilized for this 201 * core controller object. 202 */ 203 SCIC_OEM_PARAMETERS_T oem_parameters; 204 205 /** 206 * This field contains the port configuration agent for this controller. 207 */ 208 SCIC_SDS_PORT_CONFIGURATION_AGENT_T port_agent; 209 210 /** 211 * This field is the array of port objects that are controlled by this 212 * controller object. There is one dummy port object also contained within 213 * this controller object. 214 */ 215 struct SCIC_SDS_PORT port_table[SCI_MAX_PORTS + 1]; 216 217 /** 218 * This field is the array of phy objects that are controlled by this 219 * controller object. 220 */ 221 struct SCIC_SDS_PHY phy_table[SCI_MAX_PHYS]; 222 223 /** 224 * This field is the array of device objects that are currently constructed 225 * for this controller object. This table is used as a fast lookup of device 226 * objects that need to handle device completion notifications from the 227 * hardware. The table is RNi based. 228 */ 229 struct SCIC_SDS_REMOTE_DEVICE *device_table[SCI_MAX_REMOTE_DEVICES]; 230 231 /** 232 * This field is the array of IO request objects that are currently active for 233 * this controller object. This table is used as a fast lookup of the io 234 * request object that need to handle completion queue notifications. The 235 * table is TCi based. 236 */ 237 struct SCIC_SDS_REQUEST *io_request_table[SCI_MAX_IO_REQUESTS]; 238 239 /** 240 * This field is the free RNi data structure 241 */ 242 SCIC_REMOTE_NODE_TABLE_T available_remote_nodes; 243 244 /** 245 * This field is the TCi pool used to manage the task context index. 246 */ 247 SCI_POOL_CREATE(tci_pool, U16, SCI_MAX_IO_REQUESTS); 248 249 /** 250 * This filed is the SCIC_POWER_CONTROL data used to control when direct 251 * attached devices can consume power. 252 */ 253 SCIC_POWER_CONTROL_T power_control; 254 255 /** 256 * This field is the array of sequence values for the IO Tag fields. Even 257 * though only 4 bits of the field is used for the sequence the sequence is 16 258 * bits in size so the sequence can be bitwise or'd with the TCi to build the 259 * IO Tag value. 260 */ 261 U16 io_request_sequence[SCI_MAX_IO_REQUESTS]; 262 263 /** 264 * This field in the array of sequence values for the RNi. These are used 265 * to control io request build to io request start operations. The sequence 266 * value is recorded into an io request when it is built and is checked on 267 * the io request start operation to make sure that there was not a device 268 * hot plug between the build and start operation. 269 */ 270 U8 remote_device_sequence[SCI_MAX_REMOTE_DEVICES]; 271 272 /** 273 * This field is a pointer to the memory allocated by the driver for the task 274 * context table. This data is shared between the hardware and software. 275 */ 276 SCU_TASK_CONTEXT_T *task_context_table; 277 278 /** 279 * This field is a pointer to the memory allocated by the driver for the 280 * remote node context table. This table is shared between the hardware and 281 * software. 282 */ 283 SCU_REMOTE_NODE_CONTEXT_T *remote_node_context_table; 284 285 /** 286 * This field is the array of physical memory requiremets for this controller 287 * object. 288 */ 289 SCI_PHYSICAL_MEMORY_DESCRIPTOR_T memory_descriptors[SCU_MAX_MDES]; 290 291 /** 292 * This field is a pointer to the completion queue. This memory is 293 * written to by the hardware and read by the software. 294 */ 295 U32 *completion_queue; 296 297 /** 298 * This field is the software copy of the completion queue get pointer. The 299 * controller object writes this value to the hardware after processing the 300 * completion entries. 301 */ 302 U32 completion_queue_get; 303 304 /** 305 * This field is the minimum of the number of hardware supported port entries 306 * and the software requested port entries. 307 */ 308 U32 logical_port_entries; 309 310 /** 311 * This field is the minimum number of hardware supported completion queue 312 * entries and the software requested completion queue entries. 313 */ 314 U32 completion_queue_entries; 315 316 /** 317 * This field is the minimum number of hardware supported event entries and 318 * the software requested event entries. 319 */ 320 U32 completion_event_entries; 321 322 /** 323 * This field is the minimum number of devices supported by the hardware and 324 * the number of devices requested by the software. 325 */ 326 U32 remote_node_entries; 327 328 /** 329 * This field is the minimum number of IO requests supported by the hardware 330 * and the number of IO requests requested by the software. 331 */ 332 U32 task_context_entries; 333 334 /** 335 * This object contains all of the unsolicited frame specific 336 * data utilized by the core controller. 337 */ 338 SCIC_SDS_UNSOLICITED_FRAME_CONTROL_T uf_control; 339 340 /** 341 * This field records the fact that the controller has encountered a fatal 342 * error and must be reset. 343 */ 344 BOOL encountered_fatal_error; 345 346 /** 347 * This field specifies that the controller should ignore 348 * completion processing for non-fastpath events. This will 349 * cause the completions to be thrown away. 350 */ 351 BOOL restrict_completions; 352 353 // Phy Startup Data 354 /** 355 * This field is the driver timer handle for controller phy request startup. 356 * On controller start the controller will start each PHY individually in 357 * order of phy index. 358 */ 359 void *phy_startup_timer; 360 361 /** 362 * This field is set when the phy_startup_timer is running and is cleared when 363 * the phy_startup_timer is stopped. 364 */ 365 BOOL phy_startup_timer_pending; 366 367 /** 368 * This field is the index of the next phy start. It is initialized to 0 and 369 * increments for each phy index that is started. 370 */ 371 U32 next_phy_to_start; 372 373 /** 374 * This field controls the invalid link up notifications to the SCI_USER. If 375 * an invalid_link_up notification is reported a bit for the PHY index is set 376 * so further notifications are not made. Once the PHY object reports link up 377 * and is made part of a port then this bit for the PHY index is cleared. 378 */ 379 U8 invalid_phy_mask; 380 381 /** 382 * This is the controller index for this controller object. 383 */ 384 U8 controller_index; 385 386 /** 387 * This field is the PCI revision code for the controller object. 388 */ 389 enum SCU_CONTROLLER_PCI_REVISION_CODE pci_revision; 390 391 /* 392 * This field saves the current interrupt coalescing number of the controller. 393 */ 394 U16 interrupt_coalesce_number; 395 396 /* 397 * This field saves the current interrupt coalescing timeout value in microseconds. 398 */ 399 U32 interrupt_coalesce_timeout; 400 401 // Hardware memory mapped register space 402 #ifdef ARLINGTON_BUILD 403 /** 404 * This field is a pointer to the memory mapped register space for the 405 * LEX_REGISTERS. 406 */ 407 LEX_REGISTERS_T *lex_registers; 408 #endif 409 410 /** 411 * This field is a pointer to the memory mapped register space for the 412 * SMU_REGISTERS. 413 */ 414 SMU_REGISTERS_T *smu_registers; 415 416 /** 417 * This field is a pointer to the memory mapped register space for the 418 * SCU_REGISTERS. 419 */ 420 SCU_REGISTERS_T *scu_registers; 421 422 } SCIC_SDS_CONTROLLER_T; 423 424 425 typedef void (*SCIC_SDS_CONTROLLER_PHY_HANDLER_T)( 426 struct SCIC_SDS_CONTROLLER *controller, 427 struct SCIC_SDS_PORT *port, 428 struct SCIC_SDS_PHY *phy 429 ); 430 431 typedef void (*SCIC_SDS_CONTROLLER_DEVICE_HANDLER_T)( 432 struct SCIC_SDS_CONTROLLER * controller, 433 struct SCIC_SDS_REMOTE_DEVICE * device 434 ); 435 /** 436 * @struct SCIC_SDS_CONTROLLER_STATE_HANDLER 437 * 438 * This structure contains the SDS core specific definition for the state 439 * handlers. 440 */ 441 typedef struct SCIC_SDS_CONTROLLER_STATE_HANDLER 442 { 443 SCI_BASE_CONTROLLER_STATE_HANDLER_T parent; 444 445 SCI_BASE_CONTROLLER_REQUEST_HANDLER_T terminate_request_handler; 446 SCIC_SDS_CONTROLLER_PHY_HANDLER_T link_up_handler; 447 SCIC_SDS_CONTROLLER_PHY_HANDLER_T link_down_handler; 448 SCIC_SDS_CONTROLLER_DEVICE_HANDLER_T remote_device_started_handler; 449 SCIC_SDS_CONTROLLER_DEVICE_HANDLER_T remote_device_stopped_handler; 450 451 } SCIC_SDS_CONTROLLER_STATE_HANDLER_T; 452 453 extern SCIC_SDS_CONTROLLER_STATE_HANDLER_T 454 scic_sds_controller_state_handler_table[]; 455 extern SCI_BASE_STATE_T scic_sds_controller_state_table[]; 456 457 /** 458 * This macro will increment the specified index to and if the index wraps 459 * to 0 it will toggel the cycle bit. 460 */ 461 #define INCREMENT_QUEUE_GET(index, cycle, entry_count, bit_toggle) \ 462 { \ 463 if ((index) + 1 == entry_count) \ 464 { \ 465 (index) = 0; \ 466 (cycle) = (cycle) ^ (bit_toggle); \ 467 } \ 468 else \ 469 { \ 470 index = index + 1; \ 471 } \ 472 } 473 474 /** 475 * This is a helper macro that sets the state handlers for the controller 476 * object 477 */ 478 #define scic_sds_controller_set_state_handlers(this_controller, handlers) \ 479 ((this_controller)->state_handlers = (handlers)) 480 481 /** 482 * This is a helper macro that gets the base state machine for the 483 * controller object 484 */ 485 #define scic_sds_controller_get_base_state_machine(this_contoroller) \ 486 (&(this_controller)->parent.state_machine) 487 488 /** 489 * This is a helper macro to get the port configuration agent from the 490 * controller object. 491 */ 492 #define scic_sds_controller_get_port_configuration_agent(controller) \ 493 (&(controller)->port_agent) 494 495 /** 496 * This is a helper macro that sets the base state machine state handlers 497 * based on the state id 498 */ 499 #define scic_sds_controller_set_base_state_handlers(this_controller, state_id) \ 500 scic_sds_controller_set_state_handlers( \ 501 this_controller, &scic_sds_controller_state_handler_table[(state_id)]) 502 503 /** 504 * This macro writes to the smu_register for this controller 505 */ 506 #define smu_register_write(controller, reg, value) \ 507 scic_sds_pci_write_smu_dword((controller), &(reg), (value)) 508 509 /** 510 * This macro reads the smu_register for this controller 511 */ 512 #define smu_register_read(controller, reg) \ 513 scic_sds_pci_read_smu_dword((controller), &(reg)) 514 515 /** 516 * This mcaro writes the scu_register for this controller 517 */ 518 #define scu_register_write(controller, reg, value) \ 519 scic_sds_pci_write_scu_dword((controller), &(reg), (value)) 520 521 /** 522 * This macro reads the scu_register for this controller 523 */ 524 #define scu_register_read(controller, reg) \ 525 scic_sds_pci_read_scu_dword((controller), &(reg)) 526 527 #ifdef ARLINGTON_BUILD 528 /** 529 * This macro writes to the lex_register for this controller. 530 */ 531 #define lex_register_write(controller, reg, value) \ 532 scic_cb_pci_write_dword((controller), (reg), (value)) 533 534 /** 535 * This macro reads from the lex_register for this controller. 536 */ 537 #define lex_register_read(controller, reg) \ 538 scic_cb_pci_read_dword((controller), (reg)) 539 #endif // ARLINGTON_BUILD 540 541 /** 542 * This macro returns the protocol engine group for this controller object. 543 * Presently we only support protocol engine group 0 so just return that 544 */ 545 #define scic_sds_controller_get_protocol_engine_group(controller) 0 546 547 /** 548 * This macro constructs an IO tag from the sequence and index values. 549 */ 550 #define scic_sds_io_tag_construct(sequence, task_index) \ 551 ((sequence) << 12 | (task_index)) 552 553 /** 554 * This macro returns the IO sequence from the IO tag value. 555 */ 556 #define scic_sds_io_tag_get_sequence(io_tag) \ 557 (((io_tag) & 0xF000) >> 12) 558 559 /** 560 * This macro returns the TCi from the io tag value 561 */ 562 #define scic_sds_io_tag_get_index(io_tag) \ 563 ((io_tag) & 0x0FFF) 564 565 /** 566 * This is a helper macro to increment the io sequence count. 567 * 568 * We may find in the future that it will be faster to store the sequence 569 * count in such a way as we dont perform the shift operation to build io 570 * tag values so therefore need a way to incrment them correctly 571 */ 572 #define scic_sds_io_sequence_increment(value) \ 573 ((value) = (((value) + 1) & 0x000F)) 574 575 #define scic_sds_remote_device_node_count(device) \ 576 ( \ 577 ( \ 578 (device)->target_protocols.u.bits.attached_stp_target \ 579 && ((device)->is_direct_attached != TRUE) \ 580 ) \ 581 ? SCU_STP_REMOTE_NODE_COUNT : SCU_SSP_REMOTE_NODE_COUNT \ 582 ) 583 584 /** 585 * This macro will set the bit in the invalid phy mask for this controller 586 * object. This is used to control messages reported for invalid link up 587 * notifications. 588 */ 589 #define scic_sds_controller_set_invalid_phy(controller, phy) \ 590 ((controller)->invalid_phy_mask |= (1 << (phy)->phy_index)) 591 592 /** 593 * This macro will clear the bit in the invalid phy mask for this controller 594 * object. This is used to control messages reported for invalid link up 595 * notifications. 596 */ 597 #define scic_sds_controller_clear_invalid_phy(controller, phy) \ 598 ((controller)->invalid_phy_mask &= ~(1 << (phy)->phy_index)) 599 600 // --------------------------------------------------------------------------- 601 602 U32 scic_sds_controller_get_object_size(void); 603 604 // --------------------------------------------------------------------------- 605 606 U32 scic_sds_controller_get_min_timer_count(void); 607 U32 scic_sds_controller_get_max_timer_count(void); 608 609 // --------------------------------------------------------------------------- 610 611 void scic_sds_controller_post_request( 612 SCIC_SDS_CONTROLLER_T *this_controller, 613 U32 request 614 ); 615 616 // --------------------------------------------------------------------------- 617 618 void scic_sds_controller_release_frame( 619 SCIC_SDS_CONTROLLER_T *this_controller, 620 U32 frame_index 621 ); 622 623 void scic_sds_controller_copy_sata_response( 624 void * response_buffer, 625 void * frame_header, 626 void * frame_buffer 627 ); 628 629 // --------------------------------------------------------------------------- 630 631 SCI_STATUS scic_sds_controller_allocate_remote_node_context( 632 SCIC_SDS_CONTROLLER_T *this_controller, 633 struct SCIC_SDS_REMOTE_DEVICE *the_device, 634 U16 *node_id 635 ); 636 637 void scic_sds_controller_free_remote_node_context( 638 SCIC_SDS_CONTROLLER_T *this_controller, 639 struct SCIC_SDS_REMOTE_DEVICE *the_device, 640 U16 node_id 641 ); 642 643 SCU_REMOTE_NODE_CONTEXT_T *scic_sds_controller_get_remote_node_context_buffer( 644 SCIC_SDS_CONTROLLER_T *this_controller, 645 U16 node_id 646 ); 647 648 // --------------------------------------------------------------------------- 649 650 struct SCIC_SDS_REQUEST *scic_sds_controller_get_io_request_from_tag( 651 SCIC_SDS_CONTROLLER_T *this_controller, 652 U16 io_tag 653 ); 654 655 U16 scic_sds_controller_get_io_sequence_from_tag( 656 SCIC_SDS_CONTROLLER_T *this_controller, 657 U16 io_tag 658 ); 659 660 SCU_TASK_CONTEXT_T *scic_sds_controller_get_task_context_buffer( 661 SCIC_SDS_CONTROLLER_T *this_controller, 662 U16 io_tag 663 ); 664 665 //----------------------------------------------------------------------------- 666 667 SCI_STATUS scic_sds_terminate_reqests( 668 SCIC_SDS_CONTROLLER_T *this_controller, 669 struct SCIC_SDS_REMOTE_DEVICE *this_remote_device, 670 struct SCIC_SDS_PORT *this_port 671 ); 672 673 //***************************************************************************** 674 //* CORE CONTROLLER POWER CONTROL METHODS 675 //***************************************************************************** 676 677 void scic_sds_controller_power_control_timer_handler( 678 void *controller 679 ); 680 681 void scic_sds_controller_power_control_queue_insert( 682 SCIC_SDS_CONTROLLER_T *this_controller, 683 struct SCIC_SDS_PHY *the_phy 684 ); 685 686 void scic_sds_controller_power_control_queue_remove( 687 SCIC_SDS_CONTROLLER_T *this_controller, 688 struct SCIC_SDS_PHY *the_phy 689 ); 690 691 //***************************************************************************** 692 //* CORE CONTROLLER PHY MESSAGE PROCESSING 693 //***************************************************************************** 694 695 void scic_sds_controller_link_up( 696 SCIC_SDS_CONTROLLER_T *this_controller, 697 struct SCIC_SDS_PORT *the_port, 698 struct SCIC_SDS_PHY *the_phy 699 ); 700 701 void scic_sds_controller_link_down( 702 SCIC_SDS_CONTROLLER_T *this_controller, 703 struct SCIC_SDS_PORT *the_port, 704 struct SCIC_SDS_PHY *the_phy 705 ); 706 707 //***************************************************************************** 708 //* CORE CONTROLLER PORT AGENT MESSAGE PROCESSING 709 //***************************************************************************** 710 void scic_sds_controller_port_agent_configured_ports( 711 SCIC_SDS_CONTROLLER_T * this_controller 712 ); 713 714 //***************************************************************************** 715 //* CORE CONTROLLER REMOTE DEVICE MESSAGE PROCESSING 716 //***************************************************************************** 717 718 BOOL scic_sds_controller_has_remote_devices_stopping( 719 SCIC_SDS_CONTROLLER_T * this_controller 720 ); 721 722 void scic_sds_controller_remote_device_started( 723 SCIC_SDS_CONTROLLER_T * this_controller, 724 struct SCIC_SDS_REMOTE_DEVICE * the_device 725 ); 726 727 void scic_sds_controller_remote_device_stopped( 728 SCIC_SDS_CONTROLLER_T * this_controller, 729 struct SCIC_SDS_REMOTE_DEVICE * the_device 730 ); 731 732 //***************************************************************************** 733 //* CORE CONTROLLER PRIVATE METHODS 734 //***************************************************************************** 735 736 #ifdef SCI_LOGGING 737 void scic_sds_controller_initialize_state_logging( 738 SCIC_SDS_CONTROLLER_T *this_controller 739 ); 740 741 void scic_sds_controller_deinitialize_state_logging( 742 SCIC_SDS_CONTROLLER_T *this_controller 743 ); 744 #else 745 #define scic_sds_controller_initialize_state_logging(x) 746 #define scic_sds_controller_deinitialize_state_logging(x) 747 #endif 748 749 SCI_STATUS scic_sds_controller_validate_memory_descriptor_table( 750 SCIC_SDS_CONTROLLER_T *this_controller 751 ); 752 753 void scic_sds_controller_ram_initialization( 754 SCIC_SDS_CONTROLLER_T *this_controller 755 ); 756 757 void scic_sds_controller_assign_task_entries( 758 SCIC_SDS_CONTROLLER_T *this_controller 759 ); 760 761 void scic_sds_controller_afe_initialization( 762 SCIC_SDS_CONTROLLER_T * this_controller 763 ); 764 765 void scic_sds_controller_enable_port_task_scheduler( 766 SCIC_SDS_CONTROLLER_T *this_controller 767 ); 768 769 void scic_sds_controller_initialize_completion_queue( 770 SCIC_SDS_CONTROLLER_T *this_controller 771 ); 772 773 void scic_sds_controller_initialize_unsolicited_frame_queue( 774 SCIC_SDS_CONTROLLER_T *this_controller 775 ); 776 777 void scic_sds_controller_phy_timer_stop( 778 SCIC_SDS_CONTROLLER_T *this_controller 779 ); 780 781 BOOL scic_sds_controller_is_start_complete( 782 SCIC_SDS_CONTROLLER_T *this_controller 783 ); 784 785 SCI_STATUS scic_sds_controller_start_next_phy( 786 SCIC_SDS_CONTROLLER_T *this_controller 787 ); 788 789 SCI_STATUS scic_sds_controller_stop_phys( 790 SCIC_SDS_CONTROLLER_T *this_controller 791 ); 792 793 SCI_STATUS scic_sds_controller_stop_ports( 794 SCIC_SDS_CONTROLLER_T *this_controller 795 ); 796 797 SCI_STATUS scic_sds_controller_stop_devices( 798 SCIC_SDS_CONTROLLER_T *this_controller 799 ); 800 801 void scic_sds_controller_copy_task_context( 802 SCIC_SDS_CONTROLLER_T *this_controller, 803 struct SCIC_SDS_REQUEST *this_request 804 ); 805 806 void scic_sds_controller_timeout_handler( 807 SCI_CONTROLLER_HANDLE_T controller 808 ); 809 810 void scic_sds_controller_initialize_power_control( 811 SCIC_SDS_CONTROLLER_T *this_controller 812 ); 813 814 void scic_sds_controller_register_setup( 815 SCIC_SDS_CONTROLLER_T *this_controller 816 ); 817 818 void scic_sds_controller_reset_hardware( 819 SCIC_SDS_CONTROLLER_T * this_controller 820 ); 821 822 #ifdef ARLINGTON_BUILD 823 void scic_sds_controller_lex_atux_initialization( 824 SCIC_SDS_CONTROLLER_T *this_controller 825 ); 826 827 void scic_sds_controller_enable_chipwatch( 828 SCIC_SDS_CONTROLLER_T *this_controller 829 ); 830 #endif // ARLINGTON_BUILD 831 832 void scic_sds_controller_build_memory_descriptor_table( 833 SCIC_SDS_CONTROLLER_T *this_controller 834 ); 835 836 #ifdef __cplusplus 837 } 838 #endif // __cplusplus 839 840 #endif // _SCIC_SDS_CONTROLLER_H_ 841