xref: /illumos-gate/usr/src/uts/intel/io/dnet/dnet_mii.h (revision bdb9230ac765cb7af3fc1f4119caf2c5720dceb3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * mii.h
28  * Generic MII/PHY Support for MAC drivers.
29  *
30  * Copyrighted as an unpublished work. (c) Copyright 1997 Sun Microsystems, Inc.
31  * All rights reserved.
32  */
33 
34 #ifndef _DNET_MII_H
35 #define	_DNET_MII_H
36 
37 /*
38  * NOTES
39  * All calls to MII functions are assumed to be serialized by the user.
40  * In the case of the port monitor, which causes asynchronous callbacks,
41  * you must pass the address of a mutex. MII aquires this before calling
42  * the user callback, and releases it after the callback returns.
43  *
44  * All calls requiring a PHY address must be done AFTER calling
45  * mii_init_phy() for that PHY, with the exception of mii_phyexists()
46  *
47  * mii_rsan() will not accept mii_wait_interrupt as a wait type. Its futile to
48  * expect autonegotiation to happen fast enough. (You're better off using the
49  * port monitor to tell you, asynchronously that the link has been
50  * re-established than waiting at all.)
51  */
52 
53 /*
54  * MII programming Interface types
55  */
56 
57 enum mii_phy_state {phy_state_unknown, phy_state_linkup, phy_state_linkdown};
58 enum mii_wait_type {mii_wait_none, mii_wait_user, mii_wait_interrupt};
59 typedef ushort_t (*mii_readfunc_t)(dev_info_t *, int phy, int reg);
60 typedef void (*mii_writefunc_t)(dev_info_t *, int phy, int reg, int value);
61 typedef void (*mii_linkfunc_t)(dev_info_t *, int phy, enum mii_phy_state state);
62 
63 struct mii_info;	/* Private to MII! */
64 typedef struct mii_info *mii_handle_t;
65 
66 /*
67  * Entrypoints
68  */
69 
70 int mii_create(dev_info_t *, mii_writefunc_t, mii_readfunc_t, mii_handle_t *);
71 			/* Initialise the PHY interface */
72 
73 int mii_init_phy(mii_handle_t, int phy);
74 			/* Initialise a PHY */
75 
76 int mii_getspeed(mii_handle_t, int phy, int *speed, int *full_duplex);
77 			/* Check operating speed of PHY */
78 
79 int mii_probe_phy(mii_handle_t, int phy);
80 			/* Check if PHY exists at an address */
81 
82 int mii_rsan(mii_handle_t mac, int phy, enum mii_wait_type wait_type);
83 					/* Restart autonegotiation */
84 
85 int mii_fixspeed(mii_handle_t, int phy, int speed, int fullduplex);
86 			/* Fix speed and duplex mode of PHY (disable autoneg) */
87 
88 int mii_autoneg_enab(mii_handle_t mac, int phy);
89 			/* (re-)enable autonegotiation */
90 
91 int mii_reset_phy(mii_handle_t, int phy, enum mii_wait_type wait_type);
92 			/* Force PHY to reset itself */
93 
94 int mii_disable_fullduplex(mii_handle_t, int phy);
95 			/* Stop the PHY advertising full duplex capability */
96 
97 int mii_linkup(mii_handle_t, int phy);
98 			/* Check link status on a phy */
99 
100 int mii_sync(mii_handle_t, int phy);
101 			/* Sync API if something may have affected the PHY */
102 
103 int mii_isolate(mii_handle_t, int phy);
104 			/* Electrically isolate a PHY */
105 
106 int mii_unisolate(mii_handle_t, int phy);
107 			/* Unisolate */
108 
109 int mii_dump_phy(mii_handle_t, int phy);
110 			/* Dump register contents */
111 
112 int mii_start_portmon(mii_handle_t mac, mii_linkfunc_t func, kmutex_t *lock);
113 			/* Monitor initialised PHYs for link state changes */
114 
115 int mii_stop_portmon(mii_handle_t mac);
116 			/* Stop port monitor */
117 
118 void mii_destroy(mii_handle_t mac);
119 			/* Cleanup MII interface */
120 
121 /*
122  * Errorcodes
123  */
124 #define	MII_SUCCESS 0
125 #define	MII_PHYPRESENT 1	/* PHY already exists at specified address */
126 #define	MII_NOMEM 2		/* Not enough memory */
127 #define	MII_PARAM 3		/* parameters passed are incorrect */
128 #define	MII_NOTSUPPORTED 4	/* operation not supported by hardware. */
129 #define	MII_STATE 5		/* The request is not valid at this time. */
130 #define	MII_HARDFAIL 6		/* The hardware is not functioning correctly */
131 #define	MII_TIMEOUT 7		/* Timeout waiting for operation to complete */
132 #define	MII_PHYNOTPRESENT 8	/* There is no PHY at the specified address */
133 
134 /* Vendor Specific functions */
135 typedef void (*phy_genfunc)(mii_handle_t, int phy);
136 typedef int (*phy_getspeedfunc)(mii_handle_t, int phy, int *speed, int *fd);
137 
138 /* per-PHY information. */
139 struct phydata
140 {
141 	ulong_t id;			/* ID from MII registers 2,3 */
142 	char *description;		/* Text description from ID */
143 	phy_genfunc phy_dump;		/* how to dump registers this make */
144 	phy_genfunc phy_postreset;	/* What to do after a reset (or init) */
145 	phy_getspeedfunc phy_getspeed;	/* how to find current speed */
146 	unsigned short control;		/* Bits that need to be written ...  */
147 					/* ...to control register */
148 	enum mii_phy_state state;	/* Current state of link at this PHY */
149 	int fix_speed;			/* Speed fixed in conf file */
150 	int fix_duplex;
151 	/*
152 	 * ^^NEEDSWORK: We can only fix speed for the driver, never mind a
153 	 * particular PHY on a particular instance, but this is where this
154 	 * belongs.
155 	 */
156 };
157 
158 typedef struct mii_info
159 {
160 	mii_readfunc_t mii_read;	/* How to read an MII register */
161 	mii_writefunc_t mii_write;	/* How to write an MII register */
162 	mii_linkfunc_t mii_linknotify;	/* What to do when link state changes */
163 	dev_info_t *mii_dip;		/* MAC's devinfo */
164 	timeout_id_t portmon_timer;	/* ID of timer for the port monitor */
165 	kmutex_t *lock;			/* Lock to serialise mii calls */
166 	struct phydata *phys[32];	/* PHY Information indexed by address */
167 } mii_info_t;
168 
169 #define	OUI_NATIONAL_SEMICONDUCTOR 0x80017
170 #define	NS_DP83840		0x00
171 #define	MII_83840_ADDR		25
172 #define	NS83840_ADDR_SPEED10	(1<<6)
173 #define	NS83840_ADDR_CONSTAT	(1<<5)
174 #define	NS83840_ADDR_ADDR	(0x1f<<0)
175 
176 #define	OUI_INTEL		0x0aa00
177 #define	INTEL_82553_CSTEP	0x35	/* A and B steps are non-standard */
178 #define	MII_82553_EX0		16
179 #define	I82553_EX0_FDUPLEX	(1<<0)
180 #define	I82553_EX0_100MB	(1<<1)
181 #define	I82553_EX0_WAKE		(1<<2)
182 #define	I82553_EX0_SQUELCH	(3<<3) /* 3:4 */
183 #define	I82553_EX0_REVCNTR	(7<<5) /* 5:7 */
184 #define	I82553_EX0_FRCFAIL	(1<<8)
185 #define	I82553_EX0_TEST		(0x1f<<9) /* 13:9 */
186 #define	I82553_EX0_LINKDIS	(1<<14)
187 #define	I82553_EX0_JABDIS	(1<<15)
188 
189 #define	MII_82553_EX1
190 #define	I82553_EX1_RESERVE	(0x1ff<<0) /* 0:8 */
191 #define	I82553_EX1_CH2EOF	(1<<9)
192 #define	I82553_EX1_MNCHSTR	(1<<10)
193 #define	I82553_EX1_EOP		(1<<11)
194 #define	I82553_EX1_BADCODE	(1<<12)
195 #define	I82553_EX1_INVALCODE	(1<<13)
196 #define	I82553_EX1_DCBALANCE	(1<<14)
197 #define	I82553_EX1_PAIRSKEW	(1<<15)
198 
199 #define	INTEL_82555		0x15
200 #define	INTEL_82562_EH		0x33
201 #define	INTEL_82562_ET		0x32
202 #define	INTEL_82562_EM		0x31
203 
204 #define	OUI_ICS			0x57d
205 #define	ICS_1890		2
206 #define	ICS_1889		1
207 #define	ICS_EXCTRL		16
208 #define	ICS_EXCTRL_CMDOVRD	(1<<15)
209 #define	ICS_EXCTRL_PHYADDR	(0x1f<<6)
210 #define	ICS_EXCTRL_SCSTEST	(1<<5)
211 #define	ICS_EXCTRL_INVECTEST	(1<<2)
212 #define	ICS_EXCTRL_SCDISABLE	(1<<0)
213 
214 #define	ICS_QUICKPOLL		17
215 #define	ICS_QUICKPOLL_100MB	(1<<15)
216 #define	ICS_QUICKPOLL_FDUPLEX	(1<<14)
217 #define	ICS_QUICKPOLL_ANPROG	(7<<11)
218 #define	ICS_QUICKPOLL_RSE	(1<<10)
219 #define	ICS_QUICKPOLL_PLLLOCK	(1<<9)
220 #define	ICS_QUICKPOLL_FALSECD	(1<<8)
221 #define	ICS_QUICKPOLL_SYMINVAL	(1<<7)
222 #define	ICS_QUICKPOLL_SYMHALT	(1<<6)
223 #define	ICS_QUICKPOLL_PREMEND	(1<<5)
224 #define	ICS_QUICKPOLL_ANDONE	(1<<4)
225 #define	ICS_QUICKPOLL_RESERVED	(1<<3)
226 #define	ICS_QUICKPOLL_JABBER	(1<<2)
227 #define	ICS_QUICKPOLL_REMFAULT	(1<<1)
228 #define	ICS_QUICKPOLL_LINKSTAT	(1<<0)
229 
230 #define	ICS_10BASET		18
231 #define	ICS_10BASET_REMJABBER	(1<<15)
232 #define	ICS_10BASET_REVPOLARITY (1<<14)
233 #define	ICS_10BASET_RESERVED	(0xff<<6)
234 #define	ICS_10BASET_NOJABBER	(1<<5)
235 #define	ICS_10BASET_NORMLOOP	(1<<4)
236 #define	ICS_10BASET_NOAUTOPOLL	(1<<3)
237 #define	ICS_10BASET_NOSQE	(1<<2)
238 #define	ICS_10BASET_NOLINKLOSS	(1<<1)
239 #define	ICS_10BASET_NOSQUELCH	(1<<0)
240 
241 #define	ICS_EXCTRL2		19
242 #define	ICS_EXCTRL2_ISREPEATER	(1<<15)
243 #define	ICS_EXCTRL2_SOFTPRI	(1<<14)
244 #define	ICS_EXCTRL2_LPCANREMF	(1<<13)
245 #define	ICS_EXCTRL2_RMFSXMITED	(1<<10)
246 #define	ICS_EXCTRL2_ANPWRREMF	(1<<4)
247 #define	ICS_EXCTRL2_10BASETQUAL (1<<2)
248 #define	ICS_EXCTRL2_AUTOPWRDN	(1<<0)
249 
250 #endif /* _DNET_MII_H */
251