1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10 #include <linux/devcoredump.h>
11 #include <linux/etherdevice.h>
12 #include <linux/timekeeping.h>
13 #if defined(__FreeBSD__)
14 #include <linux/delay.h>
15 #endif
16 #include "mt7615.h"
17 #include "../trace.h"
18 #include "../dma.h"
19 #include "mt7615_trace.h"
20 #include "mac.h"
21 #include "mcu.h"
22
23 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
24
25 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
26 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
27 .radar_pattern = {
28 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
29 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
30 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
31 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
32 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
33 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
34 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
35 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
36 },
37 };
38
39 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
41 .radar_pattern = {
42 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
43 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
44 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
45 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
46 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
47 },
48 };
49
50 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
51 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
52 .radar_pattern = {
53 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
54 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
55 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
56 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
57 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
58 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
59 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
60 },
61 };
62
63 static enum mt76_cipher_type
mt7615_mac_get_cipher(int cipher)64 mt7615_mac_get_cipher(int cipher)
65 {
66 switch (cipher) {
67 case WLAN_CIPHER_SUITE_WEP40:
68 return MT_CIPHER_WEP40;
69 case WLAN_CIPHER_SUITE_WEP104:
70 return MT_CIPHER_WEP104;
71 case WLAN_CIPHER_SUITE_TKIP:
72 return MT_CIPHER_TKIP;
73 case WLAN_CIPHER_SUITE_AES_CMAC:
74 return MT_CIPHER_BIP_CMAC_128;
75 case WLAN_CIPHER_SUITE_CCMP:
76 return MT_CIPHER_AES_CCMP;
77 case WLAN_CIPHER_SUITE_CCMP_256:
78 return MT_CIPHER_CCMP_256;
79 case WLAN_CIPHER_SUITE_GCMP:
80 return MT_CIPHER_GCMP;
81 case WLAN_CIPHER_SUITE_GCMP_256:
82 return MT_CIPHER_GCMP_256;
83 case WLAN_CIPHER_SUITE_SMS4:
84 return MT_CIPHER_WAPI;
85 default:
86 return MT_CIPHER_NONE;
87 }
88 }
89
mt7615_rx_get_wcid(struct mt7615_dev * dev,u8 idx,bool unicast)90 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
91 u8 idx, bool unicast)
92 {
93 struct mt7615_sta *sta;
94 struct mt76_wcid *wcid;
95
96 if (idx >= MT7615_WTBL_SIZE)
97 return NULL;
98
99 wcid = rcu_dereference(dev->mt76.wcid[idx]);
100 if (unicast || !wcid)
101 return wcid;
102
103 if (!wcid->sta)
104 return NULL;
105
106 sta = container_of(wcid, struct mt7615_sta, wcid);
107 if (!sta->vif)
108 return NULL;
109
110 return &sta->vif->sta.wcid;
111 }
112
mt7615_mac_reset_counters(struct mt7615_phy * phy)113 void mt7615_mac_reset_counters(struct mt7615_phy *phy)
114 {
115 struct mt7615_dev *dev = phy->dev;
116 int i;
117
118 for (i = 0; i < 4; i++) {
119 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
120 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
121 }
122
123 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats));
124 phy->mt76->survey_time = ktime_get_boottime();
125
126 /* reset airtime counters */
127 mt76_rr(dev, MT_MIB_SDR9(0));
128 mt76_rr(dev, MT_MIB_SDR9(1));
129
130 mt76_rr(dev, MT_MIB_SDR36(0));
131 mt76_rr(dev, MT_MIB_SDR36(1));
132
133 mt76_rr(dev, MT_MIB_SDR37(0));
134 mt76_rr(dev, MT_MIB_SDR37(1));
135
136 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
137 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
138 }
139
mt7615_mac_set_timing(struct mt7615_phy * phy)140 void mt7615_mac_set_timing(struct mt7615_phy *phy)
141 {
142 s16 coverage_class = phy->coverage_class;
143 struct mt7615_dev *dev = phy->dev;
144 bool ext_phy = phy != &dev->phy;
145 u32 val, reg_offset;
146 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
147 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
148 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
149 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
150 int sifs, offset;
151 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
152
153 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
154 return;
155
156 if (is_5ghz)
157 sifs = 16;
158 else
159 sifs = 10;
160
161 if (ext_phy) {
162 coverage_class = max_t(s16, dev->phy.coverage_class,
163 coverage_class);
164 mt76_set(dev, MT_ARB_SCR,
165 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
166 } else {
167 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
168
169 if (phy_ext)
170 coverage_class = max_t(s16, phy_ext->coverage_class,
171 coverage_class);
172 mt76_set(dev, MT_ARB_SCR,
173 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
174 }
175 udelay(1);
176
177 offset = 3 * coverage_class;
178 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
179 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
180 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
181 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
182
183 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
184 FIELD_PREP(MT_IFS_EIFS, 360) |
185 FIELD_PREP(MT_IFS_RIFS, 2) |
186 FIELD_PREP(MT_IFS_SIFS, sifs) |
187 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
188
189 if (phy->slottime < 20 || is_5ghz)
190 val = MT7615_CFEND_RATE_DEFAULT;
191 else
192 val = MT7615_CFEND_RATE_11B;
193
194 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
195 if (ext_phy)
196 mt76_clear(dev, MT_ARB_SCR,
197 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
198 else
199 mt76_clear(dev, MT_ARB_SCR,
200 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
201
202 }
203
204 static void
mt7615_get_status_freq_info(struct mt7615_dev * dev,struct mt76_phy * mphy,struct mt76_rx_status * status,u8 chfreq)205 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
206 struct mt76_rx_status *status, u8 chfreq)
207 {
208 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
209 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
210 !test_bit(MT76_STATE_ROC, &mphy->state)) {
211 status->freq = mphy->chandef.chan->center_freq;
212 status->band = mphy->chandef.chan->band;
213 return;
214 }
215
216 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
217 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
218 }
219
mt7615_mac_fill_tm_rx(struct mt7615_phy * phy,__le32 * rxv)220 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv)
221 {
222 #ifdef CONFIG_NL80211_TESTMODE
223 u32 rxv1 = le32_to_cpu(rxv[0]);
224 u32 rxv3 = le32_to_cpu(rxv[2]);
225 u32 rxv4 = le32_to_cpu(rxv[3]);
226 u32 rxv5 = le32_to_cpu(rxv[4]);
227 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1);
228 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1);
229 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5);
230 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000;
231
232 if (!mode) {
233 /* CCK */
234 foe &= ~BIT(11);
235 foe *= 1000;
236 foe >>= 11;
237 } else {
238 if (foe > 2048)
239 foe -= 4096;
240
241 foe = (foe * foe_const) >> 15;
242 }
243
244 phy->test.last_freq_offset = foe;
245 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4);
246 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4);
247 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4);
248 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4);
249 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3);
250 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3);
251 #endif
252 }
253
254 /* The HW does not translate the mac header to 802.3 for mesh point */
mt7615_reverse_frag0_hdr_trans(struct sk_buff * skb,u16 hdr_gap)255 static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap)
256 {
257 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
258 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap);
259 struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid;
260 __le32 *rxd = (__le32 *)skb->data;
261 struct ieee80211_sta *sta;
262 struct ieee80211_vif *vif;
263 struct ieee80211_hdr hdr;
264 u16 frame_control;
265
266 if (le32_get_bits(rxd[1], MT_RXD1_NORMAL_ADDR_TYPE) !=
267 MT_RXD1_NORMAL_U2M)
268 return -EINVAL;
269
270 if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4))
271 return -EINVAL;
272
273 if (!msta || !msta->vif)
274 return -EINVAL;
275
276 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
277 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
278
279 /* store the info from RXD and ethhdr to avoid being overridden */
280 frame_control = le32_get_bits(rxd[4], MT_RXD4_FRAME_CONTROL);
281 hdr.frame_control = cpu_to_le16(frame_control);
282 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_SEQ_CTRL));
283 hdr.duration_id = 0;
284
285 ether_addr_copy(hdr.addr1, vif->addr);
286 ether_addr_copy(hdr.addr2, sta->addr);
287 switch (frame_control & (IEEE80211_FCTL_TODS |
288 IEEE80211_FCTL_FROMDS)) {
289 case 0:
290 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid);
291 break;
292 case IEEE80211_FCTL_FROMDS:
293 ether_addr_copy(hdr.addr3, eth_hdr->h_source);
294 break;
295 case IEEE80211_FCTL_TODS:
296 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
297 break;
298 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS:
299 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
300 ether_addr_copy(hdr.addr4, eth_hdr->h_source);
301 break;
302 default:
303 break;
304 }
305
306 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2);
307 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) ||
308 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX))
309 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header);
310 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN)
311 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header);
312 else
313 skb_pull(skb, 2);
314
315 if (ieee80211_has_order(hdr.frame_control))
316 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[7],
317 IEEE80211_HT_CTL_LEN);
318
319 if (ieee80211_is_data_qos(hdr.frame_control)) {
320 __le16 qos_ctrl;
321
322 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_QOS_CTL));
323 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl,
324 IEEE80211_QOS_CTL_LEN);
325 }
326
327 if (ieee80211_has_a4(hdr.frame_control))
328 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr));
329 else
330 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6);
331
332 status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU);
333 return 0;
334 }
335
mt7615_mac_fill_rx(struct mt7615_dev * dev,struct sk_buff * skb)336 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
337 {
338 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
339 struct mt76_phy *mphy = &dev->mt76.phy;
340 struct mt7615_phy *phy = &dev->phy;
341 struct ieee80211_supported_band *sband;
342 struct ieee80211_hdr *hdr;
343 struct mt7615_phy *phy2;
344 __le32 *rxd = (__le32 *)skb->data;
345 u32 rxd0 = le32_to_cpu(rxd[0]);
346 u32 rxd1 = le32_to_cpu(rxd[1]);
347 u32 rxd2 = le32_to_cpu(rxd[2]);
348 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
349 u32 csum_status = *(u32 *)skb->cb;
350 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false;
351 u16 hdr_gap;
352 int phy_idx;
353 int i, idx;
354 u8 chfreq, amsdu_info, qos_ctl = 0;
355 u16 seq_ctrl = 0;
356 __le16 fc = 0;
357
358 memset(status, 0, sizeof(*status));
359
360 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
361
362 phy2 = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL;
363 if (!phy2)
364 phy_idx = 0;
365 else if (phy2->chfreq == phy->chfreq)
366 phy_idx = -1;
367 else if (phy->chfreq == chfreq)
368 phy_idx = 0;
369 else if (phy2->chfreq == chfreq)
370 phy_idx = 1;
371 else
372 phy_idx = -1;
373
374 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
375 return -EINVAL;
376
377 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS;
378 if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM))
379 return -EINVAL;
380
381 /* ICV error or CCMP/BIP/WPI MIC error */
382 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR)
383 status->flag |= RX_FLAG_ONLY_MONITOR;
384
385 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
386 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
387 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
388
389 if (status->wcid) {
390 struct mt7615_sta *msta;
391
392 msta = container_of(status->wcid, struct mt7615_sta, wcid);
393 spin_lock_bh(&dev->mt76.sta_poll_lock);
394 if (list_empty(&msta->wcid.poll_list))
395 list_add_tail(&msta->wcid.poll_list,
396 &dev->mt76.sta_poll_list);
397 spin_unlock_bh(&dev->mt76.sta_poll_lock);
398 }
399
400 if (mt76_is_mmio(&dev->mt76) && (rxd0 & csum_mask) == csum_mask &&
401 !(csum_status & (BIT(0) | BIT(2) | BIT(3))))
402 skb->ip_summed = CHECKSUM_UNNECESSARY;
403
404 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
405 status->flag |= RX_FLAG_FAILED_FCS_CRC;
406
407 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
408 status->flag |= RX_FLAG_MMIC_ERROR;
409
410 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
411 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
412 status->flag |= RX_FLAG_DECRYPTED;
413 status->flag |= RX_FLAG_IV_STRIPPED;
414 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
415 }
416
417 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
418
419 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
420 return -EINVAL;
421
422 rxd += 4;
423 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
424 u32 v0 = le32_to_cpu(rxd[0]);
425 u32 v2 = le32_to_cpu(rxd[2]);
426
427 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0));
428 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2);
429 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2);
430
431 rxd += 4;
432 if ((u8 *)rxd - skb->data >= skb->len)
433 return -EINVAL;
434 }
435
436 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
437 u8 *data = (u8 *)rxd;
438
439 if (status->flag & RX_FLAG_DECRYPTED) {
440 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
441 case MT_CIPHER_AES_CCMP:
442 case MT_CIPHER_CCMP_CCX:
443 case MT_CIPHER_CCMP_256:
444 insert_ccmp_hdr =
445 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
446 fallthrough;
447 case MT_CIPHER_TKIP:
448 case MT_CIPHER_TKIP_NO_MIC:
449 case MT_CIPHER_GCMP:
450 case MT_CIPHER_GCMP_256:
451 status->iv[0] = data[5];
452 status->iv[1] = data[4];
453 status->iv[2] = data[3];
454 status->iv[3] = data[2];
455 status->iv[4] = data[1];
456 status->iv[5] = data[0];
457 break;
458 default:
459 break;
460 }
461 }
462 rxd += 4;
463 if ((u8 *)rxd - skb->data >= skb->len)
464 return -EINVAL;
465 }
466
467 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
468 status->timestamp = le32_to_cpu(rxd[0]);
469 status->flag |= RX_FLAG_MACTIME_START;
470
471 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
472 MT_RXD2_NORMAL_NON_AMPDU))) {
473 status->flag |= RX_FLAG_AMPDU_DETAILS;
474
475 /* all subframes of an A-MPDU have the same timestamp */
476 if (phy->rx_ampdu_ts != status->timestamp) {
477 if (!++phy->ampdu_ref)
478 phy->ampdu_ref++;
479 }
480 phy->rx_ampdu_ts = status->timestamp;
481
482 status->ampdu_ref = phy->ampdu_ref;
483 }
484
485 rxd += 2;
486 if ((u8 *)rxd - skb->data >= skb->len)
487 return -EINVAL;
488 }
489
490 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
491 u32 rxdg5 = le32_to_cpu(rxd[5]);
492
493 /*
494 * If both PHYs are on the same channel and we don't have a WCID,
495 * we need to figure out which PHY this packet was received on.
496 * On the primary PHY, the noise value for the chains belonging to the
497 * second PHY will be set to the noise value of the last packet from
498 * that PHY.
499 */
500 if (phy_idx < 0) {
501 int first_chain = ffs(phy2->mt76->chainmask) - 1;
502
503 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
504 }
505 }
506
507 if (phy_idx == 1 && phy2) {
508 mphy = dev->mt76.phys[MT_BAND1];
509 phy = phy2;
510 status->phy_idx = phy_idx;
511 }
512
513 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
514 return -EINVAL;
515
516 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
517 if (status->band == NL80211_BAND_5GHZ)
518 sband = &mphy->sband_5g.sband;
519 else
520 sband = &mphy->sband_2g.sband;
521
522 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
523 return -EINVAL;
524
525 if (!sband->channels)
526 return -EINVAL;
527
528 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
529 u32 rxdg0 = le32_to_cpu(rxd[0]);
530 u32 rxdg1 = le32_to_cpu(rxd[1]);
531 u32 rxdg3 = le32_to_cpu(rxd[3]);
532 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
533 bool cck = false;
534
535 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
536 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
537 case MT_PHY_TYPE_CCK:
538 cck = true;
539 fallthrough;
540 case MT_PHY_TYPE_OFDM:
541 i = mt76_get_rate(&dev->mt76, sband, i, cck);
542 break;
543 case MT_PHY_TYPE_HT_GF:
544 case MT_PHY_TYPE_HT:
545 status->encoding = RX_ENC_HT;
546 if (i > 31)
547 return -EINVAL;
548 break;
549 case MT_PHY_TYPE_VHT:
550 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
551 status->encoding = RX_ENC_VHT;
552 break;
553 default:
554 return -EINVAL;
555 }
556 status->rate_idx = i;
557
558 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
559 case MT_PHY_BW_20:
560 break;
561 case MT_PHY_BW_40:
562 status->bw = RATE_INFO_BW_40;
563 break;
564 case MT_PHY_BW_80:
565 status->bw = RATE_INFO_BW_80;
566 break;
567 case MT_PHY_BW_160:
568 status->bw = RATE_INFO_BW_160;
569 break;
570 default:
571 return -EINVAL;
572 }
573
574 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
575 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
576 if (rxdg0 & MT_RXV1_HT_AD_CODE)
577 status->enc_flags |= RX_ENC_FLAG_LDPC;
578
579 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
580
581 status->chains = mphy->antenna_mask;
582 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
583 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
584 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
585 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
586
587 mt7615_mac_fill_tm_rx(mphy->priv, rxd);
588
589 rxd += 6;
590 if ((u8 *)rxd - skb->data >= skb->len)
591 return -EINVAL;
592 }
593
594 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1);
595 status->amsdu = !!amsdu_info;
596 if (status->amsdu) {
597 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME;
598 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME;
599 }
600
601 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
602 if (hdr_trans && ieee80211_has_morefrags(fc)) {
603 if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap))
604 return -EINVAL;
605 hdr_trans = false;
606 } else {
607 int pad_start = 0;
608
609 skb_pull(skb, hdr_gap);
610 if (!hdr_trans && status->amsdu) {
611 pad_start = ieee80211_get_hdrlen_from_skb(skb);
612 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) {
613 /*
614 * When header translation failure is indicated,
615 * the hardware will insert an extra 2-byte field
616 * containing the data length after the protocol
617 * type field. This happens either when the LLC-SNAP
618 * pattern did not match, or if a VLAN header was
619 * detected.
620 */
621 pad_start = 12;
622 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q)
623 pad_start += 4;
624 else
625 pad_start = 0;
626 }
627
628 if (pad_start) {
629 memmove(skb->data + 2, skb->data, pad_start);
630 skb_pull(skb, 2);
631 }
632 }
633
634 if (insert_ccmp_hdr && !hdr_trans) {
635 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
636
637 mt76_insert_ccmp_hdr(skb, key_id);
638 }
639
640 if (!hdr_trans) {
641 hdr = (struct ieee80211_hdr *)skb->data;
642 fc = hdr->frame_control;
643 if (ieee80211_is_data_qos(fc)) {
644 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
645 qos_ctl = *ieee80211_get_qos_ctl(hdr);
646 }
647 } else {
648 status->flag |= RX_FLAG_8023;
649 }
650
651 if (!status->wcid || !ieee80211_is_data_qos(fc))
652 return 0;
653
654 status->aggr = unicast &&
655 !ieee80211_is_qos_nullfunc(fc);
656 status->qos_ctl = qos_ctl;
657 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
658
659 return 0;
660 }
661
662 static u16
mt7615_mac_tx_rate_val(struct mt7615_dev * dev,struct mt76_phy * mphy,const struct ieee80211_tx_rate * rate,bool stbc,u8 * bw)663 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
664 struct mt76_phy *mphy,
665 const struct ieee80211_tx_rate *rate,
666 bool stbc, u8 *bw)
667 {
668 u8 phy, nss, rate_idx;
669 u16 rateval = 0;
670
671 *bw = 0;
672
673 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
674 rate_idx = ieee80211_rate_get_vht_mcs(rate);
675 nss = ieee80211_rate_get_vht_nss(rate);
676 phy = MT_PHY_TYPE_VHT;
677 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
678 *bw = 1;
679 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
680 *bw = 2;
681 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
682 *bw = 3;
683 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
684 rate_idx = rate->idx;
685 nss = 1 + (rate->idx >> 3);
686 phy = MT_PHY_TYPE_HT;
687 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
688 phy = MT_PHY_TYPE_HT_GF;
689 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
690 *bw = 1;
691 } else {
692 const struct ieee80211_rate *r;
693 int band = mphy->chandef.chan->band;
694 u16 val;
695
696 nss = 1;
697 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
698 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
699 val = r->hw_value_short;
700 else
701 val = r->hw_value;
702
703 phy = val >> 8;
704 rate_idx = val & 0xff;
705 }
706
707 if (stbc && nss == 1) {
708 nss++;
709 rateval |= MT_TX_RATE_STBC;
710 }
711
712 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
713 FIELD_PREP(MT_TX_RATE_MODE, phy) |
714 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
715
716 return rateval;
717 }
718
mt7615_mac_write_txwi(struct mt7615_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_sta * sta,int pid,struct ieee80211_key_conf * key,enum mt76_txq_id qid,bool beacon)719 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
720 struct sk_buff *skb, struct mt76_wcid *wcid,
721 struct ieee80211_sta *sta, int pid,
722 struct ieee80211_key_conf *key,
723 enum mt76_txq_id qid, bool beacon)
724 {
725 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
726 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
728 struct ieee80211_tx_rate *rate = &info->control.rates[0];
729 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
730 bool multicast = is_multicast_ether_addr(hdr->addr1);
731 struct ieee80211_vif *vif = info->control.vif;
732 bool is_mmio = mt76_is_mmio(&dev->mt76);
733 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE;
734 struct mt76_phy *mphy = &dev->mphy;
735 __le16 fc = hdr->frame_control;
736 int tx_count = 8;
737 u16 seqno = 0;
738
739 if (vif) {
740 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
741
742 omac_idx = mvif->omac_idx;
743 wmm_idx = mvif->wmm_idx;
744 }
745
746 if (sta) {
747 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
748
749 tx_count = msta->rate_count;
750 }
751
752 if (phy_idx && dev->mt76.phys[MT_BAND1])
753 mphy = dev->mt76.phys[MT_BAND1];
754
755 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
756 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
757
758 if (beacon) {
759 p_fmt = MT_TX_TYPE_FW;
760 q_idx = phy_idx ? MT_LMAC_BCN1 : MT_LMAC_BCN0;
761 } else if (qid >= MT_TXQ_PSD) {
762 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
763 q_idx = phy_idx ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0;
764 } else {
765 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
766 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
767 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb));
768 }
769
770 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
771 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
772 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
773 txwi[0] = cpu_to_le32(val);
774
775 val = MT_TXD1_LONG_FORMAT |
776 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
777 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
778 FIELD_PREP(MT_TXD1_HDR_INFO,
779 ieee80211_get_hdrlen_from_skb(skb) / 2) |
780 FIELD_PREP(MT_TXD1_TID,
781 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
782 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
783 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
784 txwi[1] = cpu_to_le32(val);
785
786 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
787 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
788 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
789 if (key) {
790 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
791 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
792 val |= MT_TXD2_BIP;
793 txwi[3] = 0;
794 } else {
795 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
796 }
797 } else {
798 txwi[3] = 0;
799 }
800 txwi[2] = cpu_to_le32(val);
801
802 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
803 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
804
805 txwi[4] = 0;
806 txwi[6] = 0;
807
808 if (rate->idx >= 0 && rate->count &&
809 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
810 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
811 u8 bw;
812 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
813 &bw);
814
815 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
816
817 val = MT_TXD6_FIXED_BW |
818 FIELD_PREP(MT_TXD6_BW, bw) |
819 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
820 txwi[6] |= cpu_to_le32(val);
821
822 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
823 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
824
825 if (info->flags & IEEE80211_TX_CTL_LDPC)
826 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
827
828 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
829 IEEE80211_TX_RC_VHT_MCS)))
830 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
831
832 tx_count = rate->count;
833 }
834
835 if (!ieee80211_is_beacon(fc)) {
836 struct ieee80211_hw *hw = mt76_hw(dev);
837
838 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
839 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
840 val |= MT_TXD5_SW_POWER_MGMT;
841 txwi[5] = cpu_to_le32(val);
842 } else {
843 txwi[5] = 0;
844 /* use maximum tx count for beacons */
845 tx_count = 0x1f;
846 }
847
848 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
849 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
850 seqno = le16_to_cpu(hdr->seq_ctrl);
851
852 if (ieee80211_is_back_req(hdr->frame_control)) {
853 struct ieee80211_bar *bar;
854
855 bar = (struct ieee80211_bar *)skb->data;
856 seqno = le16_to_cpu(bar->start_seq_num);
857 }
858
859 val |= MT_TXD3_SN_VALID |
860 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
861 }
862
863 txwi[3] |= cpu_to_le32(val);
864
865 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
866 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
867
868 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
869 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
870 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
871 txwi[7] = cpu_to_le32(val);
872 if (!is_mmio) {
873 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
874 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
875 txwi[8] = cpu_to_le32(val);
876 }
877
878 return 0;
879 }
880 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
881
mt7615_mac_wtbl_update(struct mt7615_dev * dev,int idx,u32 mask)882 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
883 {
884 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
885 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
886
887 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
888 0, 5000);
889 }
890
mt7615_mac_sta_poll(struct mt7615_dev * dev)891 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
892 {
893 static const u8 ac_to_tid[4] = {
894 [IEEE80211_AC_BE] = 0,
895 [IEEE80211_AC_BK] = 1,
896 [IEEE80211_AC_VI] = 4,
897 [IEEE80211_AC_VO] = 6
898 };
899 static const u8 hw_queue_map[] = {
900 [IEEE80211_AC_BK] = 0,
901 [IEEE80211_AC_BE] = 1,
902 [IEEE80211_AC_VI] = 2,
903 [IEEE80211_AC_VO] = 3,
904 };
905 struct ieee80211_sta *sta;
906 struct mt7615_sta *msta;
907 u32 addr, tx_time[4], rx_time[4];
908 struct list_head sta_poll_list;
909 int i;
910
911 INIT_LIST_HEAD(&sta_poll_list);
912 spin_lock_bh(&dev->mt76.sta_poll_lock);
913 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list);
914 spin_unlock_bh(&dev->mt76.sta_poll_lock);
915
916 while (!list_empty(&sta_poll_list)) {
917 bool clear = false;
918
919 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
920 wcid.poll_list);
921
922 spin_lock_bh(&dev->mt76.sta_poll_lock);
923 list_del_init(&msta->wcid.poll_list);
924 spin_unlock_bh(&dev->mt76.sta_poll_lock);
925
926 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
927
928 for (i = 0; i < 4; i++, addr += 8) {
929 u32 tx_last = msta->airtime_ac[i];
930 u32 rx_last = msta->airtime_ac[i + 4];
931
932 msta->airtime_ac[i] = mt76_rr(dev, addr);
933 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
934 tx_time[i] = msta->airtime_ac[i] - tx_last;
935 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
936
937 if ((tx_last | rx_last) & BIT(30))
938 clear = true;
939 }
940
941 if (clear) {
942 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
943 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
944 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
945 }
946
947 if (!msta->wcid.sta)
948 continue;
949
950 sta = container_of((void *)msta, struct ieee80211_sta,
951 drv_priv);
952 for (i = 0; i < 4; i++) {
953 u32 tx_cur = tx_time[i];
954 u32 rx_cur = rx_time[hw_queue_map[i]];
955 u8 tid = ac_to_tid[i];
956
957 if (!tx_cur && !rx_cur)
958 continue;
959
960 ieee80211_sta_register_airtime(sta, tid, tx_cur,
961 rx_cur);
962 }
963 }
964 }
965 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
966
967 static void
mt7615_mac_update_rate_desc(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates,struct mt7615_rate_desc * rd)968 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
969 struct ieee80211_tx_rate *probe_rate,
970 struct ieee80211_tx_rate *rates,
971 struct mt7615_rate_desc *rd)
972 {
973 struct mt7615_dev *dev = phy->dev;
974 struct mt76_phy *mphy = phy->mt76;
975 struct ieee80211_tx_rate *ref;
976 bool rateset, stbc = false;
977 int n_rates = sta->n_rates;
978 u8 bw, bw_prev;
979 int i, j;
980
981 for (i = n_rates; i < 4; i++)
982 rates[i] = rates[n_rates - 1];
983
984 rateset = !(sta->rate_set_tsf & BIT(0));
985 memcpy(sta->rateset[rateset].rates, rates,
986 sizeof(sta->rateset[rateset].rates));
987 if (probe_rate) {
988 sta->rateset[rateset].probe_rate = *probe_rate;
989 ref = &sta->rateset[rateset].probe_rate;
990 } else {
991 sta->rateset[rateset].probe_rate.idx = -1;
992 ref = &sta->rateset[rateset].rates[0];
993 }
994
995 rates = sta->rateset[rateset].rates;
996 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
997 /*
998 * We don't support switching between short and long GI
999 * within the rate set. For accurate tx status reporting, we
1000 * need to make sure that flags match.
1001 * For improved performance, avoid duplicate entries by
1002 * decrementing the MCS index if necessary
1003 */
1004 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
1005 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
1006
1007 for (j = 0; j < i; j++) {
1008 if (rates[i].idx != rates[j].idx)
1009 continue;
1010 if ((rates[i].flags ^ rates[j].flags) &
1011 (IEEE80211_TX_RC_40_MHZ_WIDTH |
1012 IEEE80211_TX_RC_80_MHZ_WIDTH |
1013 IEEE80211_TX_RC_160_MHZ_WIDTH))
1014 continue;
1015
1016 if (!rates[i].idx)
1017 continue;
1018
1019 rates[i].idx--;
1020 }
1021 }
1022
1023 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
1024 bw_prev = bw;
1025
1026 if (probe_rate) {
1027 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
1028 stbc, &bw);
1029 if (bw)
1030 rd->bw_idx = 1;
1031 else
1032 bw_prev = 0;
1033 } else {
1034 rd->probe_val = rd->val[0];
1035 }
1036
1037 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
1038 if (bw_prev) {
1039 rd->bw_idx = 3;
1040 bw_prev = bw;
1041 }
1042
1043 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
1044 if (bw_prev) {
1045 rd->bw_idx = 5;
1046 bw_prev = bw;
1047 }
1048
1049 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
1050 if (bw_prev)
1051 rd->bw_idx = 7;
1052
1053 rd->rateset = rateset;
1054 rd->bw = bw;
1055 }
1056
1057 static int
mt7615_mac_queue_rate_update(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)1058 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
1059 struct ieee80211_tx_rate *probe_rate,
1060 struct ieee80211_tx_rate *rates)
1061 {
1062 struct mt7615_dev *dev = phy->dev;
1063 struct mt7615_wtbl_rate_desc *wrd;
1064
1065 if (work_pending(&dev->rate_work))
1066 return -EBUSY;
1067
1068 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC);
1069 if (!wrd)
1070 return -ENOMEM;
1071
1072 wrd->sta = sta;
1073 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
1074 &wrd->rate);
1075 list_add_tail(&wrd->node, &dev->wrd_head);
1076 queue_work(dev->mt76.wq, &dev->rate_work);
1077
1078 return 0;
1079 }
1080
mt7615_mac_get_sta_tid_sn(struct mt7615_dev * dev,int wcid,u8 tid)1081 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid)
1082 {
1083 u32 addr, val, val2;
1084 u8 offset;
1085
1086 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4;
1087
1088 offset = tid * 12;
1089 addr += 4 * (offset / 32);
1090 offset %= 32;
1091
1092 val = mt76_rr(dev, addr);
1093 val >>= offset;
1094
1095 if (offset > 20) {
1096 addr += 4;
1097 val2 = mt76_rr(dev, addr);
1098 val |= val2 << (32 - offset);
1099 }
1100
1101 return val & GENMASK(11, 0);
1102 }
1103
mt7615_mac_set_rates(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)1104 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
1105 struct ieee80211_tx_rate *probe_rate,
1106 struct ieee80211_tx_rate *rates)
1107 {
1108 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
1109 struct mt7615_dev *dev = phy->dev;
1110 struct mt7615_rate_desc rd;
1111 u32 w5, w27, addr;
1112 u16 idx = sta->vif->mt76.omac_idx;
1113
1114 if (!mt76_is_mmio(&dev->mt76)) {
1115 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
1116 return;
1117 }
1118
1119 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1120 return;
1121
1122 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
1123 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
1124
1125 addr = mt7615_mac_wtbl_addr(dev, wcid);
1126 w27 = mt76_rr(dev, addr + 27 * 4);
1127 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
1128 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
1129
1130 w5 = mt76_rr(dev, addr + 5 * 4);
1131 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
1132 MT_WTBL_W5_MPDU_OK_COUNT |
1133 MT_WTBL_W5_MPDU_FAIL_COUNT |
1134 MT_WTBL_W5_RATE_IDX);
1135 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
1136 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
1137 rd.bw_idx ? rd.bw_idx - 1 : 7);
1138
1139 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
1140
1141 mt76_wr(dev, MT_WTBL_RIUCR1,
1142 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
1143 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
1144 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
1145
1146 mt76_wr(dev, MT_WTBL_RIUCR2,
1147 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
1148 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
1149 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
1150 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
1151
1152 mt76_wr(dev, MT_WTBL_RIUCR3,
1153 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
1154 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
1155 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
1156
1157 mt76_wr(dev, MT_WTBL_UPDATE,
1158 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
1159 MT_WTBL_UPDATE_RATE_UPDATE |
1160 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
1161
1162 mt76_wr(dev, addr + 27 * 4, w27);
1163
1164 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx;
1165 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx);
1166
1167 mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */
1168 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
1169 sta->rate_set_tsf |= rd.rateset;
1170
1171 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
1172 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
1173
1174 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
1175 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
1176 sta->rate_probe = !!probe_rate;
1177 }
1178 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
1179
mt7615_mac_enable_rtscts(struct mt7615_dev * dev,struct ieee80211_vif * vif,bool enable)1180 void mt7615_mac_enable_rtscts(struct mt7615_dev *dev,
1181 struct ieee80211_vif *vif, bool enable)
1182 {
1183 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1184 u32 addr;
1185
1186 addr = mt7615_mac_wtbl_addr(dev, mvif->sta.wcid.idx) + 3 * 4;
1187
1188 if (enable)
1189 mt76_set(dev, addr, MT_WTBL_W3_RTS);
1190 else
1191 mt76_clear(dev, addr, MT_WTBL_W3_RTS);
1192 }
1193 EXPORT_SYMBOL_GPL(mt7615_mac_enable_rtscts);
1194
1195 static int
mt7615_mac_wtbl_update_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,struct ieee80211_key_conf * key,enum mt76_cipher_type cipher,u16 cipher_mask)1196 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1197 struct ieee80211_key_conf *key,
1198 enum mt76_cipher_type cipher, u16 cipher_mask)
1199 {
1200 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
1201 u8 data[32] = {};
1202
1203 if (key->keylen > sizeof(data))
1204 return -EINVAL;
1205
1206 mt76_rr_copy(dev, addr, data, sizeof(data));
1207 if (cipher == MT_CIPHER_TKIP) {
1208 /* Rx/Tx MIC keys are swapped */
1209 memcpy(data, key->key, 16);
1210 memcpy(data + 16, key->key + 24, 8);
1211 memcpy(data + 24, key->key + 16, 8);
1212 } else {
1213 if (cipher_mask == BIT(cipher))
1214 memcpy(data, key->key, key->keylen);
1215 else if (cipher != MT_CIPHER_BIP_CMAC_128)
1216 memcpy(data, key->key, 16);
1217 if (cipher == MT_CIPHER_BIP_CMAC_128)
1218 memcpy(data + 16, key->key, 16);
1219 }
1220
1221 mt76_wr_copy(dev, addr, data, sizeof(data));
1222
1223 return 0;
1224 }
1225
1226 static int
mt7615_mac_wtbl_update_pk(struct mt7615_dev * dev,struct mt76_wcid * wcid,enum mt76_cipher_type cipher,u16 cipher_mask,int keyidx)1227 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1228 enum mt76_cipher_type cipher, u16 cipher_mask,
1229 int keyidx)
1230 {
1231 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1232
1233 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1234 return -ETIMEDOUT;
1235
1236 w0 = mt76_rr(dev, addr);
1237 w1 = mt76_rr(dev, addr + 4);
1238
1239 if (cipher_mask)
1240 w0 |= MT_WTBL_W0_RX_KEY_VALID;
1241 else
1242 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX);
1243 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128))
1244 w0 |= MT_WTBL_W0_RX_IK_VALID;
1245 else
1246 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1247
1248 if (cipher != MT_CIPHER_BIP_CMAC_128 || cipher_mask == BIT(cipher)) {
1249 w0 &= ~MT_WTBL_W0_KEY_IDX;
1250 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1251 }
1252
1253 mt76_wr(dev, MT_WTBL_RICR0, w0);
1254 mt76_wr(dev, MT_WTBL_RICR1, w1);
1255
1256 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1257 MT_WTBL_UPDATE_RXINFO_UPDATE))
1258 return -ETIMEDOUT;
1259
1260 return 0;
1261 }
1262
1263 static void
mt7615_mac_wtbl_update_cipher(struct mt7615_dev * dev,struct mt76_wcid * wcid,enum mt76_cipher_type cipher,u16 cipher_mask)1264 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1265 enum mt76_cipher_type cipher, u16 cipher_mask)
1266 {
1267 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1268
1269 if (cipher == MT_CIPHER_BIP_CMAC_128 &&
1270 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128))
1271 return;
1272
1273 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1274 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1275 }
1276
__mt7615_mac_wtbl_set_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,struct ieee80211_key_conf * key)1277 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1278 struct mt76_wcid *wcid,
1279 struct ieee80211_key_conf *key)
1280 {
1281 enum mt76_cipher_type cipher;
1282 u16 cipher_mask = wcid->cipher;
1283 int err;
1284
1285 cipher = mt7615_mac_get_cipher(key->cipher);
1286 if (cipher == MT_CIPHER_NONE)
1287 return -EOPNOTSUPP;
1288
1289 cipher_mask |= BIT(cipher);
1290 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask);
1291 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask);
1292 if (err < 0)
1293 return err;
1294
1295 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask,
1296 key->keyidx);
1297 if (err < 0)
1298 return err;
1299
1300 wcid->cipher = cipher_mask;
1301
1302 return 0;
1303 }
1304
mt7615_mac_wtbl_set_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,struct ieee80211_key_conf * key)1305 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1306 struct mt76_wcid *wcid,
1307 struct ieee80211_key_conf *key)
1308 {
1309 int err;
1310
1311 spin_lock_bh(&dev->mt76.lock);
1312 err = __mt7615_mac_wtbl_set_key(dev, wcid, key);
1313 spin_unlock_bh(&dev->mt76.lock);
1314
1315 return err;
1316 }
1317
mt7615_fill_txs(struct mt7615_dev * dev,struct mt7615_sta * sta,struct ieee80211_tx_info * info,__le32 * txs_data)1318 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1319 struct ieee80211_tx_info *info, __le32 *txs_data)
1320 {
1321 struct ieee80211_supported_band *sband;
1322 struct mt7615_rate_set *rs;
1323 struct mt76_phy *mphy;
1324 int first_idx = 0, last_idx;
1325 int i, idx, count;
1326 bool fixed_rate, ack_timeout;
1327 bool ampdu, cck = false;
1328 bool rs_idx;
1329 u32 rate_set_tsf;
1330 u32 final_rate, final_rate_flags, final_nss, txs;
1331
1332 txs = le32_to_cpu(txs_data[1]);
1333 ampdu = txs & MT_TXS1_AMPDU;
1334
1335 txs = le32_to_cpu(txs_data[3]);
1336 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1337 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1338
1339 txs = le32_to_cpu(txs_data[0]);
1340 fixed_rate = txs & MT_TXS0_FIXED_RATE;
1341 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1342 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1343
1344 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1345 return false;
1346
1347 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1348 return false;
1349
1350 if (!ack_timeout)
1351 info->flags |= IEEE80211_TX_STAT_ACK;
1352
1353 info->status.ampdu_len = 1;
1354 info->status.ampdu_ack_len = !!(info->flags &
1355 IEEE80211_TX_STAT_ACK);
1356
1357 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1358 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1359
1360 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1361
1362 if (fixed_rate) {
1363 info->status.rates[0].count = count;
1364 i = 0;
1365 goto out;
1366 }
1367
1368 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1369 rs_idx = !((u32)(le32_get_bits(txs_data[4], MT_TXS4_F0_TIMESTAMP) -
1370 rate_set_tsf) < 1000000);
1371 rs_idx ^= rate_set_tsf & BIT(0);
1372 rs = &sta->rateset[rs_idx];
1373
1374 if (!first_idx && rs->probe_rate.idx >= 0) {
1375 info->status.rates[0] = rs->probe_rate;
1376
1377 spin_lock_bh(&dev->mt76.lock);
1378 if (sta->rate_probe) {
1379 struct mt7615_phy *phy = &dev->phy;
1380
1381 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1])
1382 phy = dev->mt76.phys[MT_BAND1]->priv;
1383
1384 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1385 }
1386 spin_unlock_bh(&dev->mt76.lock);
1387 } else {
1388 info->status.rates[0] = rs->rates[first_idx / 2];
1389 }
1390 info->status.rates[0].count = 0;
1391
1392 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1393 struct ieee80211_tx_rate *cur_rate;
1394 int cur_count;
1395
1396 cur_rate = &rs->rates[idx / 2];
1397 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1398 count -= cur_count;
1399
1400 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1401 cur_rate->flags != info->status.rates[i].flags)) {
1402 i++;
1403 if (i == ARRAY_SIZE(info->status.rates)) {
1404 i--;
1405 break;
1406 }
1407
1408 info->status.rates[i] = *cur_rate;
1409 info->status.rates[i].count = 0;
1410 }
1411
1412 info->status.rates[i].count += cur_count;
1413 }
1414
1415 out:
1416 final_rate_flags = info->status.rates[i].flags;
1417
1418 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1419 case MT_PHY_TYPE_CCK:
1420 cck = true;
1421 fallthrough;
1422 case MT_PHY_TYPE_OFDM:
1423 mphy = &dev->mphy;
1424 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1])
1425 mphy = dev->mt76.phys[MT_BAND1];
1426
1427 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1428 sband = &mphy->sband_5g.sband;
1429 else
1430 sband = &mphy->sband_2g.sband;
1431 final_rate &= MT_TX_RATE_IDX;
1432 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1433 cck);
1434 final_rate_flags = 0;
1435 break;
1436 case MT_PHY_TYPE_HT_GF:
1437 case MT_PHY_TYPE_HT:
1438 final_rate_flags |= IEEE80211_TX_RC_MCS;
1439 final_rate &= MT_TX_RATE_IDX;
1440 if (final_rate > 31)
1441 return false;
1442 break;
1443 case MT_PHY_TYPE_VHT:
1444 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1445
1446 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1447 final_nss--;
1448
1449 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1450 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1451 break;
1452 default:
1453 return false;
1454 }
1455
1456 info->status.rates[i].idx = final_rate;
1457 info->status.rates[i].flags = final_rate_flags;
1458
1459 return true;
1460 }
1461
mt7615_mac_add_txs_skb(struct mt7615_dev * dev,struct mt7615_sta * sta,int pid,__le32 * txs_data)1462 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1463 struct mt7615_sta *sta, int pid,
1464 __le32 *txs_data)
1465 {
1466 struct mt76_dev *mdev = &dev->mt76;
1467 struct sk_buff_head list;
1468 struct sk_buff *skb;
1469
1470 if (pid < MT_PACKET_ID_FIRST)
1471 return false;
1472
1473 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1474
1475 mt76_tx_status_lock(mdev, &list);
1476 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1477 if (skb) {
1478 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1479
1480 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1481 info->status.rates[0].count = 0;
1482 info->status.rates[0].idx = -1;
1483 }
1484
1485 mt76_tx_status_skb_done(mdev, skb, &list);
1486 }
1487 mt76_tx_status_unlock(mdev, &list);
1488
1489 return !!skb;
1490 }
1491
mt7615_mac_add_txs(struct mt7615_dev * dev,void * data)1492 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1493 {
1494 struct ieee80211_tx_info info = {};
1495 struct ieee80211_sta *sta = NULL;
1496 struct mt7615_sta *msta = NULL;
1497 struct mt76_wcid *wcid;
1498 struct mt76_phy *mphy = &dev->mt76.phy;
1499 __le32 *txs_data = data;
1500 u8 wcidx;
1501 u8 pid;
1502
1503 pid = le32_get_bits(txs_data[0], MT_TXS0_PID);
1504 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
1505
1506 if (pid == MT_PACKET_ID_NO_ACK)
1507 return;
1508
1509 if (wcidx >= MT7615_WTBL_SIZE)
1510 return;
1511
1512 rcu_read_lock();
1513
1514 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1515 if (!wcid)
1516 goto out;
1517
1518 msta = container_of(wcid, struct mt7615_sta, wcid);
1519 sta = wcid_to_sta(wcid);
1520
1521 spin_lock_bh(&dev->mt76.sta_poll_lock);
1522 if (list_empty(&msta->wcid.poll_list))
1523 list_add_tail(&msta->wcid.poll_list, &dev->mt76.sta_poll_list);
1524 spin_unlock_bh(&dev->mt76.sta_poll_lock);
1525
1526 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1527 goto out;
1528
1529 if (wcidx >= MT7615_WTBL_STA || !sta)
1530 goto out;
1531
1532 if (wcid->phy_idx && dev->mt76.phys[MT_BAND1])
1533 mphy = dev->mt76.phys[MT_BAND1];
1534
1535 if (mt7615_fill_txs(dev, msta, &info, txs_data)) {
1536 spin_lock_bh(&dev->mt76.rx_lock);
1537 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1538 spin_unlock_bh(&dev->mt76.rx_lock);
1539 }
1540
1541 out:
1542 rcu_read_unlock();
1543 }
1544
1545 static void
mt7615_txwi_free(struct mt7615_dev * dev,struct mt76_txwi_cache * txwi)1546 mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi)
1547 {
1548 struct mt76_dev *mdev = &dev->mt76;
1549 __le32 *txwi_data;
1550 u32 val;
1551 u8 wcid;
1552
1553 mt76_connac_txp_skb_unmap(mdev, txwi);
1554 if (!txwi->skb)
1555 goto out;
1556
1557 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi);
1558 val = le32_to_cpu(txwi_data[1]);
1559 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val);
1560 mt76_tx_complete_skb(mdev, wcid, txwi->skb);
1561
1562 out:
1563 txwi->skb = NULL;
1564 mt76_put_txwi(mdev, txwi);
1565 }
1566
1567 static void
mt7615_mac_tx_free_token(struct mt7615_dev * dev,u16 token)1568 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1569 {
1570 struct mt76_dev *mdev = &dev->mt76;
1571 struct mt76_txwi_cache *txwi;
1572
1573 trace_mac_tx_free(dev, token);
1574 txwi = mt76_token_put(mdev, token);
1575 if (!txwi)
1576 return;
1577
1578 mt7615_txwi_free(dev, txwi);
1579 }
1580
1581 #if defined(__linux__)
mt7615_mac_tx_free(struct mt7615_dev * dev,void * data,int len)1582 static void mt7615_mac_tx_free(struct mt7615_dev *dev, void *data, int len)
1583 #elif defined(__FreeBSD__)
1584 static void mt7615_mac_tx_free(struct mt7615_dev *dev, u8 *data, int len)
1585 #endif
1586 {
1587 #if defined(__linux__)
1588 struct mt76_connac_tx_free *free = data;
1589 #elif defined(__FreeBSD__)
1590 struct mt76_connac_tx_free *free = (void *)data;
1591 #endif
1592 void *tx_token = data + sizeof(*free);
1593 void *end = data + len;
1594 u8 i, count;
1595
1596 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1597 if (is_mt7615(&dev->mt76)) {
1598 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1599 } else {
1600 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1601 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
1602 }
1603
1604 count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_ID_CNT);
1605 if (is_mt7615(&dev->mt76)) {
1606 __le16 *token = tx_token;
1607
1608 if (WARN_ON_ONCE((void *)&token[count] > end))
1609 return;
1610
1611 for (i = 0; i < count; i++)
1612 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1613 } else {
1614 __le32 *token = tx_token;
1615
1616 if (WARN_ON_ONCE((void *)&token[count] > end))
1617 return;
1618
1619 for (i = 0; i < count; i++)
1620 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1621 }
1622
1623 rcu_read_lock();
1624 mt7615_mac_sta_poll(dev);
1625 rcu_read_unlock();
1626
1627 mt76_worker_schedule(&dev->mt76.tx_worker);
1628 }
1629
mt7615_rx_check(struct mt76_dev * mdev,void * data,int len)1630 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
1631 {
1632 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1633 __le32 *rxd = (__le32 *)data;
1634 __le32 *end = (__le32 *)&rxd[len / 4];
1635 enum rx_pkt_type type;
1636
1637 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1638
1639 switch (type) {
1640 case PKT_TYPE_TXRX_NOTIFY:
1641 mt7615_mac_tx_free(dev, data, len);
1642 return false;
1643 case PKT_TYPE_TXS:
1644 for (rxd++; rxd + 7 <= end; rxd += 7)
1645 mt7615_mac_add_txs(dev, rxd);
1646 return false;
1647 default:
1648 return true;
1649 }
1650 }
1651 EXPORT_SYMBOL_GPL(mt7615_rx_check);
1652
mt7615_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb,u32 * info)1653 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1654 struct sk_buff *skb, u32 *info)
1655 {
1656 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1657 __le32 *rxd = (__le32 *)skb->data;
1658 __le32 *end = (__le32 *)&skb->data[skb->len];
1659 enum rx_pkt_type type;
1660 u16 flag;
1661
1662 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1663 flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG);
1664 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1665 type = PKT_TYPE_NORMAL_MCU;
1666
1667 switch (type) {
1668 case PKT_TYPE_TXS:
1669 for (rxd++; rxd + 7 <= end; rxd += 7)
1670 mt7615_mac_add_txs(dev, rxd);
1671 dev_kfree_skb(skb);
1672 break;
1673 case PKT_TYPE_TXRX_NOTIFY:
1674 mt7615_mac_tx_free(dev, skb->data, skb->len);
1675 dev_kfree_skb(skb);
1676 break;
1677 case PKT_TYPE_RX_EVENT:
1678 mt7615_mcu_rx_event(dev, skb);
1679 break;
1680 case PKT_TYPE_NORMAL_MCU:
1681 case PKT_TYPE_NORMAL:
1682 if (!mt7615_mac_fill_rx(dev, skb)) {
1683 mt76_rx(&dev->mt76, q, skb);
1684 return;
1685 }
1686 fallthrough;
1687 default:
1688 dev_kfree_skb(skb);
1689 break;
1690 }
1691 }
1692 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1693
1694 static void
mt7615_mac_set_sensitivity(struct mt7615_phy * phy,int val,bool ofdm)1695 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1696 {
1697 struct mt7615_dev *dev = phy->dev;
1698 bool ext_phy = phy != &dev->phy;
1699
1700 if (is_mt7663(&dev->mt76)) {
1701 if (ofdm)
1702 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1703 MT_WF_PHY_PD_OFDM_MASK(0),
1704 MT_WF_PHY_PD_OFDM(0, val));
1705 else
1706 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1707 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1708 MT_WF_PHY_PD_CCK(ext_phy, val));
1709 return;
1710 }
1711
1712 if (ofdm)
1713 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1714 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1715 MT_WF_PHY_PD_OFDM(ext_phy, val));
1716 else
1717 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1718 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1719 MT_WF_PHY_PD_CCK(ext_phy, val));
1720 }
1721
1722 static void
mt7615_mac_set_default_sensitivity(struct mt7615_phy * phy)1723 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1724 {
1725 /* ofdm */
1726 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1727 /* cck */
1728 mt7615_mac_set_sensitivity(phy, 0x92, false);
1729
1730 phy->ofdm_sensitivity = -98;
1731 phy->cck_sensitivity = -110;
1732 phy->last_cca_adj = jiffies;
1733 }
1734
mt7615_mac_set_scs(struct mt7615_phy * phy,bool enable)1735 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1736 {
1737 struct mt7615_dev *dev = phy->dev;
1738 bool ext_phy = phy != &dev->phy;
1739 u32 reg, mask;
1740
1741 mt7615_mutex_acquire(dev);
1742
1743 if (phy->scs_en == enable)
1744 goto out;
1745
1746 if (is_mt7663(&dev->mt76)) {
1747 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1748 mask = MT_WF_PHY_PD_BLK(0);
1749 } else {
1750 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1751 mask = MT_WF_PHY_PD_BLK(ext_phy);
1752 }
1753
1754 if (enable) {
1755 mt76_set(dev, reg, mask);
1756 if (is_mt7622(&dev->mt76)) {
1757 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1758 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1759 }
1760 } else {
1761 mt76_clear(dev, reg, mask);
1762 }
1763
1764 mt7615_mac_set_default_sensitivity(phy);
1765 phy->scs_en = enable;
1766
1767 out:
1768 mt7615_mutex_release(dev);
1769 }
1770
mt7615_mac_enable_nf(struct mt7615_dev * dev,bool ext_phy)1771 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1772 {
1773 u32 rxtd, reg;
1774
1775 if (is_mt7663(&dev->mt76))
1776 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1777 else
1778 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1779
1780 if (ext_phy)
1781 rxtd = MT_WF_PHY_RXTD2(10);
1782 else
1783 rxtd = MT_WF_PHY_RXTD(12);
1784
1785 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1786 mt76_set(dev, reg, 0x5 << 12);
1787 }
1788
mt7615_mac_cca_stats_reset(struct mt7615_phy * phy)1789 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1790 {
1791 struct mt7615_dev *dev = phy->dev;
1792 bool ext_phy = phy != &dev->phy;
1793 u32 reg;
1794
1795 if (is_mt7663(&dev->mt76))
1796 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1797 else
1798 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1799
1800 /* reset PD and MDRDY counters */
1801 mt76_clear(dev, reg, GENMASK(22, 20));
1802 mt76_set(dev, reg, BIT(22) | BIT(20));
1803 }
1804
1805 static void
mt7615_mac_adjust_sensitivity(struct mt7615_phy * phy,u32 rts_err_rate,bool ofdm)1806 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1807 u32 rts_err_rate, bool ofdm)
1808 {
1809 struct mt7615_dev *dev = phy->dev;
1810 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1811 bool ext_phy = phy != &dev->phy;
1812 s16 def_th = ofdm ? -98 : -110;
1813 bool update = false;
1814 s8 *sensitivity;
1815 int signal;
1816
1817 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1818 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1819 if (!signal) {
1820 mt7615_mac_set_default_sensitivity(phy);
1821 return;
1822 }
1823
1824 signal = min(signal, -72);
1825 if (false_cca > 500) {
1826 if (rts_err_rate > MT_FRAC(40, 100))
1827 return;
1828
1829 /* decrease coverage */
1830 if (*sensitivity == def_th && signal > -90) {
1831 *sensitivity = -90;
1832 update = true;
1833 } else if (*sensitivity + 2 < signal) {
1834 *sensitivity += 2;
1835 update = true;
1836 }
1837 } else if ((false_cca > 0 && false_cca < 50) ||
1838 rts_err_rate > MT_FRAC(60, 100)) {
1839 /* increase coverage */
1840 if (*sensitivity - 2 >= def_th) {
1841 *sensitivity -= 2;
1842 update = true;
1843 }
1844 }
1845
1846 if (*sensitivity > signal) {
1847 *sensitivity = signal;
1848 update = true;
1849 }
1850
1851 if (update) {
1852 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1853
1854 mt7615_mac_set_sensitivity(phy, val, ofdm);
1855 phy->last_cca_adj = jiffies;
1856 }
1857 }
1858
1859 static void
mt7615_mac_scs_check(struct mt7615_phy * phy)1860 mt7615_mac_scs_check(struct mt7615_phy *phy)
1861 {
1862 struct mt7615_dev *dev = phy->dev;
1863 struct mib_stats *mib = &phy->mib;
1864 u32 val, rts_err_rate = 0;
1865 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1866 bool ext_phy = phy != &dev->phy;
1867
1868 if (!phy->scs_en)
1869 return;
1870
1871 if (is_mt7663(&dev->mt76))
1872 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1873 else
1874 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1875 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1876 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1877
1878 if (is_mt7663(&dev->mt76))
1879 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1880 else
1881 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1882 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1883 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1884
1885 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1886 phy->false_cca_cck = pd_cck - mdrdy_cck;
1887 mt7615_mac_cca_stats_reset(phy);
1888
1889 if (mib->rts_cnt + mib->rts_retries_cnt)
1890 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1891 mib->rts_cnt + mib->rts_retries_cnt);
1892
1893 /* cck */
1894 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1895 /* ofdm */
1896 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1897
1898 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1899 mt7615_mac_set_default_sensitivity(phy);
1900 }
1901
1902 static u8
mt7615_phy_get_nf(struct mt7615_dev * dev,int idx)1903 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1904 {
1905 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1906 u32 reg, val, sum = 0, n = 0;
1907 int i;
1908
1909 if (is_mt7663(&dev->mt76))
1910 reg = MT7663_WF_PHY_RXTD(20);
1911 else
1912 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1913
1914 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1915 val = mt76_rr(dev, reg);
1916 sum += val * nf_power[i];
1917 n += val;
1918 }
1919
1920 if (!n)
1921 return 0;
1922
1923 return sum / n;
1924 }
1925
1926 static void
mt7615_phy_update_channel(struct mt76_phy * mphy,int idx)1927 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1928 {
1929 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1930 struct mt7615_phy *phy = mphy->priv;
1931 struct mt76_channel_state *state;
1932 u64 busy_time, tx_time, rx_time, obss_time;
1933 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1934 int nf;
1935
1936 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1937 MT_MIB_SDR9_BUSY_MASK);
1938 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1939 MT_MIB_SDR36_TXTIME_MASK);
1940 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1941 MT_MIB_SDR37_RXTIME_MASK);
1942 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1943
1944 nf = mt7615_phy_get_nf(dev, idx);
1945 if (!phy->noise)
1946 phy->noise = nf << 4;
1947 else if (nf)
1948 phy->noise += nf - (phy->noise >> 4);
1949
1950 state = mphy->chan_state;
1951 state->cc_busy += busy_time;
1952 state->cc_tx += tx_time;
1953 state->cc_rx += rx_time + obss_time;
1954 state->cc_bss_rx += rx_time;
1955 state->noise = -(phy->noise >> 4);
1956 }
1957
mt7615_update_survey(struct mt7615_dev * dev)1958 static void mt7615_update_survey(struct mt7615_dev *dev)
1959 {
1960 struct mt76_dev *mdev = &dev->mt76;
1961 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1];
1962 ktime_t cur_time;
1963
1964 /* MT7615 can only update both phys simultaneously
1965 * since some reisters are shared across bands.
1966 */
1967
1968 mt7615_phy_update_channel(&mdev->phy, 0);
1969 if (mphy_ext)
1970 mt7615_phy_update_channel(mphy_ext, 1);
1971
1972 cur_time = ktime_get_boottime();
1973
1974 mt76_update_survey_active_time(&mdev->phy, cur_time);
1975 if (mphy_ext)
1976 mt76_update_survey_active_time(mphy_ext, cur_time);
1977
1978 /* reset obss airtime */
1979 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1980 }
1981
mt7615_update_channel(struct mt76_phy * mphy)1982 void mt7615_update_channel(struct mt76_phy *mphy)
1983 {
1984 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1985
1986 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm))
1987 return;
1988
1989 mt7615_update_survey(dev);
1990 mt76_connac_power_save_sched(&dev->mphy, &dev->pm);
1991 }
1992 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1993
1994 static void
mt7615_mac_update_mib_stats(struct mt7615_phy * phy)1995 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1996 {
1997 struct mt7615_dev *dev = phy->dev;
1998 struct mib_stats *mib = &phy->mib;
1999 bool ext_phy = phy != &dev->phy;
2000 int i, aggr = 0;
2001 u32 val, val2;
2002
2003 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
2004 MT_MIB_SDR3_FCS_ERR_MASK);
2005
2006 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
2007 MT_MIB_AMPDU_MPDU_COUNT);
2008 if (val) {
2009 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
2010 MT_MIB_AMPDU_ACK_COUNT);
2011 mib->aggr_per = 1000 * (val - val2) / val;
2012 }
2013
2014 for (i = 0; i < 4; i++) {
2015 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
2016 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
2017 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK,
2018 val);
2019
2020 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
2021 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
2022 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK,
2023 val);
2024
2025 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
2026 phy->mt76->aggr_stats[aggr++] += val & 0xffff;
2027 phy->mt76->aggr_stats[aggr++] += val >> 16;
2028 }
2029 }
2030
mt7615_pm_wake_work(struct work_struct * work)2031 void mt7615_pm_wake_work(struct work_struct *work)
2032 {
2033 struct mt7615_dev *dev;
2034 struct mt76_phy *mphy;
2035
2036 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2037 pm.wake_work);
2038 mphy = dev->phy.mt76;
2039
2040 if (!mt7615_mcu_set_drv_ctrl(dev)) {
2041 struct mt76_dev *mdev = &dev->mt76;
2042 int i;
2043
2044 if (mt76_is_sdio(mdev)) {
2045 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
2046 mt76_worker_schedule(&mdev->sdio.txrx_worker);
2047 } else {
2048 local_bh_disable();
2049 mt76_for_each_q_rx(mdev, i)
2050 napi_schedule(&mdev->napi[i]);
2051 local_bh_enable();
2052 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
2053 mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM],
2054 false);
2055 }
2056
2057 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) {
2058 unsigned long timeout;
2059
2060 timeout = mt7615_get_macwork_timeout(dev);
2061 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
2062 timeout);
2063 }
2064 }
2065
2066 ieee80211_wake_queues(mphy->hw);
2067 wake_up(&dev->pm.wait);
2068 }
2069
mt7615_pm_power_save_work(struct work_struct * work)2070 void mt7615_pm_power_save_work(struct work_struct *work)
2071 {
2072 struct mt7615_dev *dev;
2073 unsigned long delta;
2074
2075 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2076 pm.ps_work.work);
2077
2078 delta = dev->pm.idle_timeout;
2079 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) ||
2080 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state))
2081 goto out;
2082
2083 if (mutex_is_locked(&dev->mt76.mutex))
2084 /* if mt76 mutex is held we should not put the device
2085 * to sleep since we are currently accessing device
2086 * register map. We need to wait for the next power_save
2087 * trigger.
2088 */
2089 goto out;
2090
2091 if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
2092 delta = dev->pm.last_activity + delta - jiffies;
2093 goto out;
2094 }
2095
2096 if (!mt7615_mcu_set_fw_ctrl(dev))
2097 return;
2098 out:
2099 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
2100 }
2101
mt7615_mac_work(struct work_struct * work)2102 void mt7615_mac_work(struct work_struct *work)
2103 {
2104 struct mt7615_phy *phy;
2105 struct mt76_phy *mphy;
2106 unsigned long timeout;
2107
2108 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
2109 mac_work.work);
2110 phy = mphy->priv;
2111
2112 mt7615_mutex_acquire(phy->dev);
2113
2114 mt7615_update_survey(phy->dev);
2115 if (++mphy->mac_work_count == 5) {
2116 mphy->mac_work_count = 0;
2117
2118 mt7615_mac_update_mib_stats(phy);
2119 mt7615_mac_scs_check(phy);
2120 }
2121
2122 mt7615_mutex_release(phy->dev);
2123
2124 mt76_tx_status_check(mphy->dev, false);
2125
2126 timeout = mt7615_get_macwork_timeout(phy->dev);
2127 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout);
2128 }
2129
mt7615_tx_token_put(struct mt7615_dev * dev)2130 void mt7615_tx_token_put(struct mt7615_dev *dev)
2131 {
2132 struct mt76_txwi_cache *txwi;
2133 int id;
2134
2135 spin_lock_bh(&dev->mt76.token_lock);
2136 idr_for_each_entry(&dev->mt76.token, txwi, id)
2137 mt7615_txwi_free(dev, txwi);
2138 spin_unlock_bh(&dev->mt76.token_lock);
2139 idr_destroy(&dev->mt76.token);
2140 }
2141 EXPORT_SYMBOL_GPL(mt7615_tx_token_put);
2142
mt7615_dfs_stop_radar_detector(struct mt7615_phy * phy)2143 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
2144 {
2145 struct mt7615_dev *dev = phy->dev;
2146
2147 if (phy->rdd_state & BIT(0))
2148 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0,
2149 MT_RX_SEL0, 0);
2150 if (phy->rdd_state & BIT(1))
2151 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1,
2152 MT_RX_SEL0, 0);
2153 }
2154
mt7615_dfs_start_rdd(struct mt7615_dev * dev,int chain)2155 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
2156 {
2157 int err;
2158
2159 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain,
2160 MT_RX_SEL0, 0);
2161 if (err < 0)
2162 return err;
2163
2164 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain,
2165 MT_RX_SEL0, 1);
2166 }
2167
mt7615_dfs_start_radar_detector(struct mt7615_phy * phy)2168 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
2169 {
2170 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2171 struct mt7615_dev *dev = phy->dev;
2172 bool ext_phy = phy != &dev->phy;
2173 int err;
2174
2175 /* start CAC */
2176 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy,
2177 MT_RX_SEL0, 0);
2178 if (err < 0)
2179 return err;
2180
2181 err = mt7615_dfs_start_rdd(dev, ext_phy);
2182 if (err < 0)
2183 return err;
2184
2185 phy->rdd_state |= BIT(ext_phy);
2186
2187 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2188 chandef->width == NL80211_CHAN_WIDTH_80P80) {
2189 err = mt7615_dfs_start_rdd(dev, 1);
2190 if (err < 0)
2191 return err;
2192
2193 phy->rdd_state |= BIT(1);
2194 }
2195
2196 return 0;
2197 }
2198
2199 static int
mt7615_dfs_init_radar_specs(struct mt7615_phy * phy)2200 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
2201 {
2202 const struct mt7615_dfs_radar_spec *radar_specs;
2203 struct mt7615_dev *dev = phy->dev;
2204 int err, i, lpn = 500;
2205
2206 switch (dev->mt76.region) {
2207 case NL80211_DFS_FCC:
2208 radar_specs = &fcc_radar_specs;
2209 lpn = 8;
2210 break;
2211 case NL80211_DFS_ETSI:
2212 radar_specs = &etsi_radar_specs;
2213 break;
2214 case NL80211_DFS_JP:
2215 radar_specs = &jp_radar_specs;
2216 break;
2217 default:
2218 return -EINVAL;
2219 }
2220
2221 /* avoid FCC radar detection in non-FCC region */
2222 err = mt7615_mcu_set_fcc5_lpn(dev, lpn);
2223 if (err < 0)
2224 return err;
2225
2226 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2227 err = mt7615_mcu_set_radar_th(dev, i,
2228 &radar_specs->radar_pattern[i]);
2229 if (err < 0)
2230 return err;
2231 }
2232
2233 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2234 }
2235
mt7615_dfs_init_radar_detector(struct mt7615_phy * phy)2236 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2237 {
2238 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2239 struct mt7615_dev *dev = phy->dev;
2240 bool ext_phy = phy != &dev->phy;
2241 enum mt76_dfs_state dfs_state, prev_state;
2242 int err;
2243
2244 if (is_mt7663(&dev->mt76))
2245 return 0;
2246
2247 prev_state = phy->mt76->dfs_state;
2248 dfs_state = mt76_phy_dfs_state(phy->mt76);
2249 if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) &&
2250 dfs_state < MT_DFS_STATE_CAC)
2251 dfs_state = MT_DFS_STATE_ACTIVE;
2252
2253 if (prev_state == dfs_state)
2254 return 0;
2255
2256 if (dfs_state == MT_DFS_STATE_DISABLED)
2257 goto stop;
2258
2259 if (prev_state <= MT_DFS_STATE_DISABLED) {
2260 err = mt7615_dfs_init_radar_specs(phy);
2261 if (err < 0)
2262 return err;
2263
2264 err = mt7615_dfs_start_radar_detector(phy);
2265 if (err < 0)
2266 return err;
2267
2268 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
2269 }
2270
2271 if (dfs_state == MT_DFS_STATE_CAC)
2272 return 0;
2273
2274 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END,
2275 ext_phy, MT_RX_SEL0, 0);
2276 if (err < 0) {
2277 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
2278 return err;
2279 }
2280
2281 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
2282 return 0;
2283
2284 stop:
2285 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy,
2286 MT_RX_SEL0, 0);
2287 if (err < 0)
2288 return err;
2289
2290 mt7615_dfs_stop_radar_detector(phy);
2291 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
2292
2293 return 0;
2294 }
2295
mt7615_mac_set_beacon_filter(struct mt7615_phy * phy,struct ieee80211_vif * vif,bool enable)2296 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy,
2297 struct ieee80211_vif *vif,
2298 bool enable)
2299 {
2300 struct mt7615_dev *dev = phy->dev;
2301 bool ext_phy = phy != &dev->phy;
2302 int err;
2303
2304 if (!mt7615_firmware_offload(dev))
2305 return -EOPNOTSUPP;
2306
2307 switch (vif->type) {
2308 case NL80211_IFTYPE_MONITOR:
2309 return 0;
2310 case NL80211_IFTYPE_MESH_POINT:
2311 case NL80211_IFTYPE_ADHOC:
2312 case NL80211_IFTYPE_AP:
2313 if (enable)
2314 phy->n_beacon_vif++;
2315 else
2316 phy->n_beacon_vif--;
2317 fallthrough;
2318 default:
2319 break;
2320 }
2321
2322 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif);
2323 if (err)
2324 return err;
2325
2326 if (phy->n_beacon_vif) {
2327 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER;
2328 mt76_clear(dev, MT_WF_RFCR(ext_phy),
2329 MT_WF_RFCR_DROP_OTHER_BEACON);
2330 } else {
2331 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
2332 mt76_set(dev, MT_WF_RFCR(ext_phy),
2333 MT_WF_RFCR_DROP_OTHER_BEACON);
2334 }
2335
2336 return 0;
2337 }
2338
mt7615_coredump_work(struct work_struct * work)2339 void mt7615_coredump_work(struct work_struct *work)
2340 {
2341 struct mt7615_dev *dev;
2342 char *dump, *data;
2343
2344 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2345 coredump.work.work);
2346
2347 if (time_is_after_jiffies(dev->coredump.last_activity +
2348 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) {
2349 queue_delayed_work(dev->mt76.wq, &dev->coredump.work,
2350 MT76_CONNAC_COREDUMP_TIMEOUT);
2351 return;
2352 }
2353
2354 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ);
2355 data = dump;
2356
2357 while (true) {
2358 struct sk_buff *skb;
2359
2360 spin_lock_bh(&dev->mt76.lock);
2361 skb = __skb_dequeue(&dev->coredump.msg_list);
2362 spin_unlock_bh(&dev->mt76.lock);
2363
2364 if (!skb)
2365 break;
2366
2367 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
2368 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) {
2369 dev_kfree_skb(skb);
2370 continue;
2371 }
2372
2373 memcpy(data, skb->data, skb->len);
2374 data += skb->len;
2375
2376 dev_kfree_skb(skb);
2377 }
2378
2379 if (dump)
2380 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ,
2381 GFP_KERNEL);
2382 }
2383