xref: /linux/drivers/gpu/drm/amd/display/dc/inc/core_types.h (revision de848da12f752170c2ebe114804a985314fd5a6a)
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef _CORE_TYPES_H_
27 #define _CORE_TYPES_H_
28 
29 #include "dc.h"
30 #include "dce_calcs.h"
31 #include "dcn_calcs.h"
32 #include "ddc_service_types.h"
33 #include "dc_bios_types.h"
34 #include "mem_input.h"
35 #include "hubp.h"
36 #include "mpc.h"
37 #include "dwb.h"
38 #include "mcif_wb.h"
39 #include "panel_cntl.h"
40 #include "dmub/inc/dmub_cmd.h"
41 #include "pg_cntl.h"
42 #include "spl/dc_spl.h"
43 
44 #define MAX_CLOCK_SOURCES 7
45 #define MAX_SVP_PHANTOM_STREAMS 2
46 #define MAX_SVP_PHANTOM_PLANES 2
47 
48 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
49 		uint32_t controller_id);
50 
51 #include "grph_object_id.h"
52 #include "link_encoder.h"
53 #include "stream_encoder.h"
54 #include "clock_source.h"
55 #include "audio.h"
56 #include "dm_pp_smu.h"
57 #include "dm_cp_psp.h"
58 #include "link_hwss.h"
59 
60 /********** DAL Core*********************/
61 #include "transform.h"
62 #include "dpp.h"
63 
64 #include "dml2/dml21/inc/dml_top_dchub_registers.h"
65 #include "dml2/dml21/inc/dml_top_types.h"
66 
67 struct resource_pool;
68 struct dc_state;
69 struct resource_context;
70 struct clk_bw_params;
71 
72 struct resource_funcs {
73 	enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index);
74 	void (*destroy)(struct resource_pool **pool);
75 	void (*link_init)(struct dc_link *link);
76 	struct panel_cntl*(*panel_cntl_create)(
77 		const struct panel_cntl_init_data *panel_cntl_init_data);
78 	struct link_encoder *(*link_enc_create)(
79 			struct dc_context *ctx,
80 			const struct encoder_init_data *init);
81 	/* Create a minimal link encoder object with no dc_link object
82 	 * associated with it. */
83 	struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);
84 
85 	bool (*validate_bandwidth)(
86 					struct dc *dc,
87 					struct dc_state *context,
88 					bool fast_validate);
89 	void (*calculate_wm_and_dlg)(
90 				struct dc *dc, struct dc_state *context,
91 				display_e2e_pipe_params_st *pipes,
92 				int pipe_cnt,
93 				int vlevel);
94 	void (*update_soc_for_wm_a)(
95 				struct dc *dc, struct dc_state *context);
96 
97 	unsigned int (*calculate_mall_ways_from_bytes)(
98 				const struct dc *dc,
99 				unsigned int total_size_in_mall_bytes);
100 	void (*prepare_mcache_programming)(
101 					struct dc *dc,
102 					struct dc_state *context);
103 	/**
104 	 * @populate_dml_pipes - Populate pipe data struct
105 	 *
106 	 * Returns:
107 	 * Total of pipes available in the specific ASIC.
108 	 */
109 	int (*populate_dml_pipes)(
110 		struct dc *dc,
111 		struct dc_state *context,
112 		display_e2e_pipe_params_st *pipes,
113 		bool fast_validate);
114 
115 	/*
116 	 * Algorithm for assigning available link encoders to links.
117 	 *
118 	 * Update link_enc_assignments table and link_enc_avail list accordingly in
119 	 * struct resource_context.
120 	 */
121 	void (*link_encs_assign)(
122 			struct dc *dc,
123 			struct dc_state *state,
124 			struct dc_stream_state *streams[],
125 			uint8_t stream_count);
126 	/*
127 	 * Unassign a link encoder from a stream.
128 	 *
129 	 * Update link_enc_assignments table and link_enc_avail list accordingly in
130 	 * struct resource_context.
131 	 */
132 	void (*link_enc_unassign)(
133 			struct dc_state *state,
134 			struct dc_stream_state *stream);
135 
136 	enum dc_status (*validate_global)(
137 		struct dc *dc,
138 		struct dc_state *context);
139 
140 	struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)(
141 			const struct dc_state *cur_ctx,
142 			struct dc_state *new_ctx,
143 			const struct resource_pool *pool,
144 			const struct pipe_ctx *opp_head_pipe);
145 
146 	struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(
147 			const struct dc_state *cur_ctx,
148 			struct dc_state *new_ctx,
149 			const struct resource_pool *pool,
150 			const struct pipe_ctx *otg_master);
151 
152 	void (*release_pipe)(struct dc_state *context,
153 			struct pipe_ctx *pipe,
154 			const struct resource_pool *pool);
155 
156 	enum dc_status (*validate_plane)(
157 			const struct dc_plane_state *plane_state,
158 			struct dc_caps *caps);
159 
160 	enum dc_status (*add_stream_to_ctx)(
161 			struct dc *dc,
162 			struct dc_state *new_ctx,
163 			struct dc_stream_state *dc_stream);
164 
165 	enum dc_status (*remove_stream_from_ctx)(
166 				struct dc *dc,
167 				struct dc_state *new_ctx,
168 				struct dc_stream_state *stream);
169 
170 	enum dc_status (*patch_unknown_plane_state)(
171 			struct dc_plane_state *plane_state);
172 
173 	struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
174 			struct resource_context *res_ctx,
175 			const struct resource_pool *pool,
176 			struct dc_stream_state *stream);
177 
178 	void (*populate_dml_writeback_from_context)(
179 			struct dc *dc,
180 			struct resource_context *res_ctx,
181 			display_e2e_pipe_params_st *pipes);
182 
183 	void (*set_mcif_arb_params)(
184 			struct dc *dc,
185 			struct dc_state *context,
186 			display_e2e_pipe_params_st *pipes,
187 			int pipe_cnt);
188 
189 	void (*update_bw_bounding_box)(
190 			struct dc *dc,
191 			struct clk_bw_params *bw_params);
192 	bool (*acquire_post_bldn_3dlut)(
193 			struct resource_context *res_ctx,
194 			const struct resource_pool *pool,
195 			int mpcc_id,
196 			struct dc_3dlut **lut,
197 			struct dc_transfer_func **shaper);
198 
199 	bool (*release_post_bldn_3dlut)(
200 			struct resource_context *res_ctx,
201 			const struct resource_pool *pool,
202 			struct dc_3dlut **lut,
203 			struct dc_transfer_func **shaper);
204 
205 	enum dc_status (*add_dsc_to_stream_resource)(
206 			struct dc *dc, struct dc_state *state,
207 			struct dc_stream_state *stream);
208 
209 	void (*add_phantom_pipes)(
210             struct dc *dc,
211             struct dc_state *context,
212             display_e2e_pipe_params_st *pipes,
213 			unsigned int pipe_cnt,
214             unsigned int index);
215 
216 	void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);
217 	void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);
218 };
219 
220 struct audio_support{
221 	bool dp_audio;
222 	bool hdmi_audio_on_dongle;
223 	bool hdmi_audio_native;
224 };
225 
226 #define NO_UNDERLAY_PIPE -1
227 
228 struct resource_pool {
229 	struct mem_input *mis[MAX_PIPES];
230 	struct hubp *hubps[MAX_PIPES];
231 	struct input_pixel_processor *ipps[MAX_PIPES];
232 	struct transform *transforms[MAX_PIPES];
233 	struct dpp *dpps[MAX_PIPES];
234 	struct output_pixel_processor *opps[MAX_PIPES];
235 	struct timing_generator *timing_generators[MAX_PIPES];
236 	struct stream_encoder *stream_enc[MAX_PIPES * 2];
237 	struct hubbub *hubbub;
238 	struct mpc *mpc;
239 	struct pp_smu_funcs *pp_smu;
240 	struct dce_aux *engines[MAX_PIPES];
241 	struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
242 	struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
243 	bool i2c_hw_buffer_in_use;
244 
245 	struct dwbc *dwbc[MAX_DWB_PIPES];
246 	struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
247 	struct {
248 		unsigned int gsl_0:1;
249 		unsigned int gsl_1:1;
250 		unsigned int gsl_2:1;
251 	} gsl_groups;
252 
253 	struct display_stream_compressor *dscs[MAX_PIPES];
254 
255 	unsigned int pipe_count;
256 	unsigned int underlay_pipe_index;
257 	unsigned int stream_enc_count;
258 
259 	/* An array for accessing the link encoder objects that have been created.
260 	 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA
261 	 */
262 	struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS];
263 	/* Number of DIG link encoder objects created - i.e. number of valid
264 	 * entries in link_encoders array.
265 	 */
266 	unsigned int dig_link_enc_count;
267 	/* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/
268 	unsigned int usb4_dpia_count;
269 
270 	unsigned int hpo_dp_stream_enc_count;
271 	struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
272 	unsigned int hpo_dp_link_enc_count;
273 	struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
274 	struct dc_3dlut *mpc_lut[MAX_PIPES];
275 	struct dc_transfer_func *mpc_shaper[MAX_PIPES];
276 
277 	struct {
278 		unsigned int xtalin_clock_inKhz;
279 		unsigned int dccg_ref_clock_inKhz;
280 		unsigned int dchub_ref_clock_inKhz;
281 	} ref_clocks;
282 	unsigned int timing_generator_count;
283 	unsigned int mpcc_count;
284 
285 	unsigned int writeback_pipe_count;
286 	/*
287 	 * reserved clock source for DP
288 	 */
289 	struct clock_source *dp_clock_source;
290 
291 	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
292 	unsigned int clk_src_count;
293 
294 	struct audio *audios[MAX_AUDIOS];
295 	unsigned int audio_count;
296 	struct audio_support audio_support;
297 
298 	struct dccg *dccg;
299 	struct pg_cntl *pg_cntl;
300 	struct irq_service *irqs;
301 
302 	struct abm *abm;
303 	struct dmcu *dmcu;
304 	struct dmub_psr *psr;
305 	struct dmub_replay *replay;
306 
307 	struct abm *multiple_abms[MAX_PIPES];
308 
309 	const struct resource_funcs *funcs;
310 	const struct resource_caps *res_cap;
311 
312 	struct ddc_service *oem_device;
313 };
314 
315 struct dcn_fe_bandwidth {
316 	int dppclk_khz;
317 
318 };
319 
320 /* Parameters needed to call set_disp_pattern_generator */
321 struct test_pattern_params {
322 	enum controller_dp_test_pattern test_pattern;
323 	enum controller_dp_color_space color_space;
324 	enum dc_color_depth color_depth;
325 	int width;
326 	int height;
327 	int offset;
328 };
329 
330 struct stream_resource {
331 	struct output_pixel_processor *opp;
332 	struct display_stream_compressor *dsc;
333 	struct timing_generator *tg;
334 	struct stream_encoder *stream_enc;
335 	struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
336 	struct audio *audio;
337 
338 	struct pixel_clk_params pix_clk_params;
339 	struct encoder_info_frame encoder_info_frame;
340 
341 	struct abm *abm;
342 	/* There are only (num_pipes+1)/2 groups. 0 means unassigned,
343 	 * otherwise it's using group number 'gsl_group-1'
344 	 */
345 	uint8_t gsl_group;
346 
347 	struct test_pattern_params test_pattern_params;
348 };
349 
350 struct plane_resource {
351 	/* scl_data is scratch space required to program a plane */
352 	struct scaler_data scl_data;
353 	/* Below pointers to hw objects are required to enable the plane */
354 	/* spl_in and spl_out are the input and output structures for SPL
355 	 * which are required when using Scaler Programming Library
356 	 * these are scratch spaces needed when programming a plane
357 	 */
358 	struct spl_in spl_in;
359 	struct spl_out spl_out;
360 	/* Below pointers to hw objects are required to enable the plane */
361 	struct hubp *hubp;
362 	struct mem_input *mi;
363 	struct input_pixel_processor *ipp;
364 	struct transform *xfm;
365 	struct dpp *dpp;
366 	uint8_t mpcc_inst;
367 
368 	struct dcn_fe_bandwidth bw;
369 };
370 
371 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
372 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
373 
374 /* all mappable hardware resources used to enable a link */
375 struct link_resource {
376 	struct hpo_dp_link_encoder *hpo_dp_link_enc;
377 };
378 
379 struct link_config {
380 	struct dc_link_settings dp_link_settings;
381 };
382 union pipe_update_flags {
383 	struct {
384 		uint32_t enable : 1;
385 		uint32_t disable : 1;
386 		uint32_t odm : 1;
387 		uint32_t global_sync : 1;
388 		uint32_t opp_changed : 1;
389 		uint32_t tg_changed : 1;
390 		uint32_t mpcc : 1;
391 		uint32_t dppclk : 1;
392 		uint32_t hubp_interdependent : 1;
393 		uint32_t hubp_rq_dlg_ttu : 1;
394 		uint32_t gamut_remap : 1;
395 		uint32_t scaler : 1;
396 		uint32_t viewport : 1;
397 		uint32_t plane_changed : 1;
398 		uint32_t det_size : 1;
399 		uint32_t unbounded_req : 1;
400 		uint32_t test_pattern_changed : 1;
401 	} bits;
402 	uint32_t raw;
403 };
404 
405 struct pixel_rate_divider {
406 	uint32_t div_factor1;
407 	uint32_t div_factor2;
408 };
409 
410 enum p_state_switch_method {
411 	P_STATE_UNKNOWN						= 0,
412 	P_STATE_V_BLANK						= 1,
413 	P_STATE_FPO,
414 	P_STATE_V_ACTIVE,
415 	P_STATE_SUB_VP,
416 	P_STATE_DRR_SUB_VP,
417 	P_STATE_V_BLANK_SUB_VP
418 };
419 
420 struct pipe_ctx {
421 	struct dc_plane_state *plane_state;
422 	struct dc_stream_state *stream;
423 
424 	struct plane_resource plane_res;
425 
426 	/**
427 	 * @stream_res: Reference to DCN resource components such OPP and DSC.
428 	 */
429 	struct stream_resource stream_res;
430 	struct link_resource link_res;
431 
432 	struct clock_source *clock_source;
433 
434 	struct pll_settings pll_settings;
435 
436 	/**
437 	 * @link_config:
438 	 *
439 	 * link config records software decision for what link config should be
440 	 * enabled given current link capability and stream during hw resource
441 	 * mapping. This is to decouple the dependency on link capability during
442 	 * dc commit or update.
443 	 */
444 	struct link_config link_config;
445 
446 	uint8_t pipe_idx;
447 	uint8_t pipe_idx_syncd;
448 
449 	struct pipe_ctx *top_pipe;
450 	struct pipe_ctx *bottom_pipe;
451 	struct pipe_ctx *next_odm_pipe;
452 	struct pipe_ctx *prev_odm_pipe;
453 
454 	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
455 	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
456 	struct _vcs_dpi_display_rq_regs_st rq_regs;
457 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
458 	struct _vcs_dpi_display_rq_params_st dml_rq_param;
459 	struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param;
460 	struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
461 	int det_buffer_size_kb;
462 	bool unbounded_req;
463 	unsigned int surface_size_in_mall_bytes;
464 	struct dml2_dchub_per_pipe_register_set hubp_regs;
465 	struct dml2_hubp_pipe_mcache_regs mcache_regs;
466 
467 	struct dwbc *dwbc;
468 	struct mcif_wb *mcif_wb;
469 	union pipe_update_flags update_flags;
470 	enum p_state_switch_method p_state_type;
471 	struct tg_color visual_confirm_color;
472 	bool has_vactive_margin;
473 	/* subvp_index: only valid if the pipe is a SUBVP_MAIN*/
474 	uint8_t subvp_index;
475 	struct pixel_rate_divider pixel_rate_divider;
476 };
477 
478 /* Data used for dynamic link encoder assignment.
479  * Tracks current and future assignments; available link encoders;
480  * and mode of operation (whether to use current or future assignments).
481  */
482 struct link_enc_cfg_context {
483 	enum link_enc_cfg_mode mode;
484 	struct link_enc_assignment link_enc_assignments[MAX_PIPES];
485 	enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
486 	struct link_enc_assignment transient_assignments[MAX_PIPES];
487 };
488 
489 struct resource_context {
490 	struct pipe_ctx pipe_ctx[MAX_PIPES];
491 	bool is_stream_enc_acquired[MAX_PIPES * 2];
492 	bool is_audio_acquired[MAX_PIPES];
493 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
494 	uint8_t dp_clock_source_ref_count;
495 	bool is_dsc_acquired[MAX_PIPES];
496 	struct link_enc_cfg_context link_enc_cfg_ctx;
497 	bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
498 	unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
499 	int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
500 	bool is_mpc_3dlut_acquired[MAX_PIPES];
501 	/* solely used for build scalar data in dml2 */
502 	struct pipe_ctx temp_pipe;
503 };
504 
505 struct dce_bw_output {
506 	bool cpuc_state_change_enable;
507 	bool cpup_state_change_enable;
508 	bool stutter_mode_enable;
509 	bool nbp_state_change_enable;
510 	bool all_displays_in_sync;
511 	struct dce_watermarks urgent_wm_ns[MAX_PIPES];
512 	struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
513 	struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
514 	struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
515 	int sclk_khz;
516 	int sclk_deep_sleep_khz;
517 	int yclk_khz;
518 	int dispclk_khz;
519 	int blackout_recovery_time_us;
520 };
521 
522 struct dcn_bw_writeback {
523 	struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
524 };
525 
526 struct dcn_bw_output {
527 	struct dc_clocks clk;
528 	union dcn_watermark_set watermarks;
529 	struct dcn_bw_writeback bw_writeback;
530 	int compbuf_size_kb;
531 	unsigned int mall_ss_size_bytes;
532 	unsigned int mall_ss_psr_active_size_bytes;
533 	unsigned int mall_subvp_size_bytes;
534 	unsigned int legacy_svp_drr_stream_index;
535 	bool legacy_svp_drr_stream_index_valid;
536 	struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];
537 	struct dmub_cmd_fams2_global_config fams2_global_config;
538 	struct dmub_fams2_stream_static_state fams2_stream_params[DML2_MAX_PLANES];
539 	struct dml2_display_arb_regs arb_regs;
540 };
541 
542 union bw_output {
543 	struct dcn_bw_output dcn;
544 	struct dce_bw_output dce;
545 };
546 
547 struct bw_context {
548 	union bw_output bw;
549 	struct display_mode_lib dml;
550 	struct dml2_context *dml2;
551 	struct dml2_context *dml2_dc_power_source;
552 };
553 
554 struct dc_dmub_cmd {
555 	union dmub_rb_cmd dmub_cmd;
556 	enum dm_dmub_wait_type wait_type;
557 };
558 
559 /**
560  * struct dc_state - The full description of a state requested by users
561  */
562 struct dc_state {
563 	/**
564 	 * @streams: Stream state properties
565 	 */
566 	struct dc_stream_state *streams[MAX_PIPES];
567 
568 	/**
569 	 * @stream_status: Planes status on a given stream
570 	 */
571 	struct dc_stream_status stream_status[MAX_PIPES];
572 	/**
573 	 * @phantom_streams: Stream state properties for phantoms
574 	 */
575 	struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES];
576 	/**
577 	 * @phantom_planes: Planes state properties for phantoms
578 	 */
579 	struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES];
580 
581 	/**
582 	 * @stream_count: Total of streams in use
583 	 */
584 	uint8_t stream_count;
585 	uint8_t stream_mask;
586 
587 	/**
588 	 * @stream_count: Total phantom streams in use
589 	 */
590 	uint8_t phantom_stream_count;
591 	/**
592 	 * @stream_count: Total phantom planes in use
593 	 */
594 	uint8_t phantom_plane_count;
595 	/**
596 	 * @res_ctx: Persistent state of resources
597 	 */
598 	struct resource_context res_ctx;
599 
600 	/**
601 	 * @pp_display_cfg: PowerPlay clocks and settings
602 	 * Note: this is a big struct, do *not* put on stack!
603 	 */
604 	struct dm_pp_display_configuration pp_display_cfg;
605 
606 	/**
607 	 * @dcn_bw_vars: non-stack memory to support bandwidth calculations
608 	 * Note: this is a big struct, do *not* put on stack!
609 	 */
610 	struct dcn_bw_internal_vars dcn_bw_vars;
611 
612 	struct clk_mgr *clk_mgr;
613 
614 	/**
615 	 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
616 	 *
617 	 * Each context must have its own instance of VBA, and in order to
618 	 * initialize and obtain IP and SOC, the base DML instance from DC is
619 	 * initially copied into every context.
620 	 */
621 	struct bw_context bw_ctx;
622 
623 	struct block_sequence block_sequence[50];
624 	unsigned int block_sequence_steps;
625 	struct dc_dmub_cmd dc_dmub_cmd[10];
626 	unsigned int dmub_cmd_count;
627 
628 	/**
629 	 * @refcount: refcount reference
630 	 *
631 	 * Notice that dc_state is used around the code to capture the current
632 	 * context, so we need to pass it everywhere. That's why we want to use
633 	 * kref in this struct.
634 	 */
635 	struct kref refcount;
636 
637 	struct {
638 		unsigned int stutter_period_us;
639 	} perf_params;
640 
641 	enum dc_power_source_type power_source;
642 };
643 
644 struct replay_context {
645 	/* ddc line */
646 	enum channel_id aux_inst;
647 	/* Transmitter id */
648 	enum transmitter digbe_inst;
649 	/* Engine Id is used for Dig Be source select */
650 	enum engine_id digfe_inst;
651 	/* Controller Id used for Dig Fe source select */
652 	enum controller_id controllerId;
653 	unsigned int line_time_in_ns;
654 };
655 
656 enum dc_replay_enable {
657 	DC_REPLAY_DISABLE			= 0,
658 	DC_REPLAY_ENABLE			= 1,
659 };
660 
661 struct dc_bounding_box_max_clk {
662 	int max_dcfclk_mhz;
663 	int max_dispclk_mhz;
664 	int max_dppclk_mhz;
665 	int max_phyclk_mhz;
666 };
667 
668 #endif /* _CORE_TYPES_H_ */
669