1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_COMMON_H
9 #define OTX2_COMMON_H
10
11 #include <linux/ethtool.h>
12 #include <linux/pci.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/timecounter.h>
17 #include <linux/soc/marvell/octeontx2/asm.h>
18 #include <net/macsec.h>
19 #include <net/pkt_cls.h>
20 #include <net/devlink.h>
21 #include <linux/time64.h>
22 #include <linux/dim.h>
23 #include <uapi/linux/if_macsec.h>
24 #include <net/page_pool/helpers.h>
25
26 #include <mbox.h>
27 #include <npc.h>
28 #include "otx2_reg.h"
29 #include "otx2_txrx.h"
30 #include "otx2_devlink.h"
31 #include <rvu.h>
32 #include <rvu_trace.h>
33 #include "qos.h"
34 #include "rep.h"
35 #include "cn10k_ipsec.h"
36 #include "cn20k.h"
37
38 /* IPv4 flag more fragment bit */
39 #define IPV4_FLAG_MORE 0x20
40
41 /* PCI device IDs */
42 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
43 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
44 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
45
46 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
47 #define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF 0xB900
48 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00
49
50 #define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7
51
52 /* PCI BAR nos */
53 #define PCI_CFG_REG_BAR_NUM 2
54 #define PCI_MBOX_BAR_NUM 4
55
56 #define NAME_SIZE 32
57
58 #ifdef CONFIG_DCB
59 /* Max priority supported for PFC */
60 #define NIX_PF_PFC_PRIO_MAX 8
61 #endif
62
63 /* Number of segments per SG structure */
64 #define MAX_SEGS_PER_SG 3
65
66 irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq);
67 irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq);
68 irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq);
69 irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq);
70 irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq);
71
72 enum arua_mapped_qtypes {
73 AURA_NIX_RQ,
74 AURA_NIX_SQ,
75 };
76
77 /* NIX LF interrupts range*/
78 #define NIX_LF_QINT_VEC_START 0x00
79 #define NIX_LF_CINT_VEC_START 0x40
80 #define NIX_LF_GINT_VEC 0x80
81 #define NIX_LF_ERR_VEC 0x81
82 #define NIX_LF_POISON_VEC 0x82
83
84 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
85 #define SEND_CQ_SKID 2000
86
87 #define OTX2_GET_RX_STATS(reg) \
88 otx2_read64(pfvf, NIX_LF_RX_STATX(reg))
89 #define OTX2_GET_TX_STATS(reg) \
90 otx2_read64(pfvf, NIX_LF_TX_STATX(reg))
91
92 struct otx2_lmt_info {
93 u64 lmt_addr;
94 u16 lmt_id;
95 };
96
97 struct otx2_rss_info {
98 u8 enable;
99 u32 flowkey_cfg;
100 u16 rss_size;
101 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
102 u8 key[RSS_HASH_KEY_SIZE];
103 u32 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
104 };
105
106 /* NIX (or NPC) RX errors */
107 enum otx2_errlvl {
108 NPC_ERRLVL_RE,
109 NPC_ERRLVL_LID_LA,
110 NPC_ERRLVL_LID_LB,
111 NPC_ERRLVL_LID_LC,
112 NPC_ERRLVL_LID_LD,
113 NPC_ERRLVL_LID_LE,
114 NPC_ERRLVL_LID_LF,
115 NPC_ERRLVL_LID_LG,
116 NPC_ERRLVL_LID_LH,
117 NPC_ERRLVL_NIX = 0x0F,
118 };
119
120 enum otx2_errcodes_re {
121 /* NPC_ERRLVL_RE errcodes */
122 ERRCODE_FCS = 0x7,
123 ERRCODE_FCS_RCV = 0x8,
124 ERRCODE_UNDERSIZE = 0x10,
125 ERRCODE_OVERSIZE = 0x11,
126 ERRCODE_OL2_LEN_MISMATCH = 0x12,
127 /* NPC_ERRLVL_NIX errcodes */
128 ERRCODE_OL3_LEN = 0x10,
129 ERRCODE_OL4_LEN = 0x11,
130 ERRCODE_OL4_CSUM = 0x12,
131 ERRCODE_IL3_LEN = 0x20,
132 ERRCODE_IL4_LEN = 0x21,
133 ERRCODE_IL4_CSUM = 0x22,
134 };
135
136 enum otx2_xdp_action {
137 OTX2_XDP_TX = BIT(0),
138 OTX2_XDP_REDIRECT = BIT(1),
139 OTX2_AF_XDP_FRAME = BIT(2),
140 };
141
142 struct otx2_dev_stats {
143 u64 rx_bytes;
144 u64 rx_frames;
145 u64 rx_ucast_frames;
146 u64 rx_bcast_frames;
147 u64 rx_mcast_frames;
148 u64 rx_drops;
149
150 u64 tx_bytes;
151 u64 tx_frames;
152 u64 tx_ucast_frames;
153 u64 tx_bcast_frames;
154 u64 tx_mcast_frames;
155 u64 tx_drops;
156 atomic_long_t tx_discards;
157 };
158
159 /* Driver counted stats */
160 struct otx2_drv_stats {
161 atomic_t rx_fcs_errs;
162 atomic_t rx_oversize_errs;
163 atomic_t rx_undersize_errs;
164 atomic_t rx_csum_errs;
165 atomic_t rx_len_errs;
166 atomic_t rx_other_errs;
167 };
168
169 struct mbox {
170 struct otx2_mbox mbox;
171 struct work_struct mbox_wrk;
172 struct otx2_mbox mbox_up;
173 struct work_struct mbox_up_wrk;
174 struct otx2_nic *pfvf;
175 void *bbuf_base; /* Bounce buffer for mbox memory */
176 struct mutex lock; /* serialize mailbox access */
177 int num_msgs; /* mbox number of messages */
178 int up_num_msgs; /* mbox_up number of messages */
179 };
180
181 /* Egress rate limiting definitions */
182 #define MAX_BURST_EXPONENT 0x0FULL
183 #define MAX_BURST_MANTISSA 0xFFULL
184 #define MAX_BURST_SIZE 130816ULL
185 #define MAX_RATE_DIVIDER_EXPONENT 12ULL
186 #define MAX_RATE_EXPONENT 0x0FULL
187 #define MAX_RATE_MANTISSA 0xFFULL
188
189 /* Bitfields in NIX_TLX_PIR register */
190 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1)
191 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9)
192 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13)
193 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29)
194 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37)
195
196 struct otx2_hw {
197 struct pci_dev *pdev;
198 struct otx2_rss_info rss_info;
199 u16 rx_queues;
200 u16 tx_queues;
201 u16 xdp_queues;
202 u16 tc_tx_queues;
203 u16 non_qos_queues; /* tx queues plus xdp queues */
204 u16 max_queues;
205 u16 pool_cnt;
206 u16 rqpool_cnt;
207 u16 sqpool_cnt;
208
209 #define OTX2_DEFAULT_RBUF_LEN 2048
210 u16 rbuf_len;
211 u32 xqe_size;
212
213 /* NPA */
214 u32 stack_pg_ptrs; /* No of ptrs per stack page */
215 u32 stack_pg_bytes; /* Size of stack page */
216 u16 sqb_size;
217
218 /* NIX */
219 u8 txschq_link_cfg_lvl;
220 u8 txschq_cnt[NIX_TXSCH_LVL_CNT];
221 u8 txschq_aggr_lvl_rr_prio;
222 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
223 u16 matchall_ipolicer;
224 u32 dwrr_mtu;
225 u32 max_mtu;
226 u8 smq_link_type;
227
228 /* HW settings, coalescing etc */
229 u16 rx_chan_base;
230 u16 tx_chan_base;
231 u8 rx_chan_cnt;
232 u8 tx_chan_cnt;
233 u16 cq_qcount_wait;
234 u16 cq_ecount_wait;
235 u16 rq_skid;
236 u8 cq_time_wait;
237
238 /* Segmentation */
239 u8 lso_tsov4_idx;
240 u8 lso_tsov6_idx;
241 u8 lso_udpv4_idx;
242 u8 lso_udpv6_idx;
243
244 /* RSS */
245 u8 flowkey_alg_idx;
246
247 /* MSI-X */
248 u8 cint_cnt; /* CQ interrupt count */
249 u16 npa_msixoff; /* Offset of NPA vectors */
250 u16 nix_msixoff; /* Offset of NIX vectors */
251 char *irq_name;
252 cpumask_var_t *affinity_mask;
253 struct pf_irq_data *pfvf_irq_devid[4];
254
255 /* Stats */
256 struct otx2_dev_stats dev_stats;
257 struct otx2_drv_stats drv_stats;
258 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
259 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
260 u64 cgx_fec_corr_blks;
261 u64 cgx_fec_uncorr_blks;
262 u8 cgx_links; /* No. of CGX links present in HW */
263 u8 lbk_links; /* No. of LBK links present in HW */
264 u8 tx_link; /* Transmit channel link number */
265 #define HW_TSO 0
266 #define CN10K_MBOX 1
267 #define CN10K_LMTST 2
268 #define CN10K_RPM 3
269 #define CN10K_PTP_ONESTEP 4
270 #define CN10K_HW_MACSEC 5
271 #define QOS_CIR_PIR_SUPPORT 6
272 unsigned long cap_flag;
273
274 #define LMT_LINE_SIZE 128
275 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
276 u64 *lmt_base;
277 struct otx2_lmt_info __percpu *lmt_info;
278 };
279
280 enum vfperm {
281 OTX2_RESET_VF_PERM,
282 OTX2_TRUSTED_VF,
283 };
284
285 struct otx2_vf_config {
286 struct otx2_nic *pf;
287 struct delayed_work link_event_work;
288 bool intf_down; /* interface was either configured or not */
289 u8 mac[ETH_ALEN];
290 u16 vlan;
291 int tx_vtag_idx;
292 bool trusted;
293 };
294
295 struct flr_work {
296 struct work_struct work;
297 struct otx2_nic *pf;
298 };
299
300 struct refill_work {
301 struct delayed_work pool_refill_work;
302 struct otx2_nic *pf;
303 struct napi_struct *napi;
304 };
305
306 /* PTPv2 originTimestamp structure */
307 struct ptpv2_tstamp {
308 __be16 seconds_msb; /* 16 bits + */
309 __be32 seconds_lsb; /* 32 bits = 48 bits*/
310 __be32 nanoseconds;
311 } __packed;
312
313 struct otx2_ptp {
314 struct ptp_clock_info ptp_info;
315 struct ptp_clock *ptp_clock;
316 struct otx2_nic *nic;
317
318 struct cyclecounter cycle_counter;
319 struct timecounter time_counter;
320
321 struct delayed_work extts_work;
322 u64 last_extts;
323 u64 thresh;
324
325 struct ptp_pin_desc extts_config;
326 u64 (*convert_rx_ptp_tstmp)(u64 timestamp);
327 u64 (*convert_tx_ptp_tstmp)(u64 timestamp);
328 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp);
329 struct delayed_work synctstamp_work;
330 u64 tstamp;
331 u32 base_ns;
332 };
333
334 #define OTX2_HW_TIMESTAMP_LEN 8
335
336 struct otx2_mac_table {
337 u8 addr[ETH_ALEN];
338 u16 mcam_entry;
339 bool inuse;
340 };
341
342 struct otx2_flow_config {
343 u16 *flow_ent;
344 u16 *def_ent;
345 u16 nr_flows;
346 #define OTX2_DEFAULT_FLOWCOUNT 16
347 #define OTX2_DEFAULT_UNICAST_FLOWS 4
348 #define OTX2_MAX_VLAN_FLOWS 1
349 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
350 u16 unicast_offset;
351 u16 rx_vlan_offset;
352 u16 vf_vlan_offset;
353 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
354 #define OTX2_VF_VLAN_RX_INDEX 0
355 #define OTX2_VF_VLAN_TX_INDEX 1
356 u32 *bmap_to_dmacindex;
357 unsigned long *dmacflt_bmap;
358 struct list_head flow_list;
359 u32 dmacflt_max_flows;
360 u16 max_flows;
361 refcount_t mark_flows;
362 struct list_head flow_list_tc;
363 u8 ucast_flt_cnt;
364 bool ntuple;
365 u16 ntuple_cnt;
366 };
367
368 struct dev_hw_ops {
369 int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset,
370 u16 sqb_aura);
371 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
372 int size, int qidx);
373 int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
374 void (*aura_freeptr)(void *dev, int aura, u64 buf);
375 irqreturn_t (*pfaf_mbox_intr_handler)(int irq, void *pf_irq);
376 irqreturn_t (*vfaf_mbox_intr_handler)(int irq, void *pf_irq);
377 irqreturn_t (*pfvf_mbox_intr_handler)(int irq, void *pf_irq);
378 };
379
380 #define CN10K_MCS_SA_PER_SC 4
381
382 /* Stats which need to be accumulated in software because
383 * of shared counters in hardware.
384 */
385 struct cn10k_txsc_stats {
386 u64 InPktsUntagged;
387 u64 InPktsNoTag;
388 u64 InPktsBadTag;
389 u64 InPktsUnknownSCI;
390 u64 InPktsNoSCI;
391 u64 InPktsOverrun;
392 };
393
394 struct cn10k_rxsc_stats {
395 u64 InOctetsValidated;
396 u64 InOctetsDecrypted;
397 u64 InPktsUnchecked;
398 u64 InPktsDelayed;
399 u64 InPktsOK;
400 u64 InPktsInvalid;
401 u64 InPktsLate;
402 u64 InPktsNotValid;
403 u64 InPktsNotUsingSA;
404 u64 InPktsUnusedSA;
405 };
406
407 struct cn10k_mcs_txsc {
408 struct macsec_secy *sw_secy;
409 struct cn10k_txsc_stats stats;
410 struct list_head entry;
411 enum macsec_validation_type last_validate_frames;
412 bool last_replay_protect;
413 u16 hw_secy_id_tx;
414 u16 hw_secy_id_rx;
415 u16 hw_flow_id;
416 u16 hw_sc_id;
417 u16 hw_sa_id[CN10K_MCS_SA_PER_SC];
418 u8 sa_bmap;
419 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN];
420 u8 encoding_sa;
421 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN];
422 ssci_t ssci[CN10K_MCS_SA_PER_SC];
423 bool vlan_dev; /* macsec running on VLAN ? */
424 };
425
426 struct cn10k_mcs_rxsc {
427 struct macsec_secy *sw_secy;
428 struct macsec_rx_sc *sw_rxsc;
429 struct cn10k_rxsc_stats stats;
430 struct list_head entry;
431 u16 hw_flow_id;
432 u16 hw_sc_id;
433 u16 hw_sa_id[CN10K_MCS_SA_PER_SC];
434 u8 sa_bmap;
435 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN];
436 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN];
437 ssci_t ssci[CN10K_MCS_SA_PER_SC];
438 };
439
440 struct cn10k_mcs_cfg {
441 struct list_head txsc_list;
442 struct list_head rxsc_list;
443 };
444
445 struct pf_irq_data {
446 u64 intr_status;
447 void (*pf_queue_work_hdlr)(struct mbox *mb, struct workqueue_struct *mw,
448 int first, int mdevs, u64 intr);
449 struct otx2_nic *pf;
450 int vec_num;
451 int start;
452 int mdevs;
453 };
454
455 struct otx2_nic {
456 void __iomem *reg_base;
457 struct net_device *netdev;
458 struct dev_hw_ops *hw_ops;
459 void *iommu_domain;
460 u16 tx_max_pktlen;
461 u16 rbsize; /* Receive buffer size */
462
463 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
464 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
465 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
466 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
467 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
468 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
469 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
470 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
471 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
472 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
473 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
474 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
475 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
476 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
477 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
478 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15)
479 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16)
480 #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17)
481 #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18)
482 #define OTX2_FLAG_PORT_UP BIT_ULL(19)
483 #define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED BIT_ULL(20)
484 u64 flags;
485 u64 *cq_op_addr;
486
487 struct bpf_prog *xdp_prog;
488 struct otx2_qset qset;
489 struct otx2_hw hw;
490 struct pci_dev *pdev;
491 struct device *dev;
492
493 /* Mbox */
494 struct mbox mbox;
495 struct mbox *mbox_pfvf;
496 struct workqueue_struct *mbox_wq;
497 struct workqueue_struct *mbox_pfvf_wq;
498 struct qmem *pfvf_mbox_addr;
499
500 u8 total_vfs;
501 u16 pcifunc; /* RVU PF_FUNC */
502 u16 bpid[NIX_MAX_BPID_CHAN];
503 struct otx2_vf_config *vf_configs;
504 struct cgx_link_user_info linfo;
505
506 /* NPC MCAM */
507 struct otx2_flow_config *flow_cfg;
508 struct otx2_mac_table *mac_table;
509
510 u64 reset_count;
511 struct work_struct reset_task;
512 struct workqueue_struct *flr_wq;
513 struct flr_work *flr_wrk;
514 struct refill_work *refill_wrk;
515 struct workqueue_struct *otx2_wq;
516 struct work_struct rx_mode_work;
517
518 /* Ethtool stuff */
519 u32 msg_enable;
520
521 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
522 int nix_blkaddr;
523 /* LMTST Lines info */
524 struct qmem *dync_lmt;
525 u16 tot_lmt_lines;
526 u16 npa_lmt_lines;
527 u32 nix_lmt_size;
528
529 struct otx2_ptp *ptp;
530 struct hwtstamp_config tstamp;
531
532 unsigned long rq_bmap;
533
534 /* Devlink */
535 struct otx2_devlink *dl;
536 /* PFC */
537 u8 pfc_en;
538 #ifdef CONFIG_DCB
539 u8 *queue_to_pfc_map;
540 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
541 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX];
542 #endif
543 /* qos */
544 struct otx2_qos qos;
545
546 /* napi event count. It is needed for adaptive irq coalescing. */
547 u32 napi_events;
548
549 #if IS_ENABLED(CONFIG_MACSEC)
550 struct cn10k_mcs_cfg *macsec_cfg;
551 #endif
552
553 #if IS_ENABLED(CONFIG_RVU_ESWITCH)
554 struct rep_dev **reps;
555 int rep_cnt;
556 u16 rep_pf_map[RVU_MAX_REP];
557 u16 esw_mode;
558 #endif
559
560 /* Inline ipsec */
561 struct cn10k_ipsec ipsec;
562 /* af_xdp zero-copy */
563 unsigned long *af_xdp_zc_qidx;
564 };
565
is_otx2_lbkvf(struct pci_dev * pdev)566 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
567 {
568 return (pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF) ||
569 (pdev->device == PCI_DEVID_RVU_REP);
570 }
571
is_96xx_A0(struct pci_dev * pdev)572 static inline bool is_96xx_A0(struct pci_dev *pdev)
573 {
574 return (pdev->revision == 0x00) &&
575 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
576 }
577
is_96xx_B0(struct pci_dev * pdev)578 static inline bool is_96xx_B0(struct pci_dev *pdev)
579 {
580 return (pdev->revision == 0x01) &&
581 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
582 }
583
is_otx2_sdp_rep(struct pci_dev * pdev)584 static inline bool is_otx2_sdp_rep(struct pci_dev *pdev)
585 {
586 return pdev->device == PCI_DEVID_OCTEONTX2_SDP_REP;
587 }
588
589 /* REVID for PCIe devices.
590 * Bits 0..1: minor pass, bit 3..2: major pass
591 * bits 7..4: midr id
592 */
593 #define PCI_REVISION_ID_96XX 0x00
594 #define PCI_REVISION_ID_95XX 0x10
595 #define PCI_REVISION_ID_95XXN 0x20
596 #define PCI_REVISION_ID_98XX 0x30
597 #define PCI_REVISION_ID_95XXMM 0x40
598 #define PCI_REVISION_ID_95XXO 0xE0
599
is_dev_otx2(struct pci_dev * pdev)600 static inline bool is_dev_otx2(struct pci_dev *pdev)
601 {
602 u8 midr = pdev->revision & 0xF0;
603
604 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
605 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
606 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
607 }
608
is_dev_cn10kb(struct pci_dev * pdev)609 static inline bool is_dev_cn10kb(struct pci_dev *pdev)
610 {
611 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF;
612 }
613
is_dev_cn10ka_b0(struct pci_dev * pdev)614 static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)
615 {
616 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF &&
617 (pdev->revision & 0xFF) == 0x54)
618 return true;
619
620 return false;
621 }
622
otx2_setup_dev_hw_settings(struct otx2_nic * pfvf)623 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
624 {
625 struct otx2_hw *hw = &pfvf->hw;
626
627 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
628 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
629 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
630
631 __set_bit(HW_TSO, &hw->cap_flag);
632
633 if (is_96xx_A0(pfvf->pdev)) {
634 __clear_bit(HW_TSO, &hw->cap_flag);
635
636 /* Time based irq coalescing is not supported */
637 pfvf->hw.cq_qcount_wait = 0x0;
638
639 /* Due to HW issue previous silicons required minimum
640 * 600 unused CQE to avoid CQ overflow.
641 */
642 pfvf->hw.rq_skid = 600;
643 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
644 }
645 if (is_96xx_B0(pfvf->pdev))
646 __clear_bit(HW_TSO, &hw->cap_flag);
647
648 if (!is_dev_otx2(pfvf->pdev)) {
649 __set_bit(CN10K_MBOX, &hw->cap_flag);
650 __set_bit(CN10K_LMTST, &hw->cap_flag);
651 __set_bit(CN10K_RPM, &hw->cap_flag);
652 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag);
653 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag);
654 }
655 }
656
657 /* Register read/write APIs */
otx2_get_regaddr(struct otx2_nic * nic,u64 offset)658 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
659 {
660 u64 blkaddr;
661
662 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
663 case BLKTYPE_NIX:
664 blkaddr = nic->nix_blkaddr;
665 break;
666 case BLKTYPE_NPA:
667 blkaddr = BLKADDR_NPA;
668 break;
669 case BLKTYPE_CPT:
670 blkaddr = BLKADDR_CPT0;
671 break;
672 default:
673 blkaddr = BLKADDR_RVUM;
674 break;
675 }
676
677 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
678 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
679
680 return nic->reg_base + offset;
681 }
682
otx2_write64(struct otx2_nic * nic,u64 offset,u64 val)683 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
684 {
685 void __iomem *addr = otx2_get_regaddr(nic, offset);
686
687 writeq(val, addr);
688 }
689
otx2_read64(struct otx2_nic * nic,u64 offset)690 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
691 {
692 void __iomem *addr = otx2_get_regaddr(nic, offset);
693
694 return readq(addr);
695 }
696
697 /* Mbox bounce buffer APIs */
otx2_mbox_bbuf_init(struct mbox * mbox,struct pci_dev * pdev)698 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
699 {
700 struct otx2_mbox *otx2_mbox;
701 struct otx2_mbox_dev *mdev;
702
703 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
704 if (!mbox->bbuf_base)
705 return -ENOMEM;
706
707 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
708 * prepare all mbox messages in bounce buffer instead of directly
709 * in hw mbox memory.
710 */
711 otx2_mbox = &mbox->mbox;
712 mdev = &otx2_mbox->dev[0];
713 mdev->mbase = mbox->bbuf_base;
714
715 otx2_mbox = &mbox->mbox_up;
716 mdev = &otx2_mbox->dev[0];
717 mdev->mbase = mbox->bbuf_base;
718 return 0;
719 }
720
otx2_sync_mbox_bbuf(struct otx2_mbox * mbox,int devid)721 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
722 {
723 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
724 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
725 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
726 struct mbox_hdr *hdr;
727 u64 msg_size;
728
729 if (mdev->mbase == hw_mbase)
730 return;
731
732 hdr = hw_mbase + mbox->rx_start;
733 msg_size = hdr->msg_size;
734
735 if (msg_size > mbox->rx_size - msgs_offset)
736 msg_size = mbox->rx_size - msgs_offset;
737
738 /* Copy mbox messages from mbox memory to bounce buffer */
739 memcpy(mdev->mbase + mbox->rx_start,
740 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
741 }
742
743 /* With the absence of API for 128-bit IO memory access for arm64,
744 * implement required operations at place.
745 */
746 #if defined(CONFIG_ARM64)
otx2_write128(u64 lo,u64 hi,void __iomem * addr)747 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
748 {
749 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
750 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
751 }
752
otx2_atomic64_add(u64 incr,void __iomem * addr)753 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr)
754 {
755 u64 __iomem *ptr = addr;
756 u64 result;
757
758 __asm__ volatile(".cpu generic+lse\n"
759 "ldadd %x[i], %x[r], [%[b]]"
760 : [r]"=r"(result), "+m"(*ptr)
761 : [i]"r"(incr), [b]"r"(ptr)
762 : "memory");
763 return result;
764 }
765
766 #else
767 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
768
otx2_atomic64_add(u64 incr,void __iomem * addr)769 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr)
770 {
771 return 0;
772 }
773 #endif
774
__cn10k_aura_freeptr(struct otx2_nic * pfvf,u64 aura,u64 * ptrs,u64 num_ptrs)775 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
776 u64 *ptrs, u64 num_ptrs)
777 {
778 struct otx2_lmt_info *lmt_info;
779 u64 size = 0, count_eot = 0;
780 u64 tar_addr, val = 0;
781
782 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id());
783 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
784 /* LMTID is same as AURA Id */
785 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63);
786 /* Set if [127:64] of last 128bit word has a valid pointer */
787 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
788 /* Set AURA ID to free pointer */
789 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
790 /* Target address for LMTST flush tells HW how many 128bit
791 * words are valid from NPA_LF_AURA_BATCH_FREE0.
792 *
793 * tar_addr[6:4] is LMTST size-1 in units of 128b.
794 */
795 if (num_ptrs > 2) {
796 size = (sizeof(u64) * num_ptrs) / 16;
797 if (!count_eot)
798 size++;
799 tar_addr |= ((size - 1) & 0x7) << 4;
800 }
801 dma_wmb();
802 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs);
803 /* Perform LMTST flush */
804 cn10k_lmt_flush(val, tar_addr);
805 }
806
cn10k_aura_freeptr(void * dev,int aura,u64 buf)807 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
808 {
809 struct otx2_nic *pfvf = dev;
810 u64 ptrs[2];
811
812 ptrs[1] = buf;
813 get_cpu();
814 /* Free only one buffer at time during init and teardown */
815 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2);
816 put_cpu();
817 }
818
819 /* Alloc pointer from pool/aura */
otx2_aura_allocptr(struct otx2_nic * pfvf,int aura)820 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
821 {
822 void __iomem *ptr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0));
823 u64 incr = (u64)aura | BIT_ULL(63);
824
825 return otx2_atomic64_add(incr, ptr);
826 }
827
828 /* Free pointer to a pool/aura */
otx2_aura_freeptr(void * dev,int aura,u64 buf)829 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
830 {
831 struct otx2_nic *pfvf = dev;
832 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
833
834 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
835 }
836
otx2_get_pool_idx(struct otx2_nic * pfvf,int type,int idx)837 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
838 {
839 if (type == AURA_NIX_SQ)
840 return pfvf->hw.rqpool_cnt + idx;
841
842 /* AURA_NIX_RQ */
843 return idx;
844 }
845
846 /* Mbox APIs */
otx2_sync_mbox_msg(struct mbox * mbox)847 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
848 {
849 int err;
850
851 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
852 return 0;
853 otx2_mbox_msg_send(&mbox->mbox, 0);
854 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
855 if (err)
856 return err;
857
858 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
859 }
860
otx2_sync_mbox_up_msg(struct mbox * mbox,int devid)861 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
862 {
863 int err;
864
865 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
866 return 0;
867 otx2_mbox_msg_send_up(&mbox->mbox_up, devid);
868 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
869 if (err)
870 return err;
871
872 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
873 }
874
875 /* Use this API to send mbox msgs in atomic context
876 * where sleeping is not allowed
877 */
otx2_sync_mbox_msg_busy_poll(struct mbox * mbox)878 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
879 {
880 int err;
881
882 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
883 return 0;
884 otx2_mbox_msg_send(&mbox->mbox, 0);
885 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
886 if (err)
887 return err;
888
889 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
890 }
891
892 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
893 static struct _req_type __maybe_unused \
894 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
895 { \
896 struct _req_type *req; \
897 u16 pcifunc = mbox->pfvf->pcifunc; \
898 \
899 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
900 &mbox->mbox, 0, sizeof(struct _req_type), \
901 sizeof(struct _rsp_type)); \
902 if (!req) \
903 return NULL; \
904 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
905 req->hdr.id = _id; \
906 req->hdr.pcifunc = pcifunc; \
907 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req), pcifunc); \
908 return req; \
909 }
910
911 MBOX_MESSAGES
912 #undef M
913
914 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
915 int \
916 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
917 struct _req_type *req, \
918 struct _rsp_type *rsp); \
919
920 MBOX_UP_CGX_MESSAGES
921 MBOX_UP_MCS_MESSAGES
922 #undef M
923
924 /* Time to wait before watchdog kicks off */
925 #define OTX2_TX_TIMEOUT (100 * HZ)
926
is_otx2_vf(u16 pcifunc)927 static inline bool is_otx2_vf(u16 pcifunc)
928 {
929 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
930 }
931
otx2_dma_map_page(struct otx2_nic * pfvf,struct page * page,size_t offset,size_t size,enum dma_data_direction dir)932 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
933 struct page *page,
934 size_t offset, size_t size,
935 enum dma_data_direction dir)
936 {
937 dma_addr_t iova;
938
939 iova = dma_map_page_attrs(pfvf->dev, page,
940 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
941 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
942 return (dma_addr_t)NULL;
943 return iova;
944 }
945
otx2_dma_unmap_page(struct otx2_nic * pfvf,dma_addr_t addr,size_t size,enum dma_data_direction dir)946 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
947 dma_addr_t addr, size_t size,
948 enum dma_data_direction dir)
949 {
950 dma_unmap_page_attrs(pfvf->dev, addr, size,
951 dir, DMA_ATTR_SKIP_CPU_SYNC);
952 }
953
otx2_get_smq_idx(struct otx2_nic * pfvf,u16 qidx)954 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx)
955 {
956 u16 smq;
957 int idx;
958
959 #ifdef CONFIG_DCB
960 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx])
961 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx];
962 #endif
963 /* check if qidx falls under QOS queues */
964 if (qidx >= pfvf->hw.non_qos_queues) {
965 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues];
966 } else {
967 idx = qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ];
968 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx];
969 }
970
971 return smq;
972 }
973
otx2_get_total_tx_queues(struct otx2_nic * pfvf)974 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf)
975 {
976 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues;
977 }
978
otx2_convert_rate(u64 rate)979 static inline u64 otx2_convert_rate(u64 rate)
980 {
981 u64 converted_rate;
982
983 /* Convert bytes per second to Mbps */
984 converted_rate = rate * 8;
985 converted_rate = max_t(u64, converted_rate / 1000000, 1);
986
987 return converted_rate;
988 }
989
otx2_tc_flower_rule_cnt(struct otx2_nic * pfvf)990 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf)
991 {
992 /* return here if MCAM entries not allocated */
993 if (!pfvf->flow_cfg)
994 return 0;
995
996 return pfvf->flow_cfg->nr_flows;
997 }
998
999 /* MSI-X APIs */
1000 void otx2_free_cints(struct otx2_nic *pfvf, int n);
1001 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
1002 int otx2_set_mac_address(struct net_device *netdev, void *p);
1003 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
1004 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
1005 void otx2_get_mac_from_af(struct net_device *netdev);
1006 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
1007 int otx2_config_pause_frm(struct otx2_nic *pfvf);
1008 void otx2_setup_segmentation(struct otx2_nic *pfvf);
1009 int otx2_reset_mac_stats(struct otx2_nic *pfvf);
1010
1011 /* RVU block related APIs */
1012 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
1013 int otx2_detach_resources(struct mbox *mbox);
1014 int otx2_config_npa(struct otx2_nic *pfvf);
1015 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
1016 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
1017 void otx2_aura_pool_free(struct otx2_nic *pfvf);
1018 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
1019 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
1020 int otx2_config_nix(struct otx2_nic *pfvf);
1021 int otx2_config_nix_queues(struct otx2_nic *pfvf);
1022 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en);
1023 int otx2_txsch_alloc(struct otx2_nic *pfvf);
1024 void otx2_txschq_stop(struct otx2_nic *pfvf);
1025 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq);
1026 void otx2_free_pending_sqe(struct otx2_nic *pfvf);
1027 void otx2_sqb_flush(struct otx2_nic *pfvf);
1028 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
1029 dma_addr_t *dma, int qidx, int idx);
1030 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
1031 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
1032 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
1033 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable);
1034 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx);
1035 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
1036 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura);
1037 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura);
1038 int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura);
1039 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
1040 dma_addr_t *dma);
1041 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1042 int stack_pages, int numptrs, int buf_size, int type);
1043 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1044 int pool_id, int numptrs);
1045 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf);
1046 void otx2_free_queue_mem(struct otx2_qset *qset);
1047 int otx2_alloc_queue_mem(struct otx2_nic *pf);
1048 int otx2_init_hw_resources(struct otx2_nic *pfvf);
1049 void otx2_free_hw_resources(struct otx2_nic *pf);
1050 int otx2_wq_init(struct otx2_nic *pf);
1051 int otx2_check_pf_usable(struct otx2_nic *pf);
1052 int otx2_pfaf_mbox_init(struct otx2_nic *pf);
1053 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af);
1054 int otx2_realloc_msix_vectors(struct otx2_nic *pf);
1055 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf);
1056 void otx2_disable_mbox_intr(struct otx2_nic *pf);
1057 void otx2_disable_napi(struct otx2_nic *pf);
1058 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq);
1059 int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura);
1060 int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx);
1061 int otx2_set_hw_capabilities(struct otx2_nic *pfvf);
1062
1063 /* RSS configuration APIs*/
1064 int otx2_rss_init(struct otx2_nic *pfvf);
1065 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
1066 void otx2_set_rss_key(struct otx2_nic *pfvf);
1067 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id, const u32 *ind_tbl);
1068
1069 /* Mbox handlers */
1070 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1071 struct msix_offset_rsp *rsp);
1072 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1073 struct npa_lf_alloc_rsp *rsp);
1074 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1075 struct nix_lf_alloc_rsp *rsp);
1076 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
1077 struct nix_txsch_alloc_rsp *rsp);
1078 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1079 struct cgx_stats_rsp *rsp);
1080 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1081 struct cgx_fec_stats_rsp *rsp);
1082 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
1083 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1084 struct nix_bp_cfg_rsp *rsp);
1085
1086 /* Device stats APIs */
1087 void otx2_get_dev_stats(struct otx2_nic *pfvf);
1088 void otx2_get_stats64(struct net_device *netdev,
1089 struct rtnl_link_stats64 *stats);
1090 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
1091 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
1092 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
1093 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
1094 void otx2_set_ethtool_ops(struct net_device *netdev);
1095 void otx2vf_set_ethtool_ops(struct net_device *netdev);
1096
1097 int otx2_open(struct net_device *netdev);
1098 int otx2_stop(struct net_device *netdev);
1099 int otx2_set_real_num_queues(struct net_device *netdev,
1100 int tx_queues, int rx_queues);
1101 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd);
1102 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr);
1103
1104 /* MCAM filter related APIs */
1105 int otx2_mcam_flow_init(struct otx2_nic *pf);
1106 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf);
1107 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count);
1108 void otx2_mcam_flow_del(struct otx2_nic *pf);
1109 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
1110 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
1111 int otx2_get_flow(struct otx2_nic *pfvf,
1112 struct ethtool_rxnfc *nfc, u32 location);
1113 int otx2_get_all_flows(struct otx2_nic *pfvf,
1114 struct ethtool_rxnfc *nfc, u32 *rule_locs);
1115 int otx2_add_flow(struct otx2_nic *pfvf,
1116 struct ethtool_rxnfc *nfc);
1117 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
1118 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg);
1119 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
1120 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
1121 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
1122 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
1123 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
1124 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, struct xdp_frame *xdpf,
1125 u64 iova, int len, u16 qidx, u16 flags);
1126 void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, struct xdp_frame *xdpf,
1127 u64 dma_addr, int len, int *offset, u16 flags);
1128 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
1129 int otx2_handle_ntuple_tc_features(struct net_device *netdev,
1130 netdev_features_t features);
1131 int otx2_smq_flush(struct otx2_nic *pfvf, int smq);
1132 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool,
1133 u64 iova, int size);
1134 int otx2_mcam_entry_init(struct otx2_nic *pfvf);
1135
1136 /* tc support */
1137 int otx2_init_tc(struct otx2_nic *nic);
1138 void otx2_shutdown_tc(struct otx2_nic *nic);
1139 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
1140 void *type_data);
1141 void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic);
1142
1143 /* CGX/RPM DMAC filters support */
1144 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);
1145 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);
1146 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);
1147 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos);
1148 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf);
1149 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf);
1150
1151 #ifdef CONFIG_DCB
1152 /* DCB support*/
1153 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable);
1154 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf);
1155 int otx2_dcbnl_set_ops(struct net_device *dev);
1156 /* PFC support */
1157 int otx2_pfc_txschq_config(struct otx2_nic *pfvf);
1158 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf);
1159 int otx2_pfc_txschq_update(struct otx2_nic *pfvf);
1160 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf);
1161 #endif
1162
1163 #if IS_ENABLED(CONFIG_MACSEC)
1164 /* MACSEC offload support */
1165 int cn10k_mcs_init(struct otx2_nic *pfvf);
1166 void cn10k_mcs_free(struct otx2_nic *pfvf);
1167 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event);
1168 #else
cn10k_mcs_init(struct otx2_nic * pfvf)1169 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; }
cn10k_mcs_free(struct otx2_nic * pfvf)1170 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {}
cn10k_handle_mcs_event(struct otx2_nic * pfvf,struct mcs_intr_info * event)1171 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf,
1172 struct mcs_intr_info *event)
1173 {}
1174 #endif /* CONFIG_MACSEC */
1175
1176 /* qos support */
otx2_qos_init(struct otx2_nic * pfvf,int qos_txqs)1177 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs)
1178 {
1179 struct otx2_hw *hw = &pfvf->hw;
1180
1181 hw->tc_tx_queues = qos_txqs;
1182 INIT_LIST_HEAD(&pfvf->qos.qos_tree);
1183 mutex_init(&pfvf->qos.qos_lock);
1184 }
1185
otx2_shutdown_qos(struct otx2_nic * pfvf)1186 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf)
1187 {
1188 mutex_destroy(&pfvf->qos.qos_lock);
1189 }
1190
1191 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb,
1192 struct net_device *sb_dev);
1193 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid);
1194 void otx2_qos_config_txschq(struct otx2_nic *pfvf);
1195 void otx2_clean_qos_queues(struct otx2_nic *pfvf);
1196 int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info);
1197 int otx2_setup_tc_cls_flower(struct otx2_nic *nic,
1198 struct flow_cls_offload *cls_flower);
1199
mcam_entry_cmp(const void * a,const void * b)1200 static inline int mcam_entry_cmp(const void *a, const void *b)
1201 {
1202 return *(u16 *)a - *(u16 *)b;
1203 }
1204
1205 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
1206 struct sk_buff *skb, int seg, int *len);
1207 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg);
1208 int otx2_read_free_sqe(struct otx2_nic *pfvf, u16 qidx);
1209 void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
1210 int first, int mdevs, u64 intr);
1211 #endif /* OTX2_COMMON_H */
1212