1 /*
2 * Performance events - AMD IBS
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
5 *
6 * For licencing details see kernel-base/COPYING
7 */
8
9 #include <linux/perf_event.h>
10 #include <linux/init.h>
11 #include <linux/export.h>
12 #include <linux/pci.h>
13 #include <linux/ptrace.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/sched/clock.h>
16
17 #include <asm/apic.h>
18
19 #include "../perf_event.h"
20
21 static u32 ibs_caps;
22
23 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
24
25 #include <linux/kprobes.h>
26 #include <linux/hardirq.h>
27
28 #include <asm/nmi.h>
29 #include <asm/amd-ibs.h>
30
31 #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
32 #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
33
34 /* attr.config2 */
35 #define IBS_SW_FILTER_MASK 1
36
37 /*
38 * IBS states:
39 *
40 * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
41 * and any further add()s must fail.
42 *
43 * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
44 * complicated by the fact that the IBS hardware can send late NMIs (ie. after
45 * we've cleared the EN bit).
46 *
47 * In order to consume these late NMIs we have the STOPPED state, any NMI that
48 * happens after we've cleared the EN state will clear this bit and report the
49 * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
50 * someone else can consume our BIT and our NMI will go unhandled).
51 *
52 * And since we cannot set/clear this separate bit together with the EN bit,
53 * there are races; if we cleared STARTED early, an NMI could land in
54 * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
55 * could happen if the period is small enough), and consume our STOPPED bit
56 * and trigger streams of unhandled NMIs.
57 *
58 * If, however, we clear STARTED late, an NMI can hit between clearing the
59 * EN bit and clearing STARTED, still see STARTED set and process the event.
60 * If this event will have the VALID bit clear, we bail properly, but this
61 * is not a given. With VALID set we can end up calling pmu::stop() again
62 * (the throttle logic) and trigger the WARNs in there.
63 *
64 * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
65 * nesting, and clear STARTED late, so that we have a well defined state over
66 * the clearing of the EN bit.
67 *
68 * XXX: we could probably be using !atomic bitops for all this.
69 */
70
71 enum ibs_states {
72 IBS_ENABLED = 0,
73 IBS_STARTED = 1,
74 IBS_STOPPING = 2,
75 IBS_STOPPED = 3,
76
77 IBS_MAX_STATES,
78 };
79
80 struct cpu_perf_ibs {
81 struct perf_event *event;
82 unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
83 };
84
85 struct perf_ibs {
86 struct pmu pmu;
87 unsigned int msr;
88 u64 config_mask;
89 u64 cnt_mask;
90 u64 enable_mask;
91 u64 valid_mask;
92 u64 max_period;
93 unsigned long offset_mask[1];
94 int offset_max;
95 unsigned int fetch_count_reset_broken : 1;
96 unsigned int fetch_ignore_if_zero_rip : 1;
97 struct cpu_perf_ibs __percpu *pcpu;
98
99 u64 (*get_count)(u64 config);
100 };
101
102 static int
perf_event_set_period(struct hw_perf_event * hwc,u64 min,u64 max,u64 * hw_period)103 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
104 {
105 s64 left = local64_read(&hwc->period_left);
106 s64 period = hwc->sample_period;
107 int overflow = 0;
108
109 /*
110 * If we are way outside a reasonable range then just skip forward:
111 */
112 if (unlikely(left <= -period)) {
113 left = period;
114 local64_set(&hwc->period_left, left);
115 hwc->last_period = period;
116 overflow = 1;
117 }
118
119 if (unlikely(left < (s64)min)) {
120 left += period;
121 local64_set(&hwc->period_left, left);
122 hwc->last_period = period;
123 overflow = 1;
124 }
125
126 /*
127 * If the hw period that triggers the sw overflow is too short
128 * we might hit the irq handler. This biases the results.
129 * Thus we shorten the next-to-last period and set the last
130 * period to the max period.
131 */
132 if (left > max) {
133 left -= max;
134 if (left > max)
135 left = max;
136 else if (left < min)
137 left = min;
138 }
139
140 *hw_period = (u64)left;
141
142 return overflow;
143 }
144
145 static int
perf_event_try_update(struct perf_event * event,u64 new_raw_count,int width)146 perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
147 {
148 struct hw_perf_event *hwc = &event->hw;
149 int shift = 64 - width;
150 u64 prev_raw_count;
151 u64 delta;
152
153 /*
154 * Careful: an NMI might modify the previous event value.
155 *
156 * Our tactic to handle this is to first atomically read and
157 * exchange a new raw count - then add that new-prev delta
158 * count to the generic event atomically:
159 */
160 prev_raw_count = local64_read(&hwc->prev_count);
161 if (!local64_try_cmpxchg(&hwc->prev_count,
162 &prev_raw_count, new_raw_count))
163 return 0;
164
165 /*
166 * Now we have the new raw value and have updated the prev
167 * timestamp already. We can now calculate the elapsed delta
168 * (event-)time and add that to the generic event.
169 *
170 * Careful, not all hw sign-extends above the physical width
171 * of the count.
172 */
173 delta = (new_raw_count << shift) - (prev_raw_count << shift);
174 delta >>= shift;
175
176 local64_add(delta, &event->count);
177 local64_sub(delta, &hwc->period_left);
178
179 return 1;
180 }
181
182 static struct perf_ibs perf_ibs_fetch;
183 static struct perf_ibs perf_ibs_op;
184
get_ibs_pmu(int type)185 static struct perf_ibs *get_ibs_pmu(int type)
186 {
187 if (perf_ibs_fetch.pmu.type == type)
188 return &perf_ibs_fetch;
189 if (perf_ibs_op.pmu.type == type)
190 return &perf_ibs_op;
191 return NULL;
192 }
193
194 /*
195 * core pmu config -> IBS config
196 *
197 * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
198 * perf record -a -e r076:p ... # same as -e cpu-cycles:p
199 * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
200 *
201 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
202 * MSRC001_1033) is used to select either cycle or micro-ops counting
203 * mode.
204 */
core_pmu_ibs_config(struct perf_event * event,u64 * config)205 static int core_pmu_ibs_config(struct perf_event *event, u64 *config)
206 {
207 switch (event->attr.type) {
208 case PERF_TYPE_HARDWARE:
209 switch (event->attr.config) {
210 case PERF_COUNT_HW_CPU_CYCLES:
211 *config = 0;
212 return 0;
213 }
214 break;
215 case PERF_TYPE_RAW:
216 switch (event->attr.config) {
217 case 0x0076:
218 *config = 0;
219 return 0;
220 case 0x00C1:
221 *config = IBS_OP_CNT_CTL;
222 return 0;
223 }
224 break;
225 default:
226 return -ENOENT;
227 }
228
229 return -EOPNOTSUPP;
230 }
231
232 /*
233 * The rip of IBS samples has skid 0. Thus, IBS supports precise
234 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
235 * rip is invalid when IBS was not able to record the rip correctly.
236 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
237 */
forward_event_to_ibs(struct perf_event * event)238 int forward_event_to_ibs(struct perf_event *event)
239 {
240 u64 config = 0;
241
242 if (!event->attr.precise_ip || event->attr.precise_ip > 2)
243 return -EOPNOTSUPP;
244
245 if (!core_pmu_ibs_config(event, &config)) {
246 event->attr.type = perf_ibs_op.pmu.type;
247 event->attr.config = config;
248 }
249 return -ENOENT;
250 }
251
252 /*
253 * Grouping of IBS events is not possible since IBS can have only
254 * one event active at any point in time.
255 */
validate_group(struct perf_event * event)256 static int validate_group(struct perf_event *event)
257 {
258 struct perf_event *sibling;
259
260 if (event->group_leader == event)
261 return 0;
262
263 if (event->group_leader->pmu == event->pmu)
264 return -EINVAL;
265
266 for_each_sibling_event(sibling, event->group_leader) {
267 if (sibling->pmu == event->pmu)
268 return -EINVAL;
269 }
270 return 0;
271 }
272
perf_ibs_init(struct perf_event * event)273 static int perf_ibs_init(struct perf_event *event)
274 {
275 struct hw_perf_event *hwc = &event->hw;
276 struct perf_ibs *perf_ibs;
277 u64 max_cnt, config;
278 int ret;
279
280 perf_ibs = get_ibs_pmu(event->attr.type);
281 if (!perf_ibs)
282 return -ENOENT;
283
284 config = event->attr.config;
285
286 if (event->pmu != &perf_ibs->pmu)
287 return -ENOENT;
288
289 if (config & ~perf_ibs->config_mask)
290 return -EINVAL;
291
292 if (has_branch_stack(event))
293 return -EOPNOTSUPP;
294
295 /* handle exclude_{user,kernel} in the IRQ handler */
296 if (event->attr.exclude_host || event->attr.exclude_guest ||
297 event->attr.exclude_idle)
298 return -EINVAL;
299
300 if (!(event->attr.config2 & IBS_SW_FILTER_MASK) &&
301 (event->attr.exclude_kernel || event->attr.exclude_user ||
302 event->attr.exclude_hv))
303 return -EINVAL;
304
305 ret = validate_group(event);
306 if (ret)
307 return ret;
308
309 if (hwc->sample_period) {
310 if (config & perf_ibs->cnt_mask)
311 /* raw max_cnt may not be set */
312 return -EINVAL;
313 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
314 /*
315 * lower 4 bits can not be set in ibs max cnt,
316 * but allowing it in case we adjust the
317 * sample period to set a frequency.
318 */
319 return -EINVAL;
320 hwc->sample_period &= ~0x0FULL;
321 if (!hwc->sample_period)
322 hwc->sample_period = 0x10;
323 } else {
324 max_cnt = config & perf_ibs->cnt_mask;
325 config &= ~perf_ibs->cnt_mask;
326 event->attr.sample_period = max_cnt << 4;
327 hwc->sample_period = event->attr.sample_period;
328 }
329
330 if (!hwc->sample_period)
331 return -EINVAL;
332
333 /*
334 * If we modify hwc->sample_period, we also need to update
335 * hwc->last_period and hwc->period_left.
336 */
337 hwc->last_period = hwc->sample_period;
338 local64_set(&hwc->period_left, hwc->sample_period);
339
340 hwc->config_base = perf_ibs->msr;
341 hwc->config = config;
342
343 return 0;
344 }
345
perf_ibs_set_period(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 * period)346 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
347 struct hw_perf_event *hwc, u64 *period)
348 {
349 int overflow;
350
351 /* ignore lower 4 bits in min count: */
352 overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
353 local64_set(&hwc->prev_count, 0);
354
355 return overflow;
356 }
357
get_ibs_fetch_count(u64 config)358 static u64 get_ibs_fetch_count(u64 config)
359 {
360 union ibs_fetch_ctl fetch_ctl = (union ibs_fetch_ctl)config;
361
362 return fetch_ctl.fetch_cnt << 4;
363 }
364
get_ibs_op_count(u64 config)365 static u64 get_ibs_op_count(u64 config)
366 {
367 union ibs_op_ctl op_ctl = (union ibs_op_ctl)config;
368 u64 count = 0;
369
370 /*
371 * If the internal 27-bit counter rolled over, the count is MaxCnt
372 * and the lower 7 bits of CurCnt are randomized.
373 * Otherwise CurCnt has the full 27-bit current counter value.
374 */
375 if (op_ctl.op_val) {
376 count = op_ctl.opmaxcnt << 4;
377 if (ibs_caps & IBS_CAPS_OPCNTEXT)
378 count += op_ctl.opmaxcnt_ext << 20;
379 } else if (ibs_caps & IBS_CAPS_RDWROPCNT) {
380 count = op_ctl.opcurcnt;
381 }
382
383 return count;
384 }
385
386 static void
perf_ibs_event_update(struct perf_ibs * perf_ibs,struct perf_event * event,u64 * config)387 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
388 u64 *config)
389 {
390 u64 count = perf_ibs->get_count(*config);
391
392 /*
393 * Set width to 64 since we do not overflow on max width but
394 * instead on max count. In perf_ibs_set_period() we clear
395 * prev count manually on overflow.
396 */
397 while (!perf_event_try_update(event, count, 64)) {
398 rdmsrl(event->hw.config_base, *config);
399 count = perf_ibs->get_count(*config);
400 }
401 }
402
perf_ibs_enable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)403 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
404 struct hw_perf_event *hwc, u64 config)
405 {
406 u64 tmp = hwc->config | config;
407
408 if (perf_ibs->fetch_count_reset_broken)
409 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
410
411 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
412 }
413
414 /*
415 * Erratum #420 Instruction-Based Sampling Engine May Generate
416 * Interrupt that Cannot Be Cleared:
417 *
418 * Must clear counter mask first, then clear the enable bit. See
419 * Revision Guide for AMD Family 10h Processors, Publication #41322.
420 */
perf_ibs_disable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)421 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
422 struct hw_perf_event *hwc, u64 config)
423 {
424 config &= ~perf_ibs->cnt_mask;
425 if (boot_cpu_data.x86 == 0x10)
426 wrmsrl(hwc->config_base, config);
427 config &= ~perf_ibs->enable_mask;
428 wrmsrl(hwc->config_base, config);
429 }
430
431 /*
432 * We cannot restore the ibs pmu state, so we always needs to update
433 * the event while stopping it and then reset the state when starting
434 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
435 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
436 */
perf_ibs_start(struct perf_event * event,int flags)437 static void perf_ibs_start(struct perf_event *event, int flags)
438 {
439 struct hw_perf_event *hwc = &event->hw;
440 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
441 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
442 u64 period, config = 0;
443
444 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
445 return;
446
447 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
448 hwc->state = 0;
449
450 perf_ibs_set_period(perf_ibs, hwc, &period);
451 if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {
452 config |= period & IBS_OP_MAX_CNT_EXT_MASK;
453 period &= ~IBS_OP_MAX_CNT_EXT_MASK;
454 }
455 config |= period >> 4;
456
457 /*
458 * Set STARTED before enabling the hardware, such that a subsequent NMI
459 * must observe it.
460 */
461 set_bit(IBS_STARTED, pcpu->state);
462 clear_bit(IBS_STOPPING, pcpu->state);
463 perf_ibs_enable_event(perf_ibs, hwc, config);
464
465 perf_event_update_userpage(event);
466 }
467
perf_ibs_stop(struct perf_event * event,int flags)468 static void perf_ibs_stop(struct perf_event *event, int flags)
469 {
470 struct hw_perf_event *hwc = &event->hw;
471 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
472 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
473 u64 config;
474 int stopping;
475
476 if (test_and_set_bit(IBS_STOPPING, pcpu->state))
477 return;
478
479 stopping = test_bit(IBS_STARTED, pcpu->state);
480
481 if (!stopping && (hwc->state & PERF_HES_UPTODATE))
482 return;
483
484 rdmsrl(hwc->config_base, config);
485
486 if (stopping) {
487 /*
488 * Set STOPPED before disabling the hardware, such that it
489 * must be visible to NMIs the moment we clear the EN bit,
490 * at which point we can generate an !VALID sample which
491 * we need to consume.
492 */
493 set_bit(IBS_STOPPED, pcpu->state);
494 perf_ibs_disable_event(perf_ibs, hwc, config);
495 /*
496 * Clear STARTED after disabling the hardware; if it were
497 * cleared before an NMI hitting after the clear but before
498 * clearing the EN bit might think it a spurious NMI and not
499 * handle it.
500 *
501 * Clearing it after, however, creates the problem of the NMI
502 * handler seeing STARTED but not having a valid sample.
503 */
504 clear_bit(IBS_STARTED, pcpu->state);
505 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
506 hwc->state |= PERF_HES_STOPPED;
507 }
508
509 if (hwc->state & PERF_HES_UPTODATE)
510 return;
511
512 /*
513 * Clear valid bit to not count rollovers on update, rollovers
514 * are only updated in the irq handler.
515 */
516 config &= ~perf_ibs->valid_mask;
517
518 perf_ibs_event_update(perf_ibs, event, &config);
519 hwc->state |= PERF_HES_UPTODATE;
520 }
521
perf_ibs_add(struct perf_event * event,int flags)522 static int perf_ibs_add(struct perf_event *event, int flags)
523 {
524 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
525 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
526
527 if (test_and_set_bit(IBS_ENABLED, pcpu->state))
528 return -ENOSPC;
529
530 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
531
532 pcpu->event = event;
533
534 if (flags & PERF_EF_START)
535 perf_ibs_start(event, PERF_EF_RELOAD);
536
537 return 0;
538 }
539
perf_ibs_del(struct perf_event * event,int flags)540 static void perf_ibs_del(struct perf_event *event, int flags)
541 {
542 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
543 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
544
545 if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
546 return;
547
548 perf_ibs_stop(event, PERF_EF_UPDATE);
549
550 pcpu->event = NULL;
551
552 perf_event_update_userpage(event);
553 }
554
perf_ibs_read(struct perf_event * event)555 static void perf_ibs_read(struct perf_event *event) { }
556
557 /*
558 * We need to initialize with empty group if all attributes in the
559 * group are dynamic.
560 */
561 static struct attribute *attrs_empty[] = {
562 NULL,
563 };
564
565 static struct attribute_group empty_caps_group = {
566 .name = "caps",
567 .attrs = attrs_empty,
568 };
569
570 PMU_FORMAT_ATTR(rand_en, "config:57");
571 PMU_FORMAT_ATTR(cnt_ctl, "config:19");
572 PMU_FORMAT_ATTR(swfilt, "config2:0");
573 PMU_EVENT_ATTR_STRING(l3missonly, fetch_l3missonly, "config:59");
574 PMU_EVENT_ATTR_STRING(l3missonly, op_l3missonly, "config:16");
575 PMU_EVENT_ATTR_STRING(zen4_ibs_extensions, zen4_ibs_extensions, "1");
576
577 static umode_t
zen4_ibs_extensions_is_visible(struct kobject * kobj,struct attribute * attr,int i)578 zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *attr, int i)
579 {
580 return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0;
581 }
582
583 static struct attribute *fetch_attrs[] = {
584 &format_attr_rand_en.attr,
585 &format_attr_swfilt.attr,
586 NULL,
587 };
588
589 static struct attribute *fetch_l3missonly_attrs[] = {
590 &fetch_l3missonly.attr.attr,
591 NULL,
592 };
593
594 static struct attribute *zen4_ibs_extensions_attrs[] = {
595 &zen4_ibs_extensions.attr.attr,
596 NULL,
597 };
598
599 static struct attribute_group group_fetch_formats = {
600 .name = "format",
601 .attrs = fetch_attrs,
602 };
603
604 static struct attribute_group group_fetch_l3missonly = {
605 .name = "format",
606 .attrs = fetch_l3missonly_attrs,
607 .is_visible = zen4_ibs_extensions_is_visible,
608 };
609
610 static struct attribute_group group_zen4_ibs_extensions = {
611 .name = "caps",
612 .attrs = zen4_ibs_extensions_attrs,
613 .is_visible = zen4_ibs_extensions_is_visible,
614 };
615
616 static const struct attribute_group *fetch_attr_groups[] = {
617 &group_fetch_formats,
618 &empty_caps_group,
619 NULL,
620 };
621
622 static const struct attribute_group *fetch_attr_update[] = {
623 &group_fetch_l3missonly,
624 &group_zen4_ibs_extensions,
625 NULL,
626 };
627
628 static umode_t
cnt_ctl_is_visible(struct kobject * kobj,struct attribute * attr,int i)629 cnt_ctl_is_visible(struct kobject *kobj, struct attribute *attr, int i)
630 {
631 return ibs_caps & IBS_CAPS_OPCNT ? attr->mode : 0;
632 }
633
634 static struct attribute *op_attrs[] = {
635 &format_attr_swfilt.attr,
636 NULL,
637 };
638
639 static struct attribute *cnt_ctl_attrs[] = {
640 &format_attr_cnt_ctl.attr,
641 NULL,
642 };
643
644 static struct attribute *op_l3missonly_attrs[] = {
645 &op_l3missonly.attr.attr,
646 NULL,
647 };
648
649 static struct attribute_group group_op_formats = {
650 .name = "format",
651 .attrs = op_attrs,
652 };
653
654 static struct attribute_group group_cnt_ctl = {
655 .name = "format",
656 .attrs = cnt_ctl_attrs,
657 .is_visible = cnt_ctl_is_visible,
658 };
659
660 static struct attribute_group group_op_l3missonly = {
661 .name = "format",
662 .attrs = op_l3missonly_attrs,
663 .is_visible = zen4_ibs_extensions_is_visible,
664 };
665
666 static const struct attribute_group *op_attr_groups[] = {
667 &group_op_formats,
668 &empty_caps_group,
669 NULL,
670 };
671
672 static const struct attribute_group *op_attr_update[] = {
673 &group_cnt_ctl,
674 &group_op_l3missonly,
675 &group_zen4_ibs_extensions,
676 NULL,
677 };
678
679 static struct perf_ibs perf_ibs_fetch = {
680 .pmu = {
681 .task_ctx_nr = perf_hw_context,
682
683 .event_init = perf_ibs_init,
684 .add = perf_ibs_add,
685 .del = perf_ibs_del,
686 .start = perf_ibs_start,
687 .stop = perf_ibs_stop,
688 .read = perf_ibs_read,
689 },
690 .msr = MSR_AMD64_IBSFETCHCTL,
691 .config_mask = IBS_FETCH_CONFIG_MASK,
692 .cnt_mask = IBS_FETCH_MAX_CNT,
693 .enable_mask = IBS_FETCH_ENABLE,
694 .valid_mask = IBS_FETCH_VAL,
695 .max_period = IBS_FETCH_MAX_CNT << 4,
696 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
697 .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
698
699 .get_count = get_ibs_fetch_count,
700 };
701
702 static struct perf_ibs perf_ibs_op = {
703 .pmu = {
704 .task_ctx_nr = perf_hw_context,
705
706 .event_init = perf_ibs_init,
707 .add = perf_ibs_add,
708 .del = perf_ibs_del,
709 .start = perf_ibs_start,
710 .stop = perf_ibs_stop,
711 .read = perf_ibs_read,
712 },
713 .msr = MSR_AMD64_IBSOPCTL,
714 .config_mask = IBS_OP_CONFIG_MASK,
715 .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
716 IBS_OP_CUR_CNT_RAND,
717 .enable_mask = IBS_OP_ENABLE,
718 .valid_mask = IBS_OP_VAL,
719 .max_period = IBS_OP_MAX_CNT << 4,
720 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
721 .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
722
723 .get_count = get_ibs_op_count,
724 };
725
perf_ibs_get_mem_op(union ibs_op_data3 * op_data3,struct perf_sample_data * data)726 static void perf_ibs_get_mem_op(union ibs_op_data3 *op_data3,
727 struct perf_sample_data *data)
728 {
729 union perf_mem_data_src *data_src = &data->data_src;
730
731 data_src->mem_op = PERF_MEM_OP_NA;
732
733 if (op_data3->ld_op)
734 data_src->mem_op = PERF_MEM_OP_LOAD;
735 else if (op_data3->st_op)
736 data_src->mem_op = PERF_MEM_OP_STORE;
737 }
738
739 /*
740 * Processors having CPUID_Fn8000001B_EAX[11] aka IBS_CAPS_ZEN4 has
741 * more fine granular DataSrc encodings. Others have coarse.
742 */
perf_ibs_data_src(union ibs_op_data2 * op_data2)743 static u8 perf_ibs_data_src(union ibs_op_data2 *op_data2)
744 {
745 if (ibs_caps & IBS_CAPS_ZEN4)
746 return (op_data2->data_src_hi << 3) | op_data2->data_src_lo;
747
748 return op_data2->data_src_lo;
749 }
750
751 #define L(x) (PERF_MEM_S(LVL, x) | PERF_MEM_S(LVL, HIT))
752 #define LN(x) PERF_MEM_S(LVLNUM, x)
753 #define REM PERF_MEM_S(REMOTE, REMOTE)
754 #define HOPS(x) PERF_MEM_S(HOPS, x)
755
756 static u64 g_data_src[8] = {
757 [IBS_DATA_SRC_LOC_CACHE] = L(L3) | L(REM_CCE1) | LN(ANY_CACHE) | HOPS(0),
758 [IBS_DATA_SRC_DRAM] = L(LOC_RAM) | LN(RAM),
759 [IBS_DATA_SRC_REM_CACHE] = L(REM_CCE2) | LN(ANY_CACHE) | REM | HOPS(1),
760 [IBS_DATA_SRC_IO] = L(IO) | LN(IO),
761 };
762
763 #define RMT_NODE_BITS (1 << IBS_DATA_SRC_DRAM)
764 #define RMT_NODE_APPLICABLE(x) (RMT_NODE_BITS & (1 << x))
765
766 static u64 g_zen4_data_src[32] = {
767 [IBS_DATA_SRC_EXT_LOC_CACHE] = L(L3) | LN(L3),
768 [IBS_DATA_SRC_EXT_NEAR_CCX_CACHE] = L(REM_CCE1) | LN(ANY_CACHE) | REM | HOPS(0),
769 [IBS_DATA_SRC_EXT_DRAM] = L(LOC_RAM) | LN(RAM),
770 [IBS_DATA_SRC_EXT_FAR_CCX_CACHE] = L(REM_CCE2) | LN(ANY_CACHE) | REM | HOPS(1),
771 [IBS_DATA_SRC_EXT_PMEM] = LN(PMEM),
772 [IBS_DATA_SRC_EXT_IO] = L(IO) | LN(IO),
773 [IBS_DATA_SRC_EXT_EXT_MEM] = LN(CXL),
774 };
775
776 #define ZEN4_RMT_NODE_BITS ((1 << IBS_DATA_SRC_EXT_DRAM) | \
777 (1 << IBS_DATA_SRC_EXT_PMEM) | \
778 (1 << IBS_DATA_SRC_EXT_EXT_MEM))
779 #define ZEN4_RMT_NODE_APPLICABLE(x) (ZEN4_RMT_NODE_BITS & (1 << x))
780
perf_ibs_get_mem_lvl(union ibs_op_data2 * op_data2,union ibs_op_data3 * op_data3,struct perf_sample_data * data)781 static __u64 perf_ibs_get_mem_lvl(union ibs_op_data2 *op_data2,
782 union ibs_op_data3 *op_data3,
783 struct perf_sample_data *data)
784 {
785 union perf_mem_data_src *data_src = &data->data_src;
786 u8 ibs_data_src = perf_ibs_data_src(op_data2);
787
788 data_src->mem_lvl = 0;
789 data_src->mem_lvl_num = 0;
790
791 /*
792 * DcMiss, L2Miss, DataSrc, DcMissLat etc. are all invalid for Uncached
793 * memory accesses. So, check DcUcMemAcc bit early.
794 */
795 if (op_data3->dc_uc_mem_acc && ibs_data_src != IBS_DATA_SRC_EXT_IO)
796 return L(UNC) | LN(UNC);
797
798 /* L1 Hit */
799 if (op_data3->dc_miss == 0)
800 return L(L1) | LN(L1);
801
802 /* L2 Hit */
803 if (op_data3->l2_miss == 0) {
804 /* Erratum #1293 */
805 if (boot_cpu_data.x86 != 0x19 || boot_cpu_data.x86_model > 0xF ||
806 !(op_data3->sw_pf || op_data3->dc_miss_no_mab_alloc))
807 return L(L2) | LN(L2);
808 }
809
810 /*
811 * OP_DATA2 is valid only for load ops. Skip all checks which
812 * uses OP_DATA2[DataSrc].
813 */
814 if (data_src->mem_op != PERF_MEM_OP_LOAD)
815 goto check_mab;
816
817 if (ibs_caps & IBS_CAPS_ZEN4) {
818 u64 val = g_zen4_data_src[ibs_data_src];
819
820 if (!val)
821 goto check_mab;
822
823 /* HOPS_1 because IBS doesn't provide remote socket detail */
824 if (op_data2->rmt_node && ZEN4_RMT_NODE_APPLICABLE(ibs_data_src)) {
825 if (ibs_data_src == IBS_DATA_SRC_EXT_DRAM)
826 val = L(REM_RAM1) | LN(RAM) | REM | HOPS(1);
827 else
828 val |= REM | HOPS(1);
829 }
830
831 return val;
832 } else {
833 u64 val = g_data_src[ibs_data_src];
834
835 if (!val)
836 goto check_mab;
837
838 /* HOPS_1 because IBS doesn't provide remote socket detail */
839 if (op_data2->rmt_node && RMT_NODE_APPLICABLE(ibs_data_src)) {
840 if (ibs_data_src == IBS_DATA_SRC_DRAM)
841 val = L(REM_RAM1) | LN(RAM) | REM | HOPS(1);
842 else
843 val |= REM | HOPS(1);
844 }
845
846 return val;
847 }
848
849 check_mab:
850 /*
851 * MAB (Miss Address Buffer) Hit. MAB keeps track of outstanding
852 * DC misses. However, such data may come from any level in mem
853 * hierarchy. IBS provides detail about both MAB as well as actual
854 * DataSrc simultaneously. Prioritize DataSrc over MAB, i.e. set
855 * MAB only when IBS fails to provide DataSrc.
856 */
857 if (op_data3->dc_miss_no_mab_alloc)
858 return L(LFB) | LN(LFB);
859
860 /* Don't set HIT with NA */
861 return PERF_MEM_S(LVL, NA) | LN(NA);
862 }
863
perf_ibs_cache_hit_st_valid(void)864 static bool perf_ibs_cache_hit_st_valid(void)
865 {
866 /* 0: Uninitialized, 1: Valid, -1: Invalid */
867 static int cache_hit_st_valid;
868
869 if (unlikely(!cache_hit_st_valid)) {
870 if (boot_cpu_data.x86 == 0x19 &&
871 (boot_cpu_data.x86_model <= 0xF ||
872 (boot_cpu_data.x86_model >= 0x20 &&
873 boot_cpu_data.x86_model <= 0x5F))) {
874 cache_hit_st_valid = -1;
875 } else {
876 cache_hit_st_valid = 1;
877 }
878 }
879
880 return cache_hit_st_valid == 1;
881 }
882
perf_ibs_get_mem_snoop(union ibs_op_data2 * op_data2,struct perf_sample_data * data)883 static void perf_ibs_get_mem_snoop(union ibs_op_data2 *op_data2,
884 struct perf_sample_data *data)
885 {
886 union perf_mem_data_src *data_src = &data->data_src;
887 u8 ibs_data_src;
888
889 data_src->mem_snoop = PERF_MEM_SNOOP_NA;
890
891 if (!perf_ibs_cache_hit_st_valid() ||
892 data_src->mem_op != PERF_MEM_OP_LOAD ||
893 data_src->mem_lvl & PERF_MEM_LVL_L1 ||
894 data_src->mem_lvl & PERF_MEM_LVL_L2 ||
895 op_data2->cache_hit_st)
896 return;
897
898 ibs_data_src = perf_ibs_data_src(op_data2);
899
900 if (ibs_caps & IBS_CAPS_ZEN4) {
901 if (ibs_data_src == IBS_DATA_SRC_EXT_LOC_CACHE ||
902 ibs_data_src == IBS_DATA_SRC_EXT_NEAR_CCX_CACHE ||
903 ibs_data_src == IBS_DATA_SRC_EXT_FAR_CCX_CACHE)
904 data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
905 } else if (ibs_data_src == IBS_DATA_SRC_LOC_CACHE) {
906 data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
907 }
908 }
909
perf_ibs_get_tlb_lvl(union ibs_op_data3 * op_data3,struct perf_sample_data * data)910 static void perf_ibs_get_tlb_lvl(union ibs_op_data3 *op_data3,
911 struct perf_sample_data *data)
912 {
913 union perf_mem_data_src *data_src = &data->data_src;
914
915 data_src->mem_dtlb = PERF_MEM_TLB_NA;
916
917 if (!op_data3->dc_lin_addr_valid)
918 return;
919
920 if (!op_data3->dc_l1tlb_miss) {
921 data_src->mem_dtlb = PERF_MEM_TLB_L1 | PERF_MEM_TLB_HIT;
922 return;
923 }
924
925 if (!op_data3->dc_l2tlb_miss) {
926 data_src->mem_dtlb = PERF_MEM_TLB_L2 | PERF_MEM_TLB_HIT;
927 return;
928 }
929
930 data_src->mem_dtlb = PERF_MEM_TLB_L2 | PERF_MEM_TLB_MISS;
931 }
932
perf_ibs_get_mem_lock(union ibs_op_data3 * op_data3,struct perf_sample_data * data)933 static void perf_ibs_get_mem_lock(union ibs_op_data3 *op_data3,
934 struct perf_sample_data *data)
935 {
936 union perf_mem_data_src *data_src = &data->data_src;
937
938 data_src->mem_lock = PERF_MEM_LOCK_NA;
939
940 if (op_data3->dc_locked_op)
941 data_src->mem_lock = PERF_MEM_LOCK_LOCKED;
942 }
943
944 #define ibs_op_msr_idx(msr) (msr - MSR_AMD64_IBSOPCTL)
945
perf_ibs_get_data_src(struct perf_ibs_data * ibs_data,struct perf_sample_data * data,union ibs_op_data2 * op_data2,union ibs_op_data3 * op_data3)946 static void perf_ibs_get_data_src(struct perf_ibs_data *ibs_data,
947 struct perf_sample_data *data,
948 union ibs_op_data2 *op_data2,
949 union ibs_op_data3 *op_data3)
950 {
951 union perf_mem_data_src *data_src = &data->data_src;
952
953 data_src->val |= perf_ibs_get_mem_lvl(op_data2, op_data3, data);
954 perf_ibs_get_mem_snoop(op_data2, data);
955 perf_ibs_get_tlb_lvl(op_data3, data);
956 perf_ibs_get_mem_lock(op_data3, data);
957 }
958
perf_ibs_get_op_data2(struct perf_ibs_data * ibs_data,union ibs_op_data3 * op_data3)959 static __u64 perf_ibs_get_op_data2(struct perf_ibs_data *ibs_data,
960 union ibs_op_data3 *op_data3)
961 {
962 __u64 val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA2)];
963
964 /* Erratum #1293 */
965 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model <= 0xF &&
966 (op_data3->sw_pf || op_data3->dc_miss_no_mab_alloc)) {
967 /*
968 * OP_DATA2 has only two fields on Zen3: DataSrc and RmtNode.
969 * DataSrc=0 is 'No valid status' and RmtNode is invalid when
970 * DataSrc=0.
971 */
972 val = 0;
973 }
974 return val;
975 }
976
perf_ibs_parse_ld_st_data(__u64 sample_type,struct perf_ibs_data * ibs_data,struct perf_sample_data * data)977 static void perf_ibs_parse_ld_st_data(__u64 sample_type,
978 struct perf_ibs_data *ibs_data,
979 struct perf_sample_data *data)
980 {
981 union ibs_op_data3 op_data3;
982 union ibs_op_data2 op_data2;
983 union ibs_op_data op_data;
984
985 data->data_src.val = PERF_MEM_NA;
986 op_data3.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA3)];
987
988 perf_ibs_get_mem_op(&op_data3, data);
989 if (data->data_src.mem_op != PERF_MEM_OP_LOAD &&
990 data->data_src.mem_op != PERF_MEM_OP_STORE)
991 return;
992
993 op_data2.val = perf_ibs_get_op_data2(ibs_data, &op_data3);
994
995 if (sample_type & PERF_SAMPLE_DATA_SRC) {
996 perf_ibs_get_data_src(ibs_data, data, &op_data2, &op_data3);
997 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
998 }
999
1000 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE && op_data3.dc_miss &&
1001 data->data_src.mem_op == PERF_MEM_OP_LOAD) {
1002 op_data.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA)];
1003
1004 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
1005 data->weight.var1_dw = op_data3.dc_miss_lat;
1006 data->weight.var2_w = op_data.tag_to_ret_ctr;
1007 } else if (sample_type & PERF_SAMPLE_WEIGHT) {
1008 data->weight.full = op_data3.dc_miss_lat;
1009 }
1010 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1011 }
1012
1013 if (sample_type & PERF_SAMPLE_ADDR && op_data3.dc_lin_addr_valid) {
1014 data->addr = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSDCLINAD)];
1015 data->sample_flags |= PERF_SAMPLE_ADDR;
1016 }
1017
1018 if (sample_type & PERF_SAMPLE_PHYS_ADDR && op_data3.dc_phy_addr_valid) {
1019 data->phys_addr = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSDCPHYSAD)];
1020 data->sample_flags |= PERF_SAMPLE_PHYS_ADDR;
1021 }
1022 }
1023
perf_ibs_get_offset_max(struct perf_ibs * perf_ibs,u64 sample_type,int check_rip)1024 static int perf_ibs_get_offset_max(struct perf_ibs *perf_ibs, u64 sample_type,
1025 int check_rip)
1026 {
1027 if (sample_type & PERF_SAMPLE_RAW ||
1028 (perf_ibs == &perf_ibs_op &&
1029 (sample_type & PERF_SAMPLE_DATA_SRC ||
1030 sample_type & PERF_SAMPLE_WEIGHT_TYPE ||
1031 sample_type & PERF_SAMPLE_ADDR ||
1032 sample_type & PERF_SAMPLE_PHYS_ADDR)))
1033 return perf_ibs->offset_max;
1034 else if (check_rip)
1035 return 3;
1036 return 1;
1037 }
1038
perf_ibs_handle_irq(struct perf_ibs * perf_ibs,struct pt_regs * iregs)1039 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
1040 {
1041 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
1042 struct perf_event *event = pcpu->event;
1043 struct hw_perf_event *hwc;
1044 struct perf_sample_data data;
1045 struct perf_raw_record raw;
1046 struct pt_regs regs;
1047 struct perf_ibs_data ibs_data;
1048 int offset, size, check_rip, offset_max, throttle = 0;
1049 unsigned int msr;
1050 u64 *buf, *config, period, new_config = 0;
1051
1052 if (!test_bit(IBS_STARTED, pcpu->state)) {
1053 fail:
1054 /*
1055 * Catch spurious interrupts after stopping IBS: After
1056 * disabling IBS there could be still incoming NMIs
1057 * with samples that even have the valid bit cleared.
1058 * Mark all this NMIs as handled.
1059 */
1060 if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
1061 return 1;
1062
1063 return 0;
1064 }
1065
1066 if (WARN_ON_ONCE(!event))
1067 goto fail;
1068
1069 hwc = &event->hw;
1070 msr = hwc->config_base;
1071 buf = ibs_data.regs;
1072 rdmsrl(msr, *buf);
1073 if (!(*buf++ & perf_ibs->valid_mask))
1074 goto fail;
1075
1076 config = &ibs_data.regs[0];
1077 perf_ibs_event_update(perf_ibs, event, config);
1078 perf_sample_data_init(&data, 0, hwc->last_period);
1079 if (!perf_ibs_set_period(perf_ibs, hwc, &period))
1080 goto out; /* no sw counter overflow */
1081
1082 ibs_data.caps = ibs_caps;
1083 size = 1;
1084 offset = 1;
1085 check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
1086
1087 offset_max = perf_ibs_get_offset_max(perf_ibs, event->attr.sample_type, check_rip);
1088
1089 do {
1090 rdmsrl(msr + offset, *buf++);
1091 size++;
1092 offset = find_next_bit(perf_ibs->offset_mask,
1093 perf_ibs->offset_max,
1094 offset + 1);
1095 } while (offset < offset_max);
1096 /*
1097 * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately
1098 * depending on their availability.
1099 * Can't add to offset_max as they are staggered
1100 */
1101 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
1102 if (perf_ibs == &perf_ibs_op) {
1103 if (ibs_caps & IBS_CAPS_BRNTRGT) {
1104 rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
1105 size++;
1106 }
1107 if (ibs_caps & IBS_CAPS_OPDATA4) {
1108 rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
1109 size++;
1110 }
1111 }
1112 if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
1113 rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);
1114 size++;
1115 }
1116 }
1117 ibs_data.size = sizeof(u64) * size;
1118
1119 regs = *iregs;
1120 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
1121 regs.flags &= ~PERF_EFLAGS_EXACT;
1122 } else {
1123 /* Workaround for erratum #1197 */
1124 if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))
1125 goto out;
1126
1127 set_linear_ip(®s, ibs_data.regs[1]);
1128 regs.flags |= PERF_EFLAGS_EXACT;
1129 }
1130
1131 if (perf_ibs == &perf_ibs_op)
1132 perf_ibs_parse_ld_st_data(event->attr.sample_type, &ibs_data, &data);
1133
1134 if ((event->attr.config2 & IBS_SW_FILTER_MASK) &&
1135 (perf_exclude_event(event, ®s) ||
1136 ((data.sample_flags & PERF_SAMPLE_ADDR) &&
1137 event->attr.exclude_kernel && kernel_ip(data.addr)))) {
1138 throttle = perf_event_account_interrupt(event);
1139 goto out;
1140 }
1141
1142 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
1143 raw = (struct perf_raw_record){
1144 .frag = {
1145 .size = sizeof(u32) + ibs_data.size,
1146 .data = ibs_data.data,
1147 },
1148 };
1149 perf_sample_save_raw_data(&data, event, &raw);
1150 }
1151
1152 /*
1153 * rip recorded by IbsOpRip will not be consistent with rsp and rbp
1154 * recorded as part of interrupt regs. Thus we need to use rip from
1155 * interrupt regs while unwinding call stack.
1156 */
1157 perf_sample_save_callchain(&data, event, iregs);
1158
1159 throttle = perf_event_overflow(event, &data, ®s);
1160 out:
1161 if (throttle) {
1162 perf_ibs_stop(event, 0);
1163 } else {
1164 if (perf_ibs == &perf_ibs_op) {
1165 if (ibs_caps & IBS_CAPS_OPCNTEXT) {
1166 new_config = period & IBS_OP_MAX_CNT_EXT_MASK;
1167 period &= ~IBS_OP_MAX_CNT_EXT_MASK;
1168 }
1169 if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))
1170 new_config |= *config & IBS_OP_CUR_CNT_RAND;
1171 }
1172 new_config |= period >> 4;
1173
1174 perf_ibs_enable_event(perf_ibs, hwc, new_config);
1175 }
1176
1177 perf_event_update_userpage(event);
1178
1179 return 1;
1180 }
1181
1182 static int
perf_ibs_nmi_handler(unsigned int cmd,struct pt_regs * regs)1183 perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1184 {
1185 u64 stamp = sched_clock();
1186 int handled = 0;
1187
1188 handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
1189 handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
1190
1191 if (handled)
1192 inc_irq_stat(apic_perf_irqs);
1193
1194 perf_sample_event_took(sched_clock() - stamp);
1195
1196 return handled;
1197 }
1198 NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
1199
perf_ibs_pmu_init(struct perf_ibs * perf_ibs,char * name)1200 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
1201 {
1202 struct cpu_perf_ibs __percpu *pcpu;
1203 int ret;
1204
1205 pcpu = alloc_percpu(struct cpu_perf_ibs);
1206 if (!pcpu)
1207 return -ENOMEM;
1208
1209 perf_ibs->pcpu = pcpu;
1210
1211 ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
1212 if (ret) {
1213 perf_ibs->pcpu = NULL;
1214 free_percpu(pcpu);
1215 }
1216
1217 return ret;
1218 }
1219
perf_ibs_fetch_init(void)1220 static __init int perf_ibs_fetch_init(void)
1221 {
1222 /*
1223 * Some chips fail to reset the fetch count when it is written; instead
1224 * they need a 0-1 transition of IbsFetchEn.
1225 */
1226 if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18)
1227 perf_ibs_fetch.fetch_count_reset_broken = 1;
1228
1229 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)
1230 perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;
1231
1232 if (ibs_caps & IBS_CAPS_ZEN4)
1233 perf_ibs_fetch.config_mask |= IBS_FETCH_L3MISSONLY;
1234
1235 perf_ibs_fetch.pmu.attr_groups = fetch_attr_groups;
1236 perf_ibs_fetch.pmu.attr_update = fetch_attr_update;
1237
1238 return perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
1239 }
1240
perf_ibs_op_init(void)1241 static __init int perf_ibs_op_init(void)
1242 {
1243 if (ibs_caps & IBS_CAPS_OPCNT)
1244 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
1245
1246 if (ibs_caps & IBS_CAPS_OPCNTEXT) {
1247 perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK;
1248 perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK;
1249 perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK;
1250 }
1251
1252 if (ibs_caps & IBS_CAPS_ZEN4)
1253 perf_ibs_op.config_mask |= IBS_OP_L3MISSONLY;
1254
1255 perf_ibs_op.pmu.attr_groups = op_attr_groups;
1256 perf_ibs_op.pmu.attr_update = op_attr_update;
1257
1258 return perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
1259 }
1260
perf_event_ibs_init(void)1261 static __init int perf_event_ibs_init(void)
1262 {
1263 int ret;
1264
1265 ret = perf_ibs_fetch_init();
1266 if (ret)
1267 return ret;
1268
1269 ret = perf_ibs_op_init();
1270 if (ret)
1271 goto err_op;
1272
1273 ret = register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
1274 if (ret)
1275 goto err_nmi;
1276
1277 pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
1278 return 0;
1279
1280 err_nmi:
1281 perf_pmu_unregister(&perf_ibs_op.pmu);
1282 free_percpu(perf_ibs_op.pcpu);
1283 perf_ibs_op.pcpu = NULL;
1284 err_op:
1285 perf_pmu_unregister(&perf_ibs_fetch.pmu);
1286 free_percpu(perf_ibs_fetch.pcpu);
1287 perf_ibs_fetch.pcpu = NULL;
1288
1289 return ret;
1290 }
1291
1292 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
1293
perf_event_ibs_init(void)1294 static __init int perf_event_ibs_init(void)
1295 {
1296 return 0;
1297 }
1298
1299 #endif
1300
1301 /* IBS - apic initialization, for perf and oprofile */
1302
__get_ibs_caps(void)1303 static __init u32 __get_ibs_caps(void)
1304 {
1305 u32 caps;
1306 unsigned int max_level;
1307
1308 if (!boot_cpu_has(X86_FEATURE_IBS))
1309 return 0;
1310
1311 /* check IBS cpuid feature flags */
1312 max_level = cpuid_eax(0x80000000);
1313 if (max_level < IBS_CPUID_FEATURES)
1314 return IBS_CAPS_DEFAULT;
1315
1316 caps = cpuid_eax(IBS_CPUID_FEATURES);
1317 if (!(caps & IBS_CAPS_AVAIL))
1318 /* cpuid flags not valid */
1319 return IBS_CAPS_DEFAULT;
1320
1321 return caps;
1322 }
1323
get_ibs_caps(void)1324 u32 get_ibs_caps(void)
1325 {
1326 return ibs_caps;
1327 }
1328
1329 EXPORT_SYMBOL(get_ibs_caps);
1330
get_eilvt(int offset)1331 static inline int get_eilvt(int offset)
1332 {
1333 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
1334 }
1335
put_eilvt(int offset)1336 static inline int put_eilvt(int offset)
1337 {
1338 return !setup_APIC_eilvt(offset, 0, 0, 1);
1339 }
1340
1341 /*
1342 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
1343 */
ibs_eilvt_valid(void)1344 static inline int ibs_eilvt_valid(void)
1345 {
1346 int offset;
1347 u64 val;
1348 int valid = 0;
1349
1350 preempt_disable();
1351
1352 rdmsrl(MSR_AMD64_IBSCTL, val);
1353 offset = val & IBSCTL_LVT_OFFSET_MASK;
1354
1355 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
1356 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
1357 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
1358 goto out;
1359 }
1360
1361 if (!get_eilvt(offset)) {
1362 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
1363 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
1364 goto out;
1365 }
1366
1367 valid = 1;
1368 out:
1369 preempt_enable();
1370
1371 return valid;
1372 }
1373
setup_ibs_ctl(int ibs_eilvt_off)1374 static int setup_ibs_ctl(int ibs_eilvt_off)
1375 {
1376 struct pci_dev *cpu_cfg;
1377 int nodes;
1378 u32 value = 0;
1379
1380 nodes = 0;
1381 cpu_cfg = NULL;
1382 do {
1383 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
1384 PCI_DEVICE_ID_AMD_10H_NB_MISC,
1385 cpu_cfg);
1386 if (!cpu_cfg)
1387 break;
1388 ++nodes;
1389 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
1390 | IBSCTL_LVT_OFFSET_VALID);
1391 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
1392 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
1393 pci_dev_put(cpu_cfg);
1394 pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
1395 value);
1396 return -EINVAL;
1397 }
1398 } while (1);
1399
1400 if (!nodes) {
1401 pr_debug("No CPU node configured for IBS\n");
1402 return -ENODEV;
1403 }
1404
1405 return 0;
1406 }
1407
1408 /*
1409 * This runs only on the current cpu. We try to find an LVT offset and
1410 * setup the local APIC. For this we must disable preemption. On
1411 * success we initialize all nodes with this offset. This updates then
1412 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
1413 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
1414 * is using the new offset.
1415 */
force_ibs_eilvt_setup(void)1416 static void force_ibs_eilvt_setup(void)
1417 {
1418 int offset;
1419 int ret;
1420
1421 preempt_disable();
1422 /* find the next free available EILVT entry, skip offset 0 */
1423 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
1424 if (get_eilvt(offset))
1425 break;
1426 }
1427 preempt_enable();
1428
1429 if (offset == APIC_EILVT_NR_MAX) {
1430 pr_debug("No EILVT entry available\n");
1431 return;
1432 }
1433
1434 ret = setup_ibs_ctl(offset);
1435 if (ret)
1436 goto out;
1437
1438 if (!ibs_eilvt_valid())
1439 goto out;
1440
1441 pr_info("LVT offset %d assigned\n", offset);
1442
1443 return;
1444 out:
1445 preempt_disable();
1446 put_eilvt(offset);
1447 preempt_enable();
1448 return;
1449 }
1450
ibs_eilvt_setup(void)1451 static void ibs_eilvt_setup(void)
1452 {
1453 /*
1454 * Force LVT offset assignment for family 10h: The offsets are
1455 * not assigned by the BIOS for this family, so the OS is
1456 * responsible for doing it. If the OS assignment fails, fall
1457 * back to BIOS settings and try to setup this.
1458 */
1459 if (boot_cpu_data.x86 == 0x10)
1460 force_ibs_eilvt_setup();
1461 }
1462
get_ibs_lvt_offset(void)1463 static inline int get_ibs_lvt_offset(void)
1464 {
1465 u64 val;
1466
1467 rdmsrl(MSR_AMD64_IBSCTL, val);
1468 if (!(val & IBSCTL_LVT_OFFSET_VALID))
1469 return -EINVAL;
1470
1471 return val & IBSCTL_LVT_OFFSET_MASK;
1472 }
1473
setup_APIC_ibs(void)1474 static void setup_APIC_ibs(void)
1475 {
1476 int offset;
1477
1478 offset = get_ibs_lvt_offset();
1479 if (offset < 0)
1480 goto failed;
1481
1482 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
1483 return;
1484 failed:
1485 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
1486 smp_processor_id());
1487 }
1488
clear_APIC_ibs(void)1489 static void clear_APIC_ibs(void)
1490 {
1491 int offset;
1492
1493 offset = get_ibs_lvt_offset();
1494 if (offset >= 0)
1495 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
1496 }
1497
x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)1498 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
1499 {
1500 setup_APIC_ibs();
1501 return 0;
1502 }
1503
1504 #ifdef CONFIG_PM
1505
perf_ibs_suspend(void)1506 static int perf_ibs_suspend(void)
1507 {
1508 clear_APIC_ibs();
1509 return 0;
1510 }
1511
perf_ibs_resume(void)1512 static void perf_ibs_resume(void)
1513 {
1514 ibs_eilvt_setup();
1515 setup_APIC_ibs();
1516 }
1517
1518 static struct syscore_ops perf_ibs_syscore_ops = {
1519 .resume = perf_ibs_resume,
1520 .suspend = perf_ibs_suspend,
1521 };
1522
perf_ibs_pm_init(void)1523 static void perf_ibs_pm_init(void)
1524 {
1525 register_syscore_ops(&perf_ibs_syscore_ops);
1526 }
1527
1528 #else
1529
perf_ibs_pm_init(void)1530 static inline void perf_ibs_pm_init(void) { }
1531
1532 #endif
1533
x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)1534 static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
1535 {
1536 clear_APIC_ibs();
1537 return 0;
1538 }
1539
amd_ibs_init(void)1540 static __init int amd_ibs_init(void)
1541 {
1542 u32 caps;
1543
1544 caps = __get_ibs_caps();
1545 if (!caps)
1546 return -ENODEV; /* ibs not supported by the cpu */
1547
1548 ibs_eilvt_setup();
1549
1550 if (!ibs_eilvt_valid())
1551 return -EINVAL;
1552
1553 perf_ibs_pm_init();
1554
1555 ibs_caps = caps;
1556 /* make ibs_caps visible to other cpus: */
1557 smp_mb();
1558 /*
1559 * x86_pmu_amd_ibs_starting_cpu will be called from core on
1560 * all online cpus.
1561 */
1562 cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1563 "perf/x86/amd/ibs:starting",
1564 x86_pmu_amd_ibs_starting_cpu,
1565 x86_pmu_amd_ibs_dying_cpu);
1566
1567 return perf_event_ibs_init();
1568 }
1569
1570 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
1571 device_initcall(amd_ibs_init);
1572