xref: /titanic_41/usr/src/uts/common/sys/pcie_impl.h (revision 3d78e6ab42c6ffc02ee9dbd101ff2551b77cb45f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #ifndef	_SYS_PCIE_IMPL_H
26 #define	_SYS_PCIE_IMPL_H
27 
28 #ifdef	__cplusplus
29 extern "C" {
30 #endif
31 
32 #include <sys/pcie.h>
33 #include <sys/pciev.h>
34 
35 #define	PCI_GET_BDF(dip)	\
36 	PCIE_DIP2BUS(dip)->bus_bdf
37 #define	PCI_GET_SEC_BUS(dip)	\
38 	PCIE_DIP2BUS(dip)->bus_bdg_secbus
39 #define	PCI_GET_PCIE2PCI_SECBUS(dip) \
40 	PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus
41 
42 #define	DEVI_PORT_TYPE_PCI \
43 	((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \
44 	PCI_BRIDGE_PCI_IF_PCI2PCI)
45 
46 #define	PCIE_DIP2BUS(dip) \
47 	(ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \
48 	PCIE_DIP2UPBUS(dip) : \
49 	ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \
50 	PCIE_DIP2DOWNBUS(dip) : NULL)
51 
52 #define	PCIE_DIP2UPBUS(dip) \
53 	((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE))
54 #define	PCIE_DIP2DOWNBUS(dip) \
55 	((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE))
56 #define	PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd
57 #define	PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p
58 #define	PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip
59 #define	PCIE_BUS2DIP(bus_p) bus_p->bus_dip
60 #define	PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p))
61 #define	PCIE_BUS2DOM(bus_p) bus_p->bus_dom
62 #define	PCIE_DIP2DOM(dip) PCIE_BUS2DOM(PCIE_DIP2BUS(dip))
63 
64 /*
65  * These macros depend on initialization of type related data in bus_p.
66  */
67 #define	PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off)
68 #define	PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off)
69 #define	PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p))
70 #define	PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off)
71 /* IS_ROOT = is RC or RP */
72 #define	PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p))
73 
74 #define	PCIE_IS_HOTPLUG_CAPABLE(dip) \
75 	(PCIE_DIP2BUS(dip)->bus_hp_sup_modes)
76 
77 #define	PCIE_IS_HOTPLUG_ENABLED(dip) \
78 	((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \
79 	(PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE))
80 
81 /*
82  * This is a pseudo pcie "device type", but it's needed to explain describe
83  * nodes such as PX and NPE, which aren't really PCI devices but do control or
84  * interaction with PCI error handling.
85  */
86 #define	PCIE_IS_RC(bus_p) \
87 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO)
88 #define	PCIE_IS_RP(bus_p) \
89 	((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \
90 	    PCIE_IS_PCIE(bus_p))
91 #define	PCIE_IS_SWU(bus_p) \
92 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP)
93 #define	PCIE_IS_SWD(bus_p) \
94 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN)
95 #define	PCIE_IS_SW(bus_p) \
96 	(PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p))
97 #define	PCIE_IS_BDG(bus_p)  (bus_p->bus_hdr_type == PCI_HEADER_ONE)
98 #define	PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p))
99 #define	PCIE_IS_PCIE_BDG(bus_p) \
100 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI)
101 #define	PCIE_IS_PCI2PCIE(bus_p) \
102 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)
103 #define	PCIE_IS_PCIE_SEC(bus_p) \
104 	(PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p))
105 #define	PCIX_ECC_VERSION_CHECK(bus_p) \
106 	((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \
107 	    (bus_p->bus_ecc_ver == PCI_PCIX_VER_2))
108 
109 #define	PCIE_VENID(bus_p)	(bus_p->bus_dev_ven_id & 0xffff)
110 #define	PCIE_DEVID(bus_p)	((bus_p->bus_dev_ven_id >> 16) & 0xffff)
111 
112 /* PCIE Cap/AER shortcuts */
113 #define	PCIE_GET(sz, bus_p, off) \
114 	pci_config_get ## sz(bus_p->bus_cfg_hdl, off)
115 #define	PCIE_PUT(sz, bus_p, off, val) \
116 	pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val)
117 #define	PCIE_CAP_GET(sz, bus_p, off) \
118 	PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off)
119 #define	PCIE_CAP_PUT(sz, bus_p, off, val) \
120 	PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off, \
121 	    val)
122 #define	PCIE_AER_GET(sz, bus_p, off) \
123 	PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off)
124 #define	PCIE_AER_PUT(sz, bus_p, off, val) \
125 	PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off, \
126 	    val)
127 #define	PCIX_CAP_GET(sz, bus_p, off) \
128 	PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off)
129 #define	PCIX_CAP_PUT(sz, bus_p, off, val) \
130 	PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off, \
131 	    val)
132 
133 /* Translate PF error return values to DDI_FM values */
134 #define	PF_ERR2DDIFM_ERR(sts) \
135 	(sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL :	\
136 	(sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL))
137 
138 /*
139  * The following flag is used for Broadcom 5714/5715 bridge prefetch issue.
140  * This flag will be used both by px and pcieb nexus drivers.
141  */
142 #define	PX_DMAI_FLAGS_MAP_BUFZONE	0x40000
143 
144 /*
145  * PCI(e/-X) structures used to to gather and report errors detected by
146  * PCI(e/-X) compliant devices.  These registers only contain "dynamic" data.
147  * Static data such as Capability Offsets and Version #s is saved in the parent
148  * private data.
149  */
150 #define	PCI_ERR_REG(pfd_p)	   pfd_p->pe_pci_regs
151 #define	PCI_BDG_ERR_REG(pfd_p)	   PCI_ERR_REG(pfd_p)->pci_bdg_regs
152 #define	PCIX_ERR_REG(pfd_p)	   pfd_p->pe_ext.pe_pcix_regs
153 #define	PCIX_ECC_REG(pfd_p)	   PCIX_ERR_REG(pfd_p)->pcix_ecc_regs
154 #define	PCIX_BDG_ERR_REG(pfd_p)	   pfd_p->pe_pcix_bdg_regs
155 #define	PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n]
156 #define	PCIE_ERR_REG(pfd_p)	   pfd_p->pe_ext.pe_pcie_regs
157 #define	PCIE_RP_REG(pfd_p)	   PCIE_ERR_REG(pfd_p)->pcie_rp_regs
158 #define	PCIE_ROOT_FAULT(pfd_p)	   pfd_p->pe_root_fault
159 #define	PCIE_ROOT_EH_SRC(pfd_p)    pfd_p->pe_root_eh_src
160 #define	PCIE_ADV_REG(pfd_p)	   PCIE_ERR_REG(pfd_p)->pcie_adv_regs
161 #define	PCIE_ADV_HDR(pfd_p, n)	   PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n]
162 #define	PCIE_ADV_BDG_REG(pfd_p) \
163 	PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs
164 #define	PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n]
165 #define	PCIE_ADV_RP_REG(pfd_p) \
166 	PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs
167 #define	PFD_AFFECTED_DEV(pfd_p)	   pfd_p->pe_affected_dev
168 #define	PFD_SET_AFFECTED_FLAG(pfd_p, aff_flag) \
169 	PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = aff_flag
170 #define	PFD_SET_AFFECTED_BDF(pfd_p, bdf) \
171 	PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = bdf
172 
173 #define	PFD_IS_ROOT(pfd_p)	   PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p))
174 #define	PFD_IS_RC(pfd_p)	   PCIE_IS_RC(PCIE_PFD2BUS(pfd_p))
175 #define	PFD_IS_RP(pfd_p)	   PCIE_IS_RP(PCIE_PFD2BUS(pfd_p))
176 
177 /* bus_hp_mode field */
178 typedef enum {
179 	PCIE_NONE_HP_MODE	= 0x0,
180 	PCIE_ACPI_HP_MODE	= 0x1,
181 	PCIE_PCI_HP_MODE	= 0x2,
182 	PCIE_NATIVE_HP_MODE	= 0x4
183 } pcie_hp_mode_t;
184 
185 typedef struct pf_pci_bdg_err_regs {
186 	uint16_t pci_bdg_sec_stat;	/* PCI secondary status reg */
187 	uint16_t pci_bdg_ctrl;		/* PCI bridge control reg */
188 } pf_pci_bdg_err_regs_t;
189 
190 typedef struct pf_pci_err_regs {
191 	uint16_t pci_err_status;	/* pci status register */
192 	uint16_t pci_cfg_comm;		/* pci command register */
193 	pf_pci_bdg_err_regs_t *pci_bdg_regs;
194 } pf_pci_err_regs_t;
195 
196 typedef struct pf_pcix_ecc_regs {
197 	uint32_t pcix_ecc_ctlstat;	/* pcix ecc control status reg */
198 	uint32_t pcix_ecc_fstaddr;	/* pcix ecc first address reg */
199 	uint32_t pcix_ecc_secaddr;	/* pcix ecc second address reg */
200 	uint32_t pcix_ecc_attr;		/* pcix ecc attributes reg */
201 } pf_pcix_ecc_regs_t;
202 
203 typedef struct pf_pcix_err_regs {
204 	uint16_t pcix_command;		/* pcix command register */
205 	uint32_t pcix_status;		/* pcix status register */
206 	pf_pcix_ecc_regs_t *pcix_ecc_regs;	/* pcix ecc registers */
207 } pf_pcix_err_regs_t;
208 
209 typedef struct pf_pcix_bdg_err_regs {
210 	uint16_t pcix_bdg_sec_stat;	/* pcix bridge secondary status reg */
211 	uint32_t pcix_bdg_stat;		/* pcix bridge status reg */
212 	pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2];	/* pcix ecc registers */
213 } pf_pcix_bdg_err_regs_t;
214 
215 typedef struct pf_pcie_adv_bdg_err_regs {
216 	uint32_t pcie_sue_ctl;		/* pcie bridge secondary ue control */
217 	uint32_t pcie_sue_status;	/* pcie bridge secondary ue status */
218 	uint32_t pcie_sue_mask;		/* pcie bridge secondary ue mask */
219 	uint32_t pcie_sue_sev;		/* pcie bridge secondary ue severity */
220 	uint32_t pcie_sue_hdr[4];	/* pcie bridge secondary ue hdr log */
221 	uint32_t pcie_sue_tgt_trans;	/* Fault trans type from SAER Logs */
222 	uint64_t pcie_sue_tgt_addr;	/* Fault addr from SAER Logs */
223 	pcie_req_id_t pcie_sue_tgt_bdf;	/* Fault bdf from SAER Logs */
224 } pf_pcie_adv_bdg_err_regs_t;
225 
226 typedef struct pf_pcie_adv_rp_err_regs {
227 	uint32_t pcie_rp_err_status;	/* pcie root complex error status reg */
228 	uint32_t pcie_rp_err_cmd;	/* pcie root complex error cmd reg */
229 	uint16_t pcie_rp_ce_src_id;	/* pcie root complex ce sourpe id */
230 	uint16_t pcie_rp_ue_src_id;	/* pcie root complex ue sourpe id */
231 } pf_pcie_adv_rp_err_regs_t;
232 
233 typedef struct pf_pcie_adv_err_regs {
234 	uint32_t pcie_adv_ctl;		/* pcie advanced control reg */
235 	uint32_t pcie_ue_status;	/* pcie ue error status reg */
236 	uint32_t pcie_ue_mask;		/* pcie ue error mask reg */
237 	uint32_t pcie_ue_sev;		/* pcie ue error severity reg */
238 	uint32_t pcie_ue_hdr[4];	/* pcie ue header log */
239 	uint32_t pcie_ce_status;	/* pcie ce error status reg */
240 	uint32_t pcie_ce_mask;		/* pcie ce error mask reg */
241 	union {
242 		pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */
243 		pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs;	 /* rp regs */
244 	} pcie_ext;
245 	uint32_t pcie_ue_tgt_trans;	/* Fault trans type from AER Logs */
246 	uint64_t pcie_ue_tgt_addr;	/* Fault addr from AER Logs */
247 	pcie_req_id_t pcie_ue_tgt_bdf;	/* Fault bdf from AER Logs */
248 } pf_pcie_adv_err_regs_t;
249 
250 typedef struct pf_pcie_rp_err_regs {
251 	uint32_t pcie_rp_status;	/* root complex status register */
252 	uint16_t pcie_rp_ctl;		/* root complex control register */
253 } pf_pcie_rp_err_regs_t;
254 
255 typedef struct pf_pcie_err_regs {
256 	uint16_t pcie_err_status;	/* pcie device status register */
257 	uint16_t pcie_err_ctl;		/* pcie error control register */
258 	uint32_t pcie_dev_cap;		/* pcie device capabilities register */
259 	pf_pcie_rp_err_regs_t *pcie_rp_regs;	 /* pcie root complex regs */
260 	pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */
261 } pf_pcie_err_regs_t;
262 
263 typedef enum {
264 	PF_INTR_TYPE_NONE = 0,
265 	PF_INTR_TYPE_FABRIC = 1,	/* Fabric Message */
266 	PF_INTR_TYPE_DATA,		/* Data Access Failure, failed loads */
267 	PF_INTR_TYPE_AER,		/* Root Port AER MSI */
268 	PF_INTR_TYPE_INTERNAL		/* Chip specific internal errors */
269 } pf_intr_type_t;
270 
271 typedef struct pf_root_eh_src {
272 	pf_intr_type_t	intr_type;
273 	void		*intr_data;	/* Interrupt Data */
274 } pf_root_eh_src_t;
275 
276 typedef struct pf_root_fault {
277 	pcie_req_id_t	scan_bdf;	/* BDF from error logs */
278 	uint64_t	scan_addr;	/* Addr from error logs */
279 	boolean_t	full_scan;	/* Option to do a full scan */
280 } pf_root_fault_t;
281 
282 typedef struct pf_data pf_data_t;
283 
284 /*
285  * For hot plugged device, these data are init'ed during during probe
286  * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86),
287  * or in px_attach()(on sparc).
288  *
289  * For root complex the fields are initialized in pcie_rc_init_bus();
290  * for others part of the fields are initialized in pcie_init_bus(),
291  * and part of fields initialized in pcie_post_init_bus(). See comments
292  * on top of respective functions for details.
293  */
294 typedef struct pcie_bus {
295 	/* Needed for PCI/PCIe fabric error handling */
296 	dev_info_t	*bus_dip;
297 	dev_info_t	*bus_rp_dip;
298 	ddi_acc_handle_t bus_cfg_hdl;		/* error handling acc hdle */
299 	uint_t		bus_fm_flags;
300 	uint_t		bus_soft_state;
301 
302 	/* Static PCI/PCIe information */
303 	pcie_req_id_t	bus_bdf;
304 	pcie_req_id_t	bus_rp_bdf;		/* BDF of device's Root Port */
305 	uint32_t	bus_dev_ven_id;		/* device/vendor ID */
306 	uint8_t		bus_rev_id;		/* revision ID */
307 	uint8_t		bus_hdr_type;		/* pci header type, see pci.h */
308 	uint16_t	bus_dev_type;		/* PCI-E dev type, see pcie.h */
309 	uint8_t		bus_bdg_secbus;		/* Bridge secondary bus num */
310 	uint16_t	bus_pcie_off;		/* PCIe Capability Offset */
311 	uint16_t	bus_aer_off;		/* PCIe Advanced Error Offset */
312 	uint16_t	bus_pcix_off;		/* PCIx Capability Offset */
313 	uint16_t	bus_pci_hp_off;		/* PCI HP (SHPC) Cap Offset */
314 	uint16_t	bus_ecc_ver;		/* PCIX ecc version */
315 	pci_bus_range_t	bus_bus_range;		/* pci bus-range property */
316 	ppb_ranges_t	*bus_addr_ranges;	/* pci range property */
317 	int		bus_addr_entries;	/* number of range prop */
318 	pci_regspec_t	*bus_assigned_addr;	/* "assigned-address" prop */
319 	int		bus_assigned_entries;	/* number of prop entries */
320 
321 	/* Cache of last fault data */
322 	pf_data_t	*bus_pfd;
323 	pcie_domain_t	*bus_dom;
324 
325 	int		bus_mps;		/* Maximum Payload Size */
326 
327 	void		*bus_plat_private;	/* Platform specific */
328 	/* Hotplug specific fields */
329 	pcie_hp_mode_t	bus_hp_sup_modes;	/* HP modes supported */
330 	pcie_hp_mode_t	bus_hp_curr_mode;	/* HP mode used */
331 	void		*bus_hp_ctrl;		/* HP bus ctrl data */
332 	int		bus_ari;		/* ARI device */
333 
334 	uint64_t	bus_cfgacc_base;	/* config space base address */
335 
336 	/* workaround for PCI/PCI-X devs behind PCIe2PCI Bridge */
337 	pcie_req_id_t   bus_pcie2pci_secbus;
338 } pcie_bus_t;
339 
340 /*
341  * Data structure to log what devices are affected in relationship to the
342  * severity after all the errors bits have been analyzed.
343  */
344 #define	PF_AFFECTED_ROOT	(1 << 0) /* RP/RC is affected */
345 #define	PF_AFFECTED_SELF	(1 << 1) /* Reporting Device is affected */
346 #define	PF_AFFECTED_PARENT	(1 << 2) /* Parent device is affected */
347 #define	PF_AFFECTED_CHILDREN	(1 << 3) /* All children below are affected */
348 #define	PF_AFFECTED_BDF		(1 << 4) /* See affected_bdf */
349 #define	PF_AFFECTED_AER		(1 << 5) /* See AER Registers */
350 #define	PF_AFFECTED_SAER	(1 << 6) /* See SAER Registers */
351 #define	PF_AFFECTED_ADDR	(1 << 7) /* Device targeted by addr */
352 
353 #define	PF_MAX_AFFECTED_FLAG	PF_AFFECTED_ADDR
354 
355 typedef struct pf_affected_dev {
356 	uint16_t		pe_affected_flags;
357 	pcie_req_id_t		pe_affected_bdf;
358 } pf_affected_dev_t;
359 
360 struct pf_data {
361 	boolean_t		pe_lock;
362 	boolean_t		pe_valid;
363 	uint32_t		pe_severity_flags;	/* Severity of error */
364 	uint32_t		pe_orig_severity_flags; /* Original severity */
365 	pf_affected_dev_t	*pe_affected_dev;
366 	pcie_bus_t		*pe_bus_p;
367 	pf_root_fault_t		*pe_root_fault; /* Only valid for RC and RP */
368 	pf_root_eh_src_t	*pe_root_eh_src; /* Only valid for RC and RP */
369 	pf_pci_err_regs_t	*pe_pci_regs;	/* PCI error reg */
370 	union {
371 		pf_pcix_err_regs_t	*pe_pcix_regs;	/* PCI-X error reg */
372 		pf_pcie_err_regs_t	*pe_pcie_regs;	/* PCIe error reg */
373 	} pe_ext;
374 	pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */
375 	pf_data_t		*pe_prev;	/* Next error in queue */
376 	pf_data_t		*pe_next;	/* Next error in queue */
377 	boolean_t		pe_rber_fatal;
378 };
379 
380 /* Information used while handling errors in the fabric. */
381 typedef struct pf_impl {
382 	ddi_fm_error_t	*pf_derr;
383 	pf_root_fault_t	*pf_fault;	/* captured fault bdf/addr to scan */
384 	pf_data_t	*pf_dq_head_p;	/* ptr to fault data queue */
385 	pf_data_t	*pf_dq_tail_p;	/* ptr pt last fault data q */
386 	uint32_t	pf_total;	/* total non RC pf_datas */
387 } pf_impl_t;
388 
389 /* bus_fm_flags field */
390 #define	PF_FM_READY		(1 << 0)	/* bus_fm_lock initialized */
391 #define	PF_FM_IS_NH		(1 << 1)	/* known as non-hardened */
392 
393 /*
394  * PCIe fabric handle lookup address flags.  Used to define what type of
395  * transaction the address is for.  These same value are defined again in
396  * fabric-xlate FM module.  Do not modify these variables, without modifying
397  * those.
398  */
399 #define	PF_ADDR_DMA		(1 << 0)
400 #define	PF_ADDR_PIO		(1 << 1)
401 #define	PF_ADDR_CFG		(1 << 2)
402 
403 /* PCIe fabric error scanning status flags */
404 #define	PF_SCAN_SUCCESS		(1 << 0)
405 #define	PF_SCAN_CB_FAILURE	(1 << 1) /* hardened device callback failure */
406 #define	PF_SCAN_NO_ERR_IN_CHILD	(1 << 2) /* no errors in bridge sec stat reg */
407 #define	PF_SCAN_IN_DQ		(1 << 3) /* already present in the faultq */
408 #define	PF_SCAN_DEADLOCK	(1 << 4) /* deadlock detected */
409 #define	PF_SCAN_BAD_RESPONSE	(1 << 5) /* Incorrect device response */
410 
411 /* PCIe fabric error handling severity return flags */
412 #define	PF_ERR_NO_ERROR		(1 << 0) /* No error seen */
413 #define	PF_ERR_CE		(1 << 1) /* Correctable Error */
414 #define	PF_ERR_NO_PANIC		(1 << 2) /* Error should not panic sys */
415 #define	PF_ERR_MATCHED_DEVICE	(1 << 3) /* Error Handled By Device */
416 #define	PF_ERR_MATCHED_RC	(1 << 4) /* Error Handled By RC */
417 #define	PF_ERR_MATCHED_PARENT	(1 << 5) /* Error Handled By Parent */
418 #define	PF_ERR_PANIC		(1 << 6) /* Error should panic system */
419 #define	PF_ERR_PANIC_DEADLOCK	(1 << 7) /* deadlock detected */
420 #define	PF_ERR_PANIC_BAD_RESPONSE (1 << 8) /* Device no response */
421 #define	PF_ERR_MATCH_DOM	(1 << 9) /* Error Handled By IO domain */
422 
423 #define	PF_ERR_FATAL_FLAGS		\
424 	(PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK | PF_ERR_PANIC_BAD_RESPONSE)
425 
426 #define	PF_HDL_FOUND		1
427 #define	PF_HDL_NOTFOUND		2
428 
429 /*
430  * PCIe Capability Device Type Pseudo Definitions.
431  *
432  * PCI_PSEUDO is used on real PCI devices.  The Legacy PCI definition in the
433  * PCIe spec really refers to PCIe devices that *require* IO Space access.  IO
434  * Space access is usually frowned upon now in PCIe, but there for legacy
435  * purposes.
436  */
437 #define	PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO		0x100
438 #define	PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO	0x101
439 
440 #define	PCIE_INVALID_BDF	0xFFFF
441 #define	PCIE_CHECK_VALID_BDF(x)	(x != PCIE_INVALID_BDF)
442 
443 typedef struct {
444 	dev_info_t	*dip;
445 	int		highest_common_mps;
446 } pcie_max_supported_t;
447 
448 /*
449  * Default interrupt priority for all PCI and PCIe nexus drivers including
450  * hotplug interrupts.
451  */
452 #define	PCIE_INTR_PRI		(LOCK_LEVEL - 1)
453 
454 /*
455  * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros
456  * for non-standard PCI or PCI Express Hotplug Controllers.
457  */
458 #define	PCIE_ENABLE_ERRORS(dip)	\
459 	if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) {	\
460 		pcie_enable_errors(dip);	\
461 		(void) pcie_enable_ce(dip);	\
462 	}
463 
464 #define	PCIE_DISABLE_ERRORS(dip)		\
465 	if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) {	\
466 		pcie_disable_errors(dip);	\
467 	}
468 
469 /*
470  * pcie_init_buspcie_fini_bus specific flags
471  */
472 #define	PCIE_BUS_INITIAL	0x0001
473 #define	PCIE_BUS_FINAL		0x0002
474 #define	PCIE_BUS_ALL		(PCIE_BUS_INITIAL | PCIE_BUS_FINAL)
475 
476 #ifdef	DEBUG
477 #define	PCIE_DBG pcie_dbg
478 /* Common Debugging shortcuts */
479 #define	PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
480 	PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
481 	    ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
482 	    PCIE_GET(sz, bus_p, off))
483 #define	PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
484 	PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
485 	    ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 	    PCIE_CAP_GET(sz, bus_p, off))
487 #define	PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
488 	PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
489 	    ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 	    PCIE_AER_GET(sz, bus_p, off))
491 
492 #else	/* DEBUG */
493 
494 #define	PCIE_DBG_CFG 0 &&
495 #define	PCIE_DBG 0 &&
496 #define	PCIE_ARI_DBG 0 &&
497 #define	PCIE_DBG_CAP 0 &&
498 #define	PCIE_DBG_AER 0 &&
499 
500 #endif	/* DEBUG */
501 
502 /* PCIe Friendly Functions */
503 extern int pcie_init(dev_info_t *dip, caddr_t arg);
504 extern int pcie_uninit(dev_info_t *dip);
505 extern int pcie_hpintr_enable(dev_info_t *dip);
506 extern int pcie_hpintr_disable(dev_info_t *dip);
507 extern int pcie_intr(dev_info_t *dip);
508 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp,
509     cred_t *credp);
510 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp,
511     cred_t *credp);
512 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg,
513     int mode, cred_t *credp, int *rvalp);
514 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
515     int flags, char *name, caddr_t valuep, int *lengthp);
516 
517 extern void pcie_init_root_port_mps(dev_info_t *dip);
518 extern int pcie_initchild(dev_info_t *dip);
519 extern void pcie_uninitchild(dev_info_t *dip);
520 extern int pcie_init_cfghdl(dev_info_t *dip);
521 extern void pcie_fini_cfghdl(dev_info_t *dip);
522 extern void pcie_clear_errors(dev_info_t *dip);
523 extern int pcie_postattach_child(dev_info_t *dip);
524 extern void pcie_enable_errors(dev_info_t *dip);
525 extern void pcie_disable_errors(dev_info_t *dip);
526 extern int pcie_enable_ce(dev_info_t *dip);
527 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *);
528 
529 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf,
530     uint8_t flags);
531 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags);
532 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags);
533 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags);
534 extern void pcie_rc_init_bus(dev_info_t *dip);
535 extern void pcie_rc_fini_bus(dev_info_t *dip);
536 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd);
537 extern void pcie_rc_fini_pfd(pf_data_t *pfd);
538 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip);
539 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf);
540 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
541 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip);
542 extern int pcie_dev(dev_info_t *dip);
543 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip,
544 	int *max_supported);
545 extern int pcie_root_port(dev_info_t *dip);
546 extern int pcie_initchild_mps(dev_info_t *dip);
547 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val);
548 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip);
549 
550 extern uint32_t pcie_get_aer_uce_mask();
551 extern uint32_t pcie_get_aer_ce_mask();
552 extern uint32_t pcie_get_aer_suce_mask();
553 extern uint32_t pcie_get_serr_mask();
554 extern void pcie_set_aer_uce_mask(uint32_t mask);
555 extern void pcie_set_aer_ce_mask(uint32_t mask);
556 extern void pcie_set_aer_suce_mask(uint32_t mask);
557 extern void pcie_set_serr_mask(uint32_t mask);
558 extern void pcie_init_plat(dev_info_t *dip);
559 extern void pcie_fini_plat(dev_info_t *dip);
560 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **);
561 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function);
562 extern int pcie_ari_disable(dev_info_t *dip);
563 extern int pcie_ari_enable(dev_info_t *dip);
564 
565 #define	PCIE_ARI_FORW_NOT_SUPPORTED	0
566 #define	PCIE_ARI_FORW_SUPPORTED		1
567 
568 extern int pcie_ari_supported(dev_info_t *dip);
569 
570 #define	PCIE_ARI_FORW_DISABLED	0
571 #define	PCIE_ARI_FORW_ENABLED	1
572 
573 extern int pcie_ari_is_enabled(dev_info_t *dip);
574 
575 #define	PCIE_NOT_ARI_DEVICE		0
576 #define	PCIE_ARI_DEVICE			1
577 
578 extern int pcie_ari_device(dev_info_t *dip);
579 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func);
580 
581 /* PCIe error handling functions */
582 extern void pf_eh_enter(pcie_bus_t *bus_p);
583 extern void pf_eh_exit(pcie_bus_t *bus_p);
584 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr,
585     pf_data_t *root_pfd_p);
586 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t);
587 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t);
588 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t,
589     pcie_req_id_t);
590 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *);
591 extern void pcie_force_fullscan();
592 
593 #ifdef	DEBUG
594 extern uint_t pcie_debug_flags;
595 extern void pcie_dbg(char *fmt, ...);
596 #endif	/* DEBUG */
597 
598 /* PCIe IOV functions */
599 extern dev_info_t *pcie_find_dip_by_bdf(dev_info_t *rootp, pcie_req_id_t bdf);
600 
601 extern boolean_t pf_in_bus_range(pcie_bus_t *, pcie_req_id_t);
602 extern boolean_t pf_in_assigned_addr(pcie_bus_t *, uint64_t);
603 extern int pf_pci_decode(pf_data_t *, uint16_t *);
604 extern pcie_bus_t *pf_find_busp_by_bdf(pf_impl_t *, pcie_req_id_t);
605 extern pcie_bus_t *pf_find_busp_by_addr(pf_impl_t *, uint64_t);
606 extern pcie_bus_t *pf_find_busp_by_aer(pf_impl_t *, pf_data_t *);
607 extern pcie_bus_t *pf_find_busp_by_saer(pf_impl_t *, pf_data_t *);
608 
609 extern int pciev_eh(pf_data_t *, pf_impl_t *);
610 extern pcie_bus_t *pciev_get_affected_dev(pf_impl_t *, pf_data_t *,
611     uint16_t, uint16_t);
612 extern void pciev_eh_exit(pf_data_t *, uint_t);
613 extern boolean_t pcie_in_domain(pcie_bus_t *, uint_t);
614 
615 #define	PCIE_ZALLOC(data) kmem_zalloc(sizeof (data), KM_SLEEP)
616 
617 
618 #ifdef	__cplusplus
619 }
620 #endif
621 
622 #endif	/* _SYS_PCIE_IMPL_H */
623