1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include "amdgpu.h"
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_drv.h>
32 #include <drm/drm_fb_helper.h>
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "atom.h"
36
37 #include <linux/vga_switcheroo.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/pci.h>
41 #include <linux/pm_runtime.h>
42 #include "amdgpu_amdkfd.h"
43 #include "amdgpu_gem.h"
44 #include "amdgpu_display.h"
45 #include "amdgpu_ras.h"
46 #include "amdgpu_reset.h"
47 #include "amd_pcie.h"
48 #include "amdgpu_userq.h"
49
amdgpu_unregister_gpu_instance(struct amdgpu_device * adev)50 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
51 {
52 struct amdgpu_gpu_instance *gpu_instance;
53 int i;
54
55 mutex_lock(&mgpu_info.mutex);
56
57 for (i = 0; i < mgpu_info.num_gpu; i++) {
58 gpu_instance = &(mgpu_info.gpu_ins[i]);
59 if (gpu_instance->adev == adev) {
60 mgpu_info.gpu_ins[i] =
61 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
62 mgpu_info.num_gpu--;
63 if (adev->flags & AMD_IS_APU)
64 mgpu_info.num_apu--;
65 else
66 mgpu_info.num_dgpu--;
67 break;
68 }
69 }
70
71 mutex_unlock(&mgpu_info.mutex);
72 }
73
74 /**
75 * amdgpu_driver_unload_kms - Main unload function for KMS.
76 *
77 * @dev: drm dev pointer
78 *
79 * This is the main unload function for KMS (all asics).
80 * Returns 0 on success.
81 */
amdgpu_driver_unload_kms(struct drm_device * dev)82 void amdgpu_driver_unload_kms(struct drm_device *dev)
83 {
84 struct amdgpu_device *adev = drm_to_adev(dev);
85
86 if (adev == NULL)
87 return;
88
89 amdgpu_unregister_gpu_instance(adev);
90
91 if (adev->rmmio == NULL)
92 return;
93
94 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD))
95 DRM_WARN("smart shift update failed\n");
96
97 amdgpu_acpi_fini(adev);
98 amdgpu_device_fini_hw(adev);
99 }
100
amdgpu_register_gpu_instance(struct amdgpu_device * adev)101 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
102 {
103 struct amdgpu_gpu_instance *gpu_instance;
104
105 mutex_lock(&mgpu_info.mutex);
106
107 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
108 DRM_ERROR("Cannot register more gpu instance\n");
109 mutex_unlock(&mgpu_info.mutex);
110 return;
111 }
112
113 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
114 gpu_instance->adev = adev;
115 gpu_instance->mgpu_fan_enabled = 0;
116
117 mgpu_info.num_gpu++;
118 if (adev->flags & AMD_IS_APU)
119 mgpu_info.num_apu++;
120 else
121 mgpu_info.num_dgpu++;
122
123 mutex_unlock(&mgpu_info.mutex);
124 }
125
126 /**
127 * amdgpu_driver_load_kms - Main load function for KMS.
128 *
129 * @adev: pointer to struct amdgpu_device
130 * @flags: device flags
131 *
132 * This is the main load function for KMS (all asics).
133 * Returns 0 on success, error on failure.
134 */
amdgpu_driver_load_kms(struct amdgpu_device * adev,unsigned long flags)135 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
136 {
137 struct drm_device *dev;
138 int r, acpi_status;
139
140 dev = adev_to_drm(adev);
141
142 /* amdgpu_device_init should report only fatal error
143 * like memory allocation failure or iomapping failure,
144 * or memory manager initialization failure, it must
145 * properly initialize the GPU MC controller and permit
146 * VRAM allocation
147 */
148 r = amdgpu_device_init(adev, flags);
149 if (r) {
150 dev_err(dev->dev, "Fatal error during GPU init\n");
151 goto out;
152 }
153
154 amdgpu_device_detect_runtime_pm_mode(adev);
155
156 /* Call ACPI methods: require modeset init
157 * but failure is not fatal
158 */
159
160 acpi_status = amdgpu_acpi_init(adev);
161 if (acpi_status)
162 dev_dbg(dev->dev, "Error during ACPI methods call\n");
163
164 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD))
165 DRM_WARN("smart shift update failed\n");
166
167 out:
168 if (r)
169 amdgpu_driver_unload_kms(dev);
170
171 return r;
172 }
173
174 static enum amd_ip_block_type
amdgpu_ip_get_block_type(struct amdgpu_device * adev,uint32_t ip)175 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)
176 {
177 enum amd_ip_block_type type;
178
179 switch (ip) {
180 case AMDGPU_HW_IP_GFX:
181 type = AMD_IP_BLOCK_TYPE_GFX;
182 break;
183 case AMDGPU_HW_IP_COMPUTE:
184 type = AMD_IP_BLOCK_TYPE_GFX;
185 break;
186 case AMDGPU_HW_IP_DMA:
187 type = AMD_IP_BLOCK_TYPE_SDMA;
188 break;
189 case AMDGPU_HW_IP_UVD:
190 case AMDGPU_HW_IP_UVD_ENC:
191 type = AMD_IP_BLOCK_TYPE_UVD;
192 break;
193 case AMDGPU_HW_IP_VCE:
194 type = AMD_IP_BLOCK_TYPE_VCE;
195 break;
196 case AMDGPU_HW_IP_VCN_DEC:
197 case AMDGPU_HW_IP_VCN_ENC:
198 type = AMD_IP_BLOCK_TYPE_VCN;
199 break;
200 case AMDGPU_HW_IP_VCN_JPEG:
201 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
202 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
203 break;
204 default:
205 type = AMD_IP_BLOCK_TYPE_NUM;
206 break;
207 }
208
209 return type;
210 }
211
amdgpu_firmware_info(struct drm_amdgpu_info_firmware * fw_info,struct drm_amdgpu_query_fw * query_fw,struct amdgpu_device * adev)212 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
213 struct drm_amdgpu_query_fw *query_fw,
214 struct amdgpu_device *adev)
215 {
216 switch (query_fw->fw_type) {
217 case AMDGPU_INFO_FW_VCE:
218 fw_info->ver = adev->vce.fw_version;
219 fw_info->feature = adev->vce.fb_version;
220 break;
221 case AMDGPU_INFO_FW_UVD:
222 fw_info->ver = adev->uvd.fw_version;
223 fw_info->feature = 0;
224 break;
225 case AMDGPU_INFO_FW_VCN:
226 fw_info->ver = adev->vcn.fw_version;
227 fw_info->feature = 0;
228 break;
229 case AMDGPU_INFO_FW_GMC:
230 fw_info->ver = adev->gmc.fw_version;
231 fw_info->feature = 0;
232 break;
233 case AMDGPU_INFO_FW_GFX_ME:
234 fw_info->ver = adev->gfx.me_fw_version;
235 fw_info->feature = adev->gfx.me_feature_version;
236 break;
237 case AMDGPU_INFO_FW_GFX_PFP:
238 fw_info->ver = adev->gfx.pfp_fw_version;
239 fw_info->feature = adev->gfx.pfp_feature_version;
240 break;
241 case AMDGPU_INFO_FW_GFX_CE:
242 fw_info->ver = adev->gfx.ce_fw_version;
243 fw_info->feature = adev->gfx.ce_feature_version;
244 break;
245 case AMDGPU_INFO_FW_GFX_RLC:
246 fw_info->ver = adev->gfx.rlc_fw_version;
247 fw_info->feature = adev->gfx.rlc_feature_version;
248 break;
249 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
250 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
251 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
252 break;
253 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
254 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
255 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
256 break;
257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
258 fw_info->ver = adev->gfx.rlc_srls_fw_version;
259 fw_info->feature = adev->gfx.rlc_srls_feature_version;
260 break;
261 case AMDGPU_INFO_FW_GFX_RLCP:
262 fw_info->ver = adev->gfx.rlcp_ucode_version;
263 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
264 break;
265 case AMDGPU_INFO_FW_GFX_RLCV:
266 fw_info->ver = adev->gfx.rlcv_ucode_version;
267 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
268 break;
269 case AMDGPU_INFO_FW_GFX_MEC:
270 if (query_fw->index == 0) {
271 fw_info->ver = adev->gfx.mec_fw_version;
272 fw_info->feature = adev->gfx.mec_feature_version;
273 } else if (query_fw->index == 1) {
274 fw_info->ver = adev->gfx.mec2_fw_version;
275 fw_info->feature = adev->gfx.mec2_feature_version;
276 } else
277 return -EINVAL;
278 break;
279 case AMDGPU_INFO_FW_SMC:
280 fw_info->ver = adev->pm.fw_version;
281 fw_info->feature = 0;
282 break;
283 case AMDGPU_INFO_FW_TA:
284 switch (query_fw->index) {
285 case TA_FW_TYPE_PSP_XGMI:
286 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
287 fw_info->feature = adev->psp.xgmi_context.context
288 .bin_desc.feature_version;
289 break;
290 case TA_FW_TYPE_PSP_RAS:
291 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
292 fw_info->feature = adev->psp.ras_context.context
293 .bin_desc.feature_version;
294 break;
295 case TA_FW_TYPE_PSP_HDCP:
296 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
297 fw_info->feature = adev->psp.hdcp_context.context
298 .bin_desc.feature_version;
299 break;
300 case TA_FW_TYPE_PSP_DTM:
301 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
302 fw_info->feature = adev->psp.dtm_context.context
303 .bin_desc.feature_version;
304 break;
305 case TA_FW_TYPE_PSP_RAP:
306 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
307 fw_info->feature = adev->psp.rap_context.context
308 .bin_desc.feature_version;
309 break;
310 case TA_FW_TYPE_PSP_SECUREDISPLAY:
311 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
312 fw_info->feature =
313 adev->psp.securedisplay_context.context.bin_desc
314 .feature_version;
315 break;
316 default:
317 return -EINVAL;
318 }
319 break;
320 case AMDGPU_INFO_FW_SDMA:
321 if (query_fw->index >= adev->sdma.num_instances)
322 return -EINVAL;
323 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
324 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
325 break;
326 case AMDGPU_INFO_FW_SOS:
327 fw_info->ver = adev->psp.sos.fw_version;
328 fw_info->feature = adev->psp.sos.feature_version;
329 break;
330 case AMDGPU_INFO_FW_ASD:
331 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
332 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
333 break;
334 case AMDGPU_INFO_FW_DMCU:
335 fw_info->ver = adev->dm.dmcu_fw_version;
336 fw_info->feature = 0;
337 break;
338 case AMDGPU_INFO_FW_DMCUB:
339 fw_info->ver = adev->dm.dmcub_fw_version;
340 fw_info->feature = 0;
341 break;
342 case AMDGPU_INFO_FW_TOC:
343 fw_info->ver = adev->psp.toc.fw_version;
344 fw_info->feature = adev->psp.toc.feature_version;
345 break;
346 case AMDGPU_INFO_FW_CAP:
347 fw_info->ver = adev->psp.cap_fw_version;
348 fw_info->feature = adev->psp.cap_feature_version;
349 break;
350 case AMDGPU_INFO_FW_MES_KIQ:
351 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
352 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
353 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
354 break;
355 case AMDGPU_INFO_FW_MES:
356 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
357 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
358 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
359 break;
360 case AMDGPU_INFO_FW_IMU:
361 fw_info->ver = adev->gfx.imu_fw_version;
362 fw_info->feature = 0;
363 break;
364 case AMDGPU_INFO_FW_VPE:
365 fw_info->ver = adev->vpe.fw_version;
366 fw_info->feature = adev->vpe.feature_version;
367 break;
368 default:
369 return -EINVAL;
370 }
371 return 0;
372 }
373
amdgpu_userq_metadata_info_gfx(struct amdgpu_device * adev,struct drm_amdgpu_info * info,struct drm_amdgpu_info_uq_metadata_gfx * meta)374 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev,
375 struct drm_amdgpu_info *info,
376 struct drm_amdgpu_info_uq_metadata_gfx *meta)
377 {
378 int ret = -EOPNOTSUPP;
379
380 if (adev->gfx.funcs->get_gfx_shadow_info) {
381 struct amdgpu_gfx_shadow_info shadow = {};
382
383 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true);
384 meta->shadow_size = shadow.shadow_size;
385 meta->shadow_alignment = shadow.shadow_alignment;
386 meta->csa_size = shadow.csa_size;
387 meta->csa_alignment = shadow.csa_alignment;
388 ret = 0;
389 }
390
391 return ret;
392 }
393
amdgpu_hw_ip_info(struct amdgpu_device * adev,struct drm_amdgpu_info * info,struct drm_amdgpu_info_hw_ip * result)394 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
395 struct drm_amdgpu_info *info,
396 struct drm_amdgpu_info_hw_ip *result)
397 {
398 uint32_t ib_start_alignment = 0;
399 uint32_t ib_size_alignment = 0;
400 enum amd_ip_block_type type;
401 unsigned int num_rings = 0;
402 uint32_t num_slots = 0;
403 unsigned int i, j;
404
405 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
406 return -EINVAL;
407
408 switch (info->query_hw_ip.type) {
409 case AMDGPU_HW_IP_GFX:
410 type = AMD_IP_BLOCK_TYPE_GFX;
411 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
412 if (adev->gfx.gfx_ring[i].sched.ready &&
413 !adev->gfx.gfx_ring[i].no_user_submission)
414 ++num_rings;
415
416 if (!adev->gfx.disable_uq) {
417 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
418 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]);
419 }
420
421 ib_start_alignment = 32;
422 ib_size_alignment = 32;
423 break;
424 case AMDGPU_HW_IP_COMPUTE:
425 type = AMD_IP_BLOCK_TYPE_GFX;
426 for (i = 0; i < adev->gfx.num_compute_rings; i++)
427 if (adev->gfx.compute_ring[i].sched.ready &&
428 !adev->gfx.compute_ring[i].no_user_submission)
429 ++num_rings;
430
431 if (!adev->sdma.disable_uq) {
432 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++)
433 num_slots += hweight32(adev->mes.compute_hqd_mask[i]);
434 }
435
436 ib_start_alignment = 32;
437 ib_size_alignment = 32;
438 break;
439 case AMDGPU_HW_IP_DMA:
440 type = AMD_IP_BLOCK_TYPE_SDMA;
441 for (i = 0; i < adev->sdma.num_instances; i++)
442 if (adev->sdma.instance[i].ring.sched.ready &&
443 !adev->sdma.instance[i].ring.no_user_submission)
444 ++num_rings;
445
446 if (!adev->gfx.disable_uq) {
447 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
448 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]);
449 }
450
451 ib_start_alignment = 256;
452 ib_size_alignment = 4;
453 break;
454 case AMDGPU_HW_IP_UVD:
455 type = AMD_IP_BLOCK_TYPE_UVD;
456 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
457 if (adev->uvd.harvest_config & (1 << i))
458 continue;
459
460 if (adev->uvd.inst[i].ring.sched.ready &&
461 !adev->uvd.inst[i].ring.no_user_submission)
462 ++num_rings;
463 }
464 ib_start_alignment = 256;
465 ib_size_alignment = 64;
466 break;
467 case AMDGPU_HW_IP_VCE:
468 type = AMD_IP_BLOCK_TYPE_VCE;
469 for (i = 0; i < adev->vce.num_rings; i++)
470 if (adev->vce.ring[i].sched.ready &&
471 !adev->vce.ring[i].no_user_submission)
472 ++num_rings;
473 ib_start_alignment = 256;
474 ib_size_alignment = 4;
475 break;
476 case AMDGPU_HW_IP_UVD_ENC:
477 type = AMD_IP_BLOCK_TYPE_UVD;
478 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
479 if (adev->uvd.harvest_config & (1 << i))
480 continue;
481
482 for (j = 0; j < adev->uvd.num_enc_rings; j++)
483 if (adev->uvd.inst[i].ring_enc[j].sched.ready &&
484 !adev->uvd.inst[i].ring_enc[j].no_user_submission)
485 ++num_rings;
486 }
487 ib_start_alignment = 256;
488 ib_size_alignment = 4;
489 break;
490 case AMDGPU_HW_IP_VCN_DEC:
491 type = AMD_IP_BLOCK_TYPE_VCN;
492 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
493 if (adev->vcn.harvest_config & (1 << i))
494 continue;
495
496 if (adev->vcn.inst[i].ring_dec.sched.ready &&
497 !adev->vcn.inst[i].ring_dec.no_user_submission)
498 ++num_rings;
499 }
500 ib_start_alignment = 256;
501 ib_size_alignment = 64;
502 break;
503 case AMDGPU_HW_IP_VCN_ENC:
504 type = AMD_IP_BLOCK_TYPE_VCN;
505 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
506 if (adev->vcn.harvest_config & (1 << i))
507 continue;
508
509 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++)
510 if (adev->vcn.inst[i].ring_enc[j].sched.ready &&
511 !adev->vcn.inst[i].ring_enc[j].no_user_submission)
512 ++num_rings;
513 }
514 ib_start_alignment = 256;
515 ib_size_alignment = 4;
516 break;
517 case AMDGPU_HW_IP_VCN_JPEG:
518 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
519 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
520
521 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
522 if (adev->jpeg.harvest_config & (1 << i))
523 continue;
524
525 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
526 if (adev->jpeg.inst[i].ring_dec[j].sched.ready &&
527 !adev->jpeg.inst[i].ring_dec[j].no_user_submission)
528 ++num_rings;
529 }
530 ib_start_alignment = 256;
531 ib_size_alignment = 64;
532 break;
533 case AMDGPU_HW_IP_VPE:
534 type = AMD_IP_BLOCK_TYPE_VPE;
535 if (adev->vpe.ring.sched.ready &&
536 !adev->vpe.ring.no_user_submission)
537 ++num_rings;
538 ib_start_alignment = 256;
539 ib_size_alignment = 4;
540 break;
541 default:
542 return -EINVAL;
543 }
544
545 for (i = 0; i < adev->num_ip_blocks; i++)
546 if (adev->ip_blocks[i].version->type == type &&
547 adev->ip_blocks[i].status.valid)
548 break;
549
550 if (i == adev->num_ip_blocks)
551 return 0;
552
553 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
554 num_rings);
555
556 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
557 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
558
559 if (adev->asic_type >= CHIP_VEGA10) {
560 switch (type) {
561 case AMD_IP_BLOCK_TYPE_GFX:
562 result->ip_discovery_version =
563 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0));
564 break;
565 case AMD_IP_BLOCK_TYPE_SDMA:
566 result->ip_discovery_version =
567 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));
568 break;
569 case AMD_IP_BLOCK_TYPE_UVD:
570 case AMD_IP_BLOCK_TYPE_VCN:
571 case AMD_IP_BLOCK_TYPE_JPEG:
572 result->ip_discovery_version =
573 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
574 break;
575 case AMD_IP_BLOCK_TYPE_VCE:
576 result->ip_discovery_version =
577 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0));
578 break;
579 case AMD_IP_BLOCK_TYPE_VPE:
580 result->ip_discovery_version =
581 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
582 break;
583 default:
584 result->ip_discovery_version = 0;
585 break;
586 }
587 } else {
588 result->ip_discovery_version = 0;
589 }
590 result->capabilities_flags = 0;
591 result->available_rings = (1 << num_rings) - 1;
592 result->userq_num_slots = num_slots;
593 result->ib_start_alignment = ib_start_alignment;
594 result->ib_size_alignment = ib_size_alignment;
595 return 0;
596 }
597
598 /*
599 * Userspace get information ioctl
600 */
601 /**
602 * amdgpu_info_ioctl - answer a device specific request.
603 *
604 * @dev: drm device pointer
605 * @data: request object
606 * @filp: drm filp
607 *
608 * This function is used to pass device specific parameters to the userspace
609 * drivers. Examples include: pci device id, pipeline parms, tiling params,
610 * etc. (all asics).
611 * Returns 0 on success, -EINVAL on failure.
612 */
amdgpu_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)613 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
614 {
615 struct amdgpu_device *adev = drm_to_adev(dev);
616 struct drm_amdgpu_info *info = data;
617 struct amdgpu_mode_info *minfo = &adev->mode_info;
618 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
619 struct amdgpu_fpriv *fpriv;
620 struct amdgpu_ip_block *ip_block;
621 enum amd_ip_block_type type;
622 struct amdgpu_xcp *xcp;
623 u32 count, inst_mask;
624 uint32_t size = info->return_size;
625 struct drm_crtc *crtc;
626 uint32_t ui32 = 0;
627 uint64_t ui64 = 0;
628 int i, found, ret;
629 int ui32_size = sizeof(ui32);
630
631 if (!info->return_size || !info->return_pointer)
632 return -EINVAL;
633
634 switch (info->query) {
635 case AMDGPU_INFO_ACCEL_WORKING:
636 ui32 = adev->accel_working;
637 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
638 case AMDGPU_INFO_CRTC_FROM_ID:
639 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
640 crtc = (struct drm_crtc *)minfo->crtcs[i];
641 if (crtc && crtc->base.id == info->mode_crtc.id) {
642 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
643
644 ui32 = amdgpu_crtc->crtc_id;
645 found = 1;
646 break;
647 }
648 }
649 if (!found) {
650 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
651 return -EINVAL;
652 }
653 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
654 case AMDGPU_INFO_HW_IP_INFO: {
655 struct drm_amdgpu_info_hw_ip ip = {};
656
657 ret = amdgpu_hw_ip_info(adev, info, &ip);
658 if (ret)
659 return ret;
660
661 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
662 return ret ? -EFAULT : 0;
663 }
664 case AMDGPU_INFO_HW_IP_COUNT: {
665 fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
666 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
667 ip_block = amdgpu_device_ip_get_ip_block(adev, type);
668
669 if (!ip_block || !ip_block->status.valid)
670 return -EINVAL;
671
672 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
673 fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
674 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
675 switch (type) {
676 case AMD_IP_BLOCK_TYPE_GFX:
677 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
678 if (ret)
679 return ret;
680 count = hweight32(inst_mask);
681 break;
682 case AMD_IP_BLOCK_TYPE_SDMA:
683 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask);
684 if (ret)
685 return ret;
686 count = hweight32(inst_mask);
687 break;
688 case AMD_IP_BLOCK_TYPE_JPEG:
689 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
690 if (ret)
691 return ret;
692 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings;
693 break;
694 case AMD_IP_BLOCK_TYPE_VCN:
695 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
696 if (ret)
697 return ret;
698 count = hweight32(inst_mask);
699 break;
700 default:
701 return -EINVAL;
702 }
703
704 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
705 }
706
707 switch (type) {
708 case AMD_IP_BLOCK_TYPE_GFX:
709 case AMD_IP_BLOCK_TYPE_VCE:
710 count = 1;
711 break;
712 case AMD_IP_BLOCK_TYPE_SDMA:
713 count = adev->sdma.num_instances;
714 break;
715 case AMD_IP_BLOCK_TYPE_JPEG:
716 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings;
717 break;
718 case AMD_IP_BLOCK_TYPE_VCN:
719 count = adev->vcn.num_vcn_inst;
720 break;
721 case AMD_IP_BLOCK_TYPE_UVD:
722 count = adev->uvd.num_uvd_inst;
723 break;
724 /* For all other IP block types not listed in the switch statement
725 * the ip status is valid here and the instance count is one.
726 */
727 default:
728 count = 1;
729 break;
730 }
731
732 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
733 }
734 case AMDGPU_INFO_TIMESTAMP:
735 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
736 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
737 case AMDGPU_INFO_FW_VERSION: {
738 struct drm_amdgpu_info_firmware fw_info;
739
740 /* We only support one instance of each IP block right now. */
741 if (info->query_fw.ip_instance != 0)
742 return -EINVAL;
743
744 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
745 if (ret)
746 return ret;
747
748 return copy_to_user(out, &fw_info,
749 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
750 }
751 case AMDGPU_INFO_NUM_BYTES_MOVED:
752 ui64 = atomic64_read(&adev->num_bytes_moved);
753 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
754 case AMDGPU_INFO_NUM_EVICTIONS:
755 ui64 = atomic64_read(&adev->num_evictions);
756 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
757 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
758 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
759 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
760 case AMDGPU_INFO_VRAM_USAGE:
761 ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ?
762 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0;
763 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
764 case AMDGPU_INFO_VIS_VRAM_USAGE:
765 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
766 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
767 case AMDGPU_INFO_GTT_USAGE:
768 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
769 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
770 case AMDGPU_INFO_GDS_CONFIG: {
771 struct drm_amdgpu_info_gds gds_info;
772
773 memset(&gds_info, 0, sizeof(gds_info));
774 gds_info.compute_partition_size = adev->gds.gds_size;
775 gds_info.gds_total_size = adev->gds.gds_size;
776 gds_info.gws_per_compute_partition = adev->gds.gws_size;
777 gds_info.oa_per_compute_partition = adev->gds.oa_size;
778 return copy_to_user(out, &gds_info,
779 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
780 }
781 case AMDGPU_INFO_VRAM_GTT: {
782 struct drm_amdgpu_info_vram_gtt vram_gtt;
783
784 vram_gtt.vram_size = adev->gmc.real_vram_size -
785 atomic64_read(&adev->vram_pin_size) -
786 AMDGPU_VM_RESERVED_VRAM;
787 vram_gtt.vram_cpu_accessible_size =
788 min(adev->gmc.visible_vram_size -
789 atomic64_read(&adev->visible_pin_size),
790 vram_gtt.vram_size);
791 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
792 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
793 return copy_to_user(out, &vram_gtt,
794 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
795 }
796 case AMDGPU_INFO_MEMORY: {
797 struct drm_amdgpu_memory_info mem;
798 struct ttm_resource_manager *gtt_man =
799 &adev->mman.gtt_mgr.manager;
800 struct ttm_resource_manager *vram_man =
801 &adev->mman.vram_mgr.manager;
802
803 memset(&mem, 0, sizeof(mem));
804 mem.vram.total_heap_size = adev->gmc.real_vram_size;
805 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
806 atomic64_read(&adev->vram_pin_size) -
807 AMDGPU_VM_RESERVED_VRAM;
808 mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ?
809 ttm_resource_manager_usage(vram_man) : 0;
810 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
811
812 mem.cpu_accessible_vram.total_heap_size =
813 adev->gmc.visible_vram_size;
814 mem.cpu_accessible_vram.usable_heap_size =
815 min(adev->gmc.visible_vram_size -
816 atomic64_read(&adev->visible_pin_size),
817 mem.vram.usable_heap_size);
818 mem.cpu_accessible_vram.heap_usage =
819 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
820 mem.cpu_accessible_vram.max_allocation =
821 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
822
823 mem.gtt.total_heap_size = gtt_man->size;
824 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
825 atomic64_read(&adev->gart_pin_size);
826 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
827 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
828
829 return copy_to_user(out, &mem,
830 min((size_t)size, sizeof(mem)))
831 ? -EFAULT : 0;
832 }
833 case AMDGPU_INFO_READ_MMR_REG: {
834 int ret = 0;
835 unsigned int n, alloc_size;
836 uint32_t *regs;
837 unsigned int se_num = (info->read_mmr_reg.instance >>
838 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
839 AMDGPU_INFO_MMR_SE_INDEX_MASK;
840 unsigned int sh_num = (info->read_mmr_reg.instance >>
841 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
842 AMDGPU_INFO_MMR_SH_INDEX_MASK;
843
844 if (!down_read_trylock(&adev->reset_domain->sem))
845 return -ENOENT;
846
847 /* set full masks if the userspace set all bits
848 * in the bitfields
849 */
850 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {
851 se_num = 0xffffffff;
852 } else if (se_num >= AMDGPU_GFX_MAX_SE) {
853 ret = -EINVAL;
854 goto out;
855 }
856
857 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {
858 sh_num = 0xffffffff;
859 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {
860 ret = -EINVAL;
861 goto out;
862 }
863
864 if (info->read_mmr_reg.count > 128) {
865 ret = -EINVAL;
866 goto out;
867 }
868
869 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
870 if (!regs) {
871 ret = -ENOMEM;
872 goto out;
873 }
874
875 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
876
877 amdgpu_gfx_off_ctrl(adev, false);
878 for (i = 0; i < info->read_mmr_reg.count; i++) {
879 if (amdgpu_asic_read_register(adev, se_num, sh_num,
880 info->read_mmr_reg.dword_offset + i,
881 ®s[i])) {
882 DRM_DEBUG_KMS("unallowed offset %#x\n",
883 info->read_mmr_reg.dword_offset + i);
884 kfree(regs);
885 amdgpu_gfx_off_ctrl(adev, true);
886 ret = -EFAULT;
887 goto out;
888 }
889 }
890 amdgpu_gfx_off_ctrl(adev, true);
891 n = copy_to_user(out, regs, min(size, alloc_size));
892 kfree(regs);
893 ret = (n ? -EFAULT : 0);
894 out:
895 up_read(&adev->reset_domain->sem);
896 return ret;
897 }
898 case AMDGPU_INFO_DEV_INFO: {
899 struct drm_amdgpu_info_device *dev_info;
900 uint64_t vm_size;
901 uint32_t pcie_gen_mask, pcie_width_mask;
902
903 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
904 if (!dev_info)
905 return -ENOMEM;
906
907 dev_info->device_id = adev->pdev->device;
908 dev_info->chip_rev = adev->rev_id;
909 dev_info->external_rev = adev->external_rev_id;
910 dev_info->pci_rev = adev->pdev->revision;
911 dev_info->family = adev->family;
912 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
913 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
914 /* return all clocks in KHz */
915 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
916 if (adev->pm.dpm_enabled) {
917 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
918 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
919 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
920 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
921 } else {
922 dev_info->max_engine_clock =
923 dev_info->min_engine_clock =
924 adev->clock.default_sclk * 10;
925 dev_info->max_memory_clock =
926 dev_info->min_memory_clock =
927 adev->clock.default_mclk * 10;
928 }
929 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
930 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
931 adev->gfx.config.max_shader_engines;
932 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
933 dev_info->ids_flags = 0;
934 if (adev->flags & AMD_IS_APU)
935 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
936 if (adev->gfx.mcbp)
937 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
938 if (amdgpu_is_tmz(adev))
939 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
940 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
941 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
942
943 /* Gang submit is not supported under SRIOV currently */
944 if (!amdgpu_sriov_vf(adev))
945 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT;
946
947 if (amdgpu_passthrough(adev))
948 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT <<
949 AMDGPU_IDS_FLAGS_MODE_SHIFT) &
950 AMDGPU_IDS_FLAGS_MODE_MASK;
951 else if (amdgpu_sriov_vf(adev))
952 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF <<
953 AMDGPU_IDS_FLAGS_MODE_SHIFT) &
954 AMDGPU_IDS_FLAGS_MODE_MASK;
955
956 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
957 vm_size -= AMDGPU_VA_RESERVED_TOP;
958
959 /* Older VCE FW versions are buggy and can handle only 40bits */
960 if (adev->vce.fw_version &&
961 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
962 vm_size = min(vm_size, 1ULL << 40);
963
964 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM;
965 dev_info->virtual_address_max =
966 min(vm_size, AMDGPU_GMC_HOLE_START);
967
968 if (vm_size > AMDGPU_GMC_HOLE_START) {
969 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
970 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
971 }
972 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
973 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
974 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
975 dev_info->cu_active_number = adev->gfx.cu_info.number;
976 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
977 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
978 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
979 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
980 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
981 sizeof(dev_info->cu_bitmap));
982 dev_info->vram_type = adev->gmc.vram_type;
983 dev_info->vram_bit_width = adev->gmc.vram_width;
984 dev_info->vce_harvest_config = adev->vce.harvest_config;
985 dev_info->gc_double_offchip_lds_buf =
986 adev->gfx.config.double_offchip_lds_buf;
987 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
988 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
989 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
990 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
991 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
992 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
993 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
994
995 if (adev->family >= AMDGPU_FAMILY_NV)
996 dev_info->pa_sc_tile_steering_override =
997 adev->gfx.config.pa_sc_tile_steering_override;
998
999 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
1000
1001 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
1002 pcie_gen_mask = adev->pm.pcie_gen_mask &
1003 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT);
1004 pcie_width_mask = adev->pm.pcie_mlw_mask &
1005 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT);
1006 dev_info->pcie_gen = fls(pcie_gen_mask);
1007 dev_info->pcie_num_lanes =
1008 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
1009 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
1010 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
1011 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
1012 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
1013 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
1014
1015 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
1016 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
1017 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
1018 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
1019 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
1020 adev->gfx.config.gc_gl1c_per_sa;
1021 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
1022 dev_info->mall_size = adev->gmc.mall_size;
1023
1024
1025 if (adev->gfx.funcs->get_gfx_shadow_info) {
1026 struct amdgpu_gfx_shadow_info shadow_info;
1027
1028 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
1029 if (!ret) {
1030 dev_info->shadow_size = shadow_info.shadow_size;
1031 dev_info->shadow_alignment = shadow_info.shadow_alignment;
1032 dev_info->csa_size = shadow_info.csa_size;
1033 dev_info->csa_alignment = shadow_info.csa_alignment;
1034 }
1035 }
1036
1037 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev);
1038
1039 ret = copy_to_user(out, dev_info,
1040 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
1041 kfree(dev_info);
1042 return ret;
1043 }
1044 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
1045 unsigned int i;
1046 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
1047 struct amd_vce_state *vce_state;
1048
1049 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
1050 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
1051 if (vce_state) {
1052 vce_clk_table.entries[i].sclk = vce_state->sclk;
1053 vce_clk_table.entries[i].mclk = vce_state->mclk;
1054 vce_clk_table.entries[i].eclk = vce_state->evclk;
1055 vce_clk_table.num_valid_entries++;
1056 }
1057 }
1058
1059 return copy_to_user(out, &vce_clk_table,
1060 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
1061 }
1062 case AMDGPU_INFO_VBIOS: {
1063 uint32_t bios_size = adev->bios_size;
1064
1065 switch (info->vbios_info.type) {
1066 case AMDGPU_INFO_VBIOS_SIZE:
1067 return copy_to_user(out, &bios_size,
1068 min((size_t)size, sizeof(bios_size)))
1069 ? -EFAULT : 0;
1070 case AMDGPU_INFO_VBIOS_IMAGE: {
1071 uint8_t *bios;
1072 uint32_t bios_offset = info->vbios_info.offset;
1073
1074 if (bios_offset >= bios_size)
1075 return -EINVAL;
1076
1077 bios = adev->bios + bios_offset;
1078 return copy_to_user(out, bios,
1079 min((size_t)size, (size_t)(bios_size - bios_offset)))
1080 ? -EFAULT : 0;
1081 }
1082 case AMDGPU_INFO_VBIOS_INFO: {
1083 struct drm_amdgpu_info_vbios vbios_info = {};
1084 struct atom_context *atom_context;
1085
1086 atom_context = adev->mode_info.atom_context;
1087 if (atom_context) {
1088 memcpy(vbios_info.name, atom_context->name,
1089 sizeof(atom_context->name));
1090 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
1091 sizeof(atom_context->vbios_pn));
1092 vbios_info.version = atom_context->version;
1093 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
1094 sizeof(atom_context->vbios_ver_str));
1095 memcpy(vbios_info.date, atom_context->date,
1096 sizeof(atom_context->date));
1097 }
1098
1099 return copy_to_user(out, &vbios_info,
1100 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
1101 }
1102 default:
1103 DRM_DEBUG_KMS("Invalid request %d\n",
1104 info->vbios_info.type);
1105 return -EINVAL;
1106 }
1107 }
1108 case AMDGPU_INFO_NUM_HANDLES: {
1109 struct drm_amdgpu_info_num_handles handle;
1110
1111 switch (info->query_hw_ip.type) {
1112 case AMDGPU_HW_IP_UVD:
1113 /* Starting Polaris, we support unlimited UVD handles */
1114 if (adev->asic_type < CHIP_POLARIS10) {
1115 handle.uvd_max_handles = adev->uvd.max_handles;
1116 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
1117
1118 return copy_to_user(out, &handle,
1119 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
1120 } else {
1121 return -ENODATA;
1122 }
1123
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128 }
1129 case AMDGPU_INFO_SENSOR: {
1130 if (!adev->pm.dpm_enabled)
1131 return -ENOENT;
1132
1133 switch (info->sensor_info.type) {
1134 case AMDGPU_INFO_SENSOR_GFX_SCLK:
1135 /* get sclk in Mhz */
1136 if (amdgpu_dpm_read_sensor(adev,
1137 AMDGPU_PP_SENSOR_GFX_SCLK,
1138 (void *)&ui32, &ui32_size)) {
1139 return -EINVAL;
1140 }
1141 ui32 /= 100;
1142 break;
1143 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1144 /* get mclk in Mhz */
1145 if (amdgpu_dpm_read_sensor(adev,
1146 AMDGPU_PP_SENSOR_GFX_MCLK,
1147 (void *)&ui32, &ui32_size)) {
1148 return -EINVAL;
1149 }
1150 ui32 /= 100;
1151 break;
1152 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1153 /* get temperature in millidegrees C */
1154 if (amdgpu_dpm_read_sensor(adev,
1155 AMDGPU_PP_SENSOR_GPU_TEMP,
1156 (void *)&ui32, &ui32_size)) {
1157 return -EINVAL;
1158 }
1159 break;
1160 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1161 /* get GPU load */
1162 if (amdgpu_dpm_read_sensor(adev,
1163 AMDGPU_PP_SENSOR_GPU_LOAD,
1164 (void *)&ui32, &ui32_size)) {
1165 return -EINVAL;
1166 }
1167 break;
1168 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1169 /* get average GPU power */
1170 if (amdgpu_dpm_read_sensor(adev,
1171 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1172 (void *)&ui32, &ui32_size)) {
1173 /* fall back to input power for backwards compat */
1174 if (amdgpu_dpm_read_sensor(adev,
1175 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1176 (void *)&ui32, &ui32_size)) {
1177 return -EINVAL;
1178 }
1179 }
1180 ui32 >>= 8;
1181 break;
1182 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER:
1183 /* get input GPU power */
1184 if (amdgpu_dpm_read_sensor(adev,
1185 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1186 (void *)&ui32, &ui32_size)) {
1187 return -EINVAL;
1188 }
1189 ui32 >>= 8;
1190 break;
1191 case AMDGPU_INFO_SENSOR_VDDNB:
1192 /* get VDDNB in millivolts */
1193 if (amdgpu_dpm_read_sensor(adev,
1194 AMDGPU_PP_SENSOR_VDDNB,
1195 (void *)&ui32, &ui32_size)) {
1196 return -EINVAL;
1197 }
1198 break;
1199 case AMDGPU_INFO_SENSOR_VDDGFX:
1200 /* get VDDGFX in millivolts */
1201 if (amdgpu_dpm_read_sensor(adev,
1202 AMDGPU_PP_SENSOR_VDDGFX,
1203 (void *)&ui32, &ui32_size)) {
1204 return -EINVAL;
1205 }
1206 break;
1207 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1208 /* get stable pstate sclk in Mhz */
1209 if (amdgpu_dpm_read_sensor(adev,
1210 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1211 (void *)&ui32, &ui32_size)) {
1212 return -EINVAL;
1213 }
1214 ui32 /= 100;
1215 break;
1216 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1217 /* get stable pstate mclk in Mhz */
1218 if (amdgpu_dpm_read_sensor(adev,
1219 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1220 (void *)&ui32, &ui32_size)) {
1221 return -EINVAL;
1222 }
1223 ui32 /= 100;
1224 break;
1225 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1226 /* get peak pstate sclk in Mhz */
1227 if (amdgpu_dpm_read_sensor(adev,
1228 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1229 (void *)&ui32, &ui32_size)) {
1230 return -EINVAL;
1231 }
1232 ui32 /= 100;
1233 break;
1234 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1235 /* get peak pstate mclk in Mhz */
1236 if (amdgpu_dpm_read_sensor(adev,
1237 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1238 (void *)&ui32, &ui32_size)) {
1239 return -EINVAL;
1240 }
1241 ui32 /= 100;
1242 break;
1243 default:
1244 DRM_DEBUG_KMS("Invalid request %d\n",
1245 info->sensor_info.type);
1246 return -EINVAL;
1247 }
1248 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1249 }
1250 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1251 ui32 = atomic_read(&adev->vram_lost_counter);
1252 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1253 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1254 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1255 uint64_t ras_mask;
1256
1257 if (!ras)
1258 return -EINVAL;
1259 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1260
1261 return copy_to_user(out, &ras_mask,
1262 min_t(u64, size, sizeof(ras_mask))) ?
1263 -EFAULT : 0;
1264 }
1265 case AMDGPU_INFO_VIDEO_CAPS: {
1266 const struct amdgpu_video_codecs *codecs;
1267 struct drm_amdgpu_info_video_caps *caps;
1268 int r;
1269
1270 if (!adev->asic_funcs->query_video_codecs)
1271 return -EINVAL;
1272
1273 switch (info->video_cap.type) {
1274 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1275 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1276 if (r)
1277 return -EINVAL;
1278 break;
1279 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1280 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1281 if (r)
1282 return -EINVAL;
1283 break;
1284 default:
1285 DRM_DEBUG_KMS("Invalid request %d\n",
1286 info->video_cap.type);
1287 return -EINVAL;
1288 }
1289
1290 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1291 if (!caps)
1292 return -ENOMEM;
1293
1294 for (i = 0; i < codecs->codec_count; i++) {
1295 int idx = codecs->codec_array[i].codec_type;
1296
1297 switch (idx) {
1298 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1299 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1300 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1301 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1302 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1303 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1304 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1305 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1306 caps->codec_info[idx].valid = 1;
1307 caps->codec_info[idx].max_width =
1308 codecs->codec_array[i].max_width;
1309 caps->codec_info[idx].max_height =
1310 codecs->codec_array[i].max_height;
1311 caps->codec_info[idx].max_pixels_per_frame =
1312 codecs->codec_array[i].max_pixels_per_frame;
1313 caps->codec_info[idx].max_level =
1314 codecs->codec_array[i].max_level;
1315 break;
1316 default:
1317 break;
1318 }
1319 }
1320 r = copy_to_user(out, caps,
1321 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1322 kfree(caps);
1323 return r;
1324 }
1325 case AMDGPU_INFO_MAX_IBS: {
1326 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1327
1328 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1329 max_ibs[i] = amdgpu_ring_max_ibs(i);
1330
1331 return copy_to_user(out, max_ibs,
1332 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1333 }
1334 case AMDGPU_INFO_GPUVM_FAULT: {
1335 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1336 struct amdgpu_vm *vm = &fpriv->vm;
1337 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault;
1338 unsigned long flags;
1339
1340 if (!vm)
1341 return -EINVAL;
1342
1343 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault));
1344
1345 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
1346 gpuvm_fault.addr = vm->fault_info.addr;
1347 gpuvm_fault.status = vm->fault_info.status;
1348 gpuvm_fault.vmhub = vm->fault_info.vmhub;
1349 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
1350
1351 return copy_to_user(out, &gpuvm_fault,
1352 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
1353 }
1354 case AMDGPU_INFO_UQ_FW_AREAS: {
1355 struct drm_amdgpu_info_uq_metadata meta_info = {};
1356
1357 switch (info->query_hw_ip.type) {
1358 case AMDGPU_HW_IP_GFX:
1359 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx);
1360 if (ret)
1361 return ret;
1362
1363 ret = copy_to_user(out, &meta_info,
1364 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0;
1365 return 0;
1366 default:
1367 return -EINVAL;
1368 }
1369 }
1370 default:
1371 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1372 return -EINVAL;
1373 }
1374 return 0;
1375 }
1376
1377 /**
1378 * amdgpu_driver_open_kms - drm callback for open
1379 *
1380 * @dev: drm dev pointer
1381 * @file_priv: drm file
1382 *
1383 * On device open, init vm on cayman+ (all asics).
1384 * Returns 0 on success, error on failure.
1385 */
amdgpu_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)1386 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1387 {
1388 struct amdgpu_device *adev = drm_to_adev(dev);
1389 struct amdgpu_fpriv *fpriv;
1390 int r, pasid;
1391
1392 /* Ensure IB tests are run on ring */
1393 flush_delayed_work(&adev->delayed_init_work);
1394
1395
1396 if (amdgpu_ras_intr_triggered()) {
1397 DRM_ERROR("RAS Intr triggered, device disabled!!");
1398 return -EHWPOISON;
1399 }
1400
1401 file_priv->driver_priv = NULL;
1402
1403 r = pm_runtime_get_sync(dev->dev);
1404 if (r < 0)
1405 goto pm_put;
1406
1407 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1408 if (unlikely(!fpriv)) {
1409 r = -ENOMEM;
1410 goto out_suspend;
1411 }
1412
1413 pasid = amdgpu_pasid_alloc(16);
1414 if (pasid < 0) {
1415 dev_warn(adev->dev, "No more PASIDs available!");
1416 pasid = 0;
1417 }
1418
1419 r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1420 if (r)
1421 goto error_pasid;
1422
1423 amdgpu_debugfs_vm_init(file_priv);
1424
1425 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id, pasid);
1426 if (r)
1427 goto error_pasid;
1428
1429 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1430 if (!fpriv->prt_va) {
1431 r = -ENOMEM;
1432 goto error_vm;
1433 }
1434
1435 if (adev->gfx.mcbp) {
1436 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1437
1438 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1439 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1440 if (r)
1441 goto error_vm;
1442 }
1443
1444 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va);
1445 if (r)
1446 goto error_vm;
1447
1448 mutex_init(&fpriv->bo_list_lock);
1449 idr_init_base(&fpriv->bo_list_handles, 1);
1450
1451 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev);
1452 if (r)
1453 DRM_WARN("Can't setup usermode queues, use legacy workload submission only\n");
1454
1455 r = amdgpu_eviction_fence_init(&fpriv->evf_mgr);
1456 if (r)
1457 goto error_vm;
1458
1459 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1460
1461 file_priv->driver_priv = fpriv;
1462 goto out_suspend;
1463
1464 error_vm:
1465 amdgpu_vm_fini(adev, &fpriv->vm);
1466
1467 error_pasid:
1468 if (pasid)
1469 amdgpu_pasid_free(pasid);
1470
1471 kfree(fpriv);
1472
1473 out_suspend:
1474 pm_runtime_mark_last_busy(dev->dev);
1475 pm_put:
1476 pm_runtime_put_autosuspend(dev->dev);
1477
1478 return r;
1479 }
1480
1481 /**
1482 * amdgpu_driver_postclose_kms - drm callback for post close
1483 *
1484 * @dev: drm dev pointer
1485 * @file_priv: drm file
1486 *
1487 * On device post close, tear down vm on cayman+ (all asics).
1488 */
amdgpu_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)1489 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1490 struct drm_file *file_priv)
1491 {
1492 struct amdgpu_device *adev = drm_to_adev(dev);
1493 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1494 struct amdgpu_bo_list *list;
1495 struct amdgpu_bo *pd;
1496 u32 pasid;
1497 int handle;
1498
1499 if (!fpriv)
1500 return;
1501
1502 pm_runtime_get_sync(dev->dev);
1503
1504 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1505 amdgpu_uvd_free_handles(adev, file_priv);
1506 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1507 amdgpu_vce_free_handles(adev, file_priv);
1508
1509 if (fpriv->csa_va) {
1510 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1511
1512 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1513 fpriv->csa_va, csa_addr));
1514 fpriv->csa_va = NULL;
1515 }
1516
1517 amdgpu_seq64_unmap(adev, fpriv);
1518
1519 pasid = fpriv->vm.pasid;
1520 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1521 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1522 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1523 amdgpu_bo_unreserve(pd);
1524 }
1525
1526 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1527 amdgpu_vm_fini(adev, &fpriv->vm);
1528
1529 if (pasid)
1530 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1531 amdgpu_bo_unref(&pd);
1532
1533 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1534 amdgpu_bo_list_put(list);
1535
1536 idr_destroy(&fpriv->bo_list_handles);
1537 mutex_destroy(&fpriv->bo_list_lock);
1538
1539 kfree(fpriv);
1540 file_priv->driver_priv = NULL;
1541
1542 pm_runtime_mark_last_busy(dev->dev);
1543 pm_runtime_put_autosuspend(dev->dev);
1544 }
1545
1546
amdgpu_driver_release_kms(struct drm_device * dev)1547 void amdgpu_driver_release_kms(struct drm_device *dev)
1548 {
1549 struct amdgpu_device *adev = drm_to_adev(dev);
1550
1551 amdgpu_device_fini_sw(adev);
1552 pci_set_drvdata(adev->pdev, NULL);
1553 }
1554
1555 /*
1556 * VBlank related functions.
1557 */
1558 /**
1559 * amdgpu_get_vblank_counter_kms - get frame count
1560 *
1561 * @crtc: crtc to get the frame count from
1562 *
1563 * Gets the frame count on the requested crtc (all asics).
1564 * Returns frame count on success, -EINVAL on failure.
1565 */
amdgpu_get_vblank_counter_kms(struct drm_crtc * crtc)1566 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1567 {
1568 struct drm_device *dev = crtc->dev;
1569 unsigned int pipe = crtc->index;
1570 struct amdgpu_device *adev = drm_to_adev(dev);
1571 int vpos, hpos, stat;
1572 u32 count;
1573
1574 if (pipe >= adev->mode_info.num_crtc) {
1575 DRM_ERROR("Invalid crtc %u\n", pipe);
1576 return -EINVAL;
1577 }
1578
1579 /* The hw increments its frame counter at start of vsync, not at start
1580 * of vblank, as is required by DRM core vblank counter handling.
1581 * Cook the hw count here to make it appear to the caller as if it
1582 * incremented at start of vblank. We measure distance to start of
1583 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1584 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1585 * result by 1 to give the proper appearance to caller.
1586 */
1587 if (adev->mode_info.crtcs[pipe]) {
1588 /* Repeat readout if needed to provide stable result if
1589 * we cross start of vsync during the queries.
1590 */
1591 do {
1592 count = amdgpu_display_vblank_get_counter(adev, pipe);
1593 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1594 * vpos as distance to start of vblank, instead of
1595 * regular vertical scanout pos.
1596 */
1597 stat = amdgpu_display_get_crtc_scanoutpos(
1598 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1599 &vpos, &hpos, NULL, NULL,
1600 &adev->mode_info.crtcs[pipe]->base.hwmode);
1601 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1602
1603 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1604 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1605 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1606 } else {
1607 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1608 pipe, vpos);
1609
1610 /* Bump counter if we are at >= leading edge of vblank,
1611 * but before vsync where vpos would turn negative and
1612 * the hw counter really increments.
1613 */
1614 if (vpos >= 0)
1615 count++;
1616 }
1617 } else {
1618 /* Fallback to use value as is. */
1619 count = amdgpu_display_vblank_get_counter(adev, pipe);
1620 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1621 }
1622
1623 return count;
1624 }
1625
1626 /**
1627 * amdgpu_enable_vblank_kms - enable vblank interrupt
1628 *
1629 * @crtc: crtc to enable vblank interrupt for
1630 *
1631 * Enable the interrupt on the requested crtc (all asics).
1632 * Returns 0 on success, -EINVAL on failure.
1633 */
amdgpu_enable_vblank_kms(struct drm_crtc * crtc)1634 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1635 {
1636 struct drm_device *dev = crtc->dev;
1637 unsigned int pipe = crtc->index;
1638 struct amdgpu_device *adev = drm_to_adev(dev);
1639 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1640
1641 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1642 }
1643
1644 /**
1645 * amdgpu_disable_vblank_kms - disable vblank interrupt
1646 *
1647 * @crtc: crtc to disable vblank interrupt for
1648 *
1649 * Disable the interrupt on the requested crtc (all asics).
1650 */
amdgpu_disable_vblank_kms(struct drm_crtc * crtc)1651 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1652 {
1653 struct drm_device *dev = crtc->dev;
1654 unsigned int pipe = crtc->index;
1655 struct amdgpu_device *adev = drm_to_adev(dev);
1656 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1657
1658 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1659 }
1660
1661 /*
1662 * Debugfs info
1663 */
1664 #if defined(CONFIG_DEBUG_FS)
1665
amdgpu_debugfs_firmware_info_show(struct seq_file * m,void * unused)1666 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1667 {
1668 struct amdgpu_device *adev = m->private;
1669 struct drm_amdgpu_info_firmware fw_info;
1670 struct drm_amdgpu_query_fw query_fw;
1671 struct atom_context *ctx = adev->mode_info.atom_context;
1672 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1673 int ret, i;
1674
1675 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1676 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1677 TA_FW_NAME(XGMI),
1678 TA_FW_NAME(RAS),
1679 TA_FW_NAME(HDCP),
1680 TA_FW_NAME(DTM),
1681 TA_FW_NAME(RAP),
1682 TA_FW_NAME(SECUREDISPLAY),
1683 #undef TA_FW_NAME
1684 };
1685
1686 /* VCE */
1687 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1688 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1689 if (ret)
1690 return ret;
1691 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1692 fw_info.feature, fw_info.ver);
1693
1694 /* UVD */
1695 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1696 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1697 if (ret)
1698 return ret;
1699 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1700 fw_info.feature, fw_info.ver);
1701
1702 /* GMC */
1703 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1704 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1705 if (ret)
1706 return ret;
1707 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1708 fw_info.feature, fw_info.ver);
1709
1710 /* ME */
1711 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1712 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1713 if (ret)
1714 return ret;
1715 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1716 fw_info.feature, fw_info.ver);
1717
1718 /* PFP */
1719 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1720 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1721 if (ret)
1722 return ret;
1723 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1724 fw_info.feature, fw_info.ver);
1725
1726 /* CE */
1727 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1728 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1729 if (ret)
1730 return ret;
1731 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1732 fw_info.feature, fw_info.ver);
1733
1734 /* RLC */
1735 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1736 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1737 if (ret)
1738 return ret;
1739 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1740 fw_info.feature, fw_info.ver);
1741
1742 /* RLC SAVE RESTORE LIST CNTL */
1743 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1744 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1745 if (ret)
1746 return ret;
1747 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1748 fw_info.feature, fw_info.ver);
1749
1750 /* RLC SAVE RESTORE LIST GPM MEM */
1751 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1752 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1753 if (ret)
1754 return ret;
1755 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1756 fw_info.feature, fw_info.ver);
1757
1758 /* RLC SAVE RESTORE LIST SRM MEM */
1759 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1760 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1761 if (ret)
1762 return ret;
1763 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1764 fw_info.feature, fw_info.ver);
1765
1766 /* RLCP */
1767 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1768 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1769 if (ret)
1770 return ret;
1771 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1772 fw_info.feature, fw_info.ver);
1773
1774 /* RLCV */
1775 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1776 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1777 if (ret)
1778 return ret;
1779 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1780 fw_info.feature, fw_info.ver);
1781
1782 /* MEC */
1783 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1784 query_fw.index = 0;
1785 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1786 if (ret)
1787 return ret;
1788 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1789 fw_info.feature, fw_info.ver);
1790
1791 /* MEC2 */
1792 if (adev->gfx.mec2_fw) {
1793 query_fw.index = 1;
1794 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1795 if (ret)
1796 return ret;
1797 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1798 fw_info.feature, fw_info.ver);
1799 }
1800
1801 /* IMU */
1802 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1803 query_fw.index = 0;
1804 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1805 if (ret)
1806 return ret;
1807 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1808 fw_info.feature, fw_info.ver);
1809
1810 /* PSP SOS */
1811 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1812 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1813 if (ret)
1814 return ret;
1815 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1816 fw_info.feature, fw_info.ver);
1817
1818
1819 /* PSP ASD */
1820 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1821 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1822 if (ret)
1823 return ret;
1824 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1825 fw_info.feature, fw_info.ver);
1826
1827 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1828 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1829 query_fw.index = i;
1830 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1831 if (ret)
1832 continue;
1833
1834 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1835 ta_fw_name[i], fw_info.feature, fw_info.ver);
1836 }
1837
1838 /* SMC */
1839 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1840 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1841 if (ret)
1842 return ret;
1843 smu_program = (fw_info.ver >> 24) & 0xff;
1844 smu_major = (fw_info.ver >> 16) & 0xff;
1845 smu_minor = (fw_info.ver >> 8) & 0xff;
1846 smu_debug = (fw_info.ver >> 0) & 0xff;
1847 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1848 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1849
1850 /* SDMA */
1851 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1852 for (i = 0; i < adev->sdma.num_instances; i++) {
1853 query_fw.index = i;
1854 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1855 if (ret)
1856 return ret;
1857 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1858 i, fw_info.feature, fw_info.ver);
1859 }
1860
1861 /* VCN */
1862 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1863 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1864 if (ret)
1865 return ret;
1866 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1867 fw_info.feature, fw_info.ver);
1868
1869 /* DMCU */
1870 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1871 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1872 if (ret)
1873 return ret;
1874 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1875 fw_info.feature, fw_info.ver);
1876
1877 /* DMCUB */
1878 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1879 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1880 if (ret)
1881 return ret;
1882 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1883 fw_info.feature, fw_info.ver);
1884
1885 /* TOC */
1886 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1887 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1888 if (ret)
1889 return ret;
1890 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1891 fw_info.feature, fw_info.ver);
1892
1893 /* CAP */
1894 if (adev->psp.cap_fw) {
1895 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1896 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1897 if (ret)
1898 return ret;
1899 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1900 fw_info.feature, fw_info.ver);
1901 }
1902
1903 /* MES_KIQ */
1904 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1905 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1906 if (ret)
1907 return ret;
1908 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1909 fw_info.feature, fw_info.ver);
1910
1911 /* MES */
1912 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1913 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1914 if (ret)
1915 return ret;
1916 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1917 fw_info.feature, fw_info.ver);
1918
1919 /* VPE */
1920 query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1921 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1922 if (ret)
1923 return ret;
1924 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1925 fw_info.feature, fw_info.ver);
1926
1927 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1928
1929 return 0;
1930 }
1931
1932 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1933
1934 #endif
1935
amdgpu_debugfs_firmware_init(struct amdgpu_device * adev)1936 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1937 {
1938 #if defined(CONFIG_DEBUG_FS)
1939 struct drm_minor *minor = adev_to_drm(adev)->primary;
1940 struct dentry *root = minor->debugfs_root;
1941
1942 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1943 adev, &amdgpu_debugfs_firmware_info_fops);
1944
1945 #endif
1946 }
1947