1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin (yanmin.zhang@intel.com) 12 * Shaohua Li (shaohua.li@intel.com) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 #include <linux/args.h> 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <linux/msi_api.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54 #define PCI_NUM_RESET_METHODS 8 55 56 #define PCI_RESET_PROBE true 57 #define PCI_RESET_DO_RESET false 58 59 /* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75 /* pci_slot represents a physical slot */ 76 struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82 }; 83 84 static inline const char *pci_slot_name(const struct pci_slot *slot) 85 { 86 return kobject_name(&slot->kobj); 87 } 88 89 /* File state for mmap()s on /proc/bus/pci/X/Y */ 90 enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93 }; 94 95 /* For PCI devices, the region numbers are assigned this way: */ 96 enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105 #ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108 #endif 109 110 /* PCI-to-PCI (P2P) bridge windows */ 111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115 /* CardBus bridge windows */ 116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121 /* Total number of bridge resources for P2P and CardBus */ 122 #define PCI_BRIDGE_RESOURCE_NUM 4 123 124 /* Resources assigned to buses behind the bridge */ 125 PCI_BRIDGE_RESOURCES, 126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 127 PCI_BRIDGE_RESOURCE_NUM - 1, 128 129 /* Total resources associated with a PCI device */ 130 PCI_NUM_RESOURCES, 131 132 /* Preserve this for compatibility */ 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 134 }; 135 136 /** 137 * enum pci_interrupt_pin - PCI INTx interrupt values 138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 139 * @PCI_INTERRUPT_INTA: PCI INTA pin 140 * @PCI_INTERRUPT_INTB: PCI INTB pin 141 * @PCI_INTERRUPT_INTC: PCI INTC pin 142 * @PCI_INTERRUPT_INTD: PCI INTD pin 143 * 144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 145 * PCI_INTERRUPT_PIN register. 146 */ 147 enum pci_interrupt_pin { 148 PCI_INTERRUPT_UNKNOWN, 149 PCI_INTERRUPT_INTA, 150 PCI_INTERRUPT_INTB, 151 PCI_INTERRUPT_INTC, 152 PCI_INTERRUPT_INTD, 153 }; 154 155 /* The number of legacy PCI INTx interrupts */ 156 #define PCI_NUM_INTX 4 157 158 /* 159 * Reading from a device that doesn't respond typically returns ~0. A 160 * successful read from a device may also return ~0, so you need additional 161 * information to reliably identify errors. 162 */ 163 #define PCI_ERROR_RESPONSE (~0ULL) 164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 166 167 /* 168 * pci_power_t values must match the bits in the Capabilities PME_Support 169 * and Control/Status PowerState fields in the Power Management capability. 170 */ 171 typedef int __bitwise pci_power_t; 172 173 #define PCI_D0 ((pci_power_t __force) 0) 174 #define PCI_D1 ((pci_power_t __force) 1) 175 #define PCI_D2 ((pci_power_t __force) 2) 176 #define PCI_D3hot ((pci_power_t __force) 3) 177 #define PCI_D3cold ((pci_power_t __force) 4) 178 #define PCI_UNKNOWN ((pci_power_t __force) 5) 179 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 180 181 /* Remember to update this when the list above changes! */ 182 extern const char *pci_power_names[]; 183 184 static inline const char *pci_power_name(pci_power_t state) 185 { 186 return pci_power_names[1 + (__force int) state]; 187 } 188 189 /** 190 * typedef pci_channel_state_t 191 * 192 * The pci_channel state describes connectivity between the CPU and 193 * the PCI device. If some PCI bus between here and the PCI device 194 * has crashed or locked up, this info is reflected here. 195 */ 196 typedef unsigned int __bitwise pci_channel_state_t; 197 198 enum { 199 /* I/O channel is in normal state */ 200 pci_channel_io_normal = (__force pci_channel_state_t) 1, 201 202 /* I/O to channel is blocked */ 203 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 204 205 /* PCI card is dead */ 206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 207 }; 208 209 typedef unsigned int __bitwise pcie_reset_state_t; 210 211 enum pcie_reset_state { 212 /* Reset is NOT asserted (Use to deassert reset) */ 213 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 214 215 /* Use #PERST to reset PCIe device */ 216 pcie_warm_reset = (__force pcie_reset_state_t) 2, 217 218 /* Use PCIe Hot Reset to reset device */ 219 pcie_hot_reset = (__force pcie_reset_state_t) 3 220 }; 221 222 typedef unsigned short __bitwise pci_dev_flags_t; 223 enum pci_dev_flags { 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 226 /* Device configuration is irrevocably lost if disabled into D3 */ 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 228 /* Provide indication device is assigned by a Virtual Machine Manager */ 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 234 /* Do not use bus resets for device */ 235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 236 /* Do not use PM reset even if device advertises NoSoftRst- */ 237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 238 /* Get VPD from function 0 VPD */ 239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 240 /* A non-root bridge where translation occurs, stop alias search here */ 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 242 /* Do not use FLR even if device advertises PCI_AF_CAP */ 243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 244 /* Don't use Relaxed Ordering for TLPs directed at this device */ 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 246 /* Device does honor MSI masking despite saying otherwise */ 247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 248 }; 249 250 enum pci_irq_reroute_variant { 251 INTEL_IRQ_REROUTE_VARIANT = 1, 252 MAX_IRQ_REROUTE_VARIANTS = 3 253 }; 254 255 typedef unsigned short __bitwise pci_bus_flags_t; 256 enum pci_bus_flags { 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 261 }; 262 263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 264 enum pcie_link_width { 265 PCIE_LNK_WIDTH_RESRV = 0x00, 266 PCIE_LNK_X1 = 0x01, 267 PCIE_LNK_X2 = 0x02, 268 PCIE_LNK_X4 = 0x04, 269 PCIE_LNK_X8 = 0x08, 270 PCIE_LNK_X12 = 0x0c, 271 PCIE_LNK_X16 = 0x10, 272 PCIE_LNK_X32 = 0x20, 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 274 }; 275 276 /* See matching string table in pci_speed_string() */ 277 enum pci_bus_speed { 278 PCI_SPEED_33MHz = 0x00, 279 PCI_SPEED_66MHz = 0x01, 280 PCI_SPEED_66MHz_PCIX = 0x02, 281 PCI_SPEED_100MHz_PCIX = 0x03, 282 PCI_SPEED_133MHz_PCIX = 0x04, 283 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 284 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 285 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 286 PCI_SPEED_66MHz_PCIX_266 = 0x09, 287 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 288 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 289 AGP_UNKNOWN = 0x0c, 290 AGP_1X = 0x0d, 291 AGP_2X = 0x0e, 292 AGP_4X = 0x0f, 293 AGP_8X = 0x10, 294 PCI_SPEED_66MHz_PCIX_533 = 0x11, 295 PCI_SPEED_100MHz_PCIX_533 = 0x12, 296 PCI_SPEED_133MHz_PCIX_533 = 0x13, 297 PCIE_SPEED_2_5GT = 0x14, 298 PCIE_SPEED_5_0GT = 0x15, 299 PCIE_SPEED_8_0GT = 0x16, 300 PCIE_SPEED_16_0GT = 0x17, 301 PCIE_SPEED_32_0GT = 0x18, 302 PCIE_SPEED_64_0GT = 0x19, 303 PCI_SPEED_UNKNOWN = 0xff, 304 }; 305 306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 308 309 struct pci_vpd { 310 struct mutex lock; 311 unsigned int len; 312 u8 cap; 313 }; 314 315 struct irq_affinity; 316 struct pcie_link_state; 317 struct pci_sriov; 318 struct pci_p2pdma; 319 struct rcec_ea; 320 321 /* The pci_dev structure describes PCI devices */ 322 struct pci_dev { 323 struct list_head bus_list; /* Node in per-bus list */ 324 struct pci_bus *bus; /* Bus this device is on */ 325 struct pci_bus *subordinate; /* Bus this device bridges to */ 326 327 void *sysdata; /* Hook for sys-specific extension */ 328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 329 struct pci_slot *slot; /* Physical slot this device is in */ 330 331 unsigned int devfn; /* Encoded device & function index */ 332 unsigned short vendor; 333 unsigned short device; 334 unsigned short subsystem_vendor; 335 unsigned short subsystem_device; 336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 337 u8 revision; /* PCI revision, low byte of class word */ 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 339 #ifdef CONFIG_PCIEAER 340 u16 aer_cap; /* AER capability offset */ 341 struct aer_stats *aer_stats; /* AER stats for this device */ 342 #endif 343 #ifdef CONFIG_PCIEPORTBUS 344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 345 struct pci_dev *rcec; /* Associated RCEC device */ 346 #endif 347 u32 devcap; /* PCIe Device Capabilities */ 348 u8 pcie_cap; /* PCIe capability offset */ 349 u8 msi_cap; /* MSI capability offset */ 350 u8 msix_cap; /* MSI-X capability offset */ 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 352 u8 rom_base_reg; /* Config register controlling ROM */ 353 u8 pin; /* Interrupt pin this device uses */ 354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 356 357 struct pci_driver *driver; /* Driver bound to this device */ 358 u64 dma_mask; /* Mask of the bits of bus address this 359 device implements. Normally this is 360 0xffffffff. You only need to change 361 this if your device has broken DMA 362 or supports 64-bit transfers. */ 363 364 struct device_dma_parameters dma_parms; 365 366 pci_power_t current_state; /* Current operating state. In ACPI, 367 this is D0-D3, D0 being fully 368 functional, and D3 being off. */ 369 u8 pm_cap; /* PM capability offset */ 370 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 371 unsigned int pme_support:5; /* Bitmask of states from which PME# 372 can be generated */ 373 unsigned int pme_poll:1; /* Poll device's PME status bit */ 374 unsigned int d1_support:1; /* Low power state D1 is supported */ 375 unsigned int d2_support:1; /* Low power state D2 is supported */ 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 377 unsigned int no_d3cold:1; /* D3cold is forbidden */ 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 381 decoding during BAR sizing */ 382 unsigned int wakeup_prepared:1; 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 386 controlled exclusively by 387 user sysfs */ 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 389 bit manually */ 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 392 393 u16 l1ss; /* L1SS Capability pointer */ 394 #ifdef CONFIG_PCIEASPM 395 struct pcie_link_state *link_state; /* ASPM link state */ 396 unsigned int ltr_path:1; /* Latency Tolerance Reporting 397 supported from root to here */ 398 #endif 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 401 402 pci_channel_state_t error_state; /* Current connectivity state */ 403 struct device dev; /* Generic device interface */ 404 405 int cfg_size; /* Size of config space */ 406 407 /* 408 * Instead of touching interrupt line and base address registers 409 * directly, use the values stored here. They might be different! 410 */ 411 unsigned int irq; 412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 414 415 bool match_driver; /* Skip attaching driver */ 416 417 unsigned int transparent:1; /* Subtractive decode bridge */ 418 unsigned int io_window:1; /* Bridge has I/O window */ 419 unsigned int pref_window:1; /* Bridge has pref mem window */ 420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 421 unsigned int multifunction:1; /* Multi-function device */ 422 423 unsigned int is_busmaster:1; /* Is busmaster */ 424 unsigned int no_msi:1; /* May not use MSI */ 425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 426 unsigned int block_cfg_access:1; /* Config space access blocked */ 427 unsigned int broken_parity_status:1; /* Generates false positive parity */ 428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 429 unsigned int msi_enabled:1; 430 unsigned int msix_enabled:1; 431 unsigned int ari_enabled:1; /* ARI forwarding */ 432 unsigned int ats_enabled:1; /* Address Translation Svc */ 433 unsigned int pasid_enabled:1; /* Process Address Space ID */ 434 unsigned int pri_enabled:1; /* Page Request Interface */ 435 unsigned int is_managed:1; /* Managed via devres */ 436 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 437 unsigned int needs_freset:1; /* Requires fundamental reset */ 438 unsigned int state_saved:1; 439 unsigned int is_physfn:1; 440 unsigned int is_virtfn:1; 441 unsigned int is_hotplug_bridge:1; 442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 444 /* 445 * Devices marked being untrusted are the ones that can potentially 446 * execute DMA attacks and similar. They are typically connected 447 * through external ports such as Thunderbolt but not limited to 448 * that. When an IOMMU is enabled they should be getting full 449 * mappings to make sure they cannot access arbitrary memory. 450 */ 451 unsigned int untrusted:1; 452 /* 453 * Info from the platform, e.g., ACPI or device tree, may mark a 454 * device as "external-facing". An external-facing device is 455 * itself internal but devices downstream from it are external. 456 */ 457 unsigned int external_facing:1; 458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 460 unsigned int irq_managed:1; 461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 462 unsigned int is_probed:1; /* Device probing in progress */ 463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 467 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 468 pci_dev_flags_t dev_flags; 469 atomic_t enable_cnt; /* pci_enable_device has been called */ 470 471 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 472 u32 saved_config_space[16]; /* Config space saved at suspend time */ 473 struct hlist_head saved_cap_space; 474 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 475 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 476 477 #ifdef CONFIG_HOTPLUG_PCI_PCIE 478 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 479 #endif 480 #ifdef CONFIG_PCIE_PTM 481 u16 ptm_cap; /* PTM Capability */ 482 unsigned int ptm_root:1; 483 unsigned int ptm_enabled:1; 484 u8 ptm_granularity; 485 #endif 486 #ifdef CONFIG_PCI_MSI 487 void __iomem *msix_base; 488 raw_spinlock_t msi_lock; 489 #endif 490 struct pci_vpd vpd; 491 #ifdef CONFIG_PCIE_DPC 492 u16 dpc_cap; 493 unsigned int dpc_rp_extensions:1; 494 u8 dpc_rp_log_size; 495 #endif 496 #ifdef CONFIG_PCI_ATS 497 union { 498 struct pci_sriov *sriov; /* PF: SR-IOV info */ 499 struct pci_dev *physfn; /* VF: related PF */ 500 }; 501 u16 ats_cap; /* ATS Capability offset */ 502 u8 ats_stu; /* ATS Smallest Translation Unit */ 503 #endif 504 #ifdef CONFIG_PCI_PRI 505 u16 pri_cap; /* PRI Capability offset */ 506 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 507 unsigned int pasid_required:1; /* PRG Response PASID Required */ 508 #endif 509 #ifdef CONFIG_PCI_PASID 510 u16 pasid_cap; /* PASID Capability offset */ 511 u16 pasid_features; 512 #endif 513 #ifdef CONFIG_PCI_P2PDMA 514 struct pci_p2pdma __rcu *p2pdma; 515 #endif 516 #ifdef CONFIG_PCI_DOE 517 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 518 #endif 519 u16 acs_cap; /* ACS Capability offset */ 520 phys_addr_t rom; /* Physical address if not from BAR */ 521 size_t romlen; /* Length if not from BAR */ 522 /* 523 * Driver name to force a match. Do not set directly, because core 524 * frees it. Use driver_set_override() to set or clear it. 525 */ 526 const char *driver_override; 527 528 unsigned long priv_flags; /* Private flags for the PCI driver */ 529 530 /* These methods index pci_reset_fn_methods[] */ 531 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 532 }; 533 534 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 535 { 536 #ifdef CONFIG_PCI_IOV 537 if (dev->is_virtfn) 538 dev = dev->physfn; 539 #endif 540 return dev; 541 } 542 543 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 544 545 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 546 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 547 548 static inline int pci_channel_offline(struct pci_dev *pdev) 549 { 550 return (pdev->error_state != pci_channel_io_normal); 551 } 552 553 /* 554 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 555 * Group number is limited to a 16-bit value, therefore (int)-1 is 556 * not a valid PCI domain number, and can be used as a sentinel 557 * value indicating ->domain_nr is not set by the driver (and 558 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 559 * pci_bus_find_domain_nr()). 560 */ 561 #define PCI_DOMAIN_NR_NOT_SET (-1) 562 563 struct pci_host_bridge { 564 struct device dev; 565 struct pci_bus *bus; /* Root bus */ 566 struct pci_ops *ops; 567 struct pci_ops *child_ops; 568 void *sysdata; 569 int busnr; 570 int domain_nr; 571 struct list_head windows; /* resource_entry */ 572 struct list_head dma_ranges; /* dma ranges resource list */ 573 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 574 int (*map_irq)(const struct pci_dev *, u8, u8); 575 void (*release_fn)(struct pci_host_bridge *); 576 void *release_data; 577 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 578 unsigned int no_ext_tags:1; /* No Extended Tags */ 579 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 580 unsigned int native_aer:1; /* OS may use PCIe AER */ 581 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 582 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 583 unsigned int native_pme:1; /* OS may use PCIe PME */ 584 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 585 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 586 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 587 unsigned int preserve_config:1; /* Preserve FW resource setup */ 588 unsigned int size_windows:1; /* Enable root bus sizing */ 589 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 590 591 /* Resource alignment requirements */ 592 resource_size_t (*align_resource)(struct pci_dev *dev, 593 const struct resource *res, 594 resource_size_t start, 595 resource_size_t size, 596 resource_size_t align); 597 unsigned long private[] ____cacheline_aligned; 598 }; 599 600 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 601 602 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 603 { 604 return (void *)bridge->private; 605 } 606 607 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 608 { 609 return container_of(priv, struct pci_host_bridge, private); 610 } 611 612 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 613 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 614 size_t priv); 615 void pci_free_host_bridge(struct pci_host_bridge *bridge); 616 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 617 618 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 619 void (*release_fn)(struct pci_host_bridge *), 620 void *release_data); 621 622 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 623 624 /* 625 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 626 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 627 * buses below host bridges or subtractive decode bridges) go in the list. 628 * Use pci_bus_for_each_resource() to iterate through all the resources. 629 */ 630 631 /* 632 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 633 * and there's no way to program the bridge with the details of the window. 634 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 635 * decode bit set, because they are explicit and can be programmed with _SRS. 636 */ 637 #define PCI_SUBTRACTIVE_DECODE 0x1 638 639 struct pci_bus_resource { 640 struct list_head list; 641 struct resource *res; 642 unsigned int flags; 643 }; 644 645 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 646 647 struct pci_bus { 648 struct list_head node; /* Node in list of buses */ 649 struct pci_bus *parent; /* Parent bus this bridge is on */ 650 struct list_head children; /* List of child buses */ 651 struct list_head devices; /* List of devices on this bus */ 652 struct pci_dev *self; /* Bridge device as seen by parent */ 653 struct list_head slots; /* List of slots on this bus; 654 protected by pci_slot_mutex */ 655 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 656 struct list_head resources; /* Address space routed to this bus */ 657 struct resource busn_res; /* Bus numbers routed to this bus */ 658 659 struct pci_ops *ops; /* Configuration access functions */ 660 void *sysdata; /* Hook for sys-specific extension */ 661 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 662 663 unsigned char number; /* Bus number */ 664 unsigned char primary; /* Number of primary bridge */ 665 unsigned char max_bus_speed; /* enum pci_bus_speed */ 666 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 667 #ifdef CONFIG_PCI_DOMAINS_GENERIC 668 int domain_nr; 669 #endif 670 671 char name[48]; 672 673 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 674 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 675 struct device *bridge; 676 struct device dev; 677 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 678 struct bin_attribute *legacy_mem; /* Legacy mem */ 679 unsigned int is_added:1; 680 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 681 }; 682 683 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 684 685 static inline u16 pci_dev_id(struct pci_dev *dev) 686 { 687 return PCI_DEVID(dev->bus->number, dev->devfn); 688 } 689 690 /* 691 * Returns true if the PCI bus is root (behind host-PCI bridge), 692 * false otherwise 693 * 694 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 695 * This is incorrect because "virtual" buses added for SR-IOV (via 696 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 697 */ 698 static inline bool pci_is_root_bus(struct pci_bus *pbus) 699 { 700 return !(pbus->parent); 701 } 702 703 /** 704 * pci_is_bridge - check if the PCI device is a bridge 705 * @dev: PCI device 706 * 707 * Return true if the PCI device is bridge whether it has subordinate 708 * or not. 709 */ 710 static inline bool pci_is_bridge(struct pci_dev *dev) 711 { 712 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 713 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 714 } 715 716 /** 717 * pci_is_vga - check if the PCI device is a VGA device 718 * @pdev: PCI device 719 * 720 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 721 * VGA Base Class and Sub-Classes: 722 * 723 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 724 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 725 * 726 * Return true if the PCI device is a VGA device and uses the legacy VGA 727 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 728 * aliases). 729 */ 730 static inline bool pci_is_vga(struct pci_dev *pdev) 731 { 732 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 733 return true; 734 735 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 736 return true; 737 738 return false; 739 } 740 741 #define for_each_pci_bridge(dev, bus) \ 742 list_for_each_entry(dev, &bus->devices, bus_list) \ 743 if (!pci_is_bridge(dev)) {} else 744 745 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 746 { 747 dev = pci_physfn(dev); 748 if (pci_is_root_bus(dev->bus)) 749 return NULL; 750 751 return dev->bus->self; 752 } 753 754 #ifdef CONFIG_PCI_MSI 755 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 756 { 757 return pci_dev->msi_enabled || pci_dev->msix_enabled; 758 } 759 #else 760 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 761 #endif 762 763 /* Error values that may be returned by PCI functions */ 764 #define PCIBIOS_SUCCESSFUL 0x00 765 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 766 #define PCIBIOS_BAD_VENDOR_ID 0x83 767 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 768 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 769 #define PCIBIOS_SET_FAILED 0x88 770 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 771 772 /* Translate above to generic errno for passing back through non-PCI code */ 773 static inline int pcibios_err_to_errno(int err) 774 { 775 if (err <= PCIBIOS_SUCCESSFUL) 776 return err; /* Assume already errno */ 777 778 switch (err) { 779 case PCIBIOS_FUNC_NOT_SUPPORTED: 780 return -ENOENT; 781 case PCIBIOS_BAD_VENDOR_ID: 782 return -ENOTTY; 783 case PCIBIOS_DEVICE_NOT_FOUND: 784 return -ENODEV; 785 case PCIBIOS_BAD_REGISTER_NUMBER: 786 return -EFAULT; 787 case PCIBIOS_SET_FAILED: 788 return -EIO; 789 case PCIBIOS_BUFFER_TOO_SMALL: 790 return -ENOSPC; 791 } 792 793 return -ERANGE; 794 } 795 796 /* Low-level architecture-dependent routines */ 797 798 struct pci_ops { 799 int (*add_bus)(struct pci_bus *bus); 800 void (*remove_bus)(struct pci_bus *bus); 801 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 802 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 803 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 804 }; 805 806 /* 807 * ACPI needs to be able to access PCI config space before we've done a 808 * PCI bus scan and created pci_bus structures. 809 */ 810 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 811 int reg, int len, u32 *val); 812 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 813 int reg, int len, u32 val); 814 815 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 816 typedef u64 pci_bus_addr_t; 817 #else 818 typedef u32 pci_bus_addr_t; 819 #endif 820 821 struct pci_bus_region { 822 pci_bus_addr_t start; 823 pci_bus_addr_t end; 824 }; 825 826 struct pci_dynids { 827 spinlock_t lock; /* Protects list, index */ 828 struct list_head list; /* For IDs added at runtime */ 829 }; 830 831 832 /* 833 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 834 * a set of callbacks in struct pci_error_handlers, that device driver 835 * will be notified of PCI bus errors, and will be driven to recovery 836 * when an error occurs. 837 */ 838 839 typedef unsigned int __bitwise pci_ers_result_t; 840 841 enum pci_ers_result { 842 /* No result/none/not supported in device driver */ 843 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 844 845 /* Device driver can recover without slot reset */ 846 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 847 848 /* Device driver wants slot to be reset */ 849 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 850 851 /* Device has completely failed, is unrecoverable */ 852 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 853 854 /* Device driver is fully recovered and operational */ 855 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 856 857 /* No AER capabilities registered for the driver */ 858 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 859 }; 860 861 /* PCI bus error event callbacks */ 862 struct pci_error_handlers { 863 /* PCI bus error detected on this device */ 864 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 865 pci_channel_state_t error); 866 867 /* MMIO has been re-enabled, but not DMA */ 868 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 869 870 /* PCI slot has been reset */ 871 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 872 873 /* PCI function reset prepare or completed */ 874 void (*reset_prepare)(struct pci_dev *dev); 875 void (*reset_done)(struct pci_dev *dev); 876 877 /* Device driver may resume normal operations */ 878 void (*resume)(struct pci_dev *dev); 879 880 /* Allow device driver to record more details of a correctable error */ 881 void (*cor_error_detected)(struct pci_dev *dev); 882 }; 883 884 885 struct module; 886 887 /** 888 * struct pci_driver - PCI driver structure 889 * @name: Driver name. 890 * @id_table: Pointer to table of device IDs the driver is 891 * interested in. Most drivers should export this 892 * table using MODULE_DEVICE_TABLE(pci,...). 893 * @probe: This probing function gets called (during execution 894 * of pci_register_driver() for already existing 895 * devices or later if a new device gets inserted) for 896 * all PCI devices which match the ID table and are not 897 * "owned" by the other drivers yet. This function gets 898 * passed a "struct pci_dev \*" for each device whose 899 * entry in the ID table matches the device. The probe 900 * function returns zero when the driver chooses to 901 * take "ownership" of the device or an error code 902 * (negative number) otherwise. 903 * The probe function always gets called from process 904 * context, so it can sleep. 905 * @remove: The remove() function gets called whenever a device 906 * being handled by this driver is removed (either during 907 * deregistration of the driver or when it's manually 908 * pulled out of a hot-pluggable slot). 909 * The remove function always gets called from process 910 * context, so it can sleep. 911 * @suspend: Put device into low power state. 912 * @resume: Wake device from low power state. 913 * (Please see Documentation/power/pci.rst for descriptions 914 * of PCI Power Management and the related functions.) 915 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 916 * Intended to stop any idling DMA operations. 917 * Useful for enabling wake-on-lan (NIC) or changing 918 * the power state of a device before reboot. 919 * e.g. drivers/net/e100.c. 920 * @sriov_configure: Optional driver callback to allow configuration of 921 * number of VFs to enable via sysfs "sriov_numvfs" file. 922 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 923 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 924 * This will change MSI-X Table Size in the VF Message Control 925 * registers. 926 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 927 * MSI-X vectors available for distribution to the VFs. 928 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 929 * @groups: Sysfs attribute groups. 930 * @dev_groups: Attributes attached to the device that will be 931 * created once it is bound to the driver. 932 * @driver: Driver model structure. 933 * @dynids: List of dynamically added device IDs. 934 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 935 * For most device drivers, no need to care about this flag 936 * as long as all DMAs are handled through the kernel DMA API. 937 * For some special ones, for example VFIO drivers, they know 938 * how to manage the DMA themselves and set this flag so that 939 * the IOMMU layer will allow them to setup and manage their 940 * own I/O address space. 941 */ 942 struct pci_driver { 943 const char *name; 944 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 945 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 946 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 947 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 948 int (*resume)(struct pci_dev *dev); /* Device woken up */ 949 void (*shutdown)(struct pci_dev *dev); 950 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 951 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 952 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 953 const struct pci_error_handlers *err_handler; 954 const struct attribute_group **groups; 955 const struct attribute_group **dev_groups; 956 struct device_driver driver; 957 struct pci_dynids dynids; 958 bool driver_managed_dma; 959 }; 960 961 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 962 { 963 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 964 } 965 966 /** 967 * PCI_DEVICE - macro used to describe a specific PCI device 968 * @vend: the 16 bit PCI Vendor ID 969 * @dev: the 16 bit PCI Device ID 970 * 971 * This macro is used to create a struct pci_device_id that matches a 972 * specific device. The subvendor and subdevice fields will be set to 973 * PCI_ANY_ID. 974 */ 975 #define PCI_DEVICE(vend,dev) \ 976 .vendor = (vend), .device = (dev), \ 977 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 978 979 /** 980 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 981 * override_only flags. 982 * @vend: the 16 bit PCI Vendor ID 983 * @dev: the 16 bit PCI Device ID 984 * @driver_override: the 32 bit PCI Device override_only 985 * 986 * This macro is used to create a struct pci_device_id that matches only a 987 * driver_override device. The subvendor and subdevice fields will be set to 988 * PCI_ANY_ID. 989 */ 990 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 991 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 992 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 993 994 /** 995 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 996 * "driver_override" PCI device. 997 * @vend: the 16 bit PCI Vendor ID 998 * @dev: the 16 bit PCI Device ID 999 * 1000 * This macro is used to create a struct pci_device_id that matches a 1001 * specific device. The subvendor and subdevice fields will be set to 1002 * PCI_ANY_ID and the driver_override will be set to 1003 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1004 */ 1005 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1006 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1007 1008 /** 1009 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1010 * @vend: the 16 bit PCI Vendor ID 1011 * @dev: the 16 bit PCI Device ID 1012 * @subvend: the 16 bit PCI Subvendor ID 1013 * @subdev: the 16 bit PCI Subdevice ID 1014 * 1015 * This macro is used to create a struct pci_device_id that matches a 1016 * specific device with subsystem information. 1017 */ 1018 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1019 .vendor = (vend), .device = (dev), \ 1020 .subvendor = (subvend), .subdevice = (subdev) 1021 1022 /** 1023 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1024 * @dev_class: the class, subclass, prog-if triple for this device 1025 * @dev_class_mask: the class mask for this device 1026 * 1027 * This macro is used to create a struct pci_device_id that matches a 1028 * specific PCI class. The vendor, device, subvendor, and subdevice 1029 * fields will be set to PCI_ANY_ID. 1030 */ 1031 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1032 .class = (dev_class), .class_mask = (dev_class_mask), \ 1033 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1034 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1035 1036 /** 1037 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1038 * @vend: the vendor name 1039 * @dev: the 16 bit PCI Device ID 1040 * 1041 * This macro is used to create a struct pci_device_id that matches a 1042 * specific PCI device. The subvendor, and subdevice fields will be set 1043 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1044 * private data. 1045 */ 1046 #define PCI_VDEVICE(vend, dev) \ 1047 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1048 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1049 1050 /** 1051 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1052 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1053 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1054 * @data: the driver data to be filled 1055 * 1056 * This macro is used to create a struct pci_device_id that matches a 1057 * specific PCI device. The subvendor, and subdevice fields will be set 1058 * to PCI_ANY_ID. 1059 */ 1060 #define PCI_DEVICE_DATA(vend, dev, data) \ 1061 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1062 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1063 .driver_data = (kernel_ulong_t)(data) 1064 1065 enum { 1066 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1067 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1068 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1069 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1070 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1071 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1072 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1073 }; 1074 1075 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */ 1076 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1077 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1078 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1079 1080 /* These external functions are only available when PCI support is enabled */ 1081 #ifdef CONFIG_PCI 1082 1083 extern unsigned int pci_flags; 1084 1085 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1086 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1087 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1088 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1089 1090 void pcie_bus_configure_settings(struct pci_bus *bus); 1091 1092 enum pcie_bus_config_types { 1093 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1094 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1095 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1096 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1097 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1098 }; 1099 1100 extern enum pcie_bus_config_types pcie_bus_config; 1101 1102 extern struct bus_type pci_bus_type; 1103 1104 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1105 * code, or PCI core code. */ 1106 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1107 /* Some device drivers need know if PCI is initiated */ 1108 int no_pci_devices(void); 1109 1110 void pcibios_resource_survey_bus(struct pci_bus *bus); 1111 void pcibios_bus_add_device(struct pci_dev *pdev); 1112 void pcibios_add_bus(struct pci_bus *bus); 1113 void pcibios_remove_bus(struct pci_bus *bus); 1114 void pcibios_fixup_bus(struct pci_bus *); 1115 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1116 /* Architecture-specific versions may override this (weak) */ 1117 char *pcibios_setup(char *str); 1118 1119 /* Used only when drivers/pci/setup.c is used */ 1120 resource_size_t pcibios_align_resource(void *, const struct resource *, 1121 resource_size_t, 1122 resource_size_t); 1123 1124 /* Weak but can be overridden by arch */ 1125 void pci_fixup_cardbus(struct pci_bus *); 1126 1127 /* Generic PCI functions used internally */ 1128 1129 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1130 struct resource *res); 1131 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1132 struct pci_bus_region *region); 1133 void pcibios_scan_specific_bus(int busn); 1134 struct pci_bus *pci_find_bus(int domain, int busnr); 1135 void pci_bus_add_devices(const struct pci_bus *bus); 1136 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1137 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1138 struct pci_ops *ops, void *sysdata, 1139 struct list_head *resources); 1140 int pci_host_probe(struct pci_host_bridge *bridge); 1141 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1142 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1143 void pci_bus_release_busn_res(struct pci_bus *b); 1144 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1145 struct pci_ops *ops, void *sysdata, 1146 struct list_head *resources); 1147 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1148 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1149 int busnr); 1150 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1151 const char *name, 1152 struct hotplug_slot *hotplug); 1153 void pci_destroy_slot(struct pci_slot *slot); 1154 #ifdef CONFIG_SYSFS 1155 void pci_dev_assign_slot(struct pci_dev *dev); 1156 #else 1157 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1158 #endif 1159 int pci_scan_slot(struct pci_bus *bus, int devfn); 1160 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1161 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1162 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1163 void pci_bus_add_device(struct pci_dev *dev); 1164 void pci_read_bridge_bases(struct pci_bus *child); 1165 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1166 struct resource *res); 1167 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1168 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1169 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1170 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1171 void pci_dev_put(struct pci_dev *dev); 1172 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T)) 1173 void pci_remove_bus(struct pci_bus *b); 1174 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1175 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1176 void pci_stop_root_bus(struct pci_bus *bus); 1177 void pci_remove_root_bus(struct pci_bus *bus); 1178 void pci_setup_cardbus(struct pci_bus *bus); 1179 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1180 void pci_sort_breadthfirst(void); 1181 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1182 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1183 1184 /* Generic PCI functions exported to card drivers */ 1185 1186 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1187 u8 pci_find_capability(struct pci_dev *dev, int cap); 1188 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1189 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1190 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1191 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1192 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1193 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1194 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1195 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1196 1197 u64 pci_get_dsn(struct pci_dev *dev); 1198 1199 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1200 struct pci_dev *from); 1201 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1202 unsigned int ss_vendor, unsigned int ss_device, 1203 struct pci_dev *from); 1204 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1205 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1206 unsigned int devfn); 1207 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1208 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1209 1210 int pci_dev_present(const struct pci_device_id *ids); 1211 1212 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1213 int where, u8 *val); 1214 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1215 int where, u16 *val); 1216 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1217 int where, u32 *val); 1218 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1219 int where, u8 val); 1220 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1221 int where, u16 val); 1222 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1223 int where, u32 val); 1224 1225 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1226 int where, int size, u32 *val); 1227 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1228 int where, int size, u32 val); 1229 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1230 int where, int size, u32 *val); 1231 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1232 int where, int size, u32 val); 1233 1234 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1235 1236 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1237 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1238 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1239 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1240 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1241 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1242 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1243 u32 clear, u32 set); 1244 1245 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1246 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1247 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1248 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1249 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1250 u16 clear, u16 set); 1251 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1252 u16 clear, u16 set); 1253 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1254 u32 clear, u32 set); 1255 1256 /** 1257 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1258 * @dev: PCI device structure of the PCI Express device 1259 * @pos: PCI Express Capability Register 1260 * @clear: Clear bitmask 1261 * @set: Set bitmask 1262 * 1263 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1264 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1265 * Capability Registers are accessed concurrently in RMW fashion, hence 1266 * require locking which is handled transparently to the caller. 1267 */ 1268 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1269 int pos, 1270 u16 clear, u16 set) 1271 { 1272 switch (pos) { 1273 case PCI_EXP_LNKCTL: 1274 case PCI_EXP_RTCTL: 1275 return pcie_capability_clear_and_set_word_locked(dev, pos, 1276 clear, set); 1277 default: 1278 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1279 clear, set); 1280 } 1281 } 1282 1283 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1284 u16 set) 1285 { 1286 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1287 } 1288 1289 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1290 u32 set) 1291 { 1292 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1293 } 1294 1295 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1296 u16 clear) 1297 { 1298 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1299 } 1300 1301 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1302 u32 clear) 1303 { 1304 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1305 } 1306 1307 /* User-space driven config access */ 1308 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1309 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1310 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1311 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1312 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1313 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1314 1315 int __must_check pci_enable_device(struct pci_dev *dev); 1316 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1317 int __must_check pci_reenable_device(struct pci_dev *); 1318 int __must_check pcim_enable_device(struct pci_dev *pdev); 1319 void pcim_pin_device(struct pci_dev *pdev); 1320 1321 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1322 { 1323 /* 1324 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1325 * writable and no quirk has marked the feature broken. 1326 */ 1327 return !pdev->broken_intx_masking; 1328 } 1329 1330 static inline int pci_is_enabled(struct pci_dev *pdev) 1331 { 1332 return (atomic_read(&pdev->enable_cnt) > 0); 1333 } 1334 1335 static inline int pci_is_managed(struct pci_dev *pdev) 1336 { 1337 return pdev->is_managed; 1338 } 1339 1340 void pci_disable_device(struct pci_dev *dev); 1341 1342 extern unsigned int pcibios_max_latency; 1343 void pci_set_master(struct pci_dev *dev); 1344 void pci_clear_master(struct pci_dev *dev); 1345 1346 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1347 int pci_set_cacheline_size(struct pci_dev *dev); 1348 int __must_check pci_set_mwi(struct pci_dev *dev); 1349 int __must_check pcim_set_mwi(struct pci_dev *dev); 1350 int pci_try_set_mwi(struct pci_dev *dev); 1351 void pci_clear_mwi(struct pci_dev *dev); 1352 void pci_disable_parity(struct pci_dev *dev); 1353 void pci_intx(struct pci_dev *dev, int enable); 1354 bool pci_check_and_mask_intx(struct pci_dev *dev); 1355 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1356 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1357 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1358 int pcix_get_max_mmrbc(struct pci_dev *dev); 1359 int pcix_get_mmrbc(struct pci_dev *dev); 1360 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1361 int pcie_get_readrq(struct pci_dev *dev); 1362 int pcie_set_readrq(struct pci_dev *dev, int rq); 1363 int pcie_get_mps(struct pci_dev *dev); 1364 int pcie_set_mps(struct pci_dev *dev, int mps); 1365 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1366 enum pci_bus_speed *speed, 1367 enum pcie_link_width *width); 1368 int pcie_link_speed_mbps(struct pci_dev *pdev); 1369 void pcie_print_link_status(struct pci_dev *dev); 1370 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1371 int pcie_flr(struct pci_dev *dev); 1372 int __pci_reset_function_locked(struct pci_dev *dev); 1373 int pci_reset_function(struct pci_dev *dev); 1374 int pci_reset_function_locked(struct pci_dev *dev); 1375 int pci_try_reset_function(struct pci_dev *dev); 1376 int pci_probe_reset_slot(struct pci_slot *slot); 1377 int pci_probe_reset_bus(struct pci_bus *bus); 1378 int pci_reset_bus(struct pci_dev *dev); 1379 void pci_reset_secondary_bus(struct pci_dev *dev); 1380 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1381 void pci_update_resource(struct pci_dev *dev, int resno); 1382 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1383 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1384 void pci_release_resource(struct pci_dev *dev, int resno); 1385 static inline int pci_rebar_bytes_to_size(u64 bytes) 1386 { 1387 bytes = roundup_pow_of_two(bytes); 1388 1389 /* Return BAR size as defined in the resizable BAR specification */ 1390 return max(ilog2(bytes), 20) - 20; 1391 } 1392 1393 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1394 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1395 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1396 bool pci_device_is_present(struct pci_dev *pdev); 1397 void pci_ignore_hotplug(struct pci_dev *dev); 1398 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1399 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1400 1401 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1402 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1403 const char *fmt, ...); 1404 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1405 1406 /* ROM control related routines */ 1407 int pci_enable_rom(struct pci_dev *pdev); 1408 void pci_disable_rom(struct pci_dev *pdev); 1409 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1410 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1411 1412 /* Power management related routines */ 1413 int pci_save_state(struct pci_dev *dev); 1414 void pci_restore_state(struct pci_dev *dev); 1415 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1416 int pci_load_saved_state(struct pci_dev *dev, 1417 struct pci_saved_state *state); 1418 int pci_load_and_free_saved_state(struct pci_dev *dev, 1419 struct pci_saved_state **state); 1420 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1421 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1422 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state); 1423 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1424 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1425 void pci_pme_active(struct pci_dev *dev, bool enable); 1426 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1427 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1428 int pci_prepare_to_sleep(struct pci_dev *dev); 1429 int pci_back_from_sleep(struct pci_dev *dev); 1430 bool pci_dev_run_wake(struct pci_dev *dev); 1431 void pci_d3cold_enable(struct pci_dev *dev); 1432 void pci_d3cold_disable(struct pci_dev *dev); 1433 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1434 void pci_resume_bus(struct pci_bus *bus); 1435 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1436 1437 /* For use by arch with custom probe code */ 1438 void set_pcie_port_type(struct pci_dev *pdev); 1439 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1440 1441 /* Functions for PCI Hotplug drivers to use */ 1442 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1443 unsigned int pci_rescan_bus(struct pci_bus *bus); 1444 void pci_lock_rescan_remove(void); 1445 void pci_unlock_rescan_remove(void); 1446 1447 /* Vital Product Data routines */ 1448 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1449 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1450 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1451 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1452 1453 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1454 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1455 void pci_bus_assign_resources(const struct pci_bus *bus); 1456 void pci_bus_claim_resources(struct pci_bus *bus); 1457 void pci_bus_size_bridges(struct pci_bus *bus); 1458 int pci_claim_resource(struct pci_dev *, int); 1459 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1460 void pci_assign_unassigned_resources(void); 1461 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1462 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1463 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1464 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1465 int pci_enable_resources(struct pci_dev *, int mask); 1466 void pci_assign_irq(struct pci_dev *dev); 1467 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1468 #define HAVE_PCI_REQ_REGIONS 2 1469 int __must_check pci_request_regions(struct pci_dev *, const char *); 1470 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1471 void pci_release_regions(struct pci_dev *); 1472 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1473 void pci_release_region(struct pci_dev *, int); 1474 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1475 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1476 void pci_release_selected_regions(struct pci_dev *, int); 1477 1478 static inline __must_check struct resource * 1479 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1480 unsigned int len, const char *name) 1481 { 1482 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1483 name, IORESOURCE_EXCLUSIVE); 1484 } 1485 1486 static inline void pci_release_config_region(struct pci_dev *pdev, 1487 unsigned int offset, 1488 unsigned int len) 1489 { 1490 __release_region(&pdev->driver_exclusive_resource, offset, len); 1491 } 1492 1493 /* drivers/pci/bus.c */ 1494 void pci_add_resource(struct list_head *resources, struct resource *res); 1495 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1496 resource_size_t offset); 1497 void pci_free_resource_list(struct list_head *resources); 1498 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1499 unsigned int flags); 1500 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1501 void pci_bus_remove_resources(struct pci_bus *bus); 1502 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1503 int devm_request_pci_bus_resources(struct device *dev, 1504 struct list_head *resources); 1505 1506 /* Temporary until new and working PCI SBR API in place */ 1507 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1508 1509 #define __pci_bus_for_each_res0(bus, res, ...) \ 1510 for (unsigned int __b = 0; \ 1511 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1512 __b++) 1513 1514 #define __pci_bus_for_each_res1(bus, res, __b) \ 1515 for (__b = 0; \ 1516 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1517 __b++) 1518 1519 /** 1520 * pci_bus_for_each_resource - iterate over PCI bus resources 1521 * @bus: the PCI bus 1522 * @res: pointer to the current resource 1523 * @...: optional index of the current resource 1524 * 1525 * Iterate over PCI bus resources. The first part is to go over PCI bus 1526 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1527 * After that continue with the separate list of the additional resources, 1528 * if not empty. That's why the Logical OR is being used. 1529 * 1530 * Possible usage: 1531 * 1532 * struct pci_bus *bus = ...; 1533 * struct resource *res; 1534 * unsigned int i; 1535 * 1536 * // With optional index 1537 * pci_bus_for_each_resource(bus, res, i) 1538 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1539 * 1540 * // Without index 1541 * pci_bus_for_each_resource(bus, res) 1542 * _do_something_(res); 1543 */ 1544 #define pci_bus_for_each_resource(bus, res, ...) \ 1545 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1546 (bus, res, __VA_ARGS__) 1547 1548 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1549 struct resource *res, resource_size_t size, 1550 resource_size_t align, resource_size_t min, 1551 unsigned long type_mask, 1552 resource_size_t (*alignf)(void *, 1553 const struct resource *, 1554 resource_size_t, 1555 resource_size_t), 1556 void *alignf_data); 1557 1558 1559 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1560 resource_size_t size); 1561 unsigned long pci_address_to_pio(phys_addr_t addr); 1562 phys_addr_t pci_pio_to_address(unsigned long pio); 1563 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1564 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1565 phys_addr_t phys_addr); 1566 void pci_unmap_iospace(struct resource *res); 1567 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1568 resource_size_t offset, 1569 resource_size_t size); 1570 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1571 struct resource *res); 1572 1573 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1574 { 1575 struct pci_bus_region region; 1576 1577 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1578 return region.start; 1579 } 1580 1581 /* Proper probing supporting hot-pluggable devices */ 1582 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1583 const char *mod_name); 1584 1585 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1586 #define pci_register_driver(driver) \ 1587 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1588 1589 void pci_unregister_driver(struct pci_driver *dev); 1590 1591 /** 1592 * module_pci_driver() - Helper macro for registering a PCI driver 1593 * @__pci_driver: pci_driver struct 1594 * 1595 * Helper macro for PCI drivers which do not do anything special in module 1596 * init/exit. This eliminates a lot of boilerplate. Each module may only 1597 * use this macro once, and calling it replaces module_init() and module_exit() 1598 */ 1599 #define module_pci_driver(__pci_driver) \ 1600 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1601 1602 /** 1603 * builtin_pci_driver() - Helper macro for registering a PCI driver 1604 * @__pci_driver: pci_driver struct 1605 * 1606 * Helper macro for PCI drivers which do not do anything special in their 1607 * init code. This eliminates a lot of boilerplate. Each driver may only 1608 * use this macro once, and calling it replaces device_initcall(...) 1609 */ 1610 #define builtin_pci_driver(__pci_driver) \ 1611 builtin_driver(__pci_driver, pci_register_driver) 1612 1613 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1614 int pci_add_dynid(struct pci_driver *drv, 1615 unsigned int vendor, unsigned int device, 1616 unsigned int subvendor, unsigned int subdevice, 1617 unsigned int class, unsigned int class_mask, 1618 unsigned long driver_data); 1619 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1620 struct pci_dev *dev); 1621 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1622 int pass); 1623 1624 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1625 void *userdata); 1626 void pci_walk_bus_locked(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1627 void *userdata); 1628 int pci_cfg_space_size(struct pci_dev *dev); 1629 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1630 void pci_setup_bridge(struct pci_bus *bus); 1631 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1632 unsigned long type); 1633 1634 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1635 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1636 1637 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1638 unsigned int command_bits, u32 flags); 1639 1640 /* 1641 * Virtual interrupts allow for more interrupts to be allocated 1642 * than the device has interrupts for. These are not programmed 1643 * into the device's MSI-X table and must be handled by some 1644 * other driver means. 1645 */ 1646 #define PCI_IRQ_VIRTUAL (1 << 4) 1647 1648 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1649 1650 #include <linux/dmapool.h> 1651 1652 struct msix_entry { 1653 u32 vector; /* Kernel uses to write allocated vector */ 1654 u16 entry; /* Driver uses to specify entry, OS writes */ 1655 }; 1656 1657 #ifdef CONFIG_PCI_MSI 1658 int pci_msi_vec_count(struct pci_dev *dev); 1659 void pci_disable_msi(struct pci_dev *dev); 1660 int pci_msix_vec_count(struct pci_dev *dev); 1661 void pci_disable_msix(struct pci_dev *dev); 1662 void pci_restore_msi_state(struct pci_dev *dev); 1663 int pci_msi_enabled(void); 1664 int pci_enable_msi(struct pci_dev *dev); 1665 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1666 int minvec, int maxvec); 1667 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1668 struct msix_entry *entries, int nvec) 1669 { 1670 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1671 if (rc < 0) 1672 return rc; 1673 return 0; 1674 } 1675 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1676 unsigned int max_vecs, unsigned int flags); 1677 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1678 unsigned int max_vecs, unsigned int flags, 1679 struct irq_affinity *affd); 1680 1681 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1682 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1683 const struct irq_affinity_desc *affdesc); 1684 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1685 1686 void pci_free_irq_vectors(struct pci_dev *dev); 1687 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1688 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1689 1690 #else 1691 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1692 static inline void pci_disable_msi(struct pci_dev *dev) { } 1693 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1694 static inline void pci_disable_msix(struct pci_dev *dev) { } 1695 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1696 static inline int pci_msi_enabled(void) { return 0; } 1697 static inline int pci_enable_msi(struct pci_dev *dev) 1698 { return -ENOSYS; } 1699 static inline int pci_enable_msix_range(struct pci_dev *dev, 1700 struct msix_entry *entries, int minvec, int maxvec) 1701 { return -ENOSYS; } 1702 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1703 struct msix_entry *entries, int nvec) 1704 { return -ENOSYS; } 1705 1706 static inline int 1707 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1708 unsigned int max_vecs, unsigned int flags, 1709 struct irq_affinity *aff_desc) 1710 { 1711 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq) 1712 return 1; 1713 return -ENOSPC; 1714 } 1715 static inline int 1716 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1717 unsigned int max_vecs, unsigned int flags) 1718 { 1719 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1720 flags, NULL); 1721 } 1722 1723 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1724 { return false; } 1725 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1726 const struct irq_affinity_desc *affdesc) 1727 { 1728 struct msi_map map = { .index = -ENOSYS, }; 1729 1730 return map; 1731 } 1732 1733 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1734 { 1735 } 1736 1737 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1738 { 1739 } 1740 1741 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1742 { 1743 if (WARN_ON_ONCE(nr > 0)) 1744 return -EINVAL; 1745 return dev->irq; 1746 } 1747 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1748 int vec) 1749 { 1750 return cpu_possible_mask; 1751 } 1752 #endif 1753 1754 /** 1755 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1756 * @d: the INTx IRQ domain 1757 * @node: the DT node for the device whose interrupt we're translating 1758 * @intspec: the interrupt specifier data from the DT 1759 * @intsize: the number of entries in @intspec 1760 * @out_hwirq: pointer at which to write the hwirq number 1761 * @out_type: pointer at which to write the interrupt type 1762 * 1763 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1764 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1765 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1766 * INTx value to obtain the hwirq number. 1767 * 1768 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1769 */ 1770 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1771 struct device_node *node, 1772 const u32 *intspec, 1773 unsigned int intsize, 1774 unsigned long *out_hwirq, 1775 unsigned int *out_type) 1776 { 1777 const u32 intx = intspec[0]; 1778 1779 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1780 return -EINVAL; 1781 1782 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1783 return 0; 1784 } 1785 1786 #ifdef CONFIG_PCIEPORTBUS 1787 extern bool pcie_ports_disabled; 1788 extern bool pcie_ports_native; 1789 #else 1790 #define pcie_ports_disabled true 1791 #define pcie_ports_native false 1792 #endif 1793 1794 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */ 1795 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */ 1796 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */ 1797 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */ 1798 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */ 1799 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */ 1800 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\ 1801 PCIE_LINK_STATE_L1 |\ 1802 PCIE_LINK_STATE_L1_1 |\ 1803 PCIE_LINK_STATE_L1_2 |\ 1804 PCIE_LINK_STATE_L1_1_PCIPM |\ 1805 PCIE_LINK_STATE_L1_2_PCIPM) 1806 #define PCIE_LINK_STATE_CLKPM BIT(7) 1807 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\ 1808 PCIE_LINK_STATE_CLKPM) 1809 1810 #ifdef CONFIG_PCIEASPM 1811 int pci_disable_link_state(struct pci_dev *pdev, int state); 1812 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1813 int pci_enable_link_state(struct pci_dev *pdev, int state); 1814 int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1815 void pcie_no_aspm(void); 1816 bool pcie_aspm_support_enabled(void); 1817 bool pcie_aspm_enabled(struct pci_dev *pdev); 1818 #else 1819 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1820 { return 0; } 1821 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1822 { return 0; } 1823 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1824 { return 0; } 1825 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1826 { return 0; } 1827 static inline void pcie_no_aspm(void) { } 1828 static inline bool pcie_aspm_support_enabled(void) { return false; } 1829 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1830 #endif 1831 1832 #ifdef CONFIG_PCIEAER 1833 bool pci_aer_available(void); 1834 #else 1835 static inline bool pci_aer_available(void) { return false; } 1836 #endif 1837 1838 bool pci_ats_disabled(void); 1839 1840 #ifdef CONFIG_PCIE_PTM 1841 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1842 void pci_disable_ptm(struct pci_dev *dev); 1843 bool pcie_ptm_enabled(struct pci_dev *dev); 1844 #else 1845 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1846 { return -EINVAL; } 1847 static inline void pci_disable_ptm(struct pci_dev *dev) { } 1848 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1849 { return false; } 1850 #endif 1851 1852 void pci_cfg_access_lock(struct pci_dev *dev); 1853 bool pci_cfg_access_trylock(struct pci_dev *dev); 1854 void pci_cfg_access_unlock(struct pci_dev *dev); 1855 1856 void pci_dev_lock(struct pci_dev *dev); 1857 int pci_dev_trylock(struct pci_dev *dev); 1858 void pci_dev_unlock(struct pci_dev *dev); 1859 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T)) 1860 1861 /* 1862 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1863 * a PCI domain is defined to be a set of PCI buses which share 1864 * configuration space. 1865 */ 1866 #ifdef CONFIG_PCI_DOMAINS 1867 extern int pci_domains_supported; 1868 #else 1869 enum { pci_domains_supported = 0 }; 1870 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1871 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1872 #endif /* CONFIG_PCI_DOMAINS */ 1873 1874 /* 1875 * Generic implementation for PCI domain support. If your 1876 * architecture does not need custom management of PCI 1877 * domains then this implementation will be used 1878 */ 1879 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1880 static inline int pci_domain_nr(struct pci_bus *bus) 1881 { 1882 return bus->domain_nr; 1883 } 1884 #ifdef CONFIG_ACPI 1885 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1886 #else 1887 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1888 { return 0; } 1889 #endif 1890 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1891 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); 1892 #endif 1893 1894 /* Some architectures require additional setup to direct VGA traffic */ 1895 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1896 unsigned int command_bits, u32 flags); 1897 void pci_register_set_vga_state(arch_set_vga_state_t func); 1898 1899 static inline int 1900 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1901 { 1902 return pci_request_selected_regions(pdev, 1903 pci_select_bars(pdev, IORESOURCE_IO), name); 1904 } 1905 1906 static inline void 1907 pci_release_io_regions(struct pci_dev *pdev) 1908 { 1909 return pci_release_selected_regions(pdev, 1910 pci_select_bars(pdev, IORESOURCE_IO)); 1911 } 1912 1913 static inline int 1914 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1915 { 1916 return pci_request_selected_regions(pdev, 1917 pci_select_bars(pdev, IORESOURCE_MEM), name); 1918 } 1919 1920 static inline void 1921 pci_release_mem_regions(struct pci_dev *pdev) 1922 { 1923 return pci_release_selected_regions(pdev, 1924 pci_select_bars(pdev, IORESOURCE_MEM)); 1925 } 1926 1927 #else /* CONFIG_PCI is not enabled */ 1928 1929 static inline void pci_set_flags(int flags) { } 1930 static inline void pci_add_flags(int flags) { } 1931 static inline void pci_clear_flags(int flags) { } 1932 static inline int pci_has_flag(int flag) { return 0; } 1933 1934 /* 1935 * If the system does not have PCI, clearly these return errors. Define 1936 * these as simple inline functions to avoid hair in drivers. 1937 */ 1938 #define _PCI_NOP(o, s, t) \ 1939 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1940 int where, t val) \ 1941 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1942 1943 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1944 _PCI_NOP(o, word, u16 x) \ 1945 _PCI_NOP(o, dword, u32 x) 1946 _PCI_NOP_ALL(read, *) 1947 _PCI_NOP_ALL(write,) 1948 1949 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1950 unsigned int device, 1951 struct pci_dev *from) 1952 { return NULL; } 1953 1954 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1955 unsigned int device, 1956 unsigned int ss_vendor, 1957 unsigned int ss_device, 1958 struct pci_dev *from) 1959 { return NULL; } 1960 1961 static inline struct pci_dev *pci_get_class(unsigned int class, 1962 struct pci_dev *from) 1963 { return NULL; } 1964 1965 static inline struct pci_dev *pci_get_base_class(unsigned int class, 1966 struct pci_dev *from) 1967 { return NULL; } 1968 1969 static inline int pci_dev_present(const struct pci_device_id *ids) 1970 { return 0; } 1971 1972 #define no_pci_devices() (1) 1973 #define pci_dev_put(dev) do { } while (0) 1974 1975 static inline void pci_set_master(struct pci_dev *dev) { } 1976 static inline void pci_clear_master(struct pci_dev *dev) { } 1977 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1978 static inline void pci_disable_device(struct pci_dev *dev) { } 1979 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1980 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1981 { return -EBUSY; } 1982 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1983 struct module *owner, 1984 const char *mod_name) 1985 { return 0; } 1986 static inline int pci_register_driver(struct pci_driver *drv) 1987 { return 0; } 1988 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1989 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1990 { return 0; } 1991 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) 1992 { return 0; } 1993 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 1994 { return 0; } 1995 1996 static inline u64 pci_get_dsn(struct pci_dev *dev) 1997 { return 0; } 1998 1999 /* Power management related routines */ 2000 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2001 static inline void pci_restore_state(struct pci_dev *dev) { } 2002 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2003 { return 0; } 2004 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) 2005 { return 0; } 2006 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2007 { return 0; } 2008 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2009 pm_message_t state) 2010 { return PCI_D0; } 2011 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2012 int enable) 2013 { return 0; } 2014 2015 static inline struct resource *pci_find_resource(struct pci_dev *dev, 2016 struct resource *res) 2017 { return NULL; } 2018 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2019 { return -EIO; } 2020 static inline void pci_release_regions(struct pci_dev *dev) { } 2021 2022 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 2023 phys_addr_t addr, resource_size_t size) 2024 { return -EINVAL; } 2025 2026 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2027 2028 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2029 { return NULL; } 2030 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2031 unsigned int devfn) 2032 { return NULL; } 2033 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2034 unsigned int bus, unsigned int devfn) 2035 { return NULL; } 2036 2037 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2038 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2039 2040 #define dev_is_pci(d) (false) 2041 #define dev_is_pf(d) (false) 2042 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2043 { return false; } 2044 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2045 struct device_node *node, 2046 const u32 *intspec, 2047 unsigned int intsize, 2048 unsigned long *out_hwirq, 2049 unsigned int *out_type) 2050 { return -EINVAL; } 2051 2052 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2053 struct pci_dev *dev) 2054 { return NULL; } 2055 static inline bool pci_ats_disabled(void) { return true; } 2056 2057 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2058 { 2059 return -EINVAL; 2060 } 2061 2062 static inline int 2063 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2064 unsigned int max_vecs, unsigned int flags, 2065 struct irq_affinity *aff_desc) 2066 { 2067 return -ENOSPC; 2068 } 2069 static inline int 2070 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2071 unsigned int max_vecs, unsigned int flags) 2072 { 2073 return -ENOSPC; 2074 } 2075 #endif /* CONFIG_PCI */ 2076 2077 /* Include architecture-dependent settings and functions */ 2078 2079 #include <asm/pci.h> 2080 2081 /* 2082 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2083 * is expected to be an offset within that region. 2084 * 2085 */ 2086 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2087 struct vm_area_struct *vma, 2088 enum pci_mmap_state mmap_state, int write_combine); 2089 2090 #ifndef arch_can_pci_mmap_wc 2091 #define arch_can_pci_mmap_wc() 0 2092 #endif 2093 2094 #ifndef arch_can_pci_mmap_io 2095 #define arch_can_pci_mmap_io() 0 2096 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2097 #else 2098 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2099 #endif 2100 2101 #ifndef pci_root_bus_fwnode 2102 #define pci_root_bus_fwnode(bus) NULL 2103 #endif 2104 2105 /* 2106 * These helpers provide future and backwards compatibility 2107 * for accessing popular PCI BAR info 2108 */ 2109 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2110 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2111 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2112 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2113 #define pci_resource_len(dev,bar) \ 2114 (pci_resource_end((dev), (bar)) ? \ 2115 resource_size(pci_resource_n((dev), (bar))) : 0) 2116 2117 #define __pci_dev_for_each_res0(dev, res, ...) \ 2118 for (unsigned int __b = 0; \ 2119 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2120 __b++) 2121 2122 #define __pci_dev_for_each_res1(dev, res, __b) \ 2123 for (__b = 0; \ 2124 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2125 __b++) 2126 2127 #define pci_dev_for_each_resource(dev, res, ...) \ 2128 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2129 (dev, res, __VA_ARGS__) 2130 2131 /* 2132 * Similar to the helpers above, these manipulate per-pci_dev 2133 * driver-specific data. They are really just a wrapper around 2134 * the generic device structure functions of these calls. 2135 */ 2136 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2137 { 2138 return dev_get_drvdata(&pdev->dev); 2139 } 2140 2141 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2142 { 2143 dev_set_drvdata(&pdev->dev, data); 2144 } 2145 2146 static inline const char *pci_name(const struct pci_dev *pdev) 2147 { 2148 return dev_name(&pdev->dev); 2149 } 2150 2151 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2152 const struct resource *rsrc, 2153 resource_size_t *start, resource_size_t *end); 2154 2155 /* 2156 * The world is not perfect and supplies us with broken PCI devices. 2157 * For at least a part of these bugs we need a work-around, so both 2158 * generic (drivers/pci/quirks.c) and per-architecture code can define 2159 * fixup hooks to be called for particular buggy devices. 2160 */ 2161 2162 struct pci_fixup { 2163 u16 vendor; /* Or PCI_ANY_ID */ 2164 u16 device; /* Or PCI_ANY_ID */ 2165 u32 class; /* Or PCI_ANY_ID */ 2166 unsigned int class_shift; /* should be 0, 8, 16 */ 2167 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2168 int hook_offset; 2169 #else 2170 void (*hook)(struct pci_dev *dev); 2171 #endif 2172 }; 2173 2174 enum pci_fixup_pass { 2175 pci_fixup_early, /* Before probing BARs */ 2176 pci_fixup_header, /* After reading configuration header */ 2177 pci_fixup_final, /* Final phase of device fixups */ 2178 pci_fixup_enable, /* pci_enable_device() time */ 2179 pci_fixup_resume, /* pci_device_resume() */ 2180 pci_fixup_suspend, /* pci_device_suspend() */ 2181 pci_fixup_resume_early, /* pci_device_resume_early() */ 2182 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2183 }; 2184 2185 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2186 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2187 class_shift, hook) \ 2188 __ADDRESSABLE(hook) \ 2189 asm(".section " #sec ", \"a\" \n" \ 2190 ".balign 16 \n" \ 2191 ".short " #vendor ", " #device " \n" \ 2192 ".long " #class ", " #class_shift " \n" \ 2193 ".long " #hook " - . \n" \ 2194 ".previous \n"); 2195 2196 /* 2197 * Clang's LTO may rename static functions in C, but has no way to 2198 * handle such renamings when referenced from inline asm. To work 2199 * around this, create global C stubs for these cases. 2200 */ 2201 #ifdef CONFIG_LTO_CLANG 2202 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2203 class_shift, hook, stub) \ 2204 void stub(struct pci_dev *dev); \ 2205 void stub(struct pci_dev *dev) \ 2206 { \ 2207 hook(dev); \ 2208 } \ 2209 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2210 class_shift, stub) 2211 #else 2212 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2213 class_shift, hook, stub) \ 2214 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2215 class_shift, hook) 2216 #endif 2217 2218 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2219 class_shift, hook) \ 2220 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2221 class_shift, hook, __UNIQUE_ID(hook)) 2222 #else 2223 /* Anonymous variables would be nice... */ 2224 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2225 class_shift, hook) \ 2226 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2227 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2228 = { vendor, device, class, class_shift, hook }; 2229 #endif 2230 2231 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2232 class_shift, hook) \ 2233 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2234 hook, vendor, device, class, class_shift, hook) 2235 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2236 class_shift, hook) \ 2237 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2238 hook, vendor, device, class, class_shift, hook) 2239 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2240 class_shift, hook) \ 2241 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2242 hook, vendor, device, class, class_shift, hook) 2243 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2244 class_shift, hook) \ 2245 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2246 hook, vendor, device, class, class_shift, hook) 2247 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2248 class_shift, hook) \ 2249 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2250 resume##hook, vendor, device, class, class_shift, hook) 2251 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2252 class_shift, hook) \ 2253 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2254 resume_early##hook, vendor, device, class, class_shift, hook) 2255 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2256 class_shift, hook) \ 2257 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2258 suspend##hook, vendor, device, class, class_shift, hook) 2259 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2260 class_shift, hook) \ 2261 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2262 suspend_late##hook, vendor, device, class, class_shift, hook) 2263 2264 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2265 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2266 hook, vendor, device, PCI_ANY_ID, 0, hook) 2267 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2268 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2269 hook, vendor, device, PCI_ANY_ID, 0, hook) 2270 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2271 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2272 hook, vendor, device, PCI_ANY_ID, 0, hook) 2273 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2274 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2275 hook, vendor, device, PCI_ANY_ID, 0, hook) 2276 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2277 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2278 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2279 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2280 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2281 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2282 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2283 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2284 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2285 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2286 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2287 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2288 2289 #ifdef CONFIG_PCI_QUIRKS 2290 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2291 #else 2292 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2293 struct pci_dev *dev) { } 2294 #endif 2295 2296 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2297 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2298 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2299 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2300 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2301 const char *name); 2302 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2303 2304 extern int pci_pci_problems; 2305 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2306 #define PCIPCI_TRITON 2 2307 #define PCIPCI_NATOMA 4 2308 #define PCIPCI_VIAETBF 8 2309 #define PCIPCI_VSFX 16 2310 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2311 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2312 2313 extern unsigned long pci_cardbus_io_size; 2314 extern unsigned long pci_cardbus_mem_size; 2315 extern u8 pci_dfl_cache_line_size; 2316 extern u8 pci_cache_line_size; 2317 2318 /* Architecture-specific versions may override these (weak) */ 2319 void pcibios_disable_device(struct pci_dev *dev); 2320 void pcibios_set_master(struct pci_dev *dev); 2321 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2322 enum pcie_reset_state state); 2323 int pcibios_device_add(struct pci_dev *dev); 2324 void pcibios_release_device(struct pci_dev *dev); 2325 #ifdef CONFIG_PCI 2326 void pcibios_penalize_isa_irq(int irq, int active); 2327 #else 2328 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2329 #endif 2330 int pcibios_alloc_irq(struct pci_dev *dev); 2331 void pcibios_free_irq(struct pci_dev *dev); 2332 resource_size_t pcibios_default_alignment(void); 2333 2334 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE) 2335 extern int pci_create_resource_files(struct pci_dev *dev); 2336 extern void pci_remove_resource_files(struct pci_dev *dev); 2337 #endif 2338 2339 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2340 void __init pci_mmcfg_early_init(void); 2341 void __init pci_mmcfg_late_init(void); 2342 #else 2343 static inline void pci_mmcfg_early_init(void) { } 2344 static inline void pci_mmcfg_late_init(void) { } 2345 #endif 2346 2347 int pci_ext_cfg_avail(void); 2348 2349 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2350 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2351 2352 #ifdef CONFIG_PCI_IOV 2353 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2354 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2355 int pci_iov_vf_id(struct pci_dev *dev); 2356 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2357 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2358 void pci_disable_sriov(struct pci_dev *dev); 2359 2360 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2361 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2362 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2363 int pci_num_vf(struct pci_dev *dev); 2364 int pci_vfs_assigned(struct pci_dev *dev); 2365 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2366 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2367 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2368 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2369 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2370 2371 /* Arch may override these (weak) */ 2372 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2373 int pcibios_sriov_disable(struct pci_dev *pdev); 2374 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2375 #else 2376 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2377 { 2378 return -ENOSYS; 2379 } 2380 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2381 { 2382 return -ENOSYS; 2383 } 2384 2385 static inline int pci_iov_vf_id(struct pci_dev *dev) 2386 { 2387 return -ENOSYS; 2388 } 2389 2390 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2391 struct pci_driver *pf_driver) 2392 { 2393 return ERR_PTR(-EINVAL); 2394 } 2395 2396 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2397 { return -ENODEV; } 2398 2399 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2400 struct pci_dev *virtfn, int id) 2401 { 2402 return -ENODEV; 2403 } 2404 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2405 { 2406 return -ENOSYS; 2407 } 2408 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2409 int id) { } 2410 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2411 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2412 static inline int pci_vfs_assigned(struct pci_dev *dev) 2413 { return 0; } 2414 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2415 { return 0; } 2416 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2417 { return 0; } 2418 #define pci_sriov_configure_simple NULL 2419 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2420 { return 0; } 2421 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2422 #endif 2423 2424 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2425 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2426 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2427 #endif 2428 2429 /** 2430 * pci_pcie_cap - get the saved PCIe capability offset 2431 * @dev: PCI device 2432 * 2433 * PCIe capability offset is calculated at PCI device initialization 2434 * time and saved in the data structure. This function returns saved 2435 * PCIe capability offset. Using this instead of pci_find_capability() 2436 * reduces unnecessary search in the PCI configuration space. If you 2437 * need to calculate PCIe capability offset from raw device for some 2438 * reasons, please use pci_find_capability() instead. 2439 */ 2440 static inline int pci_pcie_cap(struct pci_dev *dev) 2441 { 2442 return dev->pcie_cap; 2443 } 2444 2445 /** 2446 * pci_is_pcie - check if the PCI device is PCI Express capable 2447 * @dev: PCI device 2448 * 2449 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2450 */ 2451 static inline bool pci_is_pcie(struct pci_dev *dev) 2452 { 2453 return pci_pcie_cap(dev); 2454 } 2455 2456 /** 2457 * pcie_caps_reg - get the PCIe Capabilities Register 2458 * @dev: PCI device 2459 */ 2460 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2461 { 2462 return dev->pcie_flags_reg; 2463 } 2464 2465 /** 2466 * pci_pcie_type - get the PCIe device/port type 2467 * @dev: PCI device 2468 */ 2469 static inline int pci_pcie_type(const struct pci_dev *dev) 2470 { 2471 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2472 } 2473 2474 /** 2475 * pcie_find_root_port - Get the PCIe root port device 2476 * @dev: PCI device 2477 * 2478 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2479 * for a given PCI/PCIe Device. 2480 */ 2481 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2482 { 2483 while (dev) { 2484 if (pci_is_pcie(dev) && 2485 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2486 return dev; 2487 dev = pci_upstream_bridge(dev); 2488 } 2489 2490 return NULL; 2491 } 2492 2493 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 2494 { 2495 /* 2496 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg() 2497 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache 2498 * the value (e.g. inside the loop in pci_dev_wait()). 2499 */ 2500 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; 2501 } 2502 2503 void pci_request_acs(void); 2504 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2505 bool pci_acs_path_enabled(struct pci_dev *start, 2506 struct pci_dev *end, u16 acs_flags); 2507 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2508 2509 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2510 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2511 2512 /* Large Resource Data Type Tag Item Names */ 2513 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2514 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2515 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2516 2517 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2518 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2519 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2520 2521 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2522 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2523 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2524 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2525 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2526 2527 /** 2528 * pci_vpd_alloc - Allocate buffer and read VPD into it 2529 * @dev: PCI device 2530 * @size: pointer to field where VPD length is returned 2531 * 2532 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2533 */ 2534 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2535 2536 /** 2537 * pci_vpd_find_id_string - Locate id string in VPD 2538 * @buf: Pointer to buffered VPD data 2539 * @len: The length of the buffer area in which to search 2540 * @size: Pointer to field where length of id string is returned 2541 * 2542 * Returns the index of the id string or -ENOENT if not found. 2543 */ 2544 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2545 2546 /** 2547 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2548 * @buf: Pointer to buffered VPD data 2549 * @len: The length of the buffer area in which to search 2550 * @kw: The keyword to search for 2551 * @size: Pointer to field where length of found keyword data is returned 2552 * 2553 * Returns the index of the information field keyword data or -ENOENT if 2554 * not found. 2555 */ 2556 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2557 const char *kw, unsigned int *size); 2558 2559 /** 2560 * pci_vpd_check_csum - Check VPD checksum 2561 * @buf: Pointer to buffered VPD data 2562 * @len: VPD size 2563 * 2564 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2565 */ 2566 int pci_vpd_check_csum(const void *buf, unsigned int len); 2567 2568 /* PCI <-> OF binding helpers */ 2569 #ifdef CONFIG_OF 2570 struct device_node; 2571 struct irq_domain; 2572 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2573 bool pci_host_of_has_msi_map(struct device *dev); 2574 2575 /* Arch may override this (weak) */ 2576 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2577 2578 #else /* CONFIG_OF */ 2579 static inline struct irq_domain * 2580 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2581 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2582 #endif /* CONFIG_OF */ 2583 2584 static inline struct device_node * 2585 pci_device_to_OF_node(const struct pci_dev *pdev) 2586 { 2587 return pdev ? pdev->dev.of_node : NULL; 2588 } 2589 2590 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2591 { 2592 return bus ? bus->dev.of_node : NULL; 2593 } 2594 2595 #ifdef CONFIG_ACPI 2596 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2597 2598 void 2599 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2600 bool pci_pr3_present(struct pci_dev *pdev); 2601 #else 2602 static inline struct irq_domain * 2603 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2604 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2605 #endif 2606 2607 #ifdef CONFIG_EEH 2608 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2609 { 2610 return pdev->dev.archdata.edev; 2611 } 2612 #endif 2613 2614 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2615 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2616 int pci_for_each_dma_alias(struct pci_dev *pdev, 2617 int (*fn)(struct pci_dev *pdev, 2618 u16 alias, void *data), void *data); 2619 2620 /* Helper functions for operation of device flag */ 2621 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2622 { 2623 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2624 } 2625 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2626 { 2627 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2628 } 2629 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2630 { 2631 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2632 } 2633 2634 /** 2635 * pci_ari_enabled - query ARI forwarding status 2636 * @bus: the PCI bus 2637 * 2638 * Returns true if ARI forwarding is enabled. 2639 */ 2640 static inline bool pci_ari_enabled(struct pci_bus *bus) 2641 { 2642 return bus->self && bus->self->ari_enabled; 2643 } 2644 2645 /** 2646 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2647 * @pdev: PCI device to check 2648 * 2649 * Walk upwards from @pdev and check for each encountered bridge if it's part 2650 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2651 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2652 */ 2653 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2654 { 2655 struct pci_dev *parent = pdev; 2656 2657 if (pdev->is_thunderbolt) 2658 return true; 2659 2660 while ((parent = pci_upstream_bridge(parent))) 2661 if (parent->is_thunderbolt) 2662 return true; 2663 2664 return false; 2665 } 2666 2667 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2668 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2669 #endif 2670 2671 #include <linux/dma-mapping.h> 2672 2673 #define pci_printk(level, pdev, fmt, arg...) \ 2674 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2675 2676 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2677 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2678 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2679 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2680 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2681 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2682 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2683 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2684 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2685 2686 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2687 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2688 2689 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2690 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2691 2692 #define pci_WARN(pdev, condition, fmt, arg...) \ 2693 WARN(condition, "%s %s: " fmt, \ 2694 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2695 2696 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2697 WARN_ONCE(condition, "%s %s: " fmt, \ 2698 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2699 2700 #endif /* LINUX_PCI_H */ 2701