1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2019 Joyent, Inc.
25 * Copyright 2024 Oxide Computer Company
26 */
27
28 /*
29 * PCI configuration space access routines
30 */
31
32 #include <sys/systm.h>
33 #include <sys/psw.h>
34 #include <sys/bootconf.h>
35 #include <sys/reboot.h>
36 #include <sys/pci_impl.h>
37 #include <sys/pci_cfgspace.h>
38 #include <sys/pci_cfgspace_impl.h>
39 #include <sys/pci_cfgacc.h>
40 #if defined(__xpv)
41 #include <sys/hypervisor.h>
42 #endif
43
44 #if defined(__xpv)
45 int pci_max_nbus = 0xFE;
46 #else
47 int pci_max_nbus = 0xFF;
48 #endif
49 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN;
50 int pci_bios_maxbus;
51 int pci_bios_mech;
52 int pci_bios_vers;
53
54 /*
55 * These two variables can be used to force a configuration mechanism or
56 * to force which function is used to probe for the presence of the PCI bus.
57 */
58 int PCI_CFG_TYPE = 0;
59 int PCI_PROBE_TYPE = 0;
60
61 /*
62 * No valid mcfg_mem_base by default, and accessing pci config space
63 * in mem-mapped way is disabled.
64 */
65 uint64_t mcfg_mem_base = 0;
66 uint8_t mcfg_bus_start = 0;
67 uint8_t mcfg_bus_end = 0xff;
68
69 /*
70 * Maximum offset in config space when not using MMIO
71 */
72 uint_t pci_iocfg_max_offset = 0xff;
73
74 /*
75 * These function pointers lead to the actual implementation routines
76 * for configuration space access. Normally they lead to either the
77 * pci_mech1_* or pci_mech2_* routines, but they can also lead to
78 * routines that work around chipset bugs.
79 * These functions are accessing pci config space via I/O way.
80 * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
81 * which also provide accessing pci config space via mem-mapped way.
82 */
83 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
84 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
85 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
86 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
87 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
88 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
89
90 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
91
92 /*
93 * Internal routines
94 */
95 static int pci_check(void);
96
97 #if !defined(__xpv)
98 static int pci_check_bios(void);
99 static int pci_get_cfg_type(void);
100 #endif
101
102 /* for legacy io-based config space access */
103 kmutex_t pcicfg_mutex;
104
105 /* for mmio-based config space access */
106 kmutex_t pcicfg_mmio_mutex;
107
108 /* ..except Orion and Neptune, which have to have their own */
109 kmutex_t pcicfg_chipset_mutex;
110
111 void
pci_cfgspace_init(void)112 pci_cfgspace_init(void)
113 {
114 mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN,
115 (ddi_iblock_cookie_t)ipltospl(15));
116 mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN,
117 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
118 mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
119 (ddi_iblock_cookie_t)ipltospl(15));
120 if (!pci_check()) {
121 mutex_destroy(&pcicfg_mutex);
122 mutex_destroy(&pcicfg_mmio_mutex);
123 mutex_destroy(&pcicfg_chipset_mutex);
124 }
125 }
126
127 /*
128 * This code determines if this system supports PCI/PCIE and which
129 * type of configuration access method is used
130 */
131 static int
pci_check(void)132 pci_check(void)
133 {
134 uint64_t ecfginfo[4];
135
136 /*
137 * Only do this once. NB: If this is not a PCI system, and we
138 * get called twice, we can't detect it and will probably die
139 * horribly when we try to ask the BIOS whether PCI is present.
140 * This code is safe *ONLY* during system startup when the
141 * BIOS is still available.
142 */
143 if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN)
144 return (TRUE);
145
146 #if defined(__xpv)
147 /*
148 * only support PCI config mechanism 1 in i86xpv. This should be fine
149 * since the other ones are workarounds for old broken H/W which won't
150 * be supported in i86xpv anyway.
151 */
152 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
153 pci_bios_cfg_type = PCI_MECHANISM_1;
154 pci_getb_func = pci_mech1_getb;
155 pci_getw_func = pci_mech1_getw;
156 pci_getl_func = pci_mech1_getl;
157 pci_putb_func = pci_mech1_putb;
158 pci_putw_func = pci_mech1_putw;
159 pci_putl_func = pci_mech1_putl;
160
161 /*
162 * Since we can't get the BIOS info in i86xpv, we will do an
163 * exhaustive search of all PCI buses. We have to do this until
164 * we start using the PCI information in ACPI.
165 */
166 pci_bios_maxbus = pci_max_nbus;
167 }
168 #else /* !__xpv */
169
170 pci_bios_cfg_type = pci_check_bios();
171
172 if (pci_bios_cfg_type == PCI_MECHANISM_NONE) {
173 /*
174 * Default to mechanism 1, and scan all PCI buses
175 */
176 pci_bios_cfg_type = PCI_MECHANISM_1;
177 pci_bios_maxbus = pci_max_nbus;
178 }
179
180 switch (pci_get_cfg_type()) {
181 case PCI_MECHANISM_1:
182 if (pci_is_broken_orion()) {
183 pci_getb_func = pci_orion_getb;
184 pci_getw_func = pci_orion_getw;
185 pci_getl_func = pci_orion_getl;
186 pci_putb_func = pci_orion_putb;
187 pci_putw_func = pci_orion_putw;
188 pci_putl_func = pci_orion_putl;
189 } else if (pci_check_amd_ioecs()) {
190 pci_getb_func = pci_mech1_amd_getb;
191 pci_getw_func = pci_mech1_amd_getw;
192 pci_getl_func = pci_mech1_amd_getl;
193 pci_putb_func = pci_mech1_amd_putb;
194 pci_putw_func = pci_mech1_amd_putw;
195 pci_putl_func = pci_mech1_amd_putl;
196 pci_iocfg_max_offset = 0xfff;
197 } else {
198 pci_getb_func = pci_mech1_getb;
199 pci_getw_func = pci_mech1_getw;
200 pci_getl_func = pci_mech1_getl;
201 pci_putb_func = pci_mech1_putb;
202 pci_putw_func = pci_mech1_putw;
203 pci_putl_func = pci_mech1_putl;
204 }
205 break;
206
207 case PCI_MECHANISM_2:
208 if (pci_check_neptune()) {
209 /*
210 * The BIOS for some systems with the Intel
211 * Neptune chipset seem to default to #2 even
212 * though the chipset can do #1. Override
213 * the BIOS so that MP systems will work
214 * correctly.
215 */
216
217 pci_getb_func = pci_neptune_getb;
218 pci_getw_func = pci_neptune_getw;
219 pci_getl_func = pci_neptune_getl;
220 pci_putb_func = pci_neptune_putb;
221 pci_putw_func = pci_neptune_putw;
222 pci_putl_func = pci_neptune_putl;
223 } else {
224 pci_getb_func = pci_mech2_getb;
225 pci_getw_func = pci_mech2_getw;
226 pci_getl_func = pci_mech2_getl;
227 pci_putb_func = pci_mech2_putb;
228 pci_putw_func = pci_mech2_putw;
229 pci_putl_func = pci_mech2_putl;
230 }
231 break;
232
233 default:
234 return (FALSE);
235 }
236 #endif /* __xpv */
237
238 /*
239 * Try to get a valid mcfg_mem_base in early boot
240 * If failed, leave mem-mapped pci config space accessing disabled
241 * until pci boot code (pci_autoconfig) makes sure this is a PCIE
242 * platform.
243 */
244 if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
245 mcfg_mem_base = ecfginfo[0];
246 mcfg_bus_start = ecfginfo[2];
247 mcfg_bus_end = ecfginfo[3];
248 }
249
250 /* See pci_cfgacc.c */
251 pci_cfgacc_acc_p = pci_cfgacc_acc;
252
253 return (TRUE);
254 }
255
256 #if !defined(__xpv)
257
258 static int
pci_check_bios(void)259 pci_check_bios(void)
260 {
261 struct bop_regs regs;
262 uint32_t carryflag;
263 uint16_t ax, dx;
264
265 /*
266 * This mechanism uses a legacy BIOS call to detect PCI configuration,
267 * but such calls are not available on systems with UEFI firmware.
268 * For UEFI systems we must assume some reasonable defaults and scan
269 * all possible buses.
270 */
271 if (BOP_GETPROPLEN(bootops, "efi-systab") > 0) {
272 pci_bios_mech = 1;
273 pci_bios_vers = 0;
274 pci_bios_maxbus = pci_max_nbus;
275 return (PCI_MECHANISM_1);
276 }
277
278 bzero(®s, sizeof (regs));
279 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
280
281 BOP_DOINT(bootops, 0x1a, ®s);
282 carryflag = regs.eflags & PS_C;
283 ax = regs.eax.word.ax;
284 dx = regs.edx.word.dx;
285
286 /* the carry flag must not be set */
287 if (carryflag != 0)
288 return (PCI_MECHANISM_NONE);
289
290 if (dx != ('P' | 'C'<<8))
291 return (PCI_MECHANISM_NONE);
292
293 /* ah (the high byte of ax) must be zero */
294 if ((ax & 0xff00) != 0)
295 return (PCI_MECHANISM_NONE);
296
297 pci_bios_mech = (ax & 0x3);
298 pci_bios_vers = regs.ebx.word.bx;
299
300 /*
301 * Several BIOS implementations have known problems where they don't end
302 * up correctly telling us to scan all PCI buses in the system. In
303 * particular, many on-die CPU PCI devices are on a last bus that is
304 * sometimes not enumerated. As such, do not trust the BIOS.
305 */
306 pci_bios_maxbus = pci_max_nbus;
307
308 switch (pci_bios_mech) {
309 default: /* ?!? */
310 case 0: /* supports neither? */
311 return (PCI_MECHANISM_NONE);
312
313 case 1:
314 case 3: /* supports both */
315 return (PCI_MECHANISM_1);
316
317 case 2:
318 return (PCI_MECHANISM_2);
319 }
320 }
321
322 static int
pci_get_cfg_type(void)323 pci_get_cfg_type(void)
324 {
325 /* Check to see if the config mechanism has been set in /etc/system */
326 switch (PCI_CFG_TYPE) {
327 default:
328 case 0:
329 break;
330 case 1:
331 return (PCI_MECHANISM_1);
332 case 2:
333 return (PCI_MECHANISM_2);
334 case -1:
335 return (PCI_MECHANISM_NONE);
336 }
337
338 /* call one of the PCI detection algorithms */
339 switch (PCI_PROBE_TYPE) {
340 default:
341 case 0:
342 /* From pci_check() and pci_check_bios() */
343 return (pci_bios_cfg_type);
344 case -1:
345 return (PCI_MECHANISM_NONE);
346 }
347 }
348
349 #endif /* __xpv */
350