1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 /* Armada 8k DesignWare PCIe driver */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/proc.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/sysctl.h>
41
42 #include <machine/bus.h>
43 #include <machine/intr.h>
44 #include <machine/resource.h>
45
46 #include <dev/clk/clk.h>
47 #include <dev/phy/phy.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/ofw/ofw_pci.h>
51 #include <dev/ofw/ofwpci.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pcib_private.h>
55 #include <dev/pci/pci_dw.h>
56
57 #include "pcib_if.h"
58 #include "pci_dw_if.h"
59
60 #define MV_GLOBAL_CONTROL_REG 0x8000
61 #define PCIE_APP_LTSSM_EN (1 << 2)
62
63 #define MV_GLOBAL_STATUS_REG 0x8008
64 #define MV_STATUS_RDLH_LINK_UP (1 << 1)
65 #define MV_STATUS_PHY_LINK_UP (1 << 9)
66
67 #define MV_INT_CAUSE1 0x801C
68 #define MV_INT_MASK1 0x8020
69 #define INT_A_ASSERT_MASK (1 << 9)
70 #define INT_B_ASSERT_MASK (1 << 10)
71 #define INT_C_ASSERT_MASK (1 << 11)
72 #define INT_D_ASSERT_MASK (1 << 12)
73
74 #define MV_INT_CAUSE2 0x8024
75 #define MV_INT_MASK2 0x8028
76 #define MV_ERR_INT_CAUSE 0x802C
77 #define MV_ERR_INT_MASK 0x8030
78
79 #define MV_ARCACHE_TRC_REG 0x8050
80 #define MV_AWCACHE_TRC_REG 0x8054
81 #define MV_ARUSER_REG 0x805C
82 #define MV_AWUSER_REG 0x8060
83
84 #define MV_MAX_LANES 8
85 struct pci_mv_softc {
86 struct pci_dw_softc dw_sc;
87 device_t dev;
88 phandle_t node;
89 struct resource *irq_res;
90 void *intr_cookie;
91 phy_t phy[MV_MAX_LANES];
92 clk_t clk_core;
93 clk_t clk_reg;
94 };
95
96 /* Compatible devices. */
97 static struct ofw_compat_data compat_data[] = {
98 {"marvell,armada8k-pcie", 1},
99 {NULL, 0},
100 };
101
102 static int
pci_mv_phy_init(struct pci_mv_softc * sc)103 pci_mv_phy_init(struct pci_mv_softc *sc)
104 {
105 int i, rv;
106
107 for (i = 0; i < MV_MAX_LANES; i++) {
108 rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i]));
109 if (rv != 0 && rv != ENOENT) {
110 device_printf(sc->dev, "Cannot get phy[%d]\n", i);
111 /* XXX revert when phy driver will be implemented */
112 #if 0
113 goto fail;
114 #else
115 continue;
116 #endif
117 }
118 if (sc->phy[i] == NULL)
119 continue;
120 rv = phy_enable(sc->phy[i]);
121 if (rv != 0) {
122 device_printf(sc->dev, "Cannot enable phy[%d]\n", i);
123 goto fail;
124 }
125 }
126 return (0);
127
128 fail:
129 for (i = 0; i < MV_MAX_LANES; i++) {
130 if (sc->phy[i] == NULL)
131 continue;
132 phy_release(sc->phy[i]);
133 }
134
135 return (rv);
136 }
137
138 static void
pci_mv_init(struct pci_mv_softc * sc)139 pci_mv_init(struct pci_mv_softc *sc)
140 {
141 uint32_t reg;
142
143 /* Set device configuration to RC */
144 reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG);
145 reg &= ~0x000000F0;
146 reg |= 0x000000040;
147 pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg);
148
149 /* AxCache master transaction attribures */
150 pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511);
151 pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311);
152
153 /* AxDomain master transaction attribures */
154 pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002);
155 pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002);
156
157 /* Enable all INTx interrupt (virtuual) pins */
158 reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1);
159 reg |= INT_A_ASSERT_MASK | INT_B_ASSERT_MASK |
160 INT_C_ASSERT_MASK | INT_D_ASSERT_MASK;
161 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg);
162
163 /* Enable local interrupts */
164 pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF);
165 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0x0001FE00);
166 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0x00000000);
167 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF);
168 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF);
169
170 /* Errors have own interrupt, not yet populated in DTt */
171 pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0);
172 }
173
pci_mv_intr(void * arg)174 static int pci_mv_intr(void *arg)
175 {
176 struct pci_mv_softc *sc = arg;
177 uint32_t cause1, cause2;
178
179 /* Ack all interrups */
180 cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1);
181 cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2);
182
183 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1);
184 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2);
185 return (FILTER_HANDLED);
186 }
187
188 static int
pci_mv_get_link(device_t dev,bool * status)189 pci_mv_get_link(device_t dev, bool *status)
190 {
191 uint32_t reg;
192
193 reg = pci_dw_dbi_rd4(dev, MV_GLOBAL_STATUS_REG);
194 if ((reg & (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) ==
195 (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP))
196 *status = true;
197 else
198 *status = false;
199
200 return (0);
201 }
202
203 static int
pci_mv_probe(device_t dev)204 pci_mv_probe(device_t dev)
205 {
206
207 if (!ofw_bus_status_okay(dev))
208 return (ENXIO);
209
210 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
211 return (ENXIO);
212
213 device_set_desc(dev, "Marvell Armada8K PCI-E Controller");
214 return (BUS_PROBE_DEFAULT);
215 }
216
217 static int
pci_mv_attach(device_t dev)218 pci_mv_attach(device_t dev)
219 {
220 struct resource_map_request req;
221 struct resource_map map;
222 struct pci_mv_softc *sc;
223 phandle_t node;
224 int rv;
225 int rid;
226
227 sc = device_get_softc(dev);
228 node = ofw_bus_get_node(dev);
229 sc->dev = dev;
230 sc->node = node;
231
232 rid = 0;
233 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
234 RF_ACTIVE | RF_UNMAPPED);
235 if (sc->dw_sc.dbi_res == NULL) {
236 device_printf(dev, "Cannot allocate DBI memory\n");
237 rv = ENXIO;
238 goto out;
239 }
240
241 resource_init_map_request(&req);
242 req.memattr = VM_MEMATTR_DEVICE_NP;
243 rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->dw_sc.dbi_res, &req,
244 &map);
245 if (rv != 0) {
246 device_printf(dev, "could not map memory.\n");
247 return (rv);
248 }
249 rman_set_mapping(sc->dw_sc.dbi_res, &map);
250
251 /* PCI interrupt */
252 rid = 0;
253 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
254 RF_ACTIVE | RF_SHAREABLE);
255 if (sc->irq_res == NULL) {
256 device_printf(dev, "Cannot allocate IRQ resources\n");
257 rv = ENXIO;
258 goto out;
259 }
260
261 /* Clocks */
262 rv = clk_get_by_ofw_name(sc->dev, 0, "core", &sc->clk_core);
263 if (rv != 0) {
264 device_printf(sc->dev, "Cannot get 'core' clock\n");
265 rv = ENXIO;
266 goto out;
267 }
268
269 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);
270 if (rv != 0) {
271 device_printf(sc->dev, "Cannot get 'reg' clock\n");
272 rv = ENXIO;
273 goto out;
274 }
275
276 rv = clk_enable(sc->clk_core);
277 if (rv != 0) {
278 device_printf(sc->dev, "Cannot enable 'core' clock\n");
279 rv = ENXIO;
280 goto out;
281 }
282
283 rv = clk_enable(sc->clk_reg);
284 if (rv != 0) {
285 device_printf(sc->dev, "Cannot enable 'reg' clock\n");
286 rv = ENXIO;
287 goto out;
288 }
289
290 rv = pci_mv_phy_init(sc);
291 if (rv)
292 goto out;
293
294 rv = pci_dw_init(dev);
295 if (rv != 0)
296 goto out;
297
298 pci_mv_init(sc);
299
300 /* Setup interrupt */
301 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
302 pci_mv_intr, NULL, sc, &sc->intr_cookie)) {
303 device_printf(dev, "cannot setup interrupt handler\n");
304 rv = ENXIO;
305 goto out;
306 }
307
308 bus_attach_children(dev);
309 return (0);
310 out:
311 /* XXX Cleanup */
312 return (rv);
313 }
314
315 static device_method_t pci_mv_methods[] = {
316 /* Device interface */
317 DEVMETHOD(device_probe, pci_mv_probe),
318 DEVMETHOD(device_attach, pci_mv_attach),
319
320 DEVMETHOD(pci_dw_get_link, pci_mv_get_link),
321
322 DEVMETHOD_END
323 };
324
325 DEFINE_CLASS_1(pcib, pci_mv_driver, pci_mv_methods,
326 sizeof(struct pci_mv_softc), pci_dw_driver);
327 DRIVER_MODULE( pci_mv, simplebus, pci_mv_driver, NULL, NULL);
328