1 /*-
2 * Copyright (C) 2018 Cavium Inc.
3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
4 * Copyright (c) 2014 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * This software was developed by Semihalf under
8 * the sponsorship of the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /* Generic ECAM PCIe driver */
33
34 #include <sys/cdefs.h>
35 #include "opt_platform.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/rman.h>
42 #include <sys/module.h>
43 #include <sys/bus.h>
44 #include <sys/endian.h>
45 #include <sys/cpuset.h>
46 #include <sys/rwlock.h>
47
48 #include <contrib/dev/acpica/include/acpi.h>
49 #include <contrib/dev/acpica/include/accommon.h>
50
51 #include <dev/acpica/acpivar.h>
52 #include <dev/acpica/acpi_pcibvar.h>
53
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcib_private.h>
57 #include <dev/pci/pci_host_generic.h>
58 #include <dev/pci/pci_host_generic_acpi.h>
59
60 #include <machine/cpu.h>
61 #include <machine/bus.h>
62 #include <machine/intr.h>
63
64 #include "pcib_if.h"
65 #include "acpi_bus_if.h"
66
67 /* Assembling ECAM Configuration Address */
68 #define PCIE_BUS_SHIFT 20
69 #define PCIE_SLOT_SHIFT 15
70 #define PCIE_FUNC_SHIFT 12
71 #define PCIE_BUS_MASK 0xFF
72 #define PCIE_SLOT_MASK 0x1F
73 #define PCIE_FUNC_MASK 0x07
74 #define PCIE_REG_MASK 0xFFF
75
76 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
77 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
78 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
79 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
80 ((reg) & PCIE_REG_MASK))
81
82 #define PCI_IO_WINDOW_OFFSET 0x1000
83
84 #define SPACE_CODE_SHIFT 24
85 #define SPACE_CODE_MASK 0x3
86 #define SPACE_CODE_IO_SPACE 0x1
87 #define PROPS_CELL_SIZE 1
88 #define PCI_ADDR_CELL_SIZE 2
89
90 static struct {
91 char oem_id[ACPI_OEM_ID_SIZE + 1];
92 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
93 uint32_t quirks;
94 } pci_acpi_quirks[] = {
95 { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
96 { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK },
97 { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK },
98 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK },
99 { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK },
100 { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK },
101 { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK },
102 };
103
104 /* Forward prototypes */
105
106 static int generic_pcie_acpi_probe(device_t dev);
107 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
108 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
109
110 /*
111 * generic_pcie_acpi_probe - look for root bridge flag
112 */
113 static int
generic_pcie_acpi_probe(device_t dev)114 generic_pcie_acpi_probe(device_t dev)
115 {
116 ACPI_DEVICE_INFO *devinfo;
117 ACPI_HANDLE h;
118 int root;
119
120 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
121 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
122 return (ENXIO);
123 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
124 AcpiOsFree(devinfo);
125 if (!root)
126 return (ENXIO);
127
128 device_set_desc(dev, "Generic PCI host controller");
129 return (BUS_PROBE_GENERIC);
130 }
131
132 /*
133 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
134 * 'produced' by this bridge
135 */
136 static ACPI_STATUS
pci_host_generic_acpi_parse_resource(ACPI_RESOURCE * res,void * arg)137 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
138 {
139 device_t dev = (device_t)arg;
140 struct generic_pcie_acpi_softc *sc;
141 rman_res_t min, max, off;
142 int r, restype;
143
144 sc = device_get_softc(dev);
145 r = sc->base.nranges;
146 switch (res->Type) {
147 case ACPI_RESOURCE_TYPE_ADDRESS16:
148 restype = res->Data.Address16.ResourceType;
149 min = res->Data.Address16.Address.Minimum;
150 max = res->Data.Address16.Address.Maximum;
151 break;
152 case ACPI_RESOURCE_TYPE_ADDRESS32:
153 restype = res->Data.Address32.ResourceType;
154 min = res->Data.Address32.Address.Minimum;
155 max = res->Data.Address32.Address.Maximum;
156 off = res->Data.Address32.Address.TranslationOffset;
157 break;
158 case ACPI_RESOURCE_TYPE_ADDRESS64:
159 restype = res->Data.Address64.ResourceType;
160 min = res->Data.Address64.Address.Minimum;
161 max = res->Data.Address64.Address.Maximum;
162 off = res->Data.Address64.Address.TranslationOffset;
163 break;
164 case ACPI_RESOURCE_TYPE_FIXED_MEMORY32:
165 /*
166 * The Microsoft Dev Kit 2023 uses a fixed memory region
167 * for some PCI controllers. For this memory the
168 * ResourceType is ACPI_IO_RANGE meaning we create an IO
169 * resource. As drivers expect it to be a memory resource
170 * force the type here.
171 */
172 restype = ACPI_MEMORY_RANGE;
173 min = res->Data.FixedMemory32.Address;
174 max = res->Data.FixedMemory32.Address +
175 res->Data.FixedMemory32.AddressLength - 1;
176 off = 0;
177 break;
178 default:
179 return (AE_OK);
180 }
181
182 /* Save detected ranges */
183 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
184 res->Data.Address.ResourceType == ACPI_IO_RANGE) {
185 sc->base.ranges[r].rid = -1;
186 sc->base.ranges[r].pci_base = min;
187 sc->base.ranges[r].phys_base = min + off;
188 sc->base.ranges[r].size = max - min + 1;
189 if (restype == ACPI_MEMORY_RANGE)
190 sc->base.ranges[r].flags |= FLAG_TYPE_MEM;
191 else if (restype == ACPI_IO_RANGE)
192 sc->base.ranges[r].flags |= FLAG_TYPE_IO;
193 sc->base.nranges++;
194 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
195 sc->base.bus_start = min;
196 sc->base.bus_end = max;
197 }
198 return (AE_OK);
199 }
200
201 static void
pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc * sc,ACPI_TABLE_HEADER * hdr)202 pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc,
203 ACPI_TABLE_HEADER *hdr)
204 {
205 size_t i;
206
207 for (i = 0; i < nitems(pci_acpi_quirks); i++) {
208 if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id,
209 ACPI_OEM_ID_SIZE) != 0)
210 continue;
211 if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id,
212 ACPI_OEM_TABLE_ID_SIZE) != 0)
213 continue;
214 sc->base.quirks |= pci_acpi_quirks[i].quirks;
215 }
216 }
217
218 static int
pci_host_acpi_get_ecam_resource(device_t dev)219 pci_host_acpi_get_ecam_resource(device_t dev)
220 {
221 struct generic_pcie_acpi_softc *sc;
222 struct acpi_device *ad;
223 struct resource_list *rl;
224 ACPI_TABLE_HEADER *hdr;
225 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
226 ACPI_HANDLE handle;
227 ACPI_STATUS status;
228 rman_res_t base, start, end;
229 int found, val;
230
231 sc = device_get_softc(dev);
232 handle = acpi_get_handle(dev);
233
234 /* Try MCFG first */
235 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
236 if (ACPI_SUCCESS(status)) {
237 found = FALSE;
238 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
239 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
240 while (mcfg_entry < mcfg_end && !found) {
241 if (mcfg_entry->PciSegment == sc->base.ecam &&
242 mcfg_entry->StartBusNumber <= sc->base.bus_start &&
243 mcfg_entry->EndBusNumber >= sc->base.bus_start)
244 found = TRUE;
245 else
246 mcfg_entry++;
247 }
248 if (found) {
249 if (mcfg_entry->EndBusNumber < sc->base.bus_end)
250 sc->base.bus_end = mcfg_entry->EndBusNumber;
251 base = mcfg_entry->Address;
252 } else {
253 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
254 sc->base.bus_start, sc->base.bus_end);
255 return (ENXIO);
256 }
257 pci_host_acpi_get_oem_quirks(sc, hdr);
258 if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK)
259 device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
260 } else {
261 status = acpi_GetInteger(handle, "_CBA", &val);
262 if (ACPI_SUCCESS(status))
263 base = val;
264 else
265 return (ENXIO);
266 }
267
268 /* add as MEM rid 0 */
269 ad = device_get_ivars(dev);
270 rl = &ad->ad_rl;
271 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
272 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
273 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
274 if (bootverbose)
275 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
276 sc->base.bus_start, sc->base.bus_end, start, end);
277 return (0);
278 }
279
280 int
pci_host_generic_acpi_init(device_t dev)281 pci_host_generic_acpi_init(device_t dev)
282 {
283 struct generic_pcie_acpi_softc *sc;
284 ACPI_HANDLE handle;
285 ACPI_STATUS status;
286 int error;
287
288 sc = device_get_softc(dev);
289 handle = acpi_get_handle(dev);
290
291 acpi_pcib_osc(dev, &sc->osc_ctl, 0);
292
293 /* Get Start bus number for the PCI host bus is from _BBN method */
294 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
295 if (ACPI_FAILURE(status)) {
296 device_printf(dev, "No _BBN, using start bus 0\n");
297 sc->base.bus_start = 0;
298 }
299 sc->base.bus_end = 255;
300
301 /* Get PCI Segment (domain) needed for MCFG lookup */
302 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
303 if (ACPI_FAILURE(status)) {
304 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
305 sc->base.ecam = 0;
306 }
307
308 /* Bus decode ranges */
309 status = AcpiWalkResources(handle, "_CRS",
310 pci_host_generic_acpi_parse_resource, (void *)dev);
311 if (ACPI_FAILURE(status))
312 return (ENXIO);
313
314 /* Coherency attribute */
315 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
316 sc->base.coherent = 0;
317 if (bootverbose)
318 device_printf(dev, "Bus is%s cache-coherent\n",
319 sc->base.coherent ? "" : " not");
320
321 /* add config space resource */
322 pci_host_acpi_get_ecam_resource(dev);
323 acpi_pcib_fetch_prt(dev, &sc->ap_prt);
324
325 error = pci_host_generic_core_attach(dev);
326 if (error != 0)
327 return (error);
328
329 return (0);
330 }
331
332 static int
pci_host_generic_acpi_attach(device_t dev)333 pci_host_generic_acpi_attach(device_t dev)
334 {
335 int error;
336
337 error = pci_host_generic_acpi_init(dev);
338 if (error != 0)
339 return (error);
340
341 device_add_child(dev, "pci", DEVICE_UNIT_ANY);
342 bus_attach_children(dev);
343 return (0);
344 }
345
346 static int
generic_pcie_acpi_read_ivar(device_t dev,device_t child,int index,uintptr_t * result)347 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
348 uintptr_t *result)
349 {
350 ACPI_HANDLE handle;
351
352 switch (index) {
353 case ACPI_IVAR_HANDLE:
354 handle = acpi_get_handle(dev);
355 *result = (uintptr_t)handle;
356 return (0);
357 }
358
359 return (generic_pcie_read_ivar(dev, child, index, result));
360 }
361
362 static int
generic_pcie_acpi_route_interrupt(device_t bus,device_t dev,int pin)363 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
364 {
365 struct generic_pcie_acpi_softc *sc;
366
367 sc = device_get_softc(bus);
368 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
369 }
370
371 static u_int
generic_pcie_get_xref(device_t pci,device_t child)372 generic_pcie_get_xref(device_t pci, device_t child)
373 {
374 struct generic_pcie_acpi_softc *sc;
375 uintptr_t rid;
376 u_int xref, devid;
377 int err;
378
379 sc = device_get_softc(pci);
380 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
381 if (err != 0)
382 return (ACPI_MSI_XREF);
383 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
384 if (err != 0)
385 return (ACPI_MSI_XREF);
386 return (xref);
387 }
388
389 static u_int
generic_pcie_map_id(device_t pci,device_t child,uintptr_t * id)390 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id)
391 {
392 struct generic_pcie_acpi_softc *sc;
393 uintptr_t rid;
394 u_int xref, devid;
395 int err;
396
397 sc = device_get_softc(pci);
398 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
399 if (err != 0)
400 return (err);
401 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid);
402 if (err == 0)
403 *id = devid;
404 else
405 *id = rid; /* RID not in IORT, likely FW bug, ignore */
406 return (0);
407 }
408
409 static int
generic_pcie_get_iommu(device_t pci,device_t child,uintptr_t * id)410 generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id)
411 {
412 struct generic_pcie_acpi_softc *sc;
413 struct pci_id_ofw_iommu *iommu;
414 u_int iommu_sid, iommu_xref;
415 uintptr_t rid;
416 int err;
417
418 iommu = (struct pci_id_ofw_iommu *)id;
419
420 sc = device_get_softc(pci);
421 err = pcib_get_id(pci, child, PCI_ID_RID, &rid);
422 if (err != 0)
423 return (err);
424 err = acpi_iort_map_pci_smmuv3(sc->base.ecam, rid, &iommu_xref,
425 &iommu_sid);
426 if (err == 0) {
427 iommu->id = iommu_sid;
428 iommu->xref = iommu_xref;
429 }
430
431 return (err);
432 }
433
434 static int
generic_pcie_acpi_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)435 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
436 int maxcount, int *irqs)
437 {
438
439 #if defined(INTRNG)
440 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child),
441 count, maxcount, irqs));
442 #else
443 return (ENXIO);
444 #endif
445 }
446
447 static int
generic_pcie_acpi_release_msi(device_t pci,device_t child,int count,int * irqs)448 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count,
449 int *irqs)
450 {
451
452 #if defined(INTRNG)
453 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child),
454 count, irqs));
455 #else
456 return (ENXIO);
457 #endif
458 }
459
460 static int
generic_pcie_acpi_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)461 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
462 uint32_t *data)
463 {
464
465 #if defined(INTRNG)
466 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq,
467 addr, data));
468 #else
469 return (ENXIO);
470 #endif
471 }
472
473 static int
generic_pcie_acpi_alloc_msix(device_t pci,device_t child,int * irq)474 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq)
475 {
476
477 #if defined(INTRNG)
478 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child),
479 irq));
480 #else
481 return (ENXIO);
482 #endif
483 }
484
485 static int
generic_pcie_acpi_release_msix(device_t pci,device_t child,int irq)486 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq)
487 {
488
489 #if defined(INTRNG)
490 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child),
491 irq));
492 #else
493 return (ENXIO);
494 #endif
495 }
496
497 static int
generic_pcie_acpi_get_id(device_t pci,device_t child,enum pci_id_type type,uintptr_t * id)498 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
499 uintptr_t *id)
500 {
501 if (type == PCI_ID_OFW_IOMMU)
502 return (generic_pcie_get_iommu(pci, child, id));
503
504 if (type == PCI_ID_MSI)
505 return (generic_pcie_map_id(pci, child, id));
506
507 return (pcib_get_id(pci, child, type, id));
508 }
509
510 static int
generic_pcie_acpi_request_feature(device_t pcib,device_t dev,enum pci_feature feature)511 generic_pcie_acpi_request_feature(device_t pcib, device_t dev,
512 enum pci_feature feature)
513 {
514 struct generic_pcie_acpi_softc *sc;
515 uint32_t osc_ctl;
516
517 sc = device_get_softc(pcib);
518
519 switch (feature) {
520 case PCI_FEATURE_HP:
521 osc_ctl = PCIM_OSC_CTL_PCIE_HP;
522 break;
523 case PCI_FEATURE_AER:
524 osc_ctl = PCIM_OSC_CTL_PCIE_AER;
525 break;
526 default:
527 return (EINVAL);
528 }
529
530 return (acpi_pcib_osc(pcib, &sc->osc_ctl, osc_ctl));
531 }
532
533
534 static device_method_t generic_pcie_acpi_methods[] = {
535 DEVMETHOD(device_probe, generic_pcie_acpi_probe),
536 DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
537 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
538
539 /* pcib interface */
540 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
541 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
542 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
543 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
544 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
545 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
546 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id),
547 DEVMETHOD(pcib_request_feature, generic_pcie_acpi_request_feature),
548
549 DEVMETHOD_END
550 };
551
552 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods,
553 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver);
554
555 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, 0, 0);
556