1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 /*
27 * PCI nexus driver interface
28 */
29
30 #include <sys/types.h>
31 #include <sys/conf.h> /* nulldev */
32 #include <sys/stat.h> /* devctl */
33 #include <sys/kmem.h>
34 #include <sys/async.h> /* ecc_flt for pci_ecc.h */
35 #include <sys/sunddi.h>
36 #include <sys/sunndi.h>
37 #include <sys/ndifm.h>
38 #include <sys/ontrap.h>
39 #include <sys/ddi_impldefs.h>
40 #include <sys/ddi_subrdefs.h>
41 #include <sys/epm.h>
42 #include <sys/hotplug/pci/pcihp.h>
43 #include <sys/pci/pci_tools_ext.h>
44 #include <sys/spl.h>
45 #include <sys/pci/pci_obj.h>
46
47 /*LINTLIBRARY*/
48
49 /*
50 * function prototype for hotplug routine:
51 */
52 static void
53 pci_init_hotplug(struct pci *);
54
55 /*
56 * function prototypes for dev ops routines:
57 */
58 static int pci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
59 static int pci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
60 static int pci_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
61 void *arg, void **result);
62 static int pci_ctlops_poke(pci_t *pci_p, peekpoke_ctlops_t *in_args);
63 static int pci_ctlops_peek(pci_t *pci_p, peekpoke_ctlops_t *in_args,
64 void *result);
65 static off_t get_reg_set_size(dev_info_t *child, int rnumber);
66
67 /*
68 * bus ops and dev ops structures:
69 */
70 static struct bus_ops pci_bus_ops = {
71 BUSO_REV,
72 pci_map,
73 0,
74 0,
75 0,
76 i_ddi_map_fault,
77 pci_dma_setup,
78 pci_dma_allochdl,
79 pci_dma_freehdl,
80 pci_dma_bindhdl,
81 pci_dma_unbindhdl,
82 pci_dma_sync,
83 pci_dma_win,
84 pci_dma_ctlops,
85 pci_ctlops,
86 ddi_bus_prop_op,
87 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */
88 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */
89 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */
90 ndi_post_event, /* (*bus_post_event)(); */
91 NULL, /* (*bus_intr_ctl)(); */
92 NULL, /* (*bus_config)(); */
93 NULL, /* (*bus_unconfig)(); */
94 pci_fm_init_child, /* (*bus_fm_init)(); */
95 NULL, /* (*bus_fm_fini)(); */
96 pci_bus_enter, /* (*bus_fm_access_enter)(); */
97 pci_bus_exit, /* (*bus_fm_access_fini)(); */
98 NULL, /* (*bus_power)(); */
99 pci_intr_ops /* (*bus_intr_op)(); */
100 };
101
102 extern struct cb_ops pci_cb_ops;
103
104 static struct dev_ops pci_ops = {
105 DEVO_REV,
106 0,
107 pci_info,
108 nulldev,
109 0,
110 pci_attach,
111 pci_detach,
112 nodev,
113 &pci_cb_ops,
114 &pci_bus_ops,
115 0,
116 ddi_quiesce_not_supported, /* devo_quiesce */
117 };
118
119 /*
120 * module definitions:
121 */
122 #include <sys/modctl.h>
123 extern struct mod_ops mod_driverops;
124
125 static struct modldrv modldrv = {
126 &mod_driverops, /* Type of module - driver */
127 "Sun4u Host to PCI nexus driver", /* Name of module. */
128 &pci_ops, /* driver ops */
129 };
130
131 static struct modlinkage modlinkage = {
132 MODREV_1, (void *)&modldrv, NULL
133 };
134
135 /*
136 * driver global data:
137 */
138 void *per_pci_state; /* per-pbm soft state pointer */
139 void *per_pci_common_state; /* per-psycho soft state pointer */
140 kmutex_t pci_global_mutex; /* attach/detach common struct lock */
141 errorq_t *pci_ecc_queue = NULL; /* per-system ecc handling queue */
142 extern errorq_t *pci_target_queue;
143 struct cb_ops *pcihp_ops = NULL; /* hotplug module cb ops */
144
145 extern void pci_child_cfg_save(dev_info_t *dip);
146 extern void pci_child_cfg_restore(dev_info_t *dip);
147
148 int
_init(void)149 _init(void)
150 {
151 int e;
152
153 /*
154 * Initialize per-pci bus soft state pointer.
155 */
156 e = ddi_soft_state_init(&per_pci_state, sizeof (pci_t), 1);
157 if (e != 0)
158 return (e);
159
160 /*
161 * Initialize per-psycho soft state pointer.
162 */
163 e = ddi_soft_state_init(&per_pci_common_state,
164 sizeof (pci_common_t), 1);
165 if (e != 0) {
166 ddi_soft_state_fini(&per_pci_state);
167 return (e);
168 }
169
170 /*
171 * Initialize global mutexes.
172 */
173 mutex_init(&pci_global_mutex, NULL, MUTEX_DRIVER, NULL);
174 pci_reloc_init();
175
176 /*
177 * Create the performance kstats.
178 */
179 pci_kstat_init();
180
181 /*
182 * Install the module.
183 */
184 e = mod_install(&modlinkage);
185 if (e != 0) {
186 ddi_soft_state_fini(&per_pci_state);
187 ddi_soft_state_fini(&per_pci_common_state);
188 mutex_destroy(&pci_global_mutex);
189 }
190 return (e);
191 }
192
193 int
_fini(void)194 _fini(void)
195 {
196 int e;
197
198 /*
199 * Remove the module.
200 */
201 e = mod_remove(&modlinkage);
202 if (e != 0)
203 return (e);
204
205 /*
206 * Destroy pci_ecc_queue, and set it to NULL.
207 */
208 if (pci_ecc_queue)
209 errorq_destroy(pci_ecc_queue);
210
211 pci_ecc_queue = NULL;
212
213 /*
214 * Destroy pci_target_queue, and set it to NULL.
215 */
216 if (pci_target_queue)
217 errorq_destroy(pci_target_queue);
218
219 pci_target_queue = NULL;
220
221 /*
222 * Destroy the performance kstats.
223 */
224 pci_kstat_fini();
225
226 /*
227 * Free the per-pci and per-psycho soft state info and destroy
228 * mutex for per-psycho soft state.
229 */
230 ddi_soft_state_fini(&per_pci_state);
231 ddi_soft_state_fini(&per_pci_common_state);
232 mutex_destroy(&pci_global_mutex);
233 pci_reloc_fini();
234 return (e);
235 }
236
237 int
_info(struct modinfo * modinfop)238 _info(struct modinfo *modinfop)
239 {
240 return (mod_info(&modlinkage, modinfop));
241 }
242
243 /*ARGSUSED*/
244 static int
pci_info(dev_info_t * dip,ddi_info_cmd_t infocmd,void * arg,void ** result)245 pci_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
246 {
247 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor((dev_t)arg));
248 pci_t *pci_p = get_pci_soft_state(instance);
249
250 /* allow hotplug to deal with ones it manages */
251 if (pci_p && (pci_p->hotplug_capable == B_TRUE))
252 return (pcihp_info(dip, infocmd, arg, result));
253
254 /* non-hotplug or not attached */
255 switch (infocmd) {
256 case DDI_INFO_DEVT2INSTANCE:
257 *result = (void *)(uintptr_t)instance;
258 return (DDI_SUCCESS);
259
260 case DDI_INFO_DEVT2DEVINFO:
261 if (pci_p == NULL)
262 return (DDI_FAILURE);
263 *result = (void *)pci_p->pci_dip;
264 return (DDI_SUCCESS);
265
266 default:
267 return (DDI_FAILURE);
268 }
269 }
270
271
272 /* device driver entry points */
273 /*
274 * attach entry point:
275 */
276 static int
pci_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)277 pci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
278 {
279 pci_t *pci_p; /* per bus state pointer */
280 int instance = ddi_get_instance(dip);
281
282 switch (cmd) {
283 case DDI_ATTACH:
284 DEBUG0(DBG_ATTACH, dip, "DDI_ATTACH\n");
285
286 /*
287 * Allocate and get the per-pci soft state structure.
288 */
289 if (alloc_pci_soft_state(instance) != DDI_SUCCESS) {
290 cmn_err(CE_WARN, "%s%d: can't allocate pci state",
291 ddi_driver_name(dip), instance);
292 goto err_bad_pci_softstate;
293 }
294 pci_p = get_pci_soft_state(instance);
295 pci_p->pci_dip = dip;
296 mutex_init(&pci_p->pci_mutex, NULL, MUTEX_DRIVER, NULL);
297 pci_p->pci_soft_state = PCI_SOFT_STATE_CLOSED;
298
299 /*
300 * Get key properties of the pci bridge node and
301 * determine it's type (psycho, schizo, etc ...).
302 */
303 if (get_pci_properties(pci_p, dip) == DDI_FAILURE)
304 goto err_bad_pci_prop;
305
306 /*
307 * Map in the registers.
308 */
309 if (map_pci_registers(pci_p, dip) == DDI_FAILURE)
310 goto err_bad_reg_prop;
311
312 if (pci_obj_setup(pci_p) != DDI_SUCCESS)
313 goto err_bad_objs;
314
315 /*
316 * If this PCI leaf has hotplug and this platform
317 * loads hotplug modules then initialize the
318 * hotplug framework.
319 */
320 pci_init_hotplug(pci_p);
321
322 /*
323 * Create the "devctl" node for hotplug support.
324 * For non-hotplug bus, we still need ":devctl" to
325 * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls.
326 */
327 if (pci_p->hotplug_capable == B_FALSE) {
328 if (ddi_create_minor_node(dip, "devctl", S_IFCHR,
329 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
330 DDI_NT_NEXUS, 0) != DDI_SUCCESS)
331 goto err_bad_devctl_node;
332 }
333
334 /*
335 * Create pcitool nodes for register access and interrupt
336 * routing.
337 */
338 if (pcitool_init(dip) != DDI_SUCCESS) {
339 goto err_bad_pcitool_nodes;
340 }
341 ddi_report_dev(dip);
342
343 pci_p->pci_state = PCI_ATTACHED;
344 DEBUG0(DBG_ATTACH, dip, "attach success\n");
345 break;
346
347 err_bad_pcitool_nodes:
348 if (pci_p->hotplug_capable == B_FALSE)
349 ddi_remove_minor_node(dip, "devctl");
350 else
351 (void) pcihp_uninit(dip);
352 err_bad_devctl_node:
353 pci_obj_destroy(pci_p);
354 err_bad_objs:
355 unmap_pci_registers(pci_p);
356 err_bad_reg_prop:
357 free_pci_properties(pci_p);
358 err_bad_pci_prop:
359 mutex_destroy(&pci_p->pci_mutex);
360 free_pci_soft_state(instance);
361 err_bad_pci_softstate:
362 return (DDI_FAILURE);
363
364 case DDI_RESUME:
365 DEBUG0(DBG_ATTACH, dip, "DDI_RESUME\n");
366
367 /*
368 * Make sure the Psycho control registers and IOMMU
369 * are configured properly.
370 */
371 pci_p = get_pci_soft_state(instance);
372 mutex_enter(&pci_p->pci_mutex);
373
374 /*
375 * Make sure this instance has been suspended.
376 */
377 if (pci_p->pci_state != PCI_SUSPENDED) {
378 DEBUG0(DBG_ATTACH, dip, "instance NOT suspended\n");
379 mutex_exit(&pci_p->pci_mutex);
380 return (DDI_FAILURE);
381 }
382 pci_obj_resume(pci_p);
383 pci_p->pci_state = PCI_ATTACHED;
384
385 pci_child_cfg_restore(dip);
386
387 mutex_exit(&pci_p->pci_mutex);
388 break;
389
390 default:
391 DEBUG0(DBG_ATTACH, dip, "unsupported attach op\n");
392 return (DDI_FAILURE);
393 }
394
395 return (DDI_SUCCESS);
396 }
397
398 /*
399 * detach entry point:
400 */
401 static int
pci_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)402 pci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
403 {
404 int instance = ddi_get_instance(dip);
405 pci_t *pci_p = get_pci_soft_state(instance);
406
407 /*
408 * Make sure we are currently attached
409 */
410 if (pci_p->pci_state != PCI_ATTACHED) {
411 DEBUG0(DBG_ATTACH, dip, "failed - instance not attached\n");
412 return (DDI_FAILURE);
413 }
414
415 mutex_enter(&pci_p->pci_mutex);
416
417 switch (cmd) {
418 case DDI_DETACH:
419 DEBUG0(DBG_DETACH, dip, "DDI_DETACH\n");
420
421 if (pci_p->hotplug_capable == B_TRUE)
422 if (pcihp_uninit(dip) == DDI_FAILURE) {
423 mutex_exit(&pci_p->pci_mutex);
424 return (DDI_FAILURE);
425 }
426
427 pcitool_uninit(dip);
428
429 pci_obj_destroy(pci_p);
430
431 /*
432 * Free the pci soft state structure and the rest of the
433 * resources it's using.
434 */
435 free_pci_properties(pci_p);
436 unmap_pci_registers(pci_p);
437 mutex_exit(&pci_p->pci_mutex);
438 mutex_destroy(&pci_p->pci_mutex);
439 free_pci_soft_state(instance);
440
441 /* Free the interrupt-priorities prop if we created it. */
442 {
443 int len;
444
445 if (ddi_getproplen(DDI_DEV_T_ANY, dip,
446 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS,
447 "interrupt-priorities", &len) == DDI_PROP_SUCCESS)
448 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
449 "interrupt-priorities");
450 }
451 return (DDI_SUCCESS);
452
453 case DDI_SUSPEND:
454 pci_child_cfg_save(dip);
455 pci_obj_suspend(pci_p);
456 pci_p->pci_state = PCI_SUSPENDED;
457
458 mutex_exit(&pci_p->pci_mutex);
459 return (DDI_SUCCESS);
460
461 default:
462 DEBUG0(DBG_DETACH, dip, "unsupported detach op\n");
463 mutex_exit(&pci_p->pci_mutex);
464 return (DDI_FAILURE);
465 }
466 }
467
468
469 /* bus driver entry points */
470
471 /*
472 * bus map entry point:
473 *
474 * if map request is for an rnumber
475 * get the corresponding regspec from device node
476 * build a new regspec in our parent's format
477 * build a new map_req with the new regspec
478 * call up the tree to complete the mapping
479 */
480 int
pci_map(dev_info_t * dip,dev_info_t * rdip,ddi_map_req_t * mp,off_t off,off_t len,caddr_t * addrp)481 pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
482 off_t off, off_t len, caddr_t *addrp)
483 {
484 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
485 struct regspec p_regspec;
486 ddi_map_req_t p_mapreq;
487 int reglen, rval, r_no;
488 pci_regspec_t reloc_reg, *rp = &reloc_reg;
489
490 DEBUG2(DBG_MAP, dip, "rdip=%s%d:",
491 ddi_driver_name(rdip), ddi_get_instance(rdip));
492
493 if (mp->map_flags & DDI_MF_USER_MAPPING)
494 return (DDI_ME_UNIMPLEMENTED);
495
496 switch (mp->map_type) {
497 case DDI_MT_REGSPEC:
498 reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */
499 break;
500
501 case DDI_MT_RNUMBER:
502 r_no = mp->map_obj.rnumber;
503 DEBUG1(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
504
505 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS,
506 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS)
507 return (DDI_ME_RNUMBER_RANGE);
508
509 if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) {
510 kmem_free(rp, reglen);
511 return (DDI_ME_RNUMBER_RANGE);
512 }
513 rp += r_no;
514 break;
515
516 default:
517 return (DDI_ME_INVAL);
518 }
519 DEBUG0(DBG_MAP | DBG_CONT, dip, "\n");
520
521 /* use "assigned-addresses" to relocate regspec within pci space */
522 if (rval = pci_reloc_reg(dip, rdip, pci_p, rp))
523 goto done;
524
525 if (len) /* adjust regspec according to mapping request */
526 rp->pci_size_low = len;
527 rp->pci_phys_low += off;
528
529 /* use "ranges" to translate relocated pci regspec into parent space */
530 if (rval = pci_xlate_reg(pci_p, rp, &p_regspec))
531 goto done;
532
533 p_mapreq = *mp; /* dup the whole structure */
534 p_mapreq.map_type = DDI_MT_REGSPEC;
535 p_mapreq.map_obj.rp = &p_regspec;
536 rval = ddi_map(dip, &p_mapreq, 0, 0, addrp);
537
538 if (rval == DDI_SUCCESS) {
539 /*
540 * Set-up access functions for FM access error capable drivers.
541 * The axq workaround prevents fault management support
542 */
543 if (DDI_FM_ACC_ERR_CAP(pci_p->pci_fm_cap) &&
544 DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)) &&
545 mp->map_handlep->ah_acc.devacc_attr_access !=
546 DDI_DEFAULT_ACC)
547 pci_fm_acc_setup(mp, rdip);
548 pci_axq_setup(mp, pci_p->pci_pbm_p);
549 }
550
551 done:
552 if (mp->map_type == DDI_MT_RNUMBER)
553 kmem_free(rp - r_no, reglen);
554
555 return (rval);
556 }
557
558 /*
559 * bus dma map entry point
560 * return value:
561 * DDI_DMA_PARTIAL_MAP 1
562 * DDI_DMA_MAPOK 0
563 * DDI_DMA_MAPPED 0
564 * DDI_DMA_NORESOURCES -1
565 * DDI_DMA_NOMAPPING -2
566 * DDI_DMA_TOOBIG -3
567 */
568 int
pci_dma_setup(dev_info_t * dip,dev_info_t * rdip,ddi_dma_req_t * dmareq,ddi_dma_handle_t * handlep)569 pci_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq,
570 ddi_dma_handle_t *handlep)
571 {
572 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
573 iommu_t *iommu_p = pci_p->pci_iommu_p;
574 ddi_dma_impl_t *mp;
575 int ret;
576
577 DEBUG3(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n",
578 ddi_driver_name(rdip), ddi_get_instance(rdip),
579 handlep ? "alloc" : "advisory");
580
581 if (!(mp = pci_dma_lmts2hdl(dip, rdip, iommu_p, dmareq)))
582 return (DDI_DMA_NORESOURCES);
583 if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING)
584 return (DDI_DMA_NOMAPPING);
585 if (ret = pci_dma_type(pci_p, dmareq, mp))
586 goto freehandle;
587 if (ret = pci_dma_pfn(pci_p, dmareq, mp))
588 goto freehandle;
589
590 switch (PCI_DMA_TYPE(mp)) {
591 case DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
592 if ((ret = pci_dvma_win(pci_p, dmareq, mp)) || !handlep)
593 goto freehandle;
594 if (!PCI_DMA_CANCACHE(mp)) { /* try fast track */
595 if (PCI_DMA_CANFAST(mp)) {
596 if (!pci_dvma_map_fast(iommu_p, mp))
597 break;
598 /* LINTED E_NOP_ELSE_STMT */
599 } else {
600 PCI_DVMA_FASTTRAK_PROF(mp);
601 }
602 }
603 if (ret = pci_dvma_map(mp, dmareq, iommu_p))
604 goto freehandle;
605 break;
606 case DMAI_FLAGS_PEER_TO_PEER: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
607 if ((ret = pci_dma_physwin(pci_p, dmareq, mp)) || !handlep)
608 goto freehandle;
609 break;
610 case DMAI_FLAGS_BYPASS:
611 default:
612 panic("%s%d: pci_dma_setup: bad dma type 0x%x",
613 ddi_driver_name(rdip), ddi_get_instance(rdip),
614 PCI_DMA_TYPE(mp));
615 /*NOTREACHED*/
616 }
617 *handlep = (ddi_dma_handle_t)mp;
618 mp->dmai_flags |= (DMAI_FLAGS_INUSE | DMAI_FLAGS_MAPPED);
619 dump_dma_handle(DBG_DMA_MAP, dip, mp);
620
621 return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
622 freehandle:
623 if (ret == DDI_DMA_NORESOURCES)
624 pci_dma_freemp(mp); /* don't run_callback() */
625 else
626 (void) pci_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
627 return (ret);
628 }
629
630
631 /*
632 * bus dma alloc handle entry point:
633 */
634 int
pci_dma_allochdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_attr_t * attrp,int (* waitfp)(caddr_t),caddr_t arg,ddi_dma_handle_t * handlep)635 pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
636 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
637 {
638 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
639 ddi_dma_impl_t *mp;
640 int rval;
641
642 DEBUG2(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n",
643 ddi_driver_name(rdip), ddi_get_instance(rdip));
644
645 if (attrp->dma_attr_version != DMA_ATTR_V0)
646 return (DDI_DMA_BADATTR);
647
648 if (!(mp = pci_dma_allocmp(dip, rdip, waitfp, arg)))
649 return (DDI_DMA_NORESOURCES);
650
651 /*
652 * Save requestor's information
653 */
654 mp->dmai_attr = *attrp; /* whole object - augmented later */
655 *DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */
656 DEBUG1(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
657
658 /* check and convert dma attributes to handle parameters */
659 if (rval = pci_dma_attr2hdl(pci_p, mp)) {
660 pci_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
661 *handlep = NULL;
662 return (rval);
663 }
664 *handlep = (ddi_dma_handle_t)mp;
665 return (DDI_SUCCESS);
666 }
667
668
669 /*
670 * bus dma free handle entry point:
671 */
672 /*ARGSUSED*/
673 int
pci_dma_freehdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle)674 pci_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
675 {
676 DEBUG3(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n",
677 ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
678 pci_dma_freemp((ddi_dma_impl_t *)handle);
679
680 if (pci_kmem_clid) {
681 DEBUG0(DBG_DMA_FREEH, dip, "run handle callback\n");
682 ddi_run_callback(&pci_kmem_clid);
683 }
684 return (DDI_SUCCESS);
685 }
686
687
688 /*
689 * bus dma bind handle entry point:
690 */
691 int
pci_dma_bindhdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,ddi_dma_req_t * dmareq,ddi_dma_cookie_t * cookiep,uint_t * ccountp)692 pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
693 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
694 ddi_dma_cookie_t *cookiep, uint_t *ccountp)
695 {
696 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
697 iommu_t *iommu_p = pci_p->pci_iommu_p;
698 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
699 int ret;
700
701 DEBUG4(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n",
702 ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq);
703
704 if (mp->dmai_flags & DMAI_FLAGS_INUSE)
705 return (DDI_DMA_INUSE);
706
707 ASSERT((mp->dmai_flags & ~DMAI_FLAGS_PRESERVE) == 0);
708 mp->dmai_flags |= DMAI_FLAGS_INUSE;
709
710 if (ret = pci_dma_type(pci_p, dmareq, mp))
711 goto err;
712 if (ret = pci_dma_pfn(pci_p, dmareq, mp))
713 goto err;
714
715 switch (PCI_DMA_TYPE(mp)) {
716 case DMAI_FLAGS_DVMA:
717 if (ret = pci_dvma_win(pci_p, dmareq, mp))
718 goto map_err;
719 if (!PCI_DMA_CANCACHE(mp)) { /* try fast track */
720 if (PCI_DMA_CANFAST(mp)) {
721 if (!pci_dvma_map_fast(iommu_p, mp))
722 goto mapped; /*LINTED E_NOP_ELSE_STMT*/
723 } else {
724 PCI_DVMA_FASTTRAK_PROF(mp);
725 }
726 }
727 if (ret = pci_dvma_map(mp, dmareq, iommu_p))
728 goto map_err;
729 mapped:
730 *ccountp = 1;
731 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size);
732 break;
733 case DMAI_FLAGS_BYPASS:
734 case DMAI_FLAGS_PEER_TO_PEER:
735 if (ret = pci_dma_physwin(pci_p, dmareq, mp))
736 goto map_err;
737 *ccountp = WINLST(mp)->win_ncookies;
738 *cookiep = *(ddi_dma_cookie_t *)(WINLST(mp) + 1); /* wholeobj */
739 break;
740 default:
741 panic("%s%d: pci_dma_bindhdl(%p): bad dma type",
742 ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
743 /*NOTREACHED*/
744 }
745 DEBUG2(DBG_DMA_BINDH, dip, "cookie %x+%x\n", cookiep->dmac_address,
746 cookiep->dmac_size);
747 dump_dma_handle(DBG_DMA_MAP, dip, mp);
748
749 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR)
750 mp->dmai_error.err_cf = impl_dma_check;
751
752 mp->dmai_flags |= DMAI_FLAGS_MAPPED;
753 return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
754 map_err:
755 pci_dvma_unregister_callbacks(pci_p, mp);
756 pci_dma_freepfn(mp);
757 err:
758 mp->dmai_flags &= DMAI_FLAGS_PRESERVE;
759 return (ret);
760 }
761
762 /*
763 * bus dma unbind handle entry point:
764 */
765 /*ARGSUSED*/
766 int
pci_dma_unbindhdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle)767 pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
768 {
769 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
770 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
771 iommu_t *iommu_p = pci_p->pci_iommu_p;
772
773 DEBUG3(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n",
774 ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
775 if ((mp->dmai_flags & DMAI_FLAGS_INUSE) == 0) {
776 DEBUG0(DBG_DMA_UNBINDH, dip, "handle not in use\n");
777 return (DDI_FAILURE);
778 }
779
780 mp->dmai_flags &= ~DMAI_FLAGS_MAPPED;
781
782 switch (PCI_DMA_TYPE(mp)) {
783 case DMAI_FLAGS_DVMA:
784 pci_dvma_unregister_callbacks(pci_p, mp);
785 pci_dma_sync_unmap(dip, rdip, mp);
786 pci_dvma_unmap(iommu_p, mp);
787 pci_dma_freepfn(mp);
788 break;
789 case DMAI_FLAGS_BYPASS:
790 case DMAI_FLAGS_PEER_TO_PEER:
791 pci_dma_freewin(mp);
792 break;
793 default:
794 panic("%s%d: pci_dma_unbindhdl:bad dma type %p",
795 ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
796 /*NOTREACHED*/
797 }
798 if (iommu_p->iommu_dvma_clid != 0) {
799 DEBUG0(DBG_DMA_UNBINDH, dip, "run dvma callback\n");
800 ddi_run_callback(&iommu_p->iommu_dvma_clid);
801 }
802 if (pci_kmem_clid) {
803 DEBUG0(DBG_DMA_UNBINDH, dip, "run handle callback\n");
804 ddi_run_callback(&pci_kmem_clid);
805 }
806 mp->dmai_flags &= DMAI_FLAGS_PRESERVE;
807 SYNC_BUF_PA(mp) = 0;
808
809 mp->dmai_error.err_cf = NULL;
810
811 return (DDI_SUCCESS);
812 }
813
814
815 /*
816 * bus dma win entry point:
817 */
818 int
pci_dma_win(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,uint_t win,off_t * offp,size_t * lenp,ddi_dma_cookie_t * cookiep,uint_t * ccountp)819 pci_dma_win(dev_info_t *dip, dev_info_t *rdip,
820 ddi_dma_handle_t handle, uint_t win, off_t *offp,
821 size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
822 {
823 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
824 DEBUG2(DBG_DMA_WIN, dip, "rdip=%s%d\n",
825 ddi_driver_name(rdip), ddi_get_instance(rdip));
826 dump_dma_handle(DBG_DMA_WIN, dip, mp);
827 if (win >= mp->dmai_nwin) {
828 DEBUG1(DBG_DMA_WIN, dip, "%x out of range\n", win);
829 return (DDI_FAILURE);
830 }
831
832 switch (PCI_DMA_TYPE(mp)) {
833 case DMAI_FLAGS_DVMA:
834 if (win != PCI_DMA_CURWIN(mp)) {
835 pci_t *pci_p =
836 get_pci_soft_state(ddi_get_instance(dip));
837 pci_dma_sync_unmap(dip, rdip, mp);
838 /* map_window sets dmai_mapping/size/offset */
839 iommu_map_window(pci_p->pci_iommu_p, mp, win);
840 }
841 if (cookiep)
842 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping,
843 mp->dmai_size);
844 if (ccountp)
845 *ccountp = 1;
846 break;
847 case DMAI_FLAGS_PEER_TO_PEER:
848 case DMAI_FLAGS_BYPASS: {
849 int i;
850 ddi_dma_cookie_t *ck_p;
851 pci_dma_win_t *win_p = mp->dmai_winlst;
852
853 for (i = 0; i < win; win_p = win_p->win_next, i++)
854 ;
855 ck_p = (ddi_dma_cookie_t *)(win_p + 1);
856 *cookiep = *ck_p;
857 mp->dmai_offset = win_p->win_offset;
858 mp->dmai_size = win_p->win_size;
859 mp->dmai_mapping = ck_p->dmac_laddress;
860 mp->dmai_cookie = ck_p + 1;
861 win_p->win_curseg = 0;
862 if (ccountp)
863 *ccountp = win_p->win_ncookies;
864 }
865 break;
866 default:
867 cmn_err(CE_WARN, "%s%d: pci_dma_win:bad dma type 0x%x",
868 ddi_driver_name(rdip), ddi_get_instance(rdip),
869 PCI_DMA_TYPE(mp));
870 return (DDI_FAILURE);
871 }
872 if (cookiep)
873 DEBUG2(DBG_DMA_WIN, dip,
874 "cookie - dmac_address=%x dmac_size=%x\n",
875 cookiep->dmac_address, cookiep->dmac_size);
876 if (offp)
877 *offp = (off_t)mp->dmai_offset;
878 if (lenp)
879 *lenp = mp->dmai_size;
880 return (DDI_SUCCESS);
881 }
882
883 #ifdef DEBUG
884 static char *pci_dmactl_str[] = {
885 "DDI_DMA_FREE",
886 "DDI_DMA_SYNC",
887 "DDI_DMA_HTOC",
888 "DDI_DMA_KVADDR",
889 "DDI_DMA_MOVWIN",
890 "DDI_DMA_REPWIN",
891 "DDI_DMA_GETERR",
892 "DDI_DMA_COFF",
893 "DDI_DMA_NEXTWIN",
894 "DDI_DMA_NEXTSEG",
895 "DDI_DMA_SEGTOC",
896 "DDI_DMA_RESERVE",
897 "DDI_DMA_RELEASE",
898 "DDI_DMA_RESETH",
899 "DDI_DMA_CKSYNC",
900 "DDI_DMA_IOPB_ALLOC",
901 "DDI_DMA_IOPB_FREE",
902 "DDI_DMA_SMEM_ALLOC",
903 "DDI_DMA_SMEM_FREE",
904 "DDI_DMA_SET_SBUS64",
905 "DDI_DMA_REMAP"
906 };
907 #endif
908
909 /*
910 * bus dma control entry point:
911 */
912 int
pci_dma_ctlops(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,enum ddi_dma_ctlops cmd,off_t * offp,size_t * lenp,caddr_t * objp,uint_t cache_flags)913 pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
914 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
915 uint_t cache_flags)
916 {
917 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
918 DEBUG3(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", pci_dmactl_str[cmd],
919 ddi_driver_name(rdip), ddi_get_instance(rdip));
920
921 switch (cmd) {
922 case DDI_DMA_FREE:
923 (void) pci_dma_unbindhdl(dip, rdip, handle);
924 (void) pci_dma_freehdl(dip, rdip, handle);
925 return (DDI_SUCCESS);
926 case DDI_DMA_RESERVE: {
927 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
928 return (pci_fdvma_reserve(dip, rdip, pci_p,
929 (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp));
930 }
931 case DDI_DMA_RELEASE: {
932 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
933 return (pci_fdvma_release(dip, pci_p, mp));
934 }
935 default:
936 break;
937 }
938
939 switch (PCI_DMA_TYPE(mp)) {
940 case DMAI_FLAGS_DVMA:
941 return (pci_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
942 cache_flags));
943 case DMAI_FLAGS_PEER_TO_PEER:
944 case DMAI_FLAGS_BYPASS:
945 return (pci_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
946 cache_flags));
947 default:
948 panic("%s%d: pci_dma_ctlops(%x):bad dma type %x",
949 ddi_driver_name(rdip), ddi_get_instance(rdip), cmd,
950 mp->dmai_flags);
951 /*NOTREACHED*/
952 }
953 }
954
955 #ifdef DEBUG
956 int pci_peekfault_cnt = 0;
957 int pci_pokefault_cnt = 0;
958 #endif /* DEBUG */
959
960 static int
pci_do_poke(pci_t * pci_p,peekpoke_ctlops_t * in_args)961 pci_do_poke(pci_t *pci_p, peekpoke_ctlops_t *in_args)
962 {
963 pbm_t *pbm_p = pci_p->pci_pbm_p;
964 int err = DDI_SUCCESS;
965 on_trap_data_t otd;
966
967 mutex_enter(&pbm_p->pbm_pokefault_mutex);
968 pbm_p->pbm_ontrap_data = &otd;
969
970 /* Set up protected environment. */
971 if (!on_trap(&otd, OT_DATA_ACCESS)) {
972 uintptr_t tramp = otd.ot_trampoline;
973
974 otd.ot_trampoline = (uintptr_t)&poke_fault;
975 err = do_poke(in_args->size, (void *)in_args->dev_addr,
976 (void *)in_args->host_addr);
977 otd.ot_trampoline = tramp;
978 } else
979 err = DDI_FAILURE;
980
981 /*
982 * Read the async fault register for the PBM to see it sees
983 * a master-abort.
984 */
985 pbm_clear_error(pbm_p);
986
987 if (otd.ot_trap & OT_DATA_ACCESS)
988 err = DDI_FAILURE;
989
990 /* Take down protected environment. */
991 no_trap();
992
993 pbm_p->pbm_ontrap_data = NULL;
994 mutex_exit(&pbm_p->pbm_pokefault_mutex);
995
996 #ifdef DEBUG
997 if (err == DDI_FAILURE)
998 pci_pokefault_cnt++;
999 #endif
1000 return (err);
1001 }
1002
1003
1004 static int
pci_do_caut_put(pci_t * pci_p,peekpoke_ctlops_t * cautacc_ctlops_arg)1005 pci_do_caut_put(pci_t *pci_p, peekpoke_ctlops_t *cautacc_ctlops_arg)
1006 {
1007 size_t size = cautacc_ctlops_arg->size;
1008 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr;
1009 uintptr_t host_addr = cautacc_ctlops_arg->host_addr;
1010 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle;
1011 size_t repcount = cautacc_ctlops_arg->repcount;
1012 uint_t flags = cautacc_ctlops_arg->flags;
1013
1014 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED;
1015
1016 /*
1017 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault
1018 * mutex.
1019 */
1020 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp);
1021
1022 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) {
1023 for (; repcount; repcount--) {
1024 switch (size) {
1025
1026 case sizeof (uint8_t):
1027 i_ddi_put8(hp, (uint8_t *)dev_addr,
1028 *(uint8_t *)host_addr);
1029 break;
1030
1031 case sizeof (uint16_t):
1032 i_ddi_put16(hp, (uint16_t *)dev_addr,
1033 *(uint16_t *)host_addr);
1034 break;
1035
1036 case sizeof (uint32_t):
1037 i_ddi_put32(hp, (uint32_t *)dev_addr,
1038 *(uint32_t *)host_addr);
1039 break;
1040
1041 case sizeof (uint64_t):
1042 i_ddi_put64(hp, (uint64_t *)dev_addr,
1043 *(uint64_t *)host_addr);
1044 break;
1045 }
1046
1047 host_addr += size;
1048
1049 if (flags == DDI_DEV_AUTOINCR)
1050 dev_addr += size;
1051
1052 }
1053 }
1054
1055 i_ddi_notrap((ddi_acc_handle_t)hp);
1056 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp);
1057 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED;
1058
1059 if (hp->ahi_err->err_status != DDI_FM_OK) {
1060 /* Clear the expected fault from the handle before returning */
1061 hp->ahi_err->err_status = DDI_FM_OK;
1062 return (DDI_FAILURE);
1063 }
1064
1065 return (DDI_SUCCESS);
1066 }
1067
1068
1069 static int
pci_ctlops_poke(pci_t * pci_p,peekpoke_ctlops_t * in_args)1070 pci_ctlops_poke(pci_t *pci_p, peekpoke_ctlops_t *in_args)
1071 {
1072 return (in_args->handle ? pci_do_caut_put(pci_p, in_args) :
1073 pci_do_poke(pci_p, in_args));
1074 }
1075
1076
1077 static int
pci_do_peek(pci_t * pci_p,peekpoke_ctlops_t * in_args)1078 pci_do_peek(pci_t *pci_p, peekpoke_ctlops_t *in_args)
1079 {
1080 int err = DDI_SUCCESS;
1081 on_trap_data_t otd;
1082
1083 if (!on_trap(&otd, OT_DATA_ACCESS)) {
1084 uintptr_t tramp = otd.ot_trampoline;
1085
1086 otd.ot_trampoline = (uintptr_t)&peek_fault;
1087 err = do_peek(in_args->size, (void *)in_args->dev_addr,
1088 (void *)in_args->host_addr);
1089 otd.ot_trampoline = tramp;
1090 } else
1091 err = DDI_FAILURE;
1092
1093 no_trap();
1094
1095 #ifdef DEBUG
1096 if (err == DDI_FAILURE)
1097 pci_peekfault_cnt++;
1098 #endif
1099 return (err);
1100 }
1101
1102 static int
pci_do_caut_get(pci_t * pci_p,peekpoke_ctlops_t * cautacc_ctlops_arg)1103 pci_do_caut_get(pci_t *pci_p, peekpoke_ctlops_t *cautacc_ctlops_arg)
1104 {
1105 size_t size = cautacc_ctlops_arg->size;
1106 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr;
1107 uintptr_t host_addr = cautacc_ctlops_arg->host_addr;
1108 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle;
1109 size_t repcount = cautacc_ctlops_arg->repcount;
1110 uint_t flags = cautacc_ctlops_arg->flags;
1111
1112 int err = DDI_SUCCESS;
1113
1114 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED;
1115 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp);
1116
1117 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) {
1118 for (; repcount; repcount--) {
1119 i_ddi_caut_get(size, (void *)dev_addr,
1120 (void *)host_addr);
1121
1122 host_addr += size;
1123
1124 if (flags == DDI_DEV_AUTOINCR)
1125 dev_addr += size;
1126 }
1127 } else {
1128 int i;
1129 uint8_t *ff_addr = (uint8_t *)host_addr;
1130 for (i = 0; i < size; i++)
1131 *ff_addr++ = 0xff;
1132
1133 err = DDI_FAILURE;
1134 }
1135
1136 i_ddi_notrap((ddi_acc_handle_t)hp);
1137 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp);
1138 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED;
1139
1140 return (err);
1141 }
1142
1143
1144 static int
pci_ctlops_peek(pci_t * pci_p,peekpoke_ctlops_t * in_args,void * result)1145 pci_ctlops_peek(pci_t *pci_p, peekpoke_ctlops_t *in_args, void *result)
1146 {
1147 result = (void *)in_args->host_addr;
1148 return (in_args->handle ? pci_do_caut_get(pci_p, in_args) :
1149 pci_do_peek(pci_p, in_args));
1150 }
1151
1152 /*
1153 * get_reg_set_size
1154 *
1155 * Given a dev info pointer to a pci child and a register number, this
1156 * routine returns the size element of that reg set property.
1157 * return value: size of reg set on success, -1 on error
1158 */
1159 static off_t
get_reg_set_size(dev_info_t * child,int rnumber)1160 get_reg_set_size(dev_info_t *child, int rnumber)
1161 {
1162 pci_regspec_t *pci_rp;
1163 off_t size;
1164 int i;
1165
1166 if (rnumber < 0)
1167 return (-1);
1168
1169 /*
1170 * Get the reg property for the device.
1171 */
1172 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, "reg",
1173 (caddr_t)&pci_rp, &i) != DDI_SUCCESS)
1174 return (-1);
1175
1176 if (rnumber >= (i / (int)sizeof (pci_regspec_t))) {
1177 kmem_free(pci_rp, i);
1178 return (-1);
1179 }
1180
1181 size = pci_rp[rnumber].pci_size_low |
1182 ((uint64_t)pci_rp[rnumber].pci_size_hi << 32);
1183 kmem_free(pci_rp, i);
1184 return (size);
1185 }
1186
1187
1188 /*
1189 * control ops entry point:
1190 *
1191 * Requests handled completely:
1192 * DDI_CTLOPS_INITCHILD see init_child() for details
1193 * DDI_CTLOPS_UNINITCHILD
1194 * DDI_CTLOPS_REPORTDEV see report_dev() for details
1195 * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1
1196 * DDI_CTLOPS_REGSIZE
1197 * DDI_CTLOPS_NREGS
1198 * DDI_CTLOPS_DVMAPAGESIZE
1199 * DDI_CTLOPS_POKE
1200 * DDI_CTLOPS_PEEK
1201 * DDI_CTLOPS_QUIESCE
1202 * DDI_CTLOPS_UNQUIESCE
1203 *
1204 * All others passed to parent.
1205 */
1206 int
pci_ctlops(dev_info_t * dip,dev_info_t * rdip,ddi_ctl_enum_t op,void * arg,void * result)1207 pci_ctlops(dev_info_t *dip, dev_info_t *rdip,
1208 ddi_ctl_enum_t op, void *arg, void *result)
1209 {
1210 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
1211
1212 switch (op) {
1213 case DDI_CTLOPS_INITCHILD:
1214 return (init_child(pci_p, (dev_info_t *)arg));
1215
1216 case DDI_CTLOPS_UNINITCHILD:
1217 return (uninit_child(pci_p, (dev_info_t *)arg));
1218
1219 case DDI_CTLOPS_REPORTDEV:
1220 return (report_dev(rdip));
1221
1222 case DDI_CTLOPS_IOMIN:
1223
1224 /*
1225 * If we are using the streaming cache, align at
1226 * least on a cache line boundary. Otherwise use
1227 * whatever alignment is passed in.
1228 */
1229
1230 if ((uintptr_t)arg) {
1231 int val = *((int *)result);
1232
1233 val = maxbit(val, PCI_SBUF_LINE_SIZE);
1234 *((int *)result) = val;
1235 }
1236 return (DDI_SUCCESS);
1237
1238 case DDI_CTLOPS_REGSIZE:
1239 *((off_t *)result) = get_reg_set_size(rdip, *((int *)arg));
1240 return (*((off_t *)result) == -1 ? DDI_FAILURE : DDI_SUCCESS);
1241
1242 case DDI_CTLOPS_NREGS:
1243 *((uint_t *)result) = get_nreg_set(rdip);
1244 return (DDI_SUCCESS);
1245
1246 case DDI_CTLOPS_DVMAPAGESIZE:
1247 *((ulong_t *)result) = IOMMU_PAGE_SIZE;
1248 return (DDI_SUCCESS);
1249
1250 case DDI_CTLOPS_POKE:
1251 return (pci_ctlops_poke(pci_p, (peekpoke_ctlops_t *)arg));
1252
1253 case DDI_CTLOPS_PEEK:
1254 return (pci_ctlops_peek(pci_p, (peekpoke_ctlops_t *)arg,
1255 result));
1256
1257 case DDI_CTLOPS_AFFINITY:
1258 break;
1259
1260 case DDI_CTLOPS_QUIESCE:
1261 return (pci_bus_quiesce(pci_p, rdip, result));
1262
1263 case DDI_CTLOPS_UNQUIESCE:
1264 return (pci_bus_unquiesce(pci_p, rdip, result));
1265
1266 default:
1267 break;
1268 }
1269
1270 /*
1271 * Now pass the request up to our parent.
1272 */
1273 DEBUG2(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n",
1274 ddi_driver_name(rdip), ddi_get_instance(rdip));
1275 return (ddi_ctlops(dip, rdip, op, arg, result));
1276 }
1277
1278
1279 /* ARGSUSED */
1280 int
pci_intr_ops(dev_info_t * dip,dev_info_t * rdip,ddi_intr_op_t intr_op,ddi_intr_handle_impl_t * hdlp,void * result)1281 pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1282 ddi_intr_handle_impl_t *hdlp, void *result)
1283 {
1284 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
1285 ib_ino_t ino;
1286 int ret = DDI_SUCCESS;
1287
1288 switch (intr_op) {
1289 case DDI_INTROP_GETCAP:
1290 /* GetCap will always fail for all non PCI devices */
1291 (void) pci_intx_get_cap(rdip, (int *)result);
1292 break;
1293 case DDI_INTROP_SETCAP:
1294 ret = DDI_ENOTSUP;
1295 break;
1296 case DDI_INTROP_ALLOC:
1297 *(int *)result = hdlp->ih_scratch1;
1298 break;
1299 case DDI_INTROP_FREE:
1300 break;
1301 case DDI_INTROP_GETPRI:
1302 *(int *)result = hdlp->ih_pri ?
1303 hdlp->ih_pri : pci_class_to_pil(rdip);
1304 break;
1305 case DDI_INTROP_SETPRI:
1306 break;
1307 case DDI_INTROP_ADDISR:
1308 ret = pci_add_intr(dip, rdip, hdlp);
1309 break;
1310 case DDI_INTROP_REMISR:
1311 ret = pci_remove_intr(dip, rdip, hdlp);
1312 break;
1313 case DDI_INTROP_GETTARGET:
1314 ino = IB_MONDO_TO_INO(pci_xlate_intr(dip, rdip,
1315 pci_p->pci_ib_p, IB_MONDO_TO_INO(hdlp->ih_vector)));
1316 ret = ib_get_intr_target(pci_p, ino, (int *)result);
1317 break;
1318 case DDI_INTROP_SETTARGET:
1319 ret = DDI_ENOTSUP;
1320 break;
1321 case DDI_INTROP_ENABLE:
1322 ret = ib_update_intr_state(pci_p, rdip, hdlp,
1323 PCI_INTR_STATE_ENABLE);
1324 break;
1325 case DDI_INTROP_DISABLE:
1326 ret = ib_update_intr_state(pci_p, rdip, hdlp,
1327 PCI_INTR_STATE_DISABLE);
1328 break;
1329 case DDI_INTROP_SETMASK:
1330 ret = pci_intx_set_mask(rdip);
1331 break;
1332 case DDI_INTROP_CLRMASK:
1333 ret = pci_intx_clr_mask(rdip);
1334 break;
1335 case DDI_INTROP_GETPENDING:
1336 ret = pci_intx_get_pending(rdip, (int *)result);
1337 break;
1338 case DDI_INTROP_NINTRS:
1339 case DDI_INTROP_NAVAIL:
1340 *(int *)result = i_ddi_get_intx_nintrs(rdip);
1341 break;
1342 case DDI_INTROP_SUPPORTED_TYPES:
1343 /* PCI nexus driver supports only fixed interrupts */
1344 *(int *)result = i_ddi_get_intx_nintrs(rdip) ?
1345 DDI_INTR_TYPE_FIXED : 0;
1346 break;
1347 default:
1348 ret = DDI_ENOTSUP;
1349 break;
1350 }
1351
1352 return (ret);
1353 }
1354
1355 static void
pci_init_hotplug(struct pci * pci_p)1356 pci_init_hotplug(struct pci *pci_p)
1357 {
1358 pci_bus_range_t bus_range;
1359 dev_info_t *dip;
1360
1361 /*
1362 * Before initializing hotplug - open up
1363 * bus range. The busra module will
1364 * initialize its pool of bus numbers from
1365 * this. "busra" will be the agent that keeps
1366 * track of them during hotplug. Also, note,
1367 * that busra will remove any bus numbers
1368 * already in use from boot time.
1369 */
1370 bus_range.lo = 0x0;
1371 bus_range.hi = 0xff;
1372 dip = pci_p->pci_dip;
1373 pci_p->hotplug_capable = B_FALSE;
1374
1375 /*
1376 * If this property exists, this nexus has hot-plug
1377 * slots.
1378 */
1379 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1380 "hotplug-capable")) {
1381 if (ndi_prop_update_int_array(DDI_DEV_T_NONE,
1382 dip, "bus-range",
1383 (int *)&bus_range,
1384 2) != DDI_PROP_SUCCESS) {
1385 return;
1386 }
1387
1388 if (pcihp_init(dip) != DDI_SUCCESS) {
1389 return;
1390 }
1391
1392 if ((pcihp_ops = pcihp_get_cb_ops()) != NULL) {
1393 DEBUG2(DBG_ATTACH, dip, "%s%d hotplug enabled",
1394 ddi_driver_name(dip), ddi_get_instance(dip));
1395 pci_p->hotplug_capable = B_TRUE;
1396 }
1397 }
1398 }
1399