xref: /titanic_41/usr/src/uts/i86pc/os/pci_cfgspace.c (revision 8d7fafffed373567f52062b634e61fd50858b8d9)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 
26 /*
27  * PCI configuration space access routines
28  */
29 
30 #include <sys/systm.h>
31 #include <sys/psw.h>
32 #include <sys/bootconf.h>
33 #include <sys/reboot.h>
34 #include <sys/pci_impl.h>
35 #include <sys/pci_cfgspace.h>
36 #include <sys/pci_cfgspace_impl.h>
37 #include <sys/pci_cfgacc.h>
38 #if defined(__xpv)
39 #include <sys/hypervisor.h>
40 #endif
41 
42 #if defined(__xpv)
43 int pci_max_nbus = 0xFE;
44 #endif
45 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN;
46 int pci_bios_maxbus;
47 int pci_bios_mech;
48 int pci_bios_vers;
49 
50 /*
51  * These two variables can be used to force a configuration mechanism or
52  * to force which function is used to probe for the presence of the PCI bus.
53  */
54 int	PCI_CFG_TYPE = 0;
55 int	PCI_PROBE_TYPE = 0;
56 
57 /*
58  * No valid mcfg_mem_base by default, and accessing pci config space
59  * in mem-mapped way is disabled.
60  */
61 uint64_t mcfg_mem_base = 0;
62 uint8_t mcfg_bus_start = 0;
63 uint8_t mcfg_bus_end = 0xff;
64 
65 /*
66  * Maximum offset in config space when not using MMIO
67  */
68 uint_t pci_iocfg_max_offset = 0xff;
69 
70 /*
71  * These function pointers lead to the actual implementation routines
72  * for configuration space access.  Normally they lead to either the
73  * pci_mech1_* or pci_mech2_* routines, but they can also lead to
74  * routines that work around chipset bugs.
75  * These functions are accessing pci config space via I/O way.
76  * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
77  * which also provide accessing pci config space via mem-mapped way.
78  */
79 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
80 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
81 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
82 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
83 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
84 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
85 
86 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
87 
88 /*
89  * Internal routines
90  */
91 static int pci_check(void);
92 
93 #if !defined(__xpv)
94 static int pci_check_bios(void);
95 static int pci_get_cfg_type(void);
96 #endif
97 
98 /* for legacy io-based config space access */
99 kmutex_t pcicfg_mutex;
100 
101 /* for mmio-based config space access */
102 kmutex_t pcicfg_mmio_mutex;
103 
104 /* ..except Orion and Neptune, which have to have their own */
105 kmutex_t pcicfg_chipset_mutex;
106 
107 void
pci_cfgspace_init(void)108 pci_cfgspace_init(void)
109 {
110 	mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN,
111 	    (ddi_iblock_cookie_t)ipltospl(15));
112 	mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN,
113 	    (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
114 	mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
115 	    (ddi_iblock_cookie_t)ipltospl(15));
116 	if (!pci_check()) {
117 		mutex_destroy(&pcicfg_mutex);
118 		mutex_destroy(&pcicfg_mmio_mutex);
119 		mutex_destroy(&pcicfg_chipset_mutex);
120 	}
121 }
122 
123 /*
124  * This code determines if this system supports PCI/PCIE and which
125  * type of configuration access method is used
126  */
127 static int
pci_check(void)128 pci_check(void)
129 {
130 	uint64_t ecfginfo[4];
131 
132 	/*
133 	 * Only do this once.  NB:  If this is not a PCI system, and we
134 	 * get called twice, we can't detect it and will probably die
135 	 * horribly when we try to ask the BIOS whether PCI is present.
136 	 * This code is safe *ONLY* during system startup when the
137 	 * BIOS is still available.
138 	 */
139 	if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN)
140 		return (TRUE);
141 
142 #if defined(__xpv)
143 	/*
144 	 * only support PCI config mechanism 1 in i86xpv. This should be fine
145 	 * since the other ones are workarounds for old broken H/W which won't
146 	 * be supported in i86xpv anyway.
147 	 */
148 	if (DOMAIN_IS_INITDOMAIN(xen_info)) {
149 		pci_bios_cfg_type = PCI_MECHANISM_1;
150 		pci_getb_func = pci_mech1_getb;
151 		pci_getw_func = pci_mech1_getw;
152 		pci_getl_func = pci_mech1_getl;
153 		pci_putb_func = pci_mech1_putb;
154 		pci_putw_func = pci_mech1_putw;
155 		pci_putl_func = pci_mech1_putl;
156 
157 		/*
158 		 * Since we can't get the BIOS info in i86xpv, we will do an
159 		 * exhaustive search of all PCI buses. We have to do this until
160 		 * we start using the PCI information in ACPI.
161 		 */
162 		pci_bios_maxbus = pci_max_nbus;
163 	}
164 #else /* !__xpv */
165 
166 	pci_bios_cfg_type = pci_check_bios();
167 
168 	if (pci_bios_cfg_type == PCI_MECHANISM_NONE)
169 		pci_bios_cfg_type = PCI_MECHANISM_1;	/* default to mech 1 */
170 
171 	switch (pci_get_cfg_type()) {
172 	case PCI_MECHANISM_1:
173 		if (pci_is_broken_orion()) {
174 			pci_getb_func = pci_orion_getb;
175 			pci_getw_func = pci_orion_getw;
176 			pci_getl_func = pci_orion_getl;
177 			pci_putb_func = pci_orion_putb;
178 			pci_putw_func = pci_orion_putw;
179 			pci_putl_func = pci_orion_putl;
180 		} else if (pci_check_amd_ioecs()) {
181 			pci_getb_func = pci_mech1_amd_getb;
182 			pci_getw_func = pci_mech1_amd_getw;
183 			pci_getl_func = pci_mech1_amd_getl;
184 			pci_putb_func = pci_mech1_amd_putb;
185 			pci_putw_func = pci_mech1_amd_putw;
186 			pci_putl_func = pci_mech1_amd_putl;
187 			pci_iocfg_max_offset = 0xfff;
188 		} else {
189 			pci_getb_func = pci_mech1_getb;
190 			pci_getw_func = pci_mech1_getw;
191 			pci_getl_func = pci_mech1_getl;
192 			pci_putb_func = pci_mech1_putb;
193 			pci_putw_func = pci_mech1_putw;
194 			pci_putl_func = pci_mech1_putl;
195 		}
196 		break;
197 
198 	case PCI_MECHANISM_2:
199 		if (pci_check_neptune()) {
200 			/*
201 			 * The BIOS for some systems with the Intel
202 			 * Neptune chipset seem to default to #2 even
203 			 * though the chipset can do #1.  Override
204 			 * the BIOS so that MP systems will work
205 			 * correctly.
206 			 */
207 
208 			pci_getb_func = pci_neptune_getb;
209 			pci_getw_func = pci_neptune_getw;
210 			pci_getl_func = pci_neptune_getl;
211 			pci_putb_func = pci_neptune_putb;
212 			pci_putw_func = pci_neptune_putw;
213 			pci_putl_func = pci_neptune_putl;
214 		} else {
215 			pci_getb_func = pci_mech2_getb;
216 			pci_getw_func = pci_mech2_getw;
217 			pci_getl_func = pci_mech2_getl;
218 			pci_putb_func = pci_mech2_putb;
219 			pci_putw_func = pci_mech2_putw;
220 			pci_putl_func = pci_mech2_putl;
221 		}
222 		break;
223 
224 	default:
225 		return (FALSE);
226 	}
227 #endif /* __xpv */
228 
229 	/*
230 	 * Try to get a valid mcfg_mem_base in early boot
231 	 * If failed, leave mem-mapped pci config space accessing disabled
232 	 * until pci boot code (pci_autoconfig) makes sure this is a PCIE
233 	 * platform.
234 	 */
235 	if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
236 		mcfg_mem_base = ecfginfo[0];
237 		mcfg_bus_start = ecfginfo[2];
238 		mcfg_bus_end = ecfginfo[3];
239 	}
240 
241 	/* See pci_cfgacc.c */
242 	pci_cfgacc_acc_p = pci_cfgacc_acc;
243 
244 	return (TRUE);
245 }
246 
247 #if !defined(__xpv)
248 
249 static int
pci_check_bios(void)250 pci_check_bios(void)
251 {
252 	struct bop_regs regs;
253 	uint32_t	carryflag;
254 	uint16_t	ax, dx;
255 
256 	bzero(&regs, sizeof (regs));
257 	regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
258 
259 	BOP_DOINT(bootops, 0x1a, &regs);
260 	carryflag = regs.eflags & PS_C;
261 	ax = regs.eax.word.ax;
262 	dx = regs.edx.word.dx;
263 
264 	/* the carry flag must not be set */
265 	if (carryflag != 0)
266 		return (PCI_MECHANISM_NONE);
267 
268 	if (dx != ('P' | 'C'<<8))
269 		return (PCI_MECHANISM_NONE);
270 
271 	/* ah (the high byte of ax) must be zero */
272 	if ((ax & 0xff00) != 0)
273 		return (PCI_MECHANISM_NONE);
274 
275 	pci_bios_mech = (ax & 0x3);
276 	pci_bios_vers = regs.ebx.word.bx;
277 	pci_bios_maxbus = (regs.ecx.word.cx & 0xff);
278 
279 	switch (pci_bios_mech) {
280 	default:	/* ?!? */
281 	case 0:		/* supports neither? */
282 		return (PCI_MECHANISM_NONE);
283 
284 	case 1:
285 	case 3:		/* supports both */
286 		return (PCI_MECHANISM_1);
287 
288 	case 2:
289 		return (PCI_MECHANISM_2);
290 	}
291 }
292 
293 static int
pci_get_cfg_type(void)294 pci_get_cfg_type(void)
295 {
296 	/* Check to see if the config mechanism has been set in /etc/system */
297 	switch (PCI_CFG_TYPE) {
298 	default:
299 	case 0:
300 		break;
301 	case 1:
302 		return (PCI_MECHANISM_1);
303 	case 2:
304 		return (PCI_MECHANISM_2);
305 	case -1:
306 		return (PCI_MECHANISM_NONE);
307 	}
308 
309 	/* call one of the PCI detection algorithms */
310 	switch (PCI_PROBE_TYPE) {
311 	default:
312 	case 0:
313 		/* From pci_check() and pci_check_bios() */
314 		return (pci_bios_cfg_type);
315 	case -1:
316 		return (PCI_MECHANISM_NONE);
317 	}
318 }
319 
320 #endif	/* __xpv */
321