1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_params.h" 23 #include "intel_display_power.h" 24 #include "intel_dpll_mgr.h" 25 #include "intel_fbc.h" 26 #include "intel_global_state.h" 27 #include "intel_gmbus.h" 28 #include "intel_opregion.h" 29 #include "intel_dmc_wl.h" 30 #include "intel_wm_types.h" 31 32 struct task_struct; 33 34 struct drm_i915_private; 35 struct drm_property; 36 struct drm_property_blob; 37 struct i915_audio_component; 38 struct i915_hdcp_arbiter; 39 struct intel_atomic_state; 40 struct intel_audio_funcs; 41 struct intel_cdclk_funcs; 42 struct intel_cdclk_vals; 43 struct intel_color_funcs; 44 struct intel_crtc; 45 struct intel_crtc_state; 46 struct intel_dmc; 47 struct intel_dpll_funcs; 48 struct intel_dpll_mgr; 49 struct intel_fbdev; 50 struct intel_fdi_funcs; 51 struct intel_hotplug_funcs; 52 struct intel_initial_plane_config; 53 struct intel_opregion; 54 struct intel_overlay; 55 56 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 57 #define I915_NUM_QGV_POINTS 8 58 59 /* Amount of PSF GV points, BSpec precisely defines this */ 60 #define I915_NUM_PSF_GV_POINTS 3 61 62 struct intel_display_funcs { 63 /* 64 * Returns the active state of the crtc, and if the crtc is active, 65 * fills out the pipe-config with the hw state. 66 */ 67 bool (*get_pipe_config)(struct intel_crtc *, 68 struct intel_crtc_state *); 69 void (*get_initial_plane_config)(struct intel_crtc *, 70 struct intel_initial_plane_config *); 71 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc, 72 const struct intel_initial_plane_config *plane_config); 73 void (*crtc_enable)(struct intel_atomic_state *state, 74 struct intel_crtc *crtc); 75 void (*crtc_disable)(struct intel_atomic_state *state, 76 struct intel_crtc *crtc); 77 void (*commit_modeset_enables)(struct intel_atomic_state *state); 78 }; 79 80 /* functions used for watermark calcs for display. */ 81 struct intel_wm_funcs { 82 /* update_wm is for legacy wm management */ 83 void (*update_wm)(struct drm_i915_private *dev_priv); 84 int (*compute_watermarks)(struct intel_atomic_state *state, 85 struct intel_crtc *crtc); 86 void (*initial_watermarks)(struct intel_atomic_state *state, 87 struct intel_crtc *crtc); 88 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 89 struct intel_crtc *crtc); 90 void (*optimize_watermarks)(struct intel_atomic_state *state, 91 struct intel_crtc *crtc); 92 int (*compute_global_watermarks)(struct intel_atomic_state *state); 93 void (*get_hw_state)(struct drm_i915_private *i915); 94 }; 95 96 struct intel_audio_state { 97 struct intel_encoder *encoder; 98 u8 eld[MAX_ELD_BYTES]; 99 }; 100 101 struct intel_audio { 102 /* hda/i915 audio component */ 103 struct i915_audio_component *component; 104 bool component_registered; 105 /* mutex for audio/video sync */ 106 struct mutex mutex; 107 int power_refcount; 108 u32 freq_cntrl; 109 110 /* current audio state for the audio component hooks */ 111 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 112 113 /* necessary resource sharing with HDMI LPE audio driver. */ 114 struct { 115 struct platform_device *platdev; 116 int irq; 117 } lpe; 118 }; 119 120 /* 121 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 122 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 123 * dpll, because on some platforms plls share registers. 124 */ 125 struct intel_dpll { 126 struct mutex lock; 127 128 int num_shared_dpll; 129 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 130 const struct intel_dpll_mgr *mgr; 131 132 struct { 133 int nssc; 134 int ssc; 135 } ref_clks; 136 137 /* 138 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 139 */ 140 u8 pch_ssc_use; 141 }; 142 143 struct intel_frontbuffer_tracking { 144 spinlock_t lock; 145 146 /* 147 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 148 * scheduled flips. 149 */ 150 unsigned busy_bits; 151 unsigned flip_bits; 152 }; 153 154 struct intel_hotplug { 155 struct delayed_work hotplug_work; 156 157 const u32 *hpd, *pch_hpd; 158 159 struct { 160 unsigned long last_jiffies; 161 int count; 162 enum { 163 HPD_ENABLED = 0, 164 HPD_DISABLED = 1, 165 HPD_MARK_DISABLED = 2 166 } state; 167 } stats[HPD_NUM_PINS]; 168 u32 event_bits; 169 u32 retry_bits; 170 struct delayed_work reenable_work; 171 172 u32 long_port_mask; 173 u32 short_port_mask; 174 struct work_struct dig_port_work; 175 176 struct work_struct poll_init_work; 177 bool poll_enabled; 178 179 /* 180 * Queuing of hotplug_work, reenable_work and poll_init_work is 181 * enabled. Protected by drm_i915_private::irq_lock. 182 */ 183 bool detection_work_enabled; 184 185 unsigned int hpd_storm_threshold; 186 /* Whether or not to count short HPD IRQs in HPD storms */ 187 u8 hpd_short_storm_enabled; 188 189 /* Last state reported by oob_hotplug_event for each encoder */ 190 unsigned long oob_hotplug_last_state; 191 192 /* 193 * if we get a HPD irq from DP and a HPD irq from non-DP 194 * the non-DP HPD could block the workqueue on a mode config 195 * mutex getting, that userspace may have taken. However 196 * userspace is waiting on the DP workqueue to run which is 197 * blocked behind the non-DP one. 198 */ 199 struct workqueue_struct *dp_wq; 200 201 /* 202 * Flag to track if long HPDs need not to be processed 203 * 204 * Some panels generate long HPDs while keep connected to the port. 205 * This can cause issues with CI tests results. In CI systems we 206 * don't expect to disconnect the panels and could ignore the long 207 * HPDs generated from the faulty panels. This flag can be used as 208 * cue to ignore the long HPDs and can be set / unset using debugfs. 209 */ 210 bool ignore_long_hpd; 211 }; 212 213 struct intel_vbt_data { 214 /* bdb version */ 215 u16 version; 216 217 /* Feature bits */ 218 unsigned int int_tv_support:1; 219 unsigned int int_crt_support:1; 220 unsigned int lvds_use_ssc:1; 221 unsigned int int_lvds_support:1; 222 unsigned int display_clock_mode:1; 223 unsigned int fdi_rx_polarity_inverted:1; 224 int lvds_ssc_freq; 225 enum drm_panel_orientation orientation; 226 227 bool override_afc_startup; 228 u8 override_afc_startup_val; 229 230 int crt_ddc_pin; 231 232 struct list_head display_devices; 233 struct list_head bdb_blocks; 234 235 struct sdvo_device_mapping { 236 u8 initialized; 237 u8 dvo_port; 238 u8 target_addr; 239 u8 dvo_wiring; 240 u8 i2c_pin; 241 u8 ddc_pin; 242 } sdvo_mappings[2]; 243 }; 244 245 struct intel_wm { 246 /* 247 * Raw watermark latency values: 248 * in 0.1us units for WM0, 249 * in 0.5us units for WM1+. 250 */ 251 /* primary */ 252 u16 pri_latency[5]; 253 /* sprite */ 254 u16 spr_latency[5]; 255 /* cursor */ 256 u16 cur_latency[5]; 257 /* 258 * Raw watermark memory latency values 259 * for SKL for all 8 levels 260 * in 1us units. 261 */ 262 u16 skl_latency[8]; 263 264 /* current hardware state */ 265 union { 266 struct ilk_wm_values hw; 267 struct vlv_wm_values vlv; 268 struct g4x_wm_values g4x; 269 }; 270 271 u8 num_levels; 272 273 /* 274 * Should be held around atomic WM register writing; also 275 * protects * intel_crtc->wm.active and 276 * crtc_state->wm.need_postvbl_update. 277 */ 278 struct mutex wm_mutex; 279 280 bool ipc_enabled; 281 }; 282 283 struct intel_display { 284 /* drm device backpointer */ 285 struct drm_device *drm; 286 287 /* Platform (and subplatform, if any) identification */ 288 struct intel_display_platforms platform; 289 290 /* Display functions */ 291 struct { 292 /* Top level crtc-ish functions */ 293 const struct intel_display_funcs *display; 294 295 /* Display CDCLK functions */ 296 const struct intel_cdclk_funcs *cdclk; 297 298 /* Display pll funcs */ 299 const struct intel_dpll_funcs *dpll; 300 301 /* irq display functions */ 302 const struct intel_hotplug_funcs *hotplug; 303 304 /* pm display functions */ 305 const struct intel_wm_funcs *wm; 306 307 /* fdi display functions */ 308 const struct intel_fdi_funcs *fdi; 309 310 /* Display internal color functions */ 311 const struct intel_color_funcs *color; 312 313 /* Display internal audio functions */ 314 const struct intel_audio_funcs *audio; 315 } funcs; 316 317 struct { 318 bool any_task_allowed; 319 struct task_struct *allowed_task; 320 } access; 321 322 struct { 323 /* backlight registers and fields in struct intel_panel */ 324 struct mutex lock; 325 } backlight; 326 327 struct { 328 struct intel_global_obj obj; 329 330 struct intel_bw_info { 331 /* for each QGV point */ 332 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 333 /* for each PSF GV point */ 334 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 335 /* Peak BW for each QGV point */ 336 unsigned int peakbw[I915_NUM_QGV_POINTS]; 337 u8 num_qgv_points; 338 u8 num_psf_gv_points; 339 u8 num_planes; 340 } max[6]; 341 } bw; 342 343 struct { 344 /* The current hardware cdclk configuration */ 345 struct intel_cdclk_config hw; 346 347 /* cdclk, divider, and ratio table from bspec */ 348 const struct intel_cdclk_vals *table; 349 350 struct intel_global_obj obj; 351 352 unsigned int max_cdclk_freq; 353 unsigned int max_dotclk_freq; 354 unsigned int skl_preferred_vco_freq; 355 } cdclk; 356 357 struct { 358 struct drm_property_blob *glk_linear_degamma_lut; 359 } color; 360 361 struct { 362 /* The current hardware dbuf configuration */ 363 u8 enabled_slices; 364 365 struct intel_global_obj obj; 366 } dbuf; 367 368 struct { 369 /* 370 * dkl.phy_lock protects against concurrent access of the 371 * Dekel TypeC PHYs. 372 */ 373 spinlock_t phy_lock; 374 } dkl; 375 376 struct { 377 struct intel_dmc *dmc; 378 intel_wakeref_t wakeref; 379 } dmc; 380 381 struct { 382 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 383 u32 mmio_base; 384 } dsi; 385 386 struct { 387 /* list of fbdev register on this device */ 388 struct intel_fbdev *fbdev; 389 struct work_struct suspend_work; 390 } fbdev; 391 392 struct { 393 unsigned int pll_freq; 394 u32 rx_config; 395 } fdi; 396 397 struct { 398 struct list_head obj_list; 399 } global; 400 401 struct { 402 /* 403 * Base address of where the gmbus and gpio blocks are located 404 * (either on PCH or on SoC for platforms without PCH). 405 */ 406 u32 mmio_base; 407 408 /* 409 * gmbus.mutex protects against concurrent usage of the single 410 * hw gmbus controller on different i2c buses. 411 */ 412 struct mutex mutex; 413 414 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 415 416 wait_queue_head_t wait_queue; 417 } gmbus; 418 419 struct { 420 struct i915_hdcp_arbiter *arbiter; 421 bool comp_added; 422 423 /* 424 * HDCP message struct for allocation of memory which can be 425 * reused when sending message to gsc cs. 426 * this is only populated post Meteorlake 427 */ 428 struct intel_hdcp_gsc_message *hdcp_message; 429 /* Mutex to protect the above hdcp related values. */ 430 struct mutex hdcp_mutex; 431 } hdcp; 432 433 struct { 434 /* 435 * HTI (aka HDPORT) state read during initial hw readout. Most 436 * platforms don't have HTI, so this will just stay 0. Those 437 * that do will use this later to figure out which PLLs and PHYs 438 * are unavailable for driver usage. 439 */ 440 u32 state; 441 } hti; 442 443 struct { 444 /* Access with DISPLAY_INFO() */ 445 const struct intel_display_device_info *__device_info; 446 447 /* Access with DISPLAY_RUNTIME_INFO() */ 448 struct intel_display_runtime_info __runtime_info; 449 } info; 450 451 struct { 452 bool false_color; 453 } ips; 454 455 struct { 456 bool display_irqs_enabled; 457 458 /* For i915gm/i945gm vblank irq workaround */ 459 u8 vblank_enabled; 460 461 int vblank_wa_num_pipes; 462 463 struct work_struct vblank_dc_work; 464 465 u32 de_irq_mask[I915_MAX_PIPES]; 466 u32 pipestat_irq_mask[I915_MAX_PIPES]; 467 } irq; 468 469 struct { 470 wait_queue_head_t waitqueue; 471 472 /* mutex to protect pmdemand programming sequence */ 473 struct mutex lock; 474 475 struct intel_global_obj obj; 476 } pmdemand; 477 478 struct { 479 struct i915_power_domains domains; 480 481 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 482 u32 chv_phy_control; 483 484 /* perform PHY state sanity checks? */ 485 bool chv_phy_assert[2]; 486 } power; 487 488 struct { 489 u32 mmio_base; 490 491 /* protects panel power sequencer state */ 492 struct mutex mutex; 493 } pps; 494 495 struct { 496 struct drm_property *broadcast_rgb; 497 struct drm_property *force_audio; 498 } properties; 499 500 struct { 501 unsigned long mask; 502 } quirks; 503 504 struct { 505 /* restore state for suspend/resume and display reset */ 506 struct drm_atomic_state *modeset_state; 507 struct drm_modeset_acquire_ctx reset_ctx; 508 } restore; 509 510 struct { 511 enum { 512 I915_SAGV_UNKNOWN = 0, 513 I915_SAGV_DISABLED, 514 I915_SAGV_ENABLED, 515 I915_SAGV_NOT_CONTROLLED 516 } status; 517 518 u32 block_time_us; 519 } sagv; 520 521 struct { 522 /* 523 * DG2: Mask of PHYs that were not calibrated by the firmware 524 * and should not be used. 525 */ 526 u8 phy_failed_calibration; 527 } snps; 528 529 struct { 530 /* 531 * Shadows for CHV DPLL_MD regs to keep the state 532 * checker somewhat working in the presence hardware 533 * crappiness (can't read out DPLL_MD for pipes B & C). 534 */ 535 u32 chv_dpll_md[I915_MAX_PIPES]; 536 u32 bxt_phy_grc; 537 } state; 538 539 struct { 540 /* ordered wq for modesets */ 541 struct workqueue_struct *modeset; 542 543 /* unbound hipri wq for page flips/plane updates */ 544 struct workqueue_struct *flip; 545 } wq; 546 547 /* Grouping using named structs. Keep sorted. */ 548 struct drm_dp_tunnel_mgr *dp_tunnel_mgr; 549 struct intel_audio audio; 550 struct intel_dpll dpll; 551 struct intel_fbc *fbc[I915_MAX_FBCS]; 552 struct intel_frontbuffer_tracking fb_tracking; 553 struct intel_hotplug hotplug; 554 struct intel_opregion *opregion; 555 struct intel_overlay *overlay; 556 struct intel_display_params params; 557 struct intel_vbt_data vbt; 558 struct intel_dmc_wl wl; 559 struct intel_wm wm; 560 }; 561 562 #endif /* __INTEL_DISPLAY_CORE_H__ */ 563