xref: /illumos-gate/usr/src/uts/sun4u/io/i2c/nexus/pcf8584.c (revision 193974072f41a843678abf5f61979c748687e66b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 
27 /*
28  * pcf8584.c is the nexus driver for all pcf8584 controller
29  * implementations.  It supports both interrupt and polled
30  * mode operation, but defaults to interrupt.
31  */
32 
33 #include <sys/types.h>
34 #include <sys/conf.h>
35 #include <sys/file.h>
36 #include <sys/open.h>
37 #include <sys/ddi.h>
38 #include <sys/sunddi.h>
39 #include <sys/sunndi.h>
40 #include <sys/modctl.h>
41 #include <sys/stat.h>
42 #include <sys/kmem.h>
43 #include <sys/archsystm.h>
44 #include <sys/platform_module.h>
45 
46 #include <sys/i2c/clients/i2c_client.h>
47 #include <sys/i2c/misc/i2c_svc.h>
48 #include <sys/i2c/misc/i2c_svc_impl.h>
49 #include <sys/i2c/nexus/pcf8584.h>
50 
51 #include <sys/note.h>
52 
53 /*
54  * static function declarations
55  */
56 static void pcf8584_resume(dev_info_t *dip);
57 static void pcf8584_suspend(dev_info_t *dip);
58 static int pcf8584_bus_ctl(dev_info_t *dip, dev_info_t *rdip,
59 	ddi_ctl_enum_t op, void *arg, void *result);
60 static  void pcf8584_acquire(pcf8584_t *, dev_info_t *dip,
61 	i2c_transfer_t *tp, boolean_t force);
62 static  void pcf8584_release(pcf8584_t *, boolean_t force);
63 static int pcf8584_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
64 static int pcf8584_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
65 static int pcf8584_open(dev_t *devp, int flag, int otyp,
66     cred_t *cred_p);
67 static int pcf8584_close(dev_t dev, int flag, int otyp,
68     cred_t *cred_p);
69 static int pcf8584_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
70 static void pcf8584_select_bus(pcf8584_t *i2c);
71 static enum tran_state pcf8584_type_to_state(int i2c_flags);
72 static void pcf8584_put_s1(pcf8584_t *i2c, char cmd);
73 static void pcf8584_put_s0(pcf8584_t *i2c, char data);
74 static uint8_t pcf8584_get_s0(pcf8584_t *i2c);
75 static uint8_t pcf8584_get_s1(pcf8584_t *i2c);
76 static int pcf8584_bbn_ready(pcf8584_t *i2c);
77 static int pcf8584_error(int status, uint8_t rdwr, pcf8584_t *i2c);
78 static void pcf8584_monitor_mode(pcf8584_t *i2c);
79 static int pcf8584_initchild(dev_info_t *cdip);
80 static void pcf8584_uninitchild(dev_info_t *cdip);
81 static void pcf8584_init(pcf8584_t *i2c);
82 static int pcf8584_setup_regs(dev_info_t *dip, pcf8584_t *i2c);
83 static void pcf8584_free_regs(pcf8584_t *i2c);
84 static void pcf8584_reportdev(dev_info_t *dip, dev_info_t *rdip);
85 static int pcf8584_dip_to_addr(dev_info_t *dip);
86 static uint_t pcf8584_intr(caddr_t arg);
87 static int pcf8584_process(pcf8584_t *i2c, uint8_t s1);
88 int pcf8584_transfer(dev_info_t *dip, i2c_transfer_t *tp);
89 
90 static void pcf8584_do_polled_io(pcf8584_t *i2c);
91 static void pcf8584_take_over(pcf8584_t *i2c, dev_info_t *dip,
92     i2c_transfer_t *tp, kcondvar_t **waiter, int *saved_mode);
93 static void pcf8584_give_up(pcf8584_t *i2c, kcondvar_t *waiter, int saved_mode);
94 
95 static struct bus_ops pcf8584_busops = {
96 	BUSO_REV,
97 	nullbusmap,			/* bus_map */
98 	NULL,				/* bus_get_intrspec */
99 	NULL,				/* bus_add_intrspec */
100 	NULL,				/* bus_remove_intrspec */
101 	NULL,				/* bus_map_fault */
102 	ddi_no_dma_map,			/* bus_dma_map */
103 	ddi_no_dma_allochdl,		/* bus_dma_allochdl */
104 	ddi_no_dma_freehdl,		/* bus_dma_freehdl */
105 	ddi_no_dma_bindhdl,		/* bus_dma_bindhdl */
106 	ddi_no_dma_unbindhdl,		/* bus_unbindhdl */
107 	ddi_no_dma_flush,		/* bus_dma_flush */
108 	ddi_no_dma_win,			/* bus_dma_win */
109 	ddi_no_dma_mctl,		/* bus_dma_ctl */
110 	pcf8584_bus_ctl,		/* bus_ctl */
111 	ddi_bus_prop_op,		/* bus_prop_op */
112 	NULL,				/* bus_get_eventcookie */
113 	NULL,				/* bus_add_eventcall */
114 	NULL,				/* bus_remove_eventcall */
115 	NULL,				/* bus_post_event */
116 	0,				/* bus_intr_ctl */
117 	0,				/* bus_config		*/
118 	0,				/* bus_unconfig		*/
119 	0,				/* bus_fm_init		*/
120 	0,				/* bus_fm_fini		*/
121 	0,				/* bus_fm_access_enter	*/
122 	0,				/* bus_fm_access_exit	*/
123 	0,				/* bus_power		*/
124 	i_ddi_intr_ops			/* bus_intr_op		*/
125 };
126 
127 struct cb_ops pcf8584_cb_ops = {
128 	pcf8584_open,		/* open */
129 	pcf8584_close,	/* close */
130 	nodev,			/* strategy */
131 	nodev,			/* print */
132 	nodev,			/* dump */
133 	nodev,			/* read */
134 	nodev,			/* write */
135 	pcf8584_ioctl,		/* ioctl */
136 	nodev,			/* devmap */
137 	nodev,			/* mmap */
138 	nodev,			/* segmap */
139 	nochpoll,		/* poll */
140 	ddi_prop_op,		/* cb_prop_op */
141 	0,			/* streamtab  */
142 	D_MP | D_NEW		/* Driver compatibility flag */
143 };
144 
145 static struct dev_ops pcf8584_ops = {
146 	DEVO_REV,
147 	0,
148 	ddi_getinfo_1to1,
149 	nulldev,
150 	nulldev,
151 	pcf8584_attach,
152 	pcf8584_detach,
153 	nodev,
154 	&pcf8584_cb_ops,
155 	&pcf8584_busops,
156 	NULL,
157 	ddi_quiesce_not_supported,	/* devo_quiesce */
158 };
159 
160 static struct modldrv modldrv = {
161 	&mod_driverops, /* Type of module. This one is a driver */
162 	"I2C Nexus Driver",	/* Name of the module. */
163 	&pcf8584_ops,		/* driver ops */
164 };
165 
166 static struct modlinkage modlinkage = {
167 	MODREV_1,
168 	&modldrv,
169 	NULL
170 };
171 
172 /*
173  * pcf8584 soft state
174  */
175 static void	*pcf8584_state;
176 
177 i2c_nexus_reg_t pcf8584_regvec = {
178 	I2C_NEXUS_REV,
179 	pcf8584_transfer,
180 };
181 
182 /*
183  * The "interrupt_priorities" property is how a driver can specify a SPARC
184  * PIL level to associate with each of its interrupt properties.  Most
185  * self-identifying busses have a better mechanism for managing this, but I2C
186  * doesn't.
187  */
188 int	pcf8584_pil = PCF8584_PIL;
189 
190 #ifdef DEBUG
191 int pcf8584_print_lvl = 0;
192 static kmutex_t msg_buf_lock;
193 static char msg_buff[1024];
194 #define	PCF8584_DDB(command)	\
195 	do {			\
196 		{ command; }	\
197 		_NOTE(CONSTANTCONDITION)	\
198 	} while (0)
199 
200 static void
pcf8584_print(int flags,const char * fmt,...)201 pcf8584_print(int flags, const char *fmt, ...)
202 {
203 	if (flags & pcf8584_print_lvl) {
204 		va_list ap;
205 
206 		va_start(ap, fmt);
207 
208 		if (pcf8584_print_lvl & PRT_PROM) {
209 			prom_vprintf(fmt, ap);
210 		} else {
211 			mutex_enter(&msg_buf_lock);
212 			(void) vsprintf(msg_buff, fmt, ap);
213 			if (pcf8584_print_lvl & PRT_BUFFONLY) {
214 				cmn_err(CE_CONT, "?%s", msg_buff);
215 			} else {
216 				cmn_err(CE_CONT, "%s", msg_buff);
217 			}
218 			mutex_exit(&msg_buf_lock);
219 		}
220 		va_end(ap);
221 	}
222 }
223 #else
224 #define	PCF8584_DDB(command) \
225 	do {			\
226 		{ _NOTE(EMPTY); }	\
227 		_NOTE(CONSTANTCONDITION)	\
228 	} while (0)
229 #endif
230 
231 #define	PCF8584_IMPL_DELAY(type, delay)	\
232 	if (type == PIC16F747) {	\
233 		drv_usecwait(delay);	\
234 	}
235 
236 int
_init(void)237 _init(void)
238 {
239 	int status;
240 
241 	status = ddi_soft_state_init(&pcf8584_state, sizeof (pcf8584_t),
242 	    PCF8584_INITIAL_SOFT_SPACE);
243 	if (status != 0) {
244 
245 		return (status);
246 	}
247 
248 	if ((status = mod_install(&modlinkage)) != 0) {
249 		ddi_soft_state_fini(&pcf8584_state);
250 	}
251 
252 	return (status);
253 }
254 
255 int
_fini(void)256 _fini(void)
257 {
258 	int status;
259 
260 	if ((status = mod_remove(&modlinkage)) == 0) {
261 		ddi_soft_state_fini(&pcf8584_state);
262 	}
263 
264 	return (status);
265 }
266 
267 /*
268  * The loadable-module _info(9E) entry point
269  */
270 int
_info(struct modinfo * modinfop)271 _info(struct modinfo *modinfop)
272 {
273 	return (mod_info(&modlinkage, modinfop));
274 }
275 
276 static void
pcf8584_dodetach(dev_info_t * dip)277 pcf8584_dodetach(dev_info_t *dip)
278 {
279 	pcf8584_t *i2c;
280 	int instance = ddi_get_instance(dip);
281 
282 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, instance);
283 
284 	if ((i2c->pcf8584_attachflags & ADD_INTR) != 0) {
285 		ddi_remove_intr(dip, 0, i2c->pcf8584_icookie);
286 	}
287 
288 	cv_destroy(&i2c->pcf8584_cv);
289 
290 	if ((i2c->pcf8584_attachflags & IMUTEX) != 0) {
291 		mutex_destroy(&i2c->pcf8584_imutex);
292 			cv_destroy(&i2c->pcf8584_icv);
293 	}
294 	if ((i2c->pcf8584_attachflags & SETUP_REGS) != 0) {
295 		pcf8584_free_regs(i2c);
296 	}
297 	if ((i2c->pcf8584_attachflags & NEXUS_REGISTER) != 0) {
298 		i2c_nexus_unregister(dip);
299 	}
300 	if ((i2c->pcf8584_attachflags & PROP_CREATE) != 0) {
301 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
302 		    "interrupt-priorities");
303 	}
304 	if ((i2c->pcf8584_attachflags & MINOR_NODE) != 0) {
305 		ddi_remove_minor_node(dip, NULL);
306 	}
307 
308 	ddi_soft_state_free(pcf8584_state, instance);
309 }
310 
311 static int
pcf8584_doattach(dev_info_t * dip)312 pcf8584_doattach(dev_info_t *dip)
313 {
314 	pcf8584_t *i2c;
315 	int instance = ddi_get_instance(dip);
316 
317 	/*
318 	 * Allocate soft state structure.
319 	 */
320 	if (ddi_soft_state_zalloc(pcf8584_state, instance) != DDI_SUCCESS) {
321 
322 		return (DDI_FAILURE);
323 	}
324 
325 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, instance);
326 
327 	i2c->pcf8584_dip = dip;
328 
329 	(void) snprintf(i2c->pcf8584_name, sizeof (i2c->pcf8584_name),
330 	    "%s_%d", ddi_node_name(dip), instance);
331 
332 	/*
333 	 * Identify which pcf8584 implementation is being attached to.
334 	 */
335 	if (strcmp(ddi_binding_name(i2c->pcf8584_dip), "SUNW,bbc-i2c") == 0) {
336 		i2c->pcf8584_impl_type = BBC;
337 		i2c->pcf8584_impl_delay = PCF8584_GENERIC_DELAY;
338 	} else if (strcmp(ddi_binding_name(i2c->pcf8584_dip),
339 	    "SUNW,i2c-pic16f747") == 0) {
340 		i2c->pcf8584_impl_type = PIC16F747;
341 		i2c->pcf8584_impl_delay = PCF8584_PIC16F747_DELAY;
342 	} else {
343 		i2c->pcf8584_impl_type = GENERIC;
344 		i2c->pcf8584_impl_delay = PCF8584_GENERIC_DELAY;
345 	}
346 
347 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip,
348 	    DDI_PROP_NOTPROM | DDI_PROP_DONTPASS,
349 	    "interrupt-priorities") != 1) {
350 		(void) ddi_prop_create(DDI_DEV_T_NONE, dip,
351 		    DDI_PROP_CANSLEEP, "interrupt-priorities",
352 		    (caddr_t)&pcf8584_pil,
353 		    sizeof (pcf8584_pil));
354 		i2c->pcf8584_attachflags |= PROP_CREATE;
355 	}
356 
357 	cv_init(&i2c->pcf8584_cv, NULL, CV_DRIVER, NULL);
358 
359 	if (pcf8584_setup_regs(dip, i2c) != DDI_SUCCESS) {
360 		goto bad;
361 	}
362 
363 	i2c->pcf8584_attachflags |= SETUP_REGS;
364 
365 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS |
366 	    DDI_PROP_CANSLEEP, "poll-mode") == 1) {
367 		i2c->pcf8584_mode = PCF8584_POLL_MODE;
368 	} else {
369 
370 		if (ddi_get_iblock_cookie(dip, 0,
371 		    &i2c->pcf8584_icookie) == DDI_SUCCESS) {
372 			mutex_init(&i2c->pcf8584_imutex, NULL, MUTEX_DRIVER,
373 			    (void *)i2c->pcf8584_icookie);
374 			cv_init(&i2c->pcf8584_icv, NULL, CV_DRIVER, NULL);
375 			i2c->pcf8584_attachflags |= IMUTEX;
376 
377 			if (ddi_add_intr(dip, 0, NULL, NULL, pcf8584_intr,
378 			    (caddr_t)i2c) == DDI_SUCCESS) {
379 				i2c->pcf8584_attachflags |= ADD_INTR;
380 				i2c->pcf8584_mode = PCF8584_INTR_MODE;
381 			} else {
382 				cmn_err(CE_WARN, "%s failed to add interrupt",
383 				    i2c->pcf8584_name);
384 				i2c->pcf8584_mode = PCF8584_POLL_MODE;
385 			}
386 		} else {
387 			cmn_err(CE_WARN, "%s failed to retrieve iblock cookie. "
388 			    "Operating in POLL MODE only", i2c->pcf8584_name);
389 			i2c->pcf8584_mode = PCF8584_POLL_MODE;
390 		}
391 	}
392 
393 	/*
394 	 * For polled mode, still initialize a cv and mutex
395 	 */
396 	if ((i2c->pcf8584_attachflags & IMUTEX) == 0) {
397 		cv_init(&i2c->pcf8584_icv, NULL, CV_DRIVER, NULL);
398 		mutex_init(&i2c->pcf8584_imutex, NULL, MUTEX_DRIVER, NULL);
399 		i2c->pcf8584_attachflags |= IMUTEX;
400 	}
401 
402 	i2c_nexus_register(dip, &pcf8584_regvec);
403 	i2c->pcf8584_attachflags |= NEXUS_REGISTER;
404 
405 	if (ddi_create_minor_node(dip, "devctl", S_IFCHR, instance,
406 	    DDI_NT_NEXUS, 0) == DDI_FAILURE) {
407 		cmn_err(CE_WARN, "%s ddi_create_minor_node failed",
408 		    i2c->pcf8584_name);
409 		goto bad;
410 	}
411 
412 	i2c->pcf8584_attachflags |= MINOR_NODE;
413 
414 	pcf8584_init(i2c);
415 
416 	i2c->pcf8584_nexus_dip = dip;
417 
418 	return (DDI_SUCCESS);
419 
420 bad:
421 	pcf8584_dodetach(dip);
422 
423 	return (DDI_FAILURE);
424 }
425 
426 static int
pcf8584_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)427 pcf8584_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
428 {
429 	switch (cmd) {
430 	case DDI_ATTACH:
431 
432 		return (pcf8584_doattach(dip));
433 	case DDI_RESUME:
434 		pcf8584_resume(dip);
435 
436 		return (DDI_SUCCESS);
437 	default:
438 
439 		return (DDI_FAILURE);
440 	}
441 }
442 
443 static int
pcf8584_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)444 pcf8584_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
445 {
446 	switch (cmd) {
447 	case DDI_DETACH:
448 		pcf8584_dodetach(dip);
449 
450 		return (DDI_SUCCESS);
451 	case DDI_SUSPEND:
452 		pcf8584_suspend(dip);
453 
454 		return (DDI_SUCCESS);
455 	default:
456 
457 		return (DDI_FAILURE);
458 	}
459 }
460 
461 /*ARGSUSED*/
462 static int
pcf8584_open(dev_t * devp,int flag,int otyp,cred_t * cred_p)463 pcf8584_open(dev_t  *devp,  int  flag,  int  otyp,  cred_t *cred_p)
464 {
465 	int instance;
466 	pcf8584_t *i2c;
467 
468 	/*
469 	 * Make sure the open is for the right file type
470 	 */
471 	if (otyp != OTYP_CHR)
472 		return (EINVAL);
473 
474 	instance = getminor(*devp);
475 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, instance);
476 	if (i2c == NULL)
477 		return (ENXIO);
478 
479 	/*
480 	 * Enforce exclusive access
481 	 */
482 	mutex_enter(&i2c->pcf8584_imutex);
483 	if (i2c->pcf8584_open) {
484 		mutex_exit(&i2c->pcf8584_imutex);
485 
486 		return (EBUSY);
487 	} else
488 		i2c->pcf8584_open = 1;
489 	mutex_exit(&i2c->pcf8584_imutex);
490 
491 	return (0);
492 }
493 
494 /*ARGSUSED*/
495 static int
pcf8584_close(dev_t dev,int flag,int otyp,cred_t * cred_p)496 pcf8584_close(dev_t  dev,  int  flag,  int  otyp,  cred_t *cred_p)
497 {
498 	int instance;
499 	pcf8584_t *i2c;
500 
501 	/*
502 	 * Make sure the close is for the right file type
503 	 */
504 	if (otyp != OTYP_CHR)
505 		return (EINVAL);
506 
507 	instance = getminor(dev);
508 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, instance);
509 	if (i2c == NULL)
510 		return (ENXIO);
511 
512 	mutex_enter(&i2c->pcf8584_imutex);
513 	i2c->pcf8584_open = 0;
514 	mutex_exit(&i2c->pcf8584_imutex);
515 
516 	return (0);
517 }
518 
519 /*ARGSUSED*/
520 static int
pcf8584_ioctl(dev_t dev,int cmd,intptr_t arg,int mode,cred_t * credp,int * rvalp)521 pcf8584_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
522 	int *rvalp)
523 {
524 	pcf8584_t *i2c;
525 	dev_info_t *self;
526 	struct devctl_iocdata *dcp;
527 	int rv;
528 
529 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, getminor(dev));
530 	if (i2c == NULL)
531 		return (ENXIO);
532 
533 	self = (dev_info_t *)i2c->pcf8584_nexus_dip;
534 
535 	/*
536 	 * read devctl ioctl data
537 	 */
538 	if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) {
539 
540 		return (EFAULT);
541 	}
542 
543 	switch (cmd) {
544 		case DEVCTL_BUS_DEV_CREATE:
545 			rv = ndi_dc_devi_create(dcp, self, 0, NULL);
546 			break;
547 		case DEVCTL_DEVICE_REMOVE:
548 			rv = ndi_devctl_device_remove(self, dcp, 0);
549 			break;
550 		default:
551 			rv = ENOTSUP;
552 	}
553 
554 	ndi_dc_freehdl(dcp);
555 
556 	return (rv);
557 }
558 
559 static int
pcf8584_bus_ctl(dev_info_t * dip,dev_info_t * rdip,ddi_ctl_enum_t op,void * arg,void * result)560 pcf8584_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op,
561     void *arg, void *result)
562 {
563 	switch (op) {
564 	case DDI_CTLOPS_INITCHILD:
565 
566 		return (pcf8584_initchild((dev_info_t *)arg));
567 	case DDI_CTLOPS_UNINITCHILD:
568 		pcf8584_uninitchild((dev_info_t *)arg);
569 
570 		return (DDI_SUCCESS);
571 	case DDI_CTLOPS_REPORTDEV:
572 		pcf8584_reportdev(dip, rdip);
573 
574 		return (DDI_SUCCESS);
575 	case DDI_CTLOPS_DMAPMAPC:
576 	case DDI_CTLOPS_POKE:
577 	case DDI_CTLOPS_PEEK:
578 	case DDI_CTLOPS_IOMIN:
579 	case DDI_CTLOPS_REPORTINT:
580 	case DDI_CTLOPS_SIDDEV:
581 	case DDI_CTLOPS_SLAVEONLY:
582 	case DDI_CTLOPS_AFFINITY:
583 	case DDI_CTLOPS_PTOB:
584 	case DDI_CTLOPS_BTOP:
585 	case DDI_CTLOPS_BTOPR:
586 	case DDI_CTLOPS_DVMAPAGESIZE:
587 
588 		return (DDI_FAILURE);
589 	default:
590 
591 		return (ddi_ctlops(dip, rdip, op, arg, result));
592 	}
593 }
594 
595 /*
596  * pcf8584_suspend() is called before the system suspends.  Existing
597  * transfer in progress or waiting will complete, but new transfers are
598  * effectively blocked by "acquiring" the bus.
599  */
600 static void
pcf8584_suspend(dev_info_t * dip)601 pcf8584_suspend(dev_info_t *dip)
602 {
603 	pcf8584_t *i2c;
604 	int instance;
605 
606 	instance = ddi_get_instance(dip);
607 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, instance);
608 
609 	pcf8584_acquire(i2c, NULL, NULL, B_FALSE);
610 }
611 
612 /*
613  * pcf8584_resume() is called when the system resumes from CPR.  It releases
614  * the hold that was placed on the i2c bus, which allows any real
615  * transfers to continue.
616  */
617 static void
pcf8584_resume(dev_info_t * dip)618 pcf8584_resume(dev_info_t *dip)
619 {
620 	pcf8584_t *i2c;
621 	int instance;
622 
623 	instance = ddi_get_instance(dip);
624 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state, instance);
625 
626 	pcf8584_release(i2c, B_FALSE);
627 
628 	pcf8584_init(i2c);
629 }
630 
631 /*
632  * pcf8584_acquire() is called by a thread wishing to "own" the I2C bus.
633  * It should not be held across multiple transfers. If the 'force' flag
634  * is set, do not try to acquire mutex or do cv_wait.
635  */
636 static void
pcf8584_acquire(pcf8584_t * i2c,dev_info_t * dip,i2c_transfer_t * tp,boolean_t force)637 pcf8584_acquire(pcf8584_t *i2c, dev_info_t *dip, i2c_transfer_t *tp,
638     boolean_t force)
639 {
640 	if (force) {
641 		i2c->pcf8584_busy = 1;
642 		i2c->pcf8584_cur_tran = tp;
643 		i2c->pcf8584_cur_dip = dip;
644 		i2c->pcf8584_cur_status = PCF8584_TRANSFER_NEW;
645 		return;
646 	}
647 
648 	mutex_enter(&i2c->pcf8584_imutex);
649 	while (i2c->pcf8584_busy) {
650 		cv_wait(&i2c->pcf8584_cv, &i2c->pcf8584_imutex);
651 	}
652 	i2c->pcf8584_busy = 1;
653 	mutex_exit(&i2c->pcf8584_imutex);
654 	/*
655 	 * On systems where OBP shares a pcf8584 controller with the
656 	 * OS, plat_shared_i2c_enter will serialize access to the
657 	 * pcf8584 controller.  Do not grab this lock during CPR
658 	 * suspend as the CPR thread also acquires this muxex
659 	 * through through prom_setprop which causes recursive
660 	 * mutex enter.
661 	 *
662 	 * dip == NULL during CPR.
663 	 */
664 	if ((&plat_shared_i2c_enter != NULL) && (dip != NULL)) {
665 		plat_shared_i2c_enter(i2c->pcf8584_dip);
666 	}
667 
668 	mutex_enter(&i2c->pcf8584_imutex);
669 	i2c->pcf8584_cur_tran = tp;
670 	i2c->pcf8584_cur_dip = dip;
671 	mutex_exit(&i2c->pcf8584_imutex);
672 }
673 
674 /*
675  * pcf8584_release() is called to release a hold made by pcf8584_acquire().
676  */
677 static void
pcf8584_release(pcf8584_t * i2c,boolean_t force)678 pcf8584_release(pcf8584_t *i2c, boolean_t force)
679 {
680 	if (force) {
681 		i2c->pcf8584_busy = 0;
682 		i2c->pcf8584_cur_tran = NULL;
683 		i2c->pcf8584_cur_dip = NULL;
684 		i2c->pcf8584_cur_status = PCF8584_TRANSFER_OVER;
685 		cv_signal(&i2c->pcf8584_cv);
686 		return;
687 	}
688 
689 	mutex_enter(&i2c->pcf8584_imutex);
690 	i2c->pcf8584_busy = 0;
691 	i2c->pcf8584_cur_tran = NULL;
692 	cv_signal(&i2c->pcf8584_cv);
693 	mutex_exit(&i2c->pcf8584_imutex);
694 
695 	if ((&plat_shared_i2c_exit != NULL) && (i2c->pcf8584_cur_dip != NULL)) {
696 		plat_shared_i2c_exit(i2c->pcf8584_dip);
697 	}
698 }
699 
700 /*
701  * if pcf8584_b_reg exists, it means the current bus controller signals
702  * are multiplexed into more than a single bus.  Select the bus needed
703  * by writing to the mux register.
704  */
705 static void
pcf8584_select_bus(pcf8584_t * i2c)706 pcf8584_select_bus(pcf8584_t *i2c)
707 {
708 	int bus;
709 	pcf8584_ppvt_t *ppvt;
710 
711 	/*
712 	 * The existence of pcf8584_b_reg means the bus registers
713 	 * are multiplexed.
714 	 */
715 
716 	PCF8584_DDB(pcf8584_print(PRT_SELECT, "bus multiplex: %X\n",
717 	    i2c->pcf8584_b_reg));
718 	if (i2c->pcf8584_b_reg != NULL) {
719 		ppvt = ddi_get_parent_data(i2c->pcf8584_cur_dip);
720 
721 		bus = ppvt->pcf8584_ppvt_bus;
722 
723 		PCF8584_DDB(pcf8584_print(PRT_SELECT,
724 		    "transmitting bus number %d\n", bus));
725 
726 		ddi_put8(i2c->pcf8584_b_rhandle, i2c->pcf8584_b_reg, bus);
727 	}
728 }
729 
730 /*
731  * pcf8584_type_to_state() converts a transfer type to the
732  * next state of the I2C state machine based on the requested
733  * transfer type.
734  */
735 static enum tran_state
pcf8584_type_to_state(int i2c_flags)736 pcf8584_type_to_state(int i2c_flags)
737 {
738 	switch (i2c_flags) {
739 	case I2C_WR:
740 
741 		return (TRAN_STATE_WR);
742 	case I2C_RD:
743 
744 		return (TRAN_STATE_DUMMY_RD);
745 	case I2C_WR_RD:
746 
747 		return (TRAN_STATE_WR_RD);
748 	}
749 	/*NOTREACHED*/
750 	return (TRAN_STATE_NULL);
751 }
752 
753 /*
754  * pcf8584_put_s1() writes out cmd to register S1.
755  */
756 static void
pcf8584_put_s1(pcf8584_t * i2c,char cmd)757 pcf8584_put_s1(pcf8584_t *i2c, char cmd)
758 {
759 	ddi_acc_handle_t hp = i2c->pcf8584_rhandle;
760 	pcf8584_regs_t *rp = &i2c->pcf8584_regs;
761 
762 	ddi_put8(hp, rp->pcf8584_regs_s1, cmd);
763 	PCF8584_IMPL_DELAY(i2c->pcf8584_impl_type,
764 	    i2c->pcf8584_impl_delay);
765 	/*
766 	 * read status to make sure write is flushed
767 	 */
768 	(void) ddi_get8(hp, rp->pcf8584_regs_s1);
769 	PCF8584_IMPL_DELAY(i2c->pcf8584_impl_type,
770 	    i2c->pcf8584_impl_delay);
771 }
772 
773 /*
774  * pcf8584_put_s0() writes out data to register S0.
775  */
776 static void
pcf8584_put_s0(pcf8584_t * i2c,char data)777 pcf8584_put_s0(pcf8584_t *i2c, char data)
778 {
779 	ddi_acc_handle_t hp = i2c->pcf8584_rhandle;
780 	pcf8584_regs_t *rp = &i2c->pcf8584_regs;
781 
782 	ddi_put8(hp, rp->pcf8584_regs_s0, data);
783 	PCF8584_IMPL_DELAY(i2c->pcf8584_impl_type,
784 	    i2c->pcf8584_impl_delay);
785 	/*
786 	 * read status to make sure write is flushed
787 	 */
788 	(void) ddi_get8(hp, rp->pcf8584_regs_s1);
789 	PCF8584_IMPL_DELAY(i2c->pcf8584_impl_type,
790 	    i2c->pcf8584_impl_delay);
791 }
792 
793 /*
794  * pcf8584_get_s0() reads from register S0.
795  */
796 static uint8_t
pcf8584_get_s0(pcf8584_t * i2c)797 pcf8584_get_s0(pcf8584_t *i2c)
798 {
799 	ddi_acc_handle_t hp = i2c->pcf8584_rhandle;
800 	pcf8584_regs_t *rp = &i2c->pcf8584_regs;
801 	uint8_t s0;
802 
803 	s0 = ddi_get8(hp, rp->pcf8584_regs_s0);
804 	PCF8584_IMPL_DELAY(i2c->pcf8584_impl_type,
805 	    i2c->pcf8584_impl_delay);
806 
807 	return (s0);
808 }
809 
810 /*
811  * pcf8584_get_s1() reads from register S1.
812  */
813 static uint8_t
pcf8584_get_s1(pcf8584_t * i2c)814 pcf8584_get_s1(pcf8584_t *i2c)
815 {
816 	ddi_acc_handle_t hp = i2c->pcf8584_rhandle;
817 	pcf8584_regs_t *rp = &i2c->pcf8584_regs;
818 	uint8_t s1;
819 
820 	s1 = ddi_get8(hp, rp->pcf8584_regs_s1);
821 	PCF8584_IMPL_DELAY(i2c->pcf8584_impl_type,
822 	    i2c->pcf8584_impl_delay);
823 
824 	return (s1);
825 }
826 
827 /*
828  * If the previous transaction was a write, the stop
829  * bit may not make it out on the wire before
830  * the next transaction startes.  And unfortunately, there
831  * is no interrupt after the stop bit is written, so this
832  * function will poll to make sure the BBC is ready.
833  */
834 static int
pcf8584_bbn_ready(pcf8584_t * i2c)835 pcf8584_bbn_ready(pcf8584_t *i2c)
836 {
837 	uint8_t s1;
838 	int usecwaits = 0;
839 
840 	s1 = pcf8584_get_s1(i2c);
841 
842 	while ((s1 & S1_BBN) == 0) {
843 
844 		if (usecwaits++ == 100) {
845 			/* Try initializing the bus */
846 			pcf8584_monitor_mode(i2c);
847 			pcf8584_put_s1(i2c, S1_STOP);
848 			delay(1);
849 			pcf8584_init(i2c);
850 			(void) pcf8584_get_s0(i2c);
851 			s1 = pcf8584_get_s1(i2c);
852 			if (s1 & S1_BBN) {
853 				cmn_err(CE_WARN,
854 				    "!%s: cleared bus busy.   addr=0x%x",
855 				    i2c->pcf8584_name,
856 				    pcf8584_dip_to_addr(i2c->pcf8584_cur_dip));
857 
858 				return (I2C_SUCCESS);
859 			} else {
860 				cmn_err(CE_WARN,
861 				    "!%s bus busy after init addr=0x%x",
862 				    i2c->pcf8584_name,
863 				    pcf8584_dip_to_addr(i2c->pcf8584_cur_dip));
864 
865 				return (I2C_FAILURE);
866 			}
867 		}
868 		drv_usecwait(1);
869 		s1 = pcf8584_get_s1(i2c);
870 	}
871 
872 	return (I2C_SUCCESS);
873 }
874 
875 static int
pcf8584_error(int status,uint8_t rdwr,pcf8584_t * i2c)876 pcf8584_error(int status, uint8_t rdwr, pcf8584_t *i2c)
877 {
878 	int addr = pcf8584_dip_to_addr(i2c->pcf8584_cur_dip);
879 	pcf8584_regs_t *rp = &i2c->pcf8584_regs;
880 
881 	if (status & S1_BER) {
882 		cmn_err(CE_WARN,
883 		    "!%s bus error; Controller = 0x%p "
884 		    " addr = 0x%x", i2c->pcf8584_name,
885 		    (void *)rp->pcf8584_regs_s1, addr);
886 		pcf8584_init(i2c);
887 
888 		return (I2C_FAILURE);
889 	} else if (status & S1_LAB) {
890 		cmn_err(CE_WARN, "!%s lost arbitration; Controller ="
891 		    " 0x%p addr = 0x%x", i2c->pcf8584_name,
892 		    (void *)rp->pcf8584_regs_s1, addr);
893 		pcf8584_init(i2c);
894 
895 		return (I2C_FAILURE);
896 	} else if ((status & S1_LRB) && (rdwr == I2C_WR)) {
897 		/*
898 		 * No error logged here, because this may be benign.
899 		 * Cf. the "Alert Response Address" feature of SMBUS.
900 		 */
901 		pcf8584_put_s1(i2c, S1_STOP);
902 
903 		return (I2C_FAILURE);
904 	}
905 
906 	return (I2C_SUCCESS);
907 }
908 
909 static void
pcf8584_monitor_mode(pcf8584_t * i2c)910 pcf8584_monitor_mode(pcf8584_t *i2c)
911 {
912 	pcf8584_put_s1(i2c, S1_PIN);
913 
914 	pcf8584_put_s0(i2c, MONITOR_ADDRESS);
915 }
916 
917 static int
pcf8584_initchild(dev_info_t * cdip)918 pcf8584_initchild(dev_info_t *cdip)
919 {
920 	int32_t cell_size;
921 	int len;
922 	int32_t regs[2];
923 	int err;
924 	pcf8584_ppvt_t *ppvt;
925 	char name[30];
926 
927 	PCF8584_DDB(pcf8584_print(PRT_INIT, "pcf8584_initchild enter: %s\n",
928 	    ddi_node_name(cdip)));
929 
930 	ppvt = kmem_alloc(sizeof (pcf8584_ppvt_t), KM_SLEEP);
931 
932 	len = sizeof (cell_size);
933 	err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip,
934 	    DDI_PROP_CANSLEEP, "#address-cells",
935 	    (caddr_t)&cell_size, &len);
936 	if (err != DDI_PROP_SUCCESS || len != sizeof (cell_size)) {
937 
938 		return (DDI_FAILURE);
939 	}
940 
941 	len = sizeof (regs);
942 	err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip,
943 	    DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP,
944 	    "reg", (caddr_t)regs, &len);
945 	if (err != DDI_PROP_SUCCESS ||
946 	    len != (cell_size * sizeof (int32_t))) {
947 
948 		return (DDI_FAILURE);
949 	}
950 
951 	if (cell_size == 1) {
952 		ppvt->pcf8584_ppvt_addr = regs[0];
953 		(void) sprintf(name, "%x", regs[0]);
954 	} else if (cell_size == 2) {
955 		ppvt->pcf8584_ppvt_bus = regs[0];
956 		ppvt->pcf8584_ppvt_addr = regs[1];
957 		(void) sprintf(name, "%x,%x", regs[0], regs[1]);
958 	} else {
959 
960 		return (DDI_FAILURE);
961 	}
962 
963 	ddi_set_parent_data(cdip, ppvt);
964 
965 	ddi_set_name_addr(cdip, name);
966 
967 	PCF8584_DDB(pcf8584_print(PRT_INIT,
968 	    "pcf8584_initchild SUCCESS: %s\n", ddi_node_name(cdip)));
969 
970 	return (DDI_SUCCESS);
971 }
972 
973 static void
pcf8584_uninitchild(dev_info_t * cdip)974 pcf8584_uninitchild(dev_info_t *cdip)
975 {
976 	pcf8584_ppvt_t *ppvt;
977 
978 	ppvt = ddi_get_parent_data(cdip);
979 	kmem_free(ppvt, sizeof (pcf8584_ppvt_t));
980 
981 	ddi_set_parent_data(cdip, NULL);
982 	ddi_set_name_addr(cdip, NULL);
983 
984 	PCF8584_DDB(pcf8584_print(PRT_INIT, "i2c_uninitchild: %s\n",
985 	    ddi_node_name(cdip)));
986 }
987 
988 static void
pcf8584_init(pcf8584_t * i2c)989 pcf8584_init(pcf8584_t *i2c)
990 {
991 	uint8_t clk_div = 0x1C;
992 
993 	pcf8584_put_s1(i2c, S1_PIN);
994 
995 	pcf8584_put_s0(i2c, S0_OWN);
996 
997 	pcf8584_put_s1(i2c, S1_PIN | S1_ES1);
998 
999 	/*
1000 	 * The default case is to set the clock divisor to the least common
1001 	 * denominator to avoid over clocking the I2C bus.  Assume that
1002 	 * BBC based systems are using the Safari clock as input, so select
1003 	 * the clk divisor based on it.
1004 	 */
1005 	if (i2c->pcf8584_impl_type == BBC) {
1006 		dev_info_t *root_node;
1007 		int clock_freq;
1008 		root_node = ddi_root_node();
1009 		clock_freq = ddi_prop_get_int(DDI_DEV_T_ANY, root_node,
1010 		    DDI_PROP_DONTPASS, "clock-frequency", 0);
1011 
1012 		if (clock_freq < 105000000) {
1013 			clk_div = 0x00;
1014 		} else if (clock_freq < 160000000) {
1015 			clk_div = 0x10;
1016 		} else {
1017 			clk_div = 0x1C;
1018 		}
1019 	}
1020 
1021 	/* set I2C clock speed */
1022 	pcf8584_put_s0(i2c, clk_div);
1023 
1024 	pcf8584_put_s1(i2c, S1_PIN | S1_ESO | S1_ACK);
1025 
1026 	/*
1027 	 * Multi-Master: Wait for a period of time equal to the
1028 	 * longest I2C message.  This accounts for the case
1029 	 * where multiple controllers and, if this particular one
1030 	 * is "lagging", misses the BB(bus busy) condition.
1031 	 * We wait 200 ms since the longest transaction at this time
1032 	 * on the i2c bus is a 256 byte read from the seprom which takes
1033 	 * about 75 ms. Some additional buffer does no harm to the driver.
1034 	 */
1035 
1036 	delay(drv_usectohz(PCF8584_INIT_WAIT));
1037 }
1038 
1039 /*
1040  * pcf8584_setup_regs() is called to map in registers specific to
1041  * the pcf8584.
1042  */
1043 static int
pcf8584_setup_regs(dev_info_t * dip,pcf8584_t * i2c)1044 pcf8584_setup_regs(dev_info_t *dip, pcf8584_t *i2c)
1045 {
1046 	int nregs;
1047 	ddi_device_acc_attr_t attr;
1048 	caddr_t reg_base;
1049 
1050 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1051 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
1052 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1053 
1054 	if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) {
1055 
1056 		return (DDI_FAILURE);
1057 	}
1058 
1059 	if (ddi_regs_map_setup(dip, 0,
1060 	    (caddr_t *)&reg_base, 0, 0, &attr,
1061 	    &i2c->pcf8584_rhandle) != DDI_SUCCESS) {
1062 
1063 		return (DDI_FAILURE);
1064 	}
1065 
1066 	/*
1067 	 * If i2c controller is on BBC, then s1 comes before s0.
1068 	 */
1069 	if (i2c->pcf8584_impl_type == BBC) {
1070 		i2c->pcf8584_regs.pcf8584_regs_s0 =
1071 		    (uint8_t *)&reg_base[1];
1072 		i2c->pcf8584_regs.pcf8584_regs_s1 =
1073 		    (uint8_t *)&reg_base[0];
1074 	} else {
1075 		i2c->pcf8584_regs.pcf8584_regs_s0 =
1076 		    (uint8_t *)&reg_base[0];
1077 		i2c->pcf8584_regs.pcf8584_regs_s1 =
1078 		    (uint8_t *)&reg_base[1];
1079 	}
1080 
1081 	if (nregs > 1) {
1082 		if (ddi_regs_map_setup(dip,
1083 		    1, (caddr_t *)&i2c->pcf8584_b_reg,
1084 		    0, 0, &attr, &i2c->pcf8584_b_rhandle) !=
1085 		    DDI_SUCCESS) {
1086 
1087 			return (DDI_FAILURE);
1088 		}
1089 	}
1090 
1091 	return (DDI_SUCCESS);
1092 }
1093 
1094 /*
1095  * pcf8584_free_regs() frees any registers previously
1096  * allocated.
1097  */
1098 static void
pcf8584_free_regs(pcf8584_t * i2c)1099 pcf8584_free_regs(pcf8584_t *i2c)
1100 {
1101 	if (i2c->pcf8584_regs.pcf8584_regs_s0 != NULL) {
1102 		ddi_regs_map_free(&i2c->pcf8584_rhandle);
1103 	}
1104 	if (i2c->pcf8584_b_reg != NULL) {
1105 		ddi_regs_map_free(&i2c->pcf8584_b_rhandle);
1106 	}
1107 }
1108 
1109 static void
pcf8584_reportdev(dev_info_t * dip,dev_info_t * rdip)1110 pcf8584_reportdev(dev_info_t *dip, dev_info_t *rdip)
1111 {
1112 	pcf8584_ppvt_t *ppvt;
1113 
1114 	ppvt = ddi_get_parent_data(rdip);
1115 
1116 	cmn_err(CE_CONT, "?%s%d at %s%d: addr 0x%x",
1117 	    ddi_driver_name(rdip), ddi_get_instance(rdip),
1118 	    ddi_driver_name(dip), ddi_get_instance(dip),
1119 	    ppvt->pcf8584_ppvt_addr);
1120 }
1121 
1122 /*
1123  * i2_nexus_dip_to_addr() takes a dip and returns an I2C address.
1124  */
1125 static int
pcf8584_dip_to_addr(dev_info_t * dip)1126 pcf8584_dip_to_addr(dev_info_t *dip)
1127 {
1128 	pcf8584_ppvt_t *ppvt;
1129 
1130 	ppvt = ddi_get_parent_data(dip);
1131 
1132 	return (ppvt->pcf8584_ppvt_addr);
1133 }
1134 
1135 /*
1136  * pcf8584_intr() is the interrupt service routine registered during
1137  * attach, and remains registered even if the driver is in POLLED mode.  So if
1138  * this is called from POLLED mode, it needs to return without doing
1139  * any work to prevent the I2C bus from entering an unknown state.
1140  */
1141 static uint_t
pcf8584_intr(caddr_t arg)1142 pcf8584_intr(caddr_t arg)
1143 {
1144 	pcf8584_t *i2c = (pcf8584_t *)arg;
1145 	uint8_t s1;
1146 
1147 	ASSERT(i2c->pcf8584_mode != PCF8584_POLL_MODE);
1148 	PCF8584_DDB(pcf8584_print(PRT_INTR, "pcf8584_intr: enter\n"));
1149 
1150 	mutex_enter(&i2c->pcf8584_imutex);
1151 
1152 	/*
1153 	 * It is necessary to check both whether the hardware is interrupting
1154 	 * and that there is a current transaction for the bus in progress.
1155 	 * Checking just one but not the other will lead to a panic on xcal
1156 	 * since both controllers share the same ino, and also because OBP
1157 	 * shares a controller with the kernel even while the kernel is running.
1158 	 */
1159 
1160 	if (i2c->pcf8584_cur_tran == NULL) {
1161 		mutex_exit(&i2c->pcf8584_imutex);
1162 
1163 		return (DDI_INTR_UNCLAIMED);
1164 	}
1165 
1166 
1167 	s1 = pcf8584_get_s1(i2c);
1168 	if (s1 & S1_PIN) {
1169 		mutex_exit(&i2c->pcf8584_imutex);
1170 
1171 		return (DDI_INTR_UNCLAIMED);
1172 	}
1173 
1174 	if (pcf8584_process(i2c, s1) == I2C_COMPLETE) {
1175 		i2c->pcf8584_tran_state = TRAN_STATE_NULL;
1176 		i2c->pcf8584_cur_status = PCF8584_TRANSFER_OVER;
1177 		cv_signal(&i2c->pcf8584_icv);
1178 	} else
1179 		i2c->pcf8584_cur_status = PCF8584_TRANSFER_ON;
1180 
1181 	mutex_exit(&i2c->pcf8584_imutex);
1182 
1183 	return (DDI_INTR_CLAIMED);
1184 }
1185 
1186 /*
1187  * Interrupt occurs after a byte is transmitted or received, indicating
1188  * the device is ready to be serviced.
1189  */
1190 static int
pcf8584_process(pcf8584_t * i2c,uint8_t s1)1191 pcf8584_process(pcf8584_t *i2c, uint8_t s1)
1192 {
1193 	i2c_transfer_t *tp = i2c->pcf8584_cur_tran;
1194 	int addr = pcf8584_dip_to_addr(i2c->pcf8584_cur_dip);
1195 	int dummy_read;
1196 
1197 	ASSERT(i2c->pcf8584_tran_state != TRAN_STATE_NULL);
1198 
1199 	switch (i2c->pcf8584_tran_state) {
1200 	case TRAN_STATE_DUMMY_DATA:
1201 		PCF8584_DDB(pcf8584_print(PRT_TRAN,
1202 		    "TRAN_STATE_DUMMY DATA: write dummy %x\n", DUMMY_DATA));
1203 		if (pcf8584_error(s1, I2C_RD, i2c) != I2C_SUCCESS) {
1204 			tp->i2c_result = I2C_FAILURE;
1205 
1206 			return (I2C_COMPLETE);
1207 		}
1208 		i2c->pcf8584_tran_state = TRAN_STATE_START;
1209 		pcf8584_put_s0(i2c, DUMMY_DATA);
1210 
1211 		return (I2C_PENDING);
1212 	case TRAN_STATE_START:
1213 		if (pcf8584_error(s1, I2C_RD, i2c) != I2C_SUCCESS) {
1214 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1215 			    "TRAN_STATE_START failure\n"));
1216 			tp->i2c_result = I2C_FAILURE;
1217 
1218 			return (I2C_COMPLETE);
1219 		}
1220 		i2c->pcf8584_tran_state =
1221 		    pcf8584_type_to_state(tp->i2c_flags);
1222 
1223 		/* Set read bit if this is a read transaction */
1224 		if (tp->i2c_flags == I2C_RD) {
1225 			addr |= I2C_READ;
1226 		}
1227 		if (i2c->pcf8584_mode == PCF8584_POLL_MODE)
1228 			pcf8584_put_s1(i2c, S1_START2);
1229 		else
1230 			pcf8584_put_s1(i2c, S1_START2 | S1_ENI);
1231 		pcf8584_put_s0(i2c, addr);
1232 		PCF8584_DDB(pcf8584_print(PRT_TRAN,
1233 		    "TRAN_STATE_START: write addr: %x\n", addr));
1234 
1235 		return (I2C_PENDING);
1236 	case TRAN_STATE_WR:
1237 
1238 		if (pcf8584_error(s1, I2C_WR, i2c) != I2C_SUCCESS) {
1239 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1240 			    "TRAN_STATE_WR failure\n"));
1241 			tp->i2c_result = I2C_FAILURE;
1242 
1243 			return (I2C_COMPLETE);
1244 		}
1245 		/* check to see if at end of buffer */
1246 		if (tp->i2c_w_resid == 0) {
1247 			pcf8584_put_s1(i2c, S1_STOP);
1248 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1249 			    "TRAN_STATE_WR: write STOP\n"));
1250 
1251 			return (I2C_COMPLETE);
1252 		}
1253 
1254 		pcf8584_put_s0(i2c, tp->i2c_wbuf[tp->i2c_wlen -
1255 		    tp->i2c_w_resid--]);
1256 		PCF8584_DDB(pcf8584_print(PRT_TRAN,
1257 		    "TRAN_STATE_WR:  write data %x\n",
1258 		    tp->i2c_wbuf[tp->i2c_wlen - (tp->i2c_w_resid + 1)]));
1259 
1260 		return (I2C_PENDING);
1261 	case TRAN_STATE_DUMMY_RD:
1262 
1263 		if (pcf8584_error(s1, I2C_WR, i2c) != I2C_SUCCESS) {
1264 			tp->i2c_result = I2C_FAILURE;
1265 
1266 			return (I2C_COMPLETE);
1267 		}
1268 		/*
1269 		 * The first read is always a dummy read, because reading S0
1270 		 * is what starts bit shifting and ACK on the I2c bus.
1271 		 * This byte is accessed during the next read, which starts
1272 		 * another 8 bit bus shift.
1273 		 *
1274 		 * special case for 1 byte reads:  Clear the ACK bit
1275 		 * here since this read causes the last and only byte
1276 		 * to be sent on the I2C bus.
1277 		 */
1278 		if (tp->i2c_r_resid  == 1) {
1279 			if (i2c->pcf8584_mode == PCF8584_POLL_MODE)
1280 				pcf8584_put_s1(i2c, S1_ESO);
1281 			else
1282 				pcf8584_put_s1(i2c, S1_ESO | S1_ENI);
1283 		}
1284 
1285 		/*
1286 		 * dummy read
1287 		 */
1288 		dummy_read = pcf8584_get_s0(i2c);
1289 
1290 		i2c->pcf8584_tran_state = TRAN_STATE_RD;
1291 		PCF8584_DDB(pcf8584_print(PRT_TRAN,
1292 		    "TRAN_STATE_DUMMY_RD: read dummy %d\n", dummy_read));
1293 
1294 		return (I2C_PENDING);
1295 	case TRAN_STATE_RD:
1296 		if (pcf8584_error(s1, I2C_RD, i2c) != I2C_SUCCESS) {
1297 			tp->i2c_result = I2C_FAILURE;
1298 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1299 			    "TRAN_STATE_RD failure\n"));
1300 
1301 			return (I2C_COMPLETE);
1302 		}
1303 
1304 		/*
1305 		 * If resid == 1, the last byte has already been shifted into
1306 		 * the accumulator.  Send the stop bit.  This also prevents the
1307 		 * last S0 read from shifting in another byte from the I2C bus.
1308 		 */
1309 		if (tp->i2c_r_resid  == 1) {
1310 			pcf8584_put_s1(i2c, S1_STOP);
1311 		}
1312 
1313 		/*
1314 		 * If resid == 2, then the next read will cause the I2C bus to
1315 		 * start shifting in the last byte on the I2C bus, which we
1316 		 * don't want to be ACK'd, so clear the ACK bit.
1317 		 */
1318 		if (tp->i2c_r_resid  == 2) {
1319 			if (i2c->pcf8584_mode == PCF8584_POLL_MODE)
1320 				pcf8584_put_s1(i2c, S1_ESO);
1321 			else
1322 				pcf8584_put_s1(i2c, S1_ESO | S1_ENI);
1323 		}
1324 
1325 		tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid] =
1326 		    pcf8584_get_s0(i2c);
1327 
1328 		PCF8584_DDB(pcf8584_print(PRT_TRAN,
1329 		    "TRAN_STATE_RD: returning. i2c_rlen = %d "
1330 		    "i2c_r_resid = %d,  data =%x\n", tp->i2c_rlen,
1331 		    tp->i2c_r_resid, tp->i2c_rbuf[tp->i2c_rlen -
1332 		    tp->i2c_r_resid]));
1333 
1334 		if (--tp->i2c_r_resid == 0) {
1335 
1336 			return (I2C_COMPLETE);
1337 		}
1338 
1339 		return (I2C_PENDING);
1340 	case TRAN_STATE_WR_RD:
1341 
1342 		if (pcf8584_error(s1, I2C_WR, i2c) != I2C_SUCCESS) {
1343 			tp->i2c_result = I2C_FAILURE;
1344 
1345 			return (I2C_COMPLETE);
1346 		}
1347 		if ((s1 & S1_LRB)) {
1348 			pcf8584_put_s1(i2c, S1_STOP);
1349 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1350 			    "TRAN_STATE_WR_RD sending STOP\n"));
1351 
1352 			return (I2C_COMPLETE);
1353 		}
1354 		if (tp->i2c_w_resid != 0) {
1355 			pcf8584_put_s0(i2c, tp->i2c_wbuf[tp->i2c_wlen -
1356 			    tp->i2c_w_resid--]);
1357 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1358 			    "TRAN_STATE_WR_RD: write data %x\n",
1359 			    tp->i2c_wbuf[tp->i2c_wlen -
1360 			    (tp->i2c_w_resid + 1)]));
1361 		} else {
1362 			if (i2c->pcf8584_mode == PCF8584_POLL_MODE)
1363 				pcf8584_put_s1(i2c, S1_START2);
1364 			else
1365 				pcf8584_put_s1(i2c, S1_START2 | S1_ENI);
1366 			pcf8584_put_s0(i2c, addr | I2C_READ);
1367 			i2c->pcf8584_tran_state =
1368 			    TRAN_STATE_DUMMY_RD;
1369 			PCF8584_DDB(pcf8584_print(PRT_TRAN,
1370 			    "TRAN_STATE_WR_RD: write addr "
1371 			    "%x\n", addr | I2C_READ));
1372 		}
1373 
1374 		return (I2C_PENDING);
1375 	default:
1376 
1377 		return (I2C_COMPLETE);
1378 	}
1379 }
1380 
1381 /*
1382  * pcf8584_transfer() is the function that is registered with
1383  * I2C services to be called from pcf8584_transfer() for each transfer.
1384  *
1385  * This function starts the transfer, and then waits for the
1386  * interrupt or polled thread to signal that the transfer has
1387  * completed.
1388  */
1389 int
pcf8584_transfer(dev_info_t * dip,i2c_transfer_t * tp)1390 pcf8584_transfer(dev_info_t *dip, i2c_transfer_t *tp)
1391 {
1392 	pcf8584_t *i2c;
1393 	int saved_mode, took_over = 0;
1394 	kcondvar_t *waiter = NULL;
1395 	extern int do_polled_io;
1396 
1397 	i2c = (pcf8584_t *)ddi_get_soft_state(pcf8584_state,
1398 	    ddi_get_instance(ddi_get_parent(dip)));
1399 
1400 	tp->i2c_r_resid = tp->i2c_rlen;
1401 	tp->i2c_w_resid = tp->i2c_wlen;
1402 	tp->i2c_result = I2C_SUCCESS;
1403 
1404 begin:
1405 	/*
1406 	 * If we're explicitly asked to do polled io (or if we are panic'ing),
1407 	 * we need to usurp ownership of the I2C bus, bypassing any other
1408 	 * waiters.
1409 	 */
1410 	if (do_polled_io || ddi_in_panic()) {
1411 		pcf8584_take_over(i2c, dip, tp, &waiter, &saved_mode);
1412 		took_over = 1;
1413 	} else {
1414 		pcf8584_acquire(i2c, dip, tp, B_FALSE);
1415 		mutex_enter(&i2c->pcf8584_imutex);
1416 
1417 		/*
1418 		 * See if someone else had intruded and taken over the bus
1419 		 * between the 'pcf8584_acquire' and 'mutex_enter' above.
1420 		 * If so, we'll have to start all over again.
1421 		 */
1422 		if (i2c->pcf8584_cur_tran != tp) {
1423 			mutex_exit(&i2c->pcf8584_imutex);
1424 			goto begin;
1425 		}
1426 	}
1427 
1428 	if (pcf8584_bbn_ready(i2c) != I2C_SUCCESS) {
1429 		if (took_over)
1430 			pcf8584_give_up(i2c, waiter, saved_mode);
1431 		else {
1432 			mutex_exit(&i2c->pcf8584_imutex);
1433 			pcf8584_release(i2c, B_FALSE);
1434 		}
1435 
1436 		return (tp->i2c_result = I2C_FAILURE);
1437 	}
1438 
1439 	/*
1440 	 * Bus selection must be followed by pcf8584_bbn_ready(),
1441 	 * otherwise the bus can be switched before the stop
1442 	 * bit is written out, causing the stop bit to get
1443 	 * sent to the wrong (new) bus.  This causes the
1444 	 * previous bus to permanently hang waiting for the
1445 	 * stop bit.
1446 	 */
1447 	pcf8584_select_bus(i2c);
1448 
1449 	i2c->pcf8584_tran_state = TRAN_STATE_DUMMY_DATA;
1450 	pcf8584_put_s0(i2c, DUMMY_ADDR);
1451 	PCF8584_DDB(pcf8584_print(PRT_TRAN,
1452 	    "FIRST WRITE DUMMY ADDR: write %x\n", DUMMY_ADDR));
1453 	if (i2c->pcf8584_mode ==  PCF8584_POLL_MODE)
1454 		pcf8584_put_s1(i2c, S1_START);
1455 	else
1456 		pcf8584_put_s1(i2c, S1_START | S1_ENI);
1457 
1458 	/*
1459 	 * Update transfer status so any polled i/o request coming in
1460 	 * after this will complete this transfer for us, before issuing
1461 	 * its own.
1462 	 */
1463 	i2c->pcf8584_cur_status = PCF8584_TRANSFER_ON;
1464 
1465 	if (i2c->pcf8584_mode ==  PCF8584_POLL_MODE)
1466 		pcf8584_do_polled_io(i2c);
1467 
1468 	if (took_over)
1469 		pcf8584_give_up(i2c, waiter, saved_mode);
1470 	else {
1471 		if (i2c->pcf8584_mode != PCF8584_POLL_MODE)
1472 			cv_wait(&i2c->pcf8584_icv, &i2c->pcf8584_imutex);
1473 		mutex_exit(&i2c->pcf8584_imutex);
1474 
1475 		/*
1476 		 * Release the I2C bus only if we still own it. If we don't
1477 		 * own it (someone usurped it from us while we were waiting),
1478 		 * we still need to drop the lock that serializes access to
1479 		 * the pcf8584 controller on systems where OBP shares the
1480 		 * controller with the OS.
1481 		 */
1482 		if (i2c->pcf8584_cur_tran == tp)
1483 			pcf8584_release(i2c, B_FALSE);
1484 		else if (&plat_shared_i2c_exit && dip)
1485 			plat_shared_i2c_exit(i2c->pcf8584_dip);
1486 	}
1487 
1488 	return (tp->i2c_result);
1489 }
1490 
1491 static void
pcf8584_do_polled_io(pcf8584_t * i2c)1492 pcf8584_do_polled_io(pcf8584_t *i2c)
1493 {
1494 	int completed = I2C_PENDING;
1495 	uint8_t s1;
1496 
1497 	while (completed != I2C_COMPLETE) {
1498 		s1 = pcf8584_get_s1(i2c);
1499 		if (!(s1 & S1_PIN)) {
1500 			ASSERT(i2c->pcf8584_cur_tran);
1501 			completed = pcf8584_process(i2c, s1);
1502 		}
1503 		drv_usecwait(1);
1504 	}
1505 
1506 	i2c->pcf8584_cur_status = PCF8584_TRANSFER_OVER;
1507 }
1508 
1509 /*
1510  * pcf8584_take_over() grabs the I2C bus and other resources by force and
1511  * flushes any pending transaction. This is called if a polled i/o
1512  * request comes in.
1513  */
1514 static void
pcf8584_take_over(pcf8584_t * i2c,dev_info_t * dip,i2c_transfer_t * tp,kcondvar_t ** waiter,int * saved_mode)1515 pcf8584_take_over(pcf8584_t *i2c, dev_info_t *dip, i2c_transfer_t *tp,
1516     kcondvar_t **waiter, int *saved_mode)
1517 {
1518 	mutex_enter(&i2c->pcf8584_imutex);
1519 	*saved_mode = i2c->pcf8584_mode;
1520 	i2c->pcf8584_mode = PCF8584_POLL_MODE;
1521 
1522 	/*
1523 	 * We need to flush out any currently pending transaction before
1524 	 * issuing ours.
1525 	 */
1526 	if (i2c->pcf8584_busy) {
1527 		if (i2c->pcf8584_cur_tran &&
1528 		    i2c->pcf8584_cur_status == PCF8584_TRANSFER_ON) {
1529 			pcf8584_do_polled_io(i2c);
1530 			*waiter = &i2c->pcf8584_icv;
1531 		}
1532 	}
1533 
1534 	/*
1535 	 * Since pcf8584_acquire() is by default a good citizen that
1536 	 * will wait its turn to acquire the I2C bus, we need to set
1537 	 * the 'force' flag on.
1538 	 */
1539 	pcf8584_acquire(i2c, dip, tp, B_TRUE);
1540 }
1541 
1542 /*
1543  * pcf8584_give_up() returns all resources that were taken over forcefully
1544  */
1545 static void
pcf8584_give_up(pcf8584_t * i2c,kcondvar_t * waiter,int saved_mode)1546 pcf8584_give_up(pcf8584_t *i2c, kcondvar_t *waiter, int saved_mode)
1547 {
1548 	i2c->pcf8584_mode = saved_mode;
1549 
1550 	/*
1551 	 * Note that pcf8584_release only wakes up threads waiting to acquire
1552 	 * the I2C bus. We still need to wake up the waiter from whom we
1553 	 * usurped the bus.
1554 	 */
1555 	pcf8584_release(i2c, B_TRUE);
1556 	if (waiter)
1557 		cv_signal(waiter);
1558 
1559 	mutex_exit(&i2c->pcf8584_imutex);
1560 }
1561