1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright 2020 NXP. */ 3 4 #ifndef __LINUX_REG_PCA9450_H__ 5 #define __LINUX_REG_PCA9450_H__ 6 7 #include <linux/regmap.h> 8 9 enum pca9450_chip_type { 10 PCA9450_TYPE_PCA9450A = 0, 11 PCA9450_TYPE_PCA9450BC, 12 PCA9450_TYPE_PCA9451A, 13 PCA9450_TYPE_PCA9452, 14 PCA9450_TYPE_AMOUNT, 15 }; 16 17 enum { 18 PCA9450_BUCK1 = 0, 19 PCA9450_BUCK2, 20 PCA9450_BUCK3, 21 PCA9450_BUCK4, 22 PCA9450_BUCK5, 23 PCA9450_BUCK6, 24 PCA9450_LDO1, 25 PCA9450_LDO2, 26 PCA9450_LDO3, 27 PCA9450_LDO4, 28 PCA9450_LDO5, 29 PCA9450_REGULATOR_CNT, 30 }; 31 32 enum { 33 PCA9450_DVS_LEVEL_RUN = 0, 34 PCA9450_DVS_LEVEL_STANDBY, 35 PCA9450_DVS_LEVEL_MAX, 36 }; 37 38 #define PCA9450_RESTART_HANDLER_PRIORITY 130 39 40 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80 41 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80 42 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80 43 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80 44 45 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80 46 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80 47 48 #define PCA9450_LDO1_VOLTAGE_NUM 0x08 49 #define PCA9450_LDO2_VOLTAGE_NUM 0x08 50 #define PCA9450_LDO3_VOLTAGE_NUM 0x20 51 #define PCA9450_LDO4_VOLTAGE_NUM 0x20 52 #define PCA9450_LDO5_VOLTAGE_NUM 0x10 53 54 enum { 55 PCA9450_REG_DEV_ID = 0x00, 56 PCA9450_REG_INT1 = 0x01, 57 PCA9450_REG_INT1_MSK = 0x02, 58 PCA9450_REG_STATUS1 = 0x03, 59 PCA9450_REG_STATUS2 = 0x04, 60 PCA9450_REG_PWRON_STAT = 0x05, 61 PCA9450_REG_SWRST = 0x06, 62 PCA9450_REG_PWRCTRL = 0x07, 63 PCA9450_REG_RESET_CTRL = 0x08, 64 PCA9450_REG_CONFIG1 = 0x09, 65 PCA9450_REG_CONFIG2 = 0x0A, 66 PCA9450_REG_BUCK123_DVS = 0x0C, 67 PCA9450_REG_BUCK1OUT_LIMIT = 0x0D, 68 PCA9450_REG_BUCK2OUT_LIMIT = 0x0E, 69 PCA9450_REG_BUCK3OUT_LIMIT = 0x0F, 70 PCA9450_REG_BUCK1CTRL = 0x10, 71 PCA9450_REG_BUCK1OUT_DVS0 = 0x11, 72 PCA9450_REG_BUCK1OUT_DVS1 = 0x12, 73 PCA9450_REG_BUCK2CTRL = 0x13, 74 PCA9450_REG_BUCK2OUT_DVS0 = 0x14, 75 PCA9450_REG_BUCK2OUT_DVS1 = 0x15, 76 PCA9450_REG_BUCK3CTRL = 0x16, 77 PCA9450_REG_BUCK3OUT_DVS0 = 0x17, 78 PCA9450_REG_BUCK3OUT_DVS1 = 0x18, 79 PCA9450_REG_BUCK4CTRL = 0x19, 80 PCA9450_REG_BUCK4OUT = 0x1A, 81 PCA9450_REG_BUCK5CTRL = 0x1B, 82 PCA9450_REG_BUCK5OUT = 0x1C, 83 PCA9450_REG_BUCK6CTRL = 0x1D, 84 PCA9450_REG_BUCK6OUT = 0x1E, 85 PCA9450_REG_LDO_AD_CTRL = 0x20, 86 PCA9450_REG_LDO1CTRL = 0x21, 87 PCA9450_REG_LDO2CTRL = 0x22, 88 PCA9450_REG_LDO3CTRL = 0x23, 89 PCA9450_REG_LDO4CTRL = 0x24, 90 PCA9450_REG_LDO5CTRL_L = 0x25, 91 PCA9450_REG_LDO5CTRL_H = 0x26, 92 PCA9450_REG_LOADSW_CTRL = 0x2A, 93 PCA9450_REG_VRFLT1_STS = 0x2B, 94 PCA9450_REG_VRFLT2_STS = 0x2C, 95 PCA9450_REG_VRFLT1_MASK = 0x2D, 96 PCA9450_REG_VRFLT2_MASK = 0x2E, 97 PCA9450_MAX_REGISTER = 0x2F, 98 }; 99 100 /* PCA9450 BUCK ENMODE bits */ 101 #define BUCK_ENMODE_OFF 0x00 102 #define BUCK_ENMODE_ONREQ 0x01 103 #define BUCK_ENMODE_ONREQ_STBYREQ 0x02 104 #define BUCK_ENMODE_ON 0x03 105 106 /* PCA9450_REG_BUCK1_CTRL bits */ 107 #define BUCK1_RAMP_MASK 0xC0 108 #define BUCK1_RAMP_25MV 0x0 109 #define BUCK1_RAMP_12P5MV 0x1 110 #define BUCK1_RAMP_6P25MV 0x2 111 #define BUCK1_RAMP_3P125MV 0x3 112 #define BUCK1_DVS_CTRL 0x10 113 #define BUCK1_AD 0x08 114 #define BUCK1_FPWM 0x04 115 #define BUCK1_ENMODE_MASK 0x03 116 117 /* PCA9450_REG_BUCK2_CTRL bits */ 118 #define BUCK2_RAMP_MASK 0xC0 119 #define BUCK2_RAMP_25MV 0x0 120 #define BUCK2_RAMP_12P5MV 0x1 121 #define BUCK2_RAMP_6P25MV 0x2 122 #define BUCK2_RAMP_3P125MV 0x3 123 #define BUCK2_DVS_CTRL 0x10 124 #define BUCK2_AD 0x08 125 #define BUCK2_FPWM 0x04 126 #define BUCK2_ENMODE_MASK 0x03 127 128 /* PCA9450_REG_BUCK3_CTRL bits */ 129 #define BUCK3_RAMP_MASK 0xC0 130 #define BUCK3_RAMP_25MV 0x0 131 #define BUCK3_RAMP_12P5MV 0x1 132 #define BUCK3_RAMP_6P25MV 0x2 133 #define BUCK3_RAMP_3P125MV 0x3 134 #define BUCK3_DVS_CTRL 0x10 135 #define BUCK3_AD 0x08 136 #define BUCK3_FPWM 0x04 137 #define BUCK3_ENMODE_MASK 0x03 138 139 /* PCA9450_REG_BUCK4_CTRL bits */ 140 #define BUCK4_AD 0x08 141 #define BUCK4_FPWM 0x04 142 #define BUCK4_ENMODE_MASK 0x03 143 144 /* PCA9450_REG_BUCK5_CTRL bits */ 145 #define BUCK5_AD 0x08 146 #define BUCK5_FPWM 0x04 147 #define BUCK5_ENMODE_MASK 0x03 148 149 /* PCA9450_REG_BUCK6_CTRL bits */ 150 #define BUCK6_AD 0x08 151 #define BUCK6_FPWM 0x04 152 #define BUCK6_ENMODE_MASK 0x03 153 154 /* PCA9450_REG_BUCK123_PRESET_EN bit */ 155 #define BUCK123_PRESET_EN 0x80 156 157 /* PCA9450_BUCK1OUT_DVS0 bits */ 158 #define BUCK1OUT_DVS0_MASK 0x7F 159 #define BUCK1OUT_DVS0_DEFAULT 0x14 160 161 /* PCA9450_BUCK1OUT_DVS1 bits */ 162 #define BUCK1OUT_DVS1_MASK 0x7F 163 #define BUCK1OUT_DVS1_DEFAULT 0x14 164 165 /* PCA9450_BUCK2OUT_DVS0 bits */ 166 #define BUCK2OUT_DVS0_MASK 0x7F 167 #define BUCK2OUT_DVS0_DEFAULT 0x14 168 169 /* PCA9450_BUCK2OUT_DVS1 bits */ 170 #define BUCK2OUT_DVS1_MASK 0x7F 171 #define BUCK2OUT_DVS1_DEFAULT 0x14 172 173 /* PCA9450_BUCK3OUT_DVS0 bits */ 174 #define BUCK3OUT_DVS0_MASK 0x7F 175 #define BUCK3OUT_DVS0_DEFAULT 0x14 176 177 /* PCA9450_BUCK3OUT_DVS1 bits */ 178 #define BUCK3OUT_DVS1_MASK 0x7F 179 #define BUCK3OUT_DVS1_DEFAULT 0x14 180 181 /* PCA9450_REG_BUCK4OUT bits */ 182 #define BUCK4OUT_MASK 0x7F 183 #define BUCK4OUT_DEFAULT 0x6C 184 185 /* PCA9450_REG_BUCK5OUT bits */ 186 #define BUCK5OUT_MASK 0x7F 187 #define BUCK5OUT_DEFAULT 0x30 188 189 /* PCA9450_REG_BUCK6OUT bits */ 190 #define BUCK6OUT_MASK 0x7F 191 #define BUCK6OUT_DEFAULT 0x14 192 193 /* PCA9450_REG_LDO1_VOLT bits */ 194 #define LDO1_EN_MASK 0xC0 195 #define LDO1OUT_MASK 0x07 196 197 /* PCA9450_REG_LDO2_VOLT bits */ 198 #define LDO2_EN_MASK 0xC0 199 #define LDO2OUT_MASK 0x07 200 201 /* PCA9450_REG_LDO3_VOLT bits */ 202 #define LDO3_EN_MASK 0xC0 203 #define LDO3OUT_MASK 0x1F 204 205 /* PCA9450_REG_LDO4_VOLT bits */ 206 #define LDO4_EN_MASK 0xC0 207 #define LDO4OUT_MASK 0x1F 208 209 /* PCA9450_REG_LDO5_VOLT bits */ 210 #define LDO5L_EN_MASK 0xC0 211 #define LDO5LOUT_MASK 0x0F 212 213 #define LDO5H_EN_MASK 0xC0 214 #define LDO5HOUT_MASK 0x0F 215 216 /* PCA9450_REG_IRQ bits */ 217 #define IRQ_PWRON 0x80 218 #define IRQ_WDOGB 0x40 219 #define IRQ_RSVD 0x20 220 #define IRQ_VR_FLT1 0x10 221 #define IRQ_VR_FLT2 0x08 222 #define IRQ_LOWVSYS 0x04 223 #define IRQ_THERM_105 0x02 224 #define IRQ_THERM_125 0x01 225 226 /* PCA9450_REG_RESET_CTRL bits */ 227 #define WDOG_B_CFG_MASK 0xC0 228 #define WDOG_B_CFG_NONE 0x00 229 #define WDOG_B_CFG_WARM 0x40 230 #define WDOG_B_CFG_COLD_LDO12 0x80 231 #define WDOG_B_CFG_COLD 0xC0 232 233 /* PCA9450_REG_CONFIG2 bits */ 234 #define I2C_LT_MASK 0x03 235 #define I2C_LT_FORCE_DISABLE 0x00 236 #define I2C_LT_ON_STANDBY_RUN 0x01 237 #define I2C_LT_ON_RUN 0x02 238 #define I2C_LT_FORCE_ENABLE 0x03 239 240 /* PCA9450_REG_SW_RST command */ 241 #define SW_RST_COMMAND 0x14 242 243 #endif /* __LINUX_REG_PCA9450_H__ */ 244