1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PCIC driver specific data structures 29 */ 30 31 #ifndef _PCIC_VAR_H 32 #define _PCIC_VAR_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * defines and default values for power management simulation 40 */ 41 #define PCIC_PM_TIME 3 /* PM timer timeout time in secs */ 42 #define PCIC_PM_DETWIN 6 /* detection window in secs */ 43 #define PCIC_PM_METHOD_TIME 0x0001 /* use time check */ 44 #define PCIC_PM_METHOD_REG 0x0002 /* use reg check */ 45 #define PCIC_PM_DEF_METHOD 0 /* use no methods as default */ 46 47 #define PCIC_PM_INIT 0x0001 /* init PM handler */ 48 #define PCIC_PM_RUN 0x0002 /* normal PM handler operation */ 49 50 typedef struct pcic_pm_t { 51 int state; /* state */ 52 uint32_t ptime; /* previous time check */ 53 dev_info_t *dip; /* dip to pass */ 54 } pcic_pm_t; 55 56 /* 57 * Card insertion/removal processing debounce parameters 58 */ 59 #define PCIC_REM_DEBOUNCE_CNT 40 60 #define PCIC_REM_DEBOUNCE_TIME 0x1000 /* in uS */ 61 #define PCIC_DEBOUNCE_OK_CNT 10 62 63 /* 64 * Loop control in pcic_ready_wait 65 * 66 * Multiplying PCIC_READY_WAIT_LOOPS * PCIC_READY_WAIT_TIME gives 67 * total loop time in mS 68 */ 69 #define PCIC_READY_WAIT_LOOPS 205 /* count */ 70 #define PCIC_READY_WAIT_TIME 20 /* mS */ 71 72 typedef struct pcs_memwin { 73 int pcw_status; 74 uint32_t pcw_base; 75 int pcw_len; 76 uint32_t pcw_speed; 77 volatile caddr_t pcw_hostmem; 78 off_t pcw_offset; 79 ddi_acc_handle_t pcw_handle; 80 dev_info_t *res_dip; /* dip from which mem is allocated */ 81 } pcs_memwin_t; 82 83 typedef struct pci_iowin { 84 int pcw_status; 85 uint32_t pcw_base; 86 int pcw_len; 87 uint32_t pcw_speed; 88 volatile caddr_t pcw_hostmem; 89 /* Cirrus Logic specific offset info */ 90 int pcw_offset; 91 ddi_acc_handle_t pcw_handle; 92 dev_info_t *res_dip; /* dip from which io is allocated */ 93 } pcs_iowin_t; 94 95 #define PCW_MAPPED 0x0001 /* window is mapped */ 96 #define PCW_ENABLED 0x0002 /* window is enabled */ 97 #define PCW_ATTRIBUTE 0x0004 /* window is in attribute memory */ 98 #define PCW_WP 0x0008 /* window is write protected */ 99 #define PCW_OFFSET 0x0010 /* window uses CL style offset */ 100 101 typedef 102 struct pcic_socket { 103 int pcs_flags; 104 uchar_t *pcs_io; /* I/O address of PCIC controller */ 105 int pcs_socket; /* socket to determine register set */ 106 char pcs_cd_softint_flg; 107 timeout_id_t pcs_debounce_id; /* timeout for CD debounce */ 108 ddi_softint_handle_t pcs_cd_softint_hdl; /* Debounce softint id */ 109 struct pcicdev_t *pcs_pcic; 110 caddr_t pcs_phys; 111 int pcs_iobase; 112 int pcs_iolen; 113 caddr_t pcs_confbase; 114 int pcs_conflen; 115 int pcs_conf_index; /* used to select which cftable entry to use */ 116 int pcs_irq; 117 int pcs_smi; 118 int pcs_state; 119 int pcs_status; 120 int pcs_intmask; 121 uint32_t pcs_vcc; 122 uint32_t pcs_vpp1; 123 uint32_t pcs_vpp2; 124 union pcic_window { 125 pcs_memwin_t mem; 126 pcs_iowin_t io; 127 } pcs_windows[PCIC_IOWINDOWS + PCIC_MEMWINDOWS]; 128 } pcic_socket_t; 129 130 #define PCS_CARD_PRESENT 0x0001 /* card inserted in socket */ 131 #define PCS_CARD_IDENTIFIED 0x0002 /* card has been identified */ 132 #define PCS_CARD_ENABLED 0x0004 /* card and socket enabled */ 133 #define PCS_CARD_WPS 0x0008 /* write protect ignored */ 134 #define PCS_IRQ_ENABLED 0x0010 /* irq is a mask of values */ 135 #define PCS_CARD_RAM 0x0020 /* ram needs to be mapped */ 136 #define PCS_CARD_IO 0x0040 /* card is I/O type */ 137 #define PCS_CARD_16BIT 0x0080 /* set in 16-bit mode */ 138 #define PCS_SOCKET_IO 0x0100 /* socket is I/O type */ 139 #define PCS_READY 0x0200 /* socket just came ready */ 140 #define PCS_WAITING 0x0400 /* Doing a wait on this socket */ 141 #define PCS_STARTING 0x0800 /* Starting up flag */ 142 #define PCS_CARD_ISCARDBUS 0x1000 /* NJH - 32 bit (CARDBUS) card */ 143 #define PCS_CARD_IS16BIT 0x2000 /* So we can tell if it's OK */ 144 #define PCS_CARD_REMOVED 0x4000 /* Removed but still work to do */ 145 #define PCS_CARD_CBREM 0x8000 /* Cardbus specific work to do */ 146 #define PCS_DEBOUNCING 0x10000 /* Socket in debouncing state */ 147 148 #define PCIC_MAX_SOCKETS 4 /* 2 per chip up to 2 chips per IO addr */ 149 150 typedef struct pcic_debounce_state { 151 int insert_cnt; 152 int remove_cnt; 153 int uncertain_cnt; 154 int prev_status; 155 int debounce_cnt; 156 timeout_id_t timeout_id; 157 } pcic_debounce_state_t; 158 159 typedef struct pcicdev_t { 160 uint32_t pc_flags; 161 uint32_t pc_type; 162 char *pc_chipname; 163 uint32_t pc_irqs; /* the possible IRQ levels */ 164 uint32_t pc_smi; /* SMI IRQ */ 165 uint32_t pc_irq; /* IO IRQ */ 166 int pc_io_type; 167 int pc_intr_mode; /* which interrupt method */ 168 dev_info_t *dip; 169 ddi_idevice_cookie_t pc_dcookie; /* Stay compatible w/ PCMCIA */ 170 inthandler_t *sirq[14]; /* List for each level */ 171 uint16_t si_actflg; /* Bit for each active level */ 172 inthandler_t *irq_top; 173 inthandler_t *irq_current; 174 ddi_intr_handle_t *pc_pci_intr_hdlp; /* For PCI based adapters */ 175 ddi_iblock_cookie_t pc_pri; /* Priority saved for mutexes */ 176 ddi_intr_handle_t *pc_intr_htblp; /* ISA: interrupt handles */ 177 ddi_softint_handle_t pc_softint_hdl; /* Softinterrupt handle */ 178 kmutex_t pc_lock; /* general register lock */ 179 kmutex_t intr_lock; /* protects fields modified */ 180 /* in pcic_intr() */ 181 int pc_numsockets; 182 /* used to inform nexus of events */ 183 int (*pc_callback)(); 184 int pc_cb_arg; 185 int (*pc_ss_bios)(); 186 struct pcic_socket pc_sockets[PCIC_MAX_SOCKETS]; 187 int pc_numpower; 188 struct power_entry *pc_power; 189 timeout_id_t pc_pmtimer; /* timeout for simulating PM */ 190 pcic_pm_t pmt; /* PM handler structure */ 191 kcondvar_t pm_cv; /* CV for suspend/resume sync */ 192 ddi_acc_handle_t handle; /* PCIC register handle */ 193 ddi_acc_handle_t cfg_handle; /* PCIC config space handle */ 194 uchar_t *cfgaddr; /* config address */ 195 uchar_t *ioaddr; /* PCIC register IO base */ 196 int mem_reg_num; /* memory space reg number */ 197 offset_t mem_reg_offset; 198 int io_reg_num; /* IO space reg number */ 199 offset_t io_reg_offset; 200 int bus_speed; /* parent bus speed */ 201 uint32_t pc_timestamp; /* last time touched */ 202 inthandler_t *pc_handlers; 203 int pc_lastreg; 204 uint32_t pc_base; /* first possible mem-addr */ 205 uint32_t pc_bound; /* bound length */ 206 uint32_t pc_iobase; /* first io addr */ 207 uint32_t pc_iobound; 208 pcic_debounce_state_t deb_state[PCIC_MAX_SOCKETS]; 209 int pc_softintr_req[PCIC_MAX_SOCKETS]; 210 struct pcic_cd_change_param { 211 struct pcicdev_t *pcic; 212 pcic_socket_t *sockp; 213 int sn; 214 } pcic_cd_change_param[PCIC_MAX_SOCKETS]; 215 } pcicdev_t; 216 217 218 219 #define PCF_ATTACHED 0x00000001 220 #define PCF_CALLBACK 0x00000002 /* callback handler registered */ 221 #define PCF_GPI_EJECT 0x00000004 /* GPI signal is eject/insert */ 222 #define PCF_INTRENAB 0x00000008 223 #define PCF_USE_SMI 0x00000010 /* use the SMI enable */ 224 #define PCF_AUDIO 0x00000020 /* use audio if available */ 225 #define PCF_SUSPENDED 0x00000040 /* driver attached but suspended */ 226 #define PCF_EXTEND_INTR 0x00000080 /* Use Vadem interrupt sharing */ 227 #define PCF_1SOCKET 0x00000100 /* Chip only has one socket */ 228 #define PCF_33VCAP 0x00000200 /* 3.3 Volt capable and coded */ 229 #define PCF_CBPWRCTL 0x00000400 /* Use cardbus regs for power ctl */ 230 #define PCF_DEBOUNCE 0x00002000 /* Chip has hardware debounce enabled */ 231 #define PCF_VPPX 0x00004000 /* Vpp1 and Vpp2 tied together */ 232 #define PCF_EXTBUFF 0x00008000 /* Chip strapped for external buffers */ 233 #define PCF_PCIBUS 0x00010000 /* this instance on a PCI bus */ 234 #define PCF_NOIO_OFF 0x00020000 /* 0 offset for IO mapping */ 235 #define PCF_MULT_IRQ 0x00040000 236 #define PCF_IO_REMAP 0x00080000 /* adapter can remap I/O */ 237 #define PCF_CARDBUS 0x00100000 /* Yenta CardBus */ 238 #define PCF_MEM_PAGE 0x00200000 /* all windows same 16M page */ 239 240 /* newer features */ 241 #define PCF_DMA 0x00400000 /* supports DMA */ 242 #define PCF_ZV 0x00800000 /* supports Zoom Video */ 243 244 #define PCF_ISA6729 0x01000000 /* 6729 */ 245 246 /* 247 * misc flags 248 */ 249 #define PCIC_FOUND_ADAPTER 0x00000001 250 #define PCIC_ENABLE_IO 0x00000002 251 #define PCIC_ENABLE_MEM 0x00000004 252 253 #define PCIC_SOFTINT_PRI_VAL 0x04 /* value used while adding softint */ 254 255 /* 256 * interrupt modes 257 * the pcic variants provide a number of interrupt modes. 258 * e.g. on PCI, we can either use PCI interrupts or ISA interrupts 259 * but the SPARC version must use PCI interrupts and x86 "depends" 260 */ 261 262 #define PCIC_INTR_MODE_ISA 00 /* default- use ISA mode */ 263 #define PCIC_INTR_MODE_PCI 01 /* use pure PCI */ 264 #define PCIC_INTR_MODE_PCI_1 02 /* use pure PCI but share */ 265 #define PCIC_INTR_MODE_PCI_S 03 /* serial PCI interrupts */ 266 267 #define PCIC_INTR_DEF_PRI 11 /* default IPL level */ 268 269 /* 270 * I/O access types 271 */ 272 #define PCIC_IO_TYPE_82365SL 0 /* uses index/data reg model */ 273 #define PCIC_IO_TYPE_YENTA 1 /* uses the Yenta spec memory model */ 274 275 /* 276 * On some PCI busses, the IO and memory resources available to us are 277 * available via the last two tuples in the reg property. The 278 * following defines are the reg numbers from the end of the reg 279 * property, and NOT the reg number itself. 280 */ 281 #define PCIC_PCI_MEM_REG_OFFSET 2 282 #define PCIC_PCI_IO_REG_OFFSET 3 283 284 /* I/O type 82365SL is default, Yenta is alternative */ 285 #define PCIC_IOTYPE_82365SL 0 286 #define PCIC_IOTYPE_YENTA 1 /* CardBus memory mode */ 287 288 /* 289 * On Yenta cards, the PCI configuration space bridge control register 290 * must match the interrupt * type we have selected. 291 */ 292 293 #define PCIC_CB_BRIDGE_CTL 0x3E 294 #define PCIC_BCTL_IREQ_ISA 0x80 295 296 /* 297 * On all PCI busses, we get at least two tuples in the reg property. One 298 * of the tuples is the config space tuple and the other is the PCIC 299 * IO control register space tuple. 300 */ 301 302 #define PCIC_PCI_CONFIG_REG_NUM 0 303 #define PCIC_PCI_CONFIG_REG_OFFSET 0 304 #define PCIC_PCI_CONFIG_REG_LENGTH 0x100 305 306 #define PCIC_PCI_CONTROL_REG_NUM 1 307 #define PCIC_PCI_CONTROL_REG_OFFSET 0 308 #define PCIC_PCI_CONTROL_REG_LENGTH 4 309 #define PCIC_CB_CONTROL_REG_LENGTH 4096 /* CardBus is 4K mem page */ 310 311 /* 312 * On ISA/EISA/MCA our reg property must look like this: 313 * 314 * IOreg,0x0,0x8, 0x0,0x0,0x100000, 0x1,0x0,0x1000 315 * ^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^ 316 * adapter regs general memory general IO 317 * 318 * where IOreg specifies the adapter's control registers in 319 * IO space. 320 * The value of PCIC_ISA_IO_REG_OFFSET must be the first 321 * component of the third (general IO) register spec. 322 */ 323 #define PCIC_ISA_IO_REG_OFFSET 1 324 #define PCIC_ISA_CONTROL_REG_NUM 0 325 #define PCIC_ISA_CONTROL_REG_OFFSET 0 /* XXX MUST be 0! */ 326 #define PCIC_ISA_CONTROL_REG_LENGTH 2 327 328 #define PCIC_ISA_MEM_REG_NUM 1 329 #define PCIC_ISA_IO_REG_NUM 2 330 331 /* 332 * there are several variants of the 82365 chip from different "clone" 333 * vendors. Each has a few differences which may or may not have to be 334 * handled. The following defines are used to identify the chip being 335 * used. If it can't be determined, then 82365SL is assumed. 336 * 337 * The following are ISA/EISA/MCA-R2 adapters 338 */ 339 #define PCIC_I82365SL 0x00 /* Intel 82365SL */ 340 #define PCIC_TYPE_I82365SL "i82365SL" 341 #define PCIC_CL_PD6710 0x01 /* Cirrus Logic CL-PD6710/6720 */ 342 #define PCIC_CL_PD6722 0x05 /* Cirrus Logic CL-PD6722 */ 343 #define PCIC_TYPE_PD6710 "PD6710" 344 #define PCIC_TYPE_PD6720 "PD6720" 345 #define PCIC_TYPE_PD6722 "PD6722" 346 #define PCIC_VADEM 0x02 /* Vadem VG465/365 */ 347 #define PCIC_VADEM_VG469 0x03 /* Vadem VG469 - P&P, etc. */ 348 #define PCIC_VG_465 "VG465" 349 #define PCIC_VG_365 "VG365" 350 #define PCIC_VG_468 "VG468" 351 #define PCIC_VG_469 "VG469" 352 #define PCIC_RICOH 0x04 353 #define PCIC_TYPE_RF5C296 "RF5C296" 354 #define PCIC_TYPE_RF5C396 "RF5C396" 355 356 /* PCI adapters are known by 32-bit value of vendor+device id */ 357 #define PCI_ID(vend, dev) ((uint32_t)(((uint32_t)(vend) << 16) | (dev))) 358 359 /* 360 * The following are PCI-R2 adapters 361 * The Cirrus Logic PCI adapters typically have their IRQ3 line 362 * routed to the PCI INT A# line. 363 */ 364 #define PCIC_CL_VENDORID 0x1013 365 #define PCIC_PD6729_DEVID 0x1100 366 #define PCIC_TYPE_PD6729 "PD6729" 367 #define PCIC_CL_PD6729 PCI_ID(PCIC_CL_VENDORID, PCIC_PD6729_DEVID) 368 #define PCIC_PD6729_INTA_ROUTE 0x03 369 370 #define PCIC_TYPE_PD6730 "PD6730" 371 #define PCIC_PD6730_DEVID 0x1101 372 #define PCIC_CL_PD6730 PCI_ID(PCIC_CL_VENDORID, PCIC_PD6730_DEVID) 373 #define PCIC_PD6730_INTA_ROUTE 0x09 374 375 #define PCIC_TYPE_PD6832 "PD6832" 376 #define PCIC_PD6832_DEVID 0x1110 377 #define PCIC_CL_PD6832 PCI_ID(PCIC_CL_VENDORID, PCIC_PD6832_DEVID) 378 379 /* Intel i82092AA controller */ 380 381 #define PCIC_INTEL_VENDORID 0x8086 382 #define PCIC_TYPE_i82092 "i82092" 383 #define PCIC_i82092_DEVID 0x1221 384 #define PCIC_INTEL_i82092 PCI_ID(PCIC_INTEL_VENDORID, \ 385 PCIC_i82092_DEVID) 386 #define PCIC_i82092_INTA_ROUTE 0x0 /* XXX ? what is it really ? XXX */ 387 388 /* Texas Instruments */ 389 390 #define PCIC_TI_VENDORID 0x104C 391 #define PCIC_PCI1050_DEVID 0xAC10 392 #define PCIC_PCI1130_DEVID 0xAC12 393 #define PCIC_PCI1031_DEVID 0xAC13 /* R2 only with Yenta IF */ 394 #define PCIC_PCI1131_DEVID 0xAC15 395 #define PCIC_PCI1250_DEVID 0xAC16 396 #define PCIC_PCI1221_DEVID 0xAC19 397 #define PCIC_PCI1225_DEVID 0xAC1C 398 #define PCIC_PCI1220_DEVID 0xAC17 399 #define PCIC_PCI1260_DEVID 0xAC18 400 #define PCIC_PCI1210_DEVID 0xAC1A 401 #define PCIC_PCI1450_DEVID 0xAC1B 402 #define PCIC_PCI1251_DEVID 0xAC1D 403 #define PCIC_PCI1211_DEVID 0xAC1E 404 #define PCIC_PCI1251B_DEVID 0xAC1F 405 #define PCIC_PCI1260B_DEVID 0xAC30 406 #define PCIC_PCI4450_DEVID 0xAC40 407 #define PCIC_PCI4410_DEVID 0xAC41 408 #define PCIC_PCI4451_DEVID 0xAC42 409 #define PCIC_PCI4510_DEVID 0xAC44 410 #define PCIC_PCI1410_DEVID 0xAC50 411 #define PCIC_PCI1420_DEVID 0xAC51 412 #define PCIC_PCI1451_DEVID 0xAC52 413 #define PCIC_PCI1421_DEVID 0xAC53 414 #define PCIC_PCI1520_DEVID 0xAC55 415 #define PCIC_PCI1510_DEVID 0xAC56 416 417 #define PCIC_TI_PCI1130 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1130_DEVID) 418 #define PCIC_TYPE_PCI1130 "PCI1130" 419 #define PCIC_TI_PCI1031 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1031_DEVID) 420 #define PCIC_TYPE_PCI1031 "PCI1031" 421 #define PCIC_TI_PCI1131 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1131_DEVID) 422 #define PCIC_TYPE_PCI1131 "PCI1131" 423 #define PCIC_TI_PCI1250 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1250_DEVID) 424 #define PCIC_TYPE_PCI1250 "PCI1250" 425 #define PCIC_TI_PCI1050 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1050_DEVID) 426 #define PCIC_TYPE_PCI1050 "PCI1050" 427 #define PCIC_TI_PCI1221 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1221_DEVID) 428 #define PCIC_TYPE_PCI1221 "PCI1221" 429 #define PCIC_TI_PCI1225 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1225_DEVID) 430 #define PCIC_TYPE_PCI1225 "PCI1225" 431 #define PCIC_TI_PCI1220 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1220_DEVID) 432 #define PCIC_TYPE_PCI1220 "PCI1220" 433 #define PCIC_TI_PCI1260 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1260_DEVID) 434 #define PCIC_TYPE_PCI1260 "PCI1260" 435 #define PCIC_TI_PCI1210 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1210_DEVID) 436 #define PCIC_TYPE_PCI1210 "PCI1210" 437 #define PCIC_TI_PCI1450 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1450_DEVID) 438 #define PCIC_TYPE_PCI1450 "PCI1450" 439 #define PCIC_TI_PCI1251 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1251_DEVID) 440 #define PCIC_TYPE_PCI1251 "PCI1251" 441 #define PCIC_TI_PCI1211 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1211_DEVID) 442 #define PCIC_TYPE_PCI1211 "PCI1211" 443 #define PCIC_TI_PCI1251B PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1251B_DEVID) 444 #define PCIC_TYPE_PCI1251B "PCI1251B" 445 #define PCIC_TI_PCI1260B PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1260B_DEVID) 446 #define PCIC_TYPE_PCI1260B "PCI1260B" 447 #define PCIC_TI_PCI4450 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4450_DEVID) 448 #define PCIC_TYPE_PCI4450 "PCI4450" 449 #define PCIC_TI_PCI4410 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4410_DEVID) 450 #define PCIC_TYPE_PCI4410 "PCI4410" 451 #define PCIC_TI_PCI4451 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4451_DEVID) 452 #define PCIC_TYPE_PCI4451 "PCI4451" 453 #define PCIC_TI_PCI4510 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4510_DEVID) 454 #define PCIC_TYPE_PCI4510 "PCI4510" 455 #define PCIC_TI_PCI1410 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1410_DEVID) 456 #define PCIC_TYPE_PCI1410 "PCI1410" 457 #define PCIC_TI_PCI1420 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1420_DEVID) 458 #define PCIC_TYPE_PCI1420 "PCI1420" 459 #define PCIC_TI_PCI1451 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1451_DEVID) 460 #define PCIC_TYPE_PCI1451 "PCI1451" 461 #define PCIC_TI_PCI1421 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1421_DEVID) 462 #define PCIC_TYPE_PCI1421 "PCI1421" 463 #define PCIC_TI_PCI1510 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1510_DEVID) 464 #define PCIC_TYPE_PCI1510 "PCI1510" 465 #define PCIC_TI_PCI1520 PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1520_DEVID) 466 #define PCIC_TYPE_PCI1520 "PCI1520" 467 #define PCIC_TI_VENDOR PCI_ID(PCIC_TI_VENDORID, 0x0000) 468 #define PCIC_TYPE_TI "PCIC_TI" 469 470 /* O2 Micro */ 471 #define PCIC_O2_VENDORID 0x1217 472 #define PCIC_OZ6912_DEVID 0x6972 473 #define PCIC_O2_OZ6912 PCI_ID(PCIC_O2_VENDORID, PCIC_OZ6912_DEVID) 474 #define PCIC_TYPE_OZ6912 "OZ6912" 475 #define PCIC_O2MICRO_VENDOR PCI_ID(PCIC_O2_VENDORID, 0x0000) 476 #define PCIC_TYPE_O2MICRO "O2Micro" 477 478 /* ENE */ 479 #define PCIC_ENE_VENDORID 0x1524 480 #define PCIC_ENE1410_DEVID 0x1410 481 #define PCIC_ENE_1410 PCI_ID(PCIC_ENE_VENDORID, PCIC_ENE1410_DEVID) 482 #define PCIC_TYPE_1410 "ENE1410" 483 #define PCIC_ENE1420_DEVID 0x1420 484 #define PCIC_ENE_1420 PCI_ID(PCIC_ENE_VENDORID, PCIC_ENE1420_DEVID) 485 #define PCIC_TYPE_1420 "ENE1420" 486 487 /* SMC 34C90 */ 488 #define PCIC_SMC_VENDORID 0x10B3 489 #define PCIC_SMC34C90_DEVID 0xB106 490 #define PCIC_SMC_34C90 PCI_ID(PCIC_SMC_VENDORID, PCIC_SMC34C90_DEVID) 491 #define PCIC_TYPE_34C90 "SMC34c90" 492 493 /* Ricoh RL5CXXX */ 494 #define PCIC_RICOH_VENDORID 0x1180 495 #define PCIC_RL5C466_DEVID 0x0466 496 #define PCIC_RL5C475_DEVID 0x0475 497 #define PCIC_RL5C476_DEVID 0x0476 498 #define PCIC_RL5C477_DEVID 0x0477 499 #define PCIC_RL5C478_DEVID 0x0478 500 #define PCIC_RICOH_RL5C466 PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C466_DEVID) 501 #define PCIC_RICOH_RL5C475 PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C475_DEVID) 502 #define PCIC_RICOH_RL5C476 PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C476_DEVID) 503 #define PCIC_RICOH_RL5C477 PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C477_DEVID) 504 #define PCIC_RICOH_RL5C478 PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C478_DEVID) 505 #define PCIC_TYPE_RL5C466 "RL5C466" 506 #define PCIC_TYPE_RL5C475 "RL5C475" 507 #define PCIC_TYPE_RL5C476 "RL5C476" 508 #define PCIC_TYPE_RL5C477 "RL5C477" 509 #define PCIC_TYPE_RL5C478 "RL5C478" 510 #define PCIC_RICOH_VENDOR PCI_ID(PCIC_RICOH_VENDORID, 0x0000) 511 #define PCIC_TYPE_RICOH "Ricoh" 512 513 /* Toshiba */ 514 #define PCIC_TOSHIBA_VENDORID 0x1179 515 #define PCIC_TOPIC95_DEVID 0x0603 516 #define PCIC_TOSHIBA_TOPIC95 PCI_ID(PCIC_TOSHIBA_VENDORID, \ 517 PCIC_TOPIC95_DEVID) 518 #define PCIC_TYPE_TOPIC95 "ToPIC95" 519 #define PCIC_TOPIC100_DEVID 0x0617 520 #define PCIC_TOSHIBA_TOPIC100 PCI_ID(PCIC_TOSHIBA_VENDORID, \ 521 PCIC_TOPIC100_DEVID) 522 #define PCIC_TYPE_TOPIC100 "ToPIC100" 523 #define PCIC_TOSHIBA_VENDOR PCI_ID(PCIC_TOSHIBA_VENDORID, 0x0000) 524 #define PCIC_TYPE_TOSHIBA "Toshiba" 525 526 /* Generic Yenta compliant chip */ 527 #define PCIC_TYPE_YENTA "Yenta" 528 529 /* Yenta-compliant vcc register, bits */ 530 #define PCIC_PRESENT_STATE_REG 0x8 531 #define PCIC_VCC_MASK 0xc00 532 #define PCIC_VCC_3VCARD 0x800 533 #define PCIC_VCC_5VCARD 0x400 534 535 #define PCIC_16BIT_CARD 0x010 /* 16 bit card */ 536 #define PCIC_CB_CARD 0x020 /* cardbus card */ 537 #define PCIC_CINT_IREQ 0x040 /* Interrupt present */ 538 #define PCIC_NOT_A_CARD 0x080 /* Not a card */ 539 #define PCIC_DATA_LOST 0x100 /* Data lost */ 540 #define PCIC_BAD_VCC_REQ 0x200 /* Bad Vcc request */ 541 542 543 /* TI Multi Function Terminal selection (MFUNC0 selected as INTA) */ 544 #define PCIC_TI_MFUNC_SEL 0x22 545 546 #define PCICPROP_CTL "controller" 547 548 #define PCIC_REV_LEVEL_LOW 0x02 549 #define PCIC_REV_LEVEL_HI 0x04 550 #define PCIC_REV_C 0x04 551 #define PCIC_REV_MASK 0x0f 552 553 #define PCIC_ID_NAME "pcic" 554 #define PCIC_DEV_NAME "pcic" 555 556 #ifndef DEVI_PCI_NEXNAME 557 #define DEVI_PCI_NEXNAME "pci" 558 #endif 559 560 #ifndef DEVI_PCIEX_NEXNAME 561 #define DEVI_PCIEX_NEXNAME "pciex" 562 #endif 563 564 /* PCI Class Code stuff */ 565 #define PCIC_PCI_CLASS(cls, subclass) (((cls) << 16) | ((subclass) << 8)) 566 #define PCIC_PCI_PCMCIA PCIC_PCI_CLASS(PCI_CLASS_BRIDGE, PCI_BRIDGE_PCMCIA) 567 #define PCIC_PCI_CARDBUS PCIC_PCI_CLASS(PCI_CLASS_BRIDGE, PCI_BRIDGE_CARDBUS) 568 569 #define PCIC_MEM_AM 0 /* Attribute Memory */ 570 #define PCIC_MEM_CM 1 /* Common Memory */ 571 572 #define PCS_SUBTYPE_UNKNOWN 0x00 /* haven't processed this yet */ 573 #define PCS_SUBTYPE_MEMORY 0x01 /* normal memory access */ 574 #define PCS_SUBTYPE_FAT 0x02 /* DOS floppy (FAT) file system */ 575 576 /* 577 * For speed calculation, assume a SYSCLK rate of 8.33MHz 578 * unless our parent tells us otherwise. 8.33MHz is a 579 * reasonable default for an ISA bus. 580 */ 581 #define PCIC_ISA_DEF_SYSCLK 8 /* MHZ */ 582 #define PCIC_PCI_DEF_SYSCLK 33 /* MHZ */ 583 #define PCIC_PCI_25MHZ 25 584 #define mhztons(c) (1000000 / (uint32_t)((c) * 1000)) 585 #define PCIC_SYSCLK_25MHZ 25 * 1000 * 1000 586 #define PCIC_SYSCLK_33MHZ 33 * 1000 * 1000 587 588 /* simplify the callback so it looks like straight function call */ 589 #define PC_CALLBACK (*pcic->pc_callback) 590 591 /* hardware event capabilities -- needs sservice.h */ 592 #define PCIC_DEFAULT_INT_CAPS (SBM_BVD1|SBM_BVD2|SBM_RDYBSY|SBM_CD) 593 #define PCIC_DEFAULT_RPT_CAPS (PCIC_DEFAULT_INT_CAPS|SBM_WP) 594 /* note that we don't support indicators via the PCIC */ 595 #define PCIC_DEFAULT_CTL_CAPS (0) 596 597 /* format of pcic "ranges" property */ 598 typedef struct pcic_ranges { 599 uint32_t pcic_range_caddrhi; 600 uint32_t pcic_range_caddrlo; 601 uint32_t pcic_range_paddrhi; 602 uint32_t pcic_range_paddrmid; 603 uint32_t pcic_range_paddrlo; 604 uint32_t pcic_range_size; 605 } pcic_ranges_t; 606 607 /* debug stuff */ 608 #if defined(DEBUG) 609 #define PCIC_DEBUG 610 #endif 611 612 #ifdef __cplusplus 613 } 614 #endif 615 616 #endif /* _PCIC_VAR_H */ 617