1 /*- 2 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org> 3 * 4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/fbio.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/queue.h> 35 #include <sys/rman.h> 36 #include <sys/resource.h> 37 #include <machine/bus.h> 38 #include <vm/vm.h> 39 #include <vm/vm_extern.h> 40 #include <vm/vm_kern.h> 41 #include <vm/pmap.h> 42 43 #include <dev/fdt/simplebus.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/clk/clk.h> 49 50 #include <arm/ti/ti_sysc.h> 51 #include <arm/ti/clk/clock_common.h> 52 53 #define DEBUG_SYSC 0 54 55 #if DEBUG_SYSC 56 #define DPRINTF(dev, msg...) device_printf(dev, msg) 57 #else 58 #define DPRINTF(dev, msg...) 59 #endif 60 61 /* Documentation/devicetree/bindings/bus/ti-sysc.txt 62 * 63 * Documentation/devicetree/clock/clock-bindings.txt 64 * Defines phandle + optional pair 65 * Documentation/devicetree/clock/ti-clkctl.txt 66 */ 67 68 static int ti_sysc_probe(device_t dev); 69 static int ti_sysc_attach(device_t dev); 70 static int ti_sysc_detach(device_t dev); 71 72 #define TI_SYSC_DRA7_MCAN 15 73 #define TI_SYSC_USB_HOST_FS 14 74 #define TI_SYSC_DRA7_MCASP 13 75 #define TI_SYSC_MCASP 12 76 #define TI_SYSC_OMAP_AES 11 77 #define TI_SYSC_OMAP3_SHAM 10 78 #define TI_SYSC_OMAP4_SR 9 79 #define TI_SYSC_OMAP3630_SR 8 80 #define TI_SYSC_OMAP3430_SR 7 81 #define TI_SYSC_OMAP4_TIMER 6 82 #define TI_SYSC_OMAP2_TIMER 5 83 /* Above needs special workarounds */ 84 #define TI_SYSC_OMAP4_SIMPLE 4 85 #define TI_SYSC_OMAP4 3 86 #define TI_SYSC_OMAP2 2 87 #define TI_SYSC 1 88 #define TI_SYSC_END 0 89 90 static struct ofw_compat_data compat_data[] = { 91 { "ti,sysc-dra7-mcan", TI_SYSC_DRA7_MCAN }, 92 { "ti,sysc-usb-host-fs", TI_SYSC_USB_HOST_FS }, 93 { "ti,sysc-dra7-mcasp", TI_SYSC_DRA7_MCASP }, 94 { "ti,sysc-mcasp", TI_SYSC_MCASP }, 95 { "ti,sysc-omap-aes", TI_SYSC_OMAP_AES }, 96 { "ti,sysc-omap3-sham", TI_SYSC_OMAP3_SHAM }, 97 { "ti,sysc-omap4-sr", TI_SYSC_OMAP4_SR }, 98 { "ti,sysc-omap3630-sr", TI_SYSC_OMAP3630_SR }, 99 { "ti,sysc-omap3430-sr", TI_SYSC_OMAP3430_SR }, 100 { "ti,sysc-omap4-timer", TI_SYSC_OMAP4_TIMER }, 101 { "ti,sysc-omap2-timer", TI_SYSC_OMAP2_TIMER }, 102 /* Above needs special workarounds */ 103 { "ti,sysc-omap4-simple", TI_SYSC_OMAP4_SIMPLE }, 104 { "ti,sysc-omap4", TI_SYSC_OMAP4 }, 105 { "ti,sysc-omap2", TI_SYSC_OMAP2 }, 106 { "ti,sysc", TI_SYSC }, 107 { NULL, TI_SYSC_END } 108 }; 109 110 /* reg-names can be "rev", "sysc" and "syss" */ 111 static const char * reg_names[] = { "rev", "sysc", "syss" }; 112 #define REG_REV 0 113 #define REG_SYSC 1 114 #define REG_SYSS 2 115 #define REG_MAX 3 116 117 /* master idle / slave idle mode defined in 8.1.3.2.1 / 8.1.3.2.2 */ 118 #include <dt-bindings/bus/ti-sysc.h> 119 #define SYSC_IDLE_MAX 4 120 121 struct sysc_reg { 122 uint64_t address; 123 uint64_t size; 124 }; 125 126 struct clk_list { 127 TAILQ_ENTRY(clk_list) next; 128 clk_t clk; 129 }; 130 131 struct ti_sysc_softc { 132 bool attach_done; 133 134 device_t dev; 135 int device_type; 136 137 struct sysc_reg reg[REG_MAX]; 138 /* Offset from host base address */ 139 uint64_t offset_reg[REG_MAX]; 140 141 uint32_t ti_sysc_mask; 142 int32_t ti_sysc_midle[SYSC_IDLE_MAX]; 143 int32_t ti_sysc_sidle[SYSC_IDLE_MAX]; 144 uint32_t ti_sysc_delay_us; 145 uint32_t ti_syss_mask; 146 147 int num_clocks; 148 TAILQ_HEAD(, clk_list) clk_list; 149 150 /* deprecated ti_hwmods */ 151 bool ti_no_reset_on_init; 152 bool ti_no_idle_on_init; 153 bool ti_no_idle; 154 }; 155 156 /* 157 * All sysc seems to have a reg["rev"] register. 158 * Lets use that for identification of which module the driver are connected to. 159 */ 160 uint64_t 161 ti_sysc_get_rev_address(device_t dev) { 162 struct ti_sysc_softc *sc = device_get_softc(dev); 163 164 return (sc->reg[REG_REV].address); 165 } 166 167 uint64_t 168 ti_sysc_get_rev_address_offset_host(device_t dev) { 169 struct ti_sysc_softc *sc = device_get_softc(dev); 170 171 return (sc->offset_reg[REG_REV]); 172 } 173 174 uint64_t 175 ti_sysc_get_sysc_address(device_t dev) { 176 struct ti_sysc_softc *sc = device_get_softc(dev); 177 178 return (sc->reg[REG_SYSC].address); 179 } 180 181 uint64_t 182 ti_sysc_get_sysc_address_offset_host(device_t dev) { 183 struct ti_sysc_softc *sc = device_get_softc(dev); 184 185 return (sc->offset_reg[REG_SYSC]); 186 } 187 188 uint64_t 189 ti_sysc_get_syss_address(device_t dev) { 190 struct ti_sysc_softc *sc = device_get_softc(dev); 191 192 return (sc->reg[REG_SYSS].address); 193 } 194 195 uint64_t 196 ti_sysc_get_syss_address_offset_host(device_t dev) { 197 struct ti_sysc_softc *sc = device_get_softc(dev); 198 199 return (sc->offset_reg[REG_SYSS]); 200 } 201 202 /* 203 * Due no memory region is assigned the sysc driver the children needs to 204 * handle the practical read/writes to the registers. 205 * Check if sysc has reset bit. 206 */ 207 uint32_t 208 ti_sysc_get_soft_reset_bit(device_t dev) { 209 struct ti_sysc_softc *sc = device_get_softc(dev); 210 switch (sc->device_type) { 211 case TI_SYSC_OMAP4_TIMER: 212 case TI_SYSC_OMAP4_SIMPLE: 213 case TI_SYSC_OMAP4: 214 if (sc->ti_sysc_mask & SYSC_OMAP4_SOFTRESET) { 215 return (SYSC_OMAP4_SOFTRESET); 216 } 217 break; 218 219 case TI_SYSC_OMAP2_TIMER: 220 case TI_SYSC_OMAP2: 221 case TI_SYSC: 222 if (sc->ti_sysc_mask & SYSC_OMAP2_SOFTRESET) { 223 return (SYSC_OMAP2_SOFTRESET); 224 } 225 break; 226 default: 227 break; 228 } 229 230 return (0); 231 } 232 233 int 234 ti_sysc_clock_enable(device_t dev) { 235 struct clk_list *clkp, *clkp_tmp; 236 struct ti_sysc_softc *sc = device_get_softc(dev); 237 int err; 238 239 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 240 err = clk_enable(clkp->clk); 241 242 if (err) { 243 DPRINTF(sc->dev, "clk_enable %s failed %d\n", 244 clk_get_name(clkp->clk), err); 245 break; 246 } 247 } 248 return (err); 249 } 250 251 int 252 ti_sysc_clock_disable(device_t dev) { 253 struct clk_list *clkp, *clkp_tmp; 254 struct ti_sysc_softc *sc = device_get_softc(dev); 255 int err = 0; 256 257 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 258 err = clk_disable(clkp->clk); 259 260 if (err) { 261 DPRINTF(sc->dev, "clk_enable %s failed %d\n", 262 clk_get_name(clkp->clk), err); 263 break; 264 } 265 } 266 return (err); 267 } 268 269 static int 270 parse_regfields(struct ti_sysc_softc *sc) { 271 phandle_t node; 272 uint32_t parent_address_cells; 273 uint32_t parent_size_cells; 274 cell_t *reg; 275 ssize_t nreg; 276 int err, k, reg_i, prop_idx; 277 uint32_t idx; 278 279 node = ofw_bus_get_node(sc->dev); 280 281 /* Get parents address and size properties */ 282 err = OF_searchencprop(OF_parent(node), "#address-cells", 283 &parent_address_cells, sizeof(parent_address_cells)); 284 if (err == -1) 285 return (ENXIO); 286 if (!(parent_address_cells == 1 || parent_address_cells == 2)) { 287 DPRINTF(sc->dev, "Expect parent #address-cells=[1||2]\n"); 288 return (ENXIO); 289 } 290 291 err = OF_searchencprop(OF_parent(node), "#size-cells", 292 &parent_size_cells, sizeof(parent_size_cells)); 293 if (err == -1) 294 return (ENXIO); 295 296 if (!(parent_size_cells == 1 || parent_size_cells == 2)) { 297 DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n"); 298 return (ENXIO); 299 } 300 301 /* Grab the content of reg properties */ 302 nreg = OF_getproplen(node, "reg"); 303 if (nreg <= 0) 304 return (ENXIO); 305 306 reg = malloc(nreg, M_DEVBUF, M_WAITOK); 307 OF_getencprop(node, "reg", reg, nreg); 308 309 /* Make sure address & size are 0 */ 310 for (idx = 0; idx < REG_MAX; idx++) { 311 sc->reg[idx].address = 0; 312 sc->reg[idx].size = 0; 313 } 314 315 /* Loop through reg-names and figure out which reg-name corresponds to 316 * index populate the values into the reg array. 317 */ 318 for (idx = 0, reg_i = 0; idx < REG_MAX && reg_i < nreg; idx++) { 319 err = ofw_bus_find_string_index(node, "reg-names", 320 reg_names[idx], &prop_idx); 321 if (err != 0) 322 continue; 323 324 for (k = 0; k < parent_address_cells; k++) { 325 sc->reg[prop_idx].address <<= 32; 326 sc->reg[prop_idx].address |= reg[reg_i++]; 327 } 328 329 for (k = 0; k < parent_size_cells; k++) { 330 sc->reg[prop_idx].size <<= 32; 331 sc->reg[prop_idx].size |= reg[reg_i++]; 332 } 333 334 if (sc->sc.nranges == 0) 335 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address; 336 else 337 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address - 338 sc->sc.ranges[REG_REV].host; 339 340 DPRINTF(sc->dev, "reg[%s] address %#jx size %#jx\n", 341 reg_names[idx], 342 sc->reg[prop_idx].address, 343 sc->reg[prop_idx].size); 344 } 345 free(reg, M_DEVBUF); 346 return (0); 347 } 348 349 static void 350 parse_idle(struct ti_sysc_softc *sc, const char *name, uint32_t *idle) { 351 phandle_t node; 352 cell_t value[SYSC_IDLE_MAX]; 353 int len, no, i; 354 355 node = ofw_bus_get_node(sc->dev); 356 357 if (!OF_hasprop(node, name)) { 358 return; 359 } 360 361 len = OF_getproplen(node, name); 362 no = len / sizeof(cell_t); 363 if (no >= SYSC_IDLE_MAX) { 364 DPRINTF(sc->dev, "Limit %s\n", name); 365 no = SYSC_IDLE_MAX-1; 366 len = no * sizeof(cell_t); 367 } 368 369 OF_getencprop(node, name, value, len); 370 for (i = 0; i < no; i++) { 371 idle[i] = value[i]; 372 #if DEBUG_SYSC 373 DPRINTF(sc->dev, "%s[%d] = %d ", 374 name, i, value[i]); 375 switch(value[i]) { 376 case SYSC_IDLE_FORCE: 377 DPRINTF(sc->dev, "SYSC_IDLE_FORCE\n"); 378 break; 379 case SYSC_IDLE_NO: 380 DPRINTF(sc->dev, "SYSC_IDLE_NO\n"); 381 break; 382 case SYSC_IDLE_SMART: 383 DPRINTF(sc->dev, "SYSC_IDLE_SMART\n"); 384 break; 385 case SYSC_IDLE_SMART_WKUP: 386 DPRINTF(sc->dev, "SYSC_IDLE_SMART_WKUP\n"); 387 break; 388 } 389 #endif 390 } 391 for ( ; i < SYSC_IDLE_MAX; i++) 392 idle[i] = -1; 393 } 394 395 static int 396 ti_sysc_attach_clocks(struct ti_sysc_softc *sc) { 397 clk_t *clk; 398 struct clk_list *clkp; 399 int index, err; 400 401 clk = malloc(sc->num_clocks*sizeof(clk_t), M_DEVBUF, M_WAITOK | M_ZERO); 402 403 /* Check if all clocks can be found */ 404 for (index = 0; index < sc->num_clocks; index++) { 405 err = clk_get_by_ofw_index(sc->dev, 0, index, &clk[index]); 406 407 if (err != 0) { 408 free(clk, M_DEVBUF); 409 return (1); 410 } 411 } 412 413 /* All clocks are found, add to list */ 414 for (index = 0; index < sc->num_clocks; index++) { 415 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); 416 clkp->clk = clk[index]; 417 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); 418 } 419 420 /* Release the clk array */ 421 free(clk, M_DEVBUF); 422 return (0); 423 } 424 425 static int 426 ti_sysc_simplebus_attach_child(device_t dev) { 427 device_t cdev; 428 phandle_t node, child; 429 struct ti_sysc_softc *sc = device_get_softc(dev); 430 431 node = ofw_bus_get_node(sc->dev); 432 433 for (child = OF_child(node); child > 0; child = OF_peer(child)) { 434 cdev = simplebus_add_device(sc->dev, child, 0, NULL, -1, NULL); 435 if (cdev != NULL) 436 device_probe_and_attach(cdev); 437 } 438 return (0); 439 } 440 441 /* Device interface */ 442 static int 443 ti_sysc_probe(device_t dev) 444 { 445 if (!ofw_bus_status_okay(dev)) 446 return (ENXIO); 447 448 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 449 return (ENXIO); 450 451 device_set_desc(dev, "TI SYSC Interconnect"); 452 453 return (BUS_PROBE_DEFAULT); 454 } 455 456 static int 457 ti_sysc_attach(device_t dev) 458 { 459 struct ti_sysc_softc *sc; 460 phandle_t node; 461 int err; 462 cell_t value; 463 464 sc = device_get_softc(dev); 465 sc->dev = dev; 466 sc->device_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 467 468 node = ofw_bus_get_node(sc->dev); 469 /* ranges - use simplebus */ 470 simplebus_init(sc->dev, node); 471 if (simplebus_fill_ranges(node, &sc->sc) < 0) { 472 DPRINTF(sc->dev, "could not get ranges\n"); 473 return (ENXIO); 474 } 475 476 if (sc->sc.nranges == 0) { 477 DPRINTF(sc->dev, "nranges == 0\n"); 478 return (ENXIO); 479 } 480 481 /* Required field reg & reg-names - assume at least "rev" exists */ 482 err = parse_regfields(sc); 483 if (err) { 484 DPRINTF(sc->dev, "parse_regfields failed %d\n", err); 485 return (ENXIO); 486 } 487 488 /* Optional */ 489 if (OF_hasprop(node, "ti,sysc-mask")) { 490 OF_getencprop(node, "ti,sysc-mask", &value, sizeof(cell_t)); 491 sc->ti_sysc_mask = value; 492 } 493 if (OF_hasprop(node, "ti,syss-mask")) { 494 OF_getencprop(node, "ti,syss-mask", &value, sizeof(cell_t)); 495 sc->ti_syss_mask = value; 496 } 497 if (OF_hasprop(node, "ti,sysc-delay-us")) { 498 OF_getencprop(node, "ti,sysc-delay-us", &value, sizeof(cell_t)); 499 sc->ti_sysc_delay_us = value; 500 } 501 502 DPRINTF(sc->dev, "sysc_mask %x syss_mask %x delay_us %x\n", 503 sc->ti_sysc_mask, sc->ti_syss_mask, sc->ti_sysc_delay_us); 504 505 parse_idle(sc, "ti,sysc-midle", sc->ti_sysc_midle); 506 parse_idle(sc, "ti,sysc-sidle", sc->ti_sysc_sidle); 507 508 if (OF_hasprop(node, "ti,no-reset-on-init")) 509 sc->ti_no_reset_on_init = true; 510 else 511 sc->ti_no_reset_on_init = false; 512 513 if (OF_hasprop(node, "ti,no-idle-on-init")) 514 sc->ti_no_idle_on_init = true; 515 else 516 sc->ti_no_idle_on_init = false; 517 518 if (OF_hasprop(node, "ti,no-idle")) 519 sc->ti_no_idle = true; 520 else 521 sc->ti_no_idle = false; 522 523 DPRINTF(sc->dev, 524 "no-reset-on-init %d, no-idle-on-init %d, no-idle %d\n", 525 sc->ti_no_reset_on_init, 526 sc->ti_no_idle_on_init, 527 sc->ti_no_idle); 528 529 if (OF_hasprop(node, "clocks")) { 530 struct clock_cell_info cell_info; 531 read_clock_cells(sc->dev, &cell_info); 532 free(cell_info.clock_cells, M_DEVBUF); 533 free(cell_info.clock_cells_ncells, M_DEVBUF); 534 535 sc->num_clocks = cell_info.num_real_clocks; 536 TAILQ_INIT(&sc->clk_list); 537 538 err = ti_sysc_attach_clocks(sc); 539 if (err) { 540 DPRINTF(sc->dev, "Failed to attach clocks\n"); 541 bus_attach_children(sc->dev); 542 return (0); 543 } 544 } 545 546 err = ti_sysc_simplebus_attach_child(sc->dev); 547 if (err) { 548 DPRINTF(sc->dev, "ti_sysc_simplebus_attach_child %d\n", 549 err); 550 return (err); 551 } 552 553 sc->attach_done = true; 554 555 bus_attach_children(sc->dev); 556 return (0); 557 } 558 559 static int 560 ti_sysc_detach(device_t dev) 561 { 562 return (EBUSY); 563 } 564 565 /* Bus interface */ 566 static void 567 ti_sysc_new_pass(device_t dev) 568 { 569 struct ti_sysc_softc *sc; 570 int err; 571 phandle_t node; 572 573 sc = device_get_softc(dev); 574 575 if (sc->attach_done) { 576 bus_generic_new_pass(sc->dev); 577 return; 578 } 579 580 node = ofw_bus_get_node(sc->dev); 581 if (OF_hasprop(node, "clocks")) { 582 err = ti_sysc_attach_clocks(sc); 583 if (err) { 584 DPRINTF(sc->dev, "Failed to attach clocks\n"); 585 return; 586 } 587 } 588 589 err = ti_sysc_simplebus_attach_child(sc->dev); 590 if (err) { 591 DPRINTF(sc->dev, 592 "ti_sysc_simplebus_attach_child failed %d\n", err); 593 return; 594 } 595 sc->attach_done = true; 596 597 bus_attach_children(sc->dev); 598 } 599 600 static device_method_t ti_sysc_methods[] = { 601 /* Device interface */ 602 DEVMETHOD(device_probe, ti_sysc_probe), 603 DEVMETHOD(device_attach, ti_sysc_attach), 604 DEVMETHOD(device_detach, ti_sysc_detach), 605 606 /* Bus interface */ 607 DEVMETHOD(bus_new_pass, ti_sysc_new_pass), 608 609 DEVMETHOD_END 610 }; 611 612 DEFINE_CLASS_1(ti_sysc, ti_sysc_driver, ti_sysc_methods, 613 sizeof(struct ti_sysc_softc), simplebus_driver); 614 615 EARLY_DRIVER_MODULE(ti_sysc, simplebus, ti_sysc_driver, 0, 0, 616 BUS_PASS_BUS + BUS_PASS_ORDER_FIRST); 617