1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AppliedMicro X-Gene SoC GPIO-Standby Driver
4 *
5 * Copyright (c) 2014, Applied Micro Circuits Corporation
6 * Author: Tin Huynh <tnhuynh@apm.com>.
7 * Y Vo <yvo@apm.com>.
8 * Quan Nguyen <qnguyen@apm.com>.
9 */
10
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/types.h>
22
23 #include <linux/gpio/driver.h>
24
25 #include "gpiolib-acpi.h"
26
27 #define XGENE_DFLT_MAX_NGPIO 22
28 #define XGENE_DFLT_MAX_NIRQ 6
29 #define XGENE_DFLT_IRQ_START_PIN 8
30 #define GPIO_MASK(x) (1U << ((x) % 32))
31
32 #define MPA_GPIO_INT_LVL 0x0290
33 #define MPA_GPIO_OE_ADDR 0x029c
34 #define MPA_GPIO_OUT_ADDR 0x02a0
35 #define MPA_GPIO_IN_ADDR 0x02a4
36 #define MPA_GPIO_SEL_LO 0x0294
37
38 #define GPIO_INT_LEVEL_H 0x000001
39 #define GPIO_INT_LEVEL_L 0x000000
40
41 /**
42 * struct xgene_gpio_sb - GPIO-Standby private data structure.
43 * @gc: memory-mapped GPIO controllers.
44 * @regs: GPIO register base offset
45 * @irq_domain: GPIO interrupt domain
46 * @irq_start: GPIO pin that start support interrupt
47 * @nirq: Number of GPIO pins that supports interrupt
48 * @parent_irq_base: Start parent HWIRQ
49 */
50 struct xgene_gpio_sb {
51 struct gpio_chip gc;
52 void __iomem *regs;
53 struct irq_domain *irq_domain;
54 u16 irq_start;
55 u16 nirq;
56 u16 parent_irq_base;
57 };
58
59 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
60 #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
61
xgene_gpio_set_bit(struct gpio_chip * gc,void __iomem * reg,u32 gpio,int val)62 static void xgene_gpio_set_bit(struct gpio_chip *gc,
63 void __iomem *reg, u32 gpio, int val)
64 {
65 u32 data;
66
67 data = gc->read_reg(reg);
68 if (val)
69 data |= GPIO_MASK(gpio);
70 else
71 data &= ~GPIO_MASK(gpio);
72 gc->write_reg(reg, data);
73 }
74
xgene_gpio_sb_irq_set_type(struct irq_data * d,unsigned int type)75 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
76 {
77 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
78 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
79 int lvl_type = GPIO_INT_LEVEL_H;
80
81 switch (type & IRQ_TYPE_SENSE_MASK) {
82 case IRQ_TYPE_EDGE_RISING:
83 case IRQ_TYPE_LEVEL_HIGH:
84 lvl_type = GPIO_INT_LEVEL_H;
85 break;
86 case IRQ_TYPE_EDGE_FALLING:
87 case IRQ_TYPE_LEVEL_LOW:
88 lvl_type = GPIO_INT_LEVEL_L;
89 break;
90 default:
91 break;
92 }
93
94 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
95 gpio * 2, 1);
96 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
97 d->hwirq, lvl_type);
98
99 /* Propagate IRQ type setting to parent */
100 if (type & IRQ_TYPE_EDGE_BOTH)
101 return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
102 else
103 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
104 }
105
xgene_gpio_sb_irq_mask(struct irq_data * d)106 static void xgene_gpio_sb_irq_mask(struct irq_data *d)
107 {
108 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
109
110 irq_chip_mask_parent(d);
111
112 gpiochip_disable_irq(&priv->gc, d->hwirq);
113 }
114
xgene_gpio_sb_irq_unmask(struct irq_data * d)115 static void xgene_gpio_sb_irq_unmask(struct irq_data *d)
116 {
117 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
118
119 gpiochip_enable_irq(&priv->gc, d->hwirq);
120
121 irq_chip_unmask_parent(d);
122 }
123
124 static const struct irq_chip xgene_gpio_sb_irq_chip = {
125 .name = "sbgpio",
126 .irq_eoi = irq_chip_eoi_parent,
127 .irq_mask = xgene_gpio_sb_irq_mask,
128 .irq_unmask = xgene_gpio_sb_irq_unmask,
129 .irq_set_type = xgene_gpio_sb_irq_set_type,
130 .flags = IRQCHIP_IMMUTABLE,
131 GPIOCHIP_IRQ_RESOURCE_HELPERS,
132 };
133
xgene_gpio_sb_to_irq(struct gpio_chip * gc,u32 gpio)134 static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
135 {
136 struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
137 struct irq_fwspec fwspec;
138
139 if ((gpio < priv->irq_start) ||
140 (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
141 return -ENXIO;
142
143 fwspec.fwnode = gc->parent->fwnode;
144 fwspec.param_count = 2;
145 fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
146 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
147 return irq_create_fwspec_mapping(&fwspec);
148 }
149
xgene_gpio_sb_domain_activate(struct irq_domain * d,struct irq_data * irq_data,bool reserve)150 static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
151 struct irq_data *irq_data,
152 bool reserve)
153 {
154 struct xgene_gpio_sb *priv = d->host_data;
155 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
156 int ret;
157
158 ret = gpiochip_lock_as_irq(&priv->gc, gpio);
159 if (ret) {
160 dev_err(priv->gc.parent,
161 "Unable to configure XGene GPIO standby pin %d as IRQ\n",
162 gpio);
163 return ret;
164 }
165
166 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
167 gpio * 2, 1);
168 return 0;
169 }
170
xgene_gpio_sb_domain_deactivate(struct irq_domain * d,struct irq_data * irq_data)171 static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
172 struct irq_data *irq_data)
173 {
174 struct xgene_gpio_sb *priv = d->host_data;
175 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
176
177 gpiochip_unlock_as_irq(&priv->gc, gpio);
178 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
179 gpio * 2, 0);
180 }
181
xgene_gpio_sb_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)182 static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
183 struct irq_fwspec *fwspec,
184 unsigned long *hwirq,
185 unsigned int *type)
186 {
187 struct xgene_gpio_sb *priv = d->host_data;
188
189 if ((fwspec->param_count != 2) ||
190 (fwspec->param[0] >= priv->nirq))
191 return -EINVAL;
192 *hwirq = fwspec->param[0];
193 *type = fwspec->param[1];
194 return 0;
195 }
196
xgene_gpio_sb_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)197 static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
198 unsigned int virq,
199 unsigned int nr_irqs, void *data)
200 {
201 struct irq_fwspec *fwspec = data;
202 struct irq_fwspec parent_fwspec;
203 struct xgene_gpio_sb *priv = domain->host_data;
204 irq_hw_number_t hwirq;
205 unsigned int i;
206
207 hwirq = fwspec->param[0];
208 for (i = 0; i < nr_irqs; i++)
209 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
210 &xgene_gpio_sb_irq_chip, priv);
211
212 parent_fwspec.fwnode = domain->parent->fwnode;
213 if (is_of_node(parent_fwspec.fwnode)) {
214 parent_fwspec.param_count = 3;
215 parent_fwspec.param[0] = 0;/* SPI */
216 /* Skip SGIs and PPIs*/
217 parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
218 parent_fwspec.param[2] = fwspec->param[1];
219 } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
220 parent_fwspec.param_count = 2;
221 parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
222 parent_fwspec.param[1] = fwspec->param[1];
223 } else
224 return -EINVAL;
225
226 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
227 &parent_fwspec);
228 }
229
230 static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
231 .translate = xgene_gpio_sb_domain_translate,
232 .alloc = xgene_gpio_sb_domain_alloc,
233 .free = irq_domain_free_irqs_common,
234 .activate = xgene_gpio_sb_domain_activate,
235 .deactivate = xgene_gpio_sb_domain_deactivate,
236 };
237
xgene_gpio_sb_probe(struct platform_device * pdev)238 static int xgene_gpio_sb_probe(struct platform_device *pdev)
239 {
240 struct xgene_gpio_sb *priv;
241 int ret;
242 void __iomem *regs;
243 struct irq_domain *parent_domain = NULL;
244 u32 val32;
245
246 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
247 if (!priv)
248 return -ENOMEM;
249
250 regs = devm_platform_ioremap_resource(pdev, 0);
251 if (IS_ERR(regs))
252 return PTR_ERR(regs);
253
254 priv->regs = regs;
255
256 ret = platform_get_irq(pdev, 0);
257 if (ret > 0) {
258 priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
259 parent_domain = irq_get_irq_data(ret)->domain;
260 }
261 if (!parent_domain) {
262 dev_err(&pdev->dev, "unable to obtain parent domain\n");
263 return -ENODEV;
264 }
265
266 ret = bgpio_init(&priv->gc, &pdev->dev, 4,
267 regs + MPA_GPIO_IN_ADDR,
268 regs + MPA_GPIO_OUT_ADDR, NULL,
269 regs + MPA_GPIO_OE_ADDR, NULL, 0);
270 if (ret)
271 return ret;
272
273 priv->gc.to_irq = xgene_gpio_sb_to_irq;
274
275 /* Retrieve start irq pin, use default if property not found */
276 priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
277 if (!device_property_read_u32(&pdev->dev, "apm,irq-start", &val32))
278 priv->irq_start = val32;
279
280 /* Retrieve number irqs, use default if property not found */
281 priv->nirq = XGENE_DFLT_MAX_NIRQ;
282 if (!device_property_read_u32(&pdev->dev, "apm,nr-irqs", &val32))
283 priv->nirq = val32;
284
285 /* Retrieve number gpio, use default if property not found */
286 priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
287 if (!device_property_read_u32(&pdev->dev, "apm,nr-gpios", &val32))
288 priv->gc.ngpio = val32;
289
290 dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
291 priv->gc.ngpio, priv->nirq, priv->irq_start);
292
293 platform_set_drvdata(pdev, priv);
294
295 priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
296 0, priv->nirq, pdev->dev.fwnode,
297 &xgene_gpio_sb_domain_ops, priv);
298 if (!priv->irq_domain)
299 return -ENODEV;
300
301 priv->gc.irq.domain = priv->irq_domain;
302
303 ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
304 if (ret) {
305 dev_err(&pdev->dev,
306 "failed to register X-Gene GPIO Standby driver\n");
307 irq_domain_remove(priv->irq_domain);
308 return ret;
309 }
310
311 dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
312
313 /* Register interrupt handlers for GPIO signaled ACPI Events */
314 acpi_gpiochip_request_interrupts(&priv->gc);
315
316 return ret;
317 }
318
xgene_gpio_sb_remove(struct platform_device * pdev)319 static void xgene_gpio_sb_remove(struct platform_device *pdev)
320 {
321 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
322
323 acpi_gpiochip_free_interrupts(&priv->gc);
324
325 irq_domain_remove(priv->irq_domain);
326 }
327
328 static const struct of_device_id xgene_gpio_sb_of_match[] = {
329 { .compatible = "apm,xgene-gpio-sb" },
330 {}
331 };
332 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
333
334 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
335 { "APMC0D15" },
336 {}
337 };
338 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
339
340 static struct platform_driver xgene_gpio_sb_driver = {
341 .driver = {
342 .name = "xgene-gpio-sb",
343 .of_match_table = xgene_gpio_sb_of_match,
344 .acpi_match_table = xgene_gpio_sb_acpi_match,
345 },
346 .probe = xgene_gpio_sb_probe,
347 .remove = xgene_gpio_sb_remove,
348 };
349 module_platform_driver(xgene_gpio_sb_driver);
350
351 MODULE_AUTHOR("AppliedMicro");
352 MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
353 MODULE_LICENSE("GPL");
354