1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/string_helpers.h>
27 #include <linux/uaccess.h>
28 #include <media/cec-notifier.h>
29
30 #include "dc.h"
31 #include "amdgpu.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_debugfs.h"
34 #include "amdgpu_dm_replay.h"
35 #include "dm_helpers.h"
36 #include "dmub/dmub_srv.h"
37 #include "resource.h"
38 #include "dsc.h"
39 #include "link_hwss.h"
40 #include "dc/dc_dmub_srv.h"
41 #include "link/protocols/link_dp_capability.h"
42 #include "inc/hw/dchubbub.h"
43
44 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
45 #include "amdgpu_dm_psr.h"
46 #endif
47
48 struct dmub_debugfs_trace_header {
49 uint32_t entry_count;
50 uint32_t reserved[3];
51 };
52
53 struct dmub_debugfs_trace_entry {
54 uint32_t trace_code;
55 uint32_t tick_count;
56 uint32_t param0;
57 uint32_t param1;
58 };
59
60 static const char *const mst_progress_status[] = {
61 "probe",
62 "remote_edid",
63 "allocate_new_payload",
64 "clear_allocated_payload",
65 };
66
67 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
68 *
69 * Function takes in attributes passed to debugfs write entry
70 * and writes into param array.
71 * The user passes max_param_num to identify maximum number of
72 * parameters that could be parsed.
73 *
74 */
parse_write_buffer_into_params(char * wr_buf,uint32_t wr_buf_size,long * param,const char __user * buf,int max_param_num,uint8_t * param_nums)75 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
76 long *param, const char __user *buf,
77 int max_param_num,
78 uint8_t *param_nums)
79 {
80 char *wr_buf_ptr = NULL;
81 uint32_t wr_buf_count = 0;
82 int r;
83 char *sub_str = NULL;
84 const char delimiter[3] = {' ', '\n', '\0'};
85 uint8_t param_index = 0;
86
87 *param_nums = 0;
88
89 wr_buf_ptr = wr_buf;
90
91 /* r is bytes not be copied */
92 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
93 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
94 return -EFAULT;
95 }
96
97 /* check number of parameters. isspace could not differ space and \n */
98 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
99 /* skip space*/
100 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
101 wr_buf_ptr++;
102 wr_buf_count++;
103 }
104
105 if (wr_buf_count == wr_buf_size)
106 break;
107
108 /* skip non-space*/
109 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
110 wr_buf_ptr++;
111 wr_buf_count++;
112 }
113
114 (*param_nums)++;
115
116 if (wr_buf_count == wr_buf_size)
117 break;
118 }
119
120 if (*param_nums > max_param_num)
121 *param_nums = max_param_num;
122
123 wr_buf_ptr = wr_buf; /* reset buf pointer */
124 wr_buf_count = 0; /* number of char already checked */
125
126 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
127 wr_buf_ptr++;
128 wr_buf_count++;
129 }
130
131 while (param_index < *param_nums) {
132 /* after strsep, wr_buf_ptr will be moved to after space */
133 sub_str = strsep(&wr_buf_ptr, delimiter);
134
135 r = kstrtol(sub_str, 16, &(param[param_index]));
136
137 if (r)
138 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
139
140 param_index++;
141 }
142
143 return 0;
144 }
145
146 /* function description
147 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
148 *
149 * valid lane count value: 1, 2, 4
150 * valid link rate value:
151 * 06h = 1.62Gbps per lane
152 * 0Ah = 2.7Gbps per lane
153 * 0Ch = 3.24Gbps per lane
154 * 14h = 5.4Gbps per lane
155 * 1Eh = 8.1Gbps per lane
156 *
157 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
158 *
159 * --- to get dp configuration
160 *
161 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
162 *
163 * It will list current, verified, reported, preferred dp configuration.
164 * current -- for current video mode
165 * verified --- maximum configuration which pass link training
166 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
167 * preferred --- user force settings
168 *
169 * --- set (or force) dp configuration
170 *
171 * echo <lane_count> <link_rate> > link_settings
172 *
173 * for example, to force to 2 lane, 2.7GHz,
174 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
175 *
176 * spread_spectrum could not be changed dynamically.
177 *
178 * in case invalid lane count, link rate are force, no hw programming will be
179 * done. please check link settings after force operation to see if HW get
180 * programming.
181 *
182 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
183 *
184 * check current and preferred settings.
185 *
186 */
dp_link_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)187 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
188 size_t size, loff_t *pos)
189 {
190 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
191 struct dc_link *link = connector->dc_link;
192 char *rd_buf = NULL;
193 char *rd_buf_ptr = NULL;
194 const uint32_t rd_buf_size = 100;
195 uint32_t result = 0;
196 uint8_t str_len = 0;
197 int r;
198
199 if (*pos & 3 || size & 3)
200 return -EINVAL;
201
202 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
203 if (!rd_buf)
204 return 0;
205
206 rd_buf_ptr = rd_buf;
207
208 str_len = strlen("Current: %d 0x%x %d ");
209 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ",
210 link->cur_link_settings.lane_count,
211 link->cur_link_settings.link_rate,
212 link->cur_link_settings.link_spread);
213 rd_buf_ptr += str_len;
214
215 str_len = strlen("Verified: %d 0x%x %d ");
216 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ",
217 link->verified_link_cap.lane_count,
218 link->verified_link_cap.link_rate,
219 link->verified_link_cap.link_spread);
220 rd_buf_ptr += str_len;
221
222 str_len = strlen("Reported: %d 0x%x %d ");
223 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ",
224 link->reported_link_cap.lane_count,
225 link->reported_link_cap.link_rate,
226 link->reported_link_cap.link_spread);
227 rd_buf_ptr += str_len;
228
229 str_len = strlen("Preferred: %d 0x%x %d ");
230 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n",
231 link->preferred_link_setting.lane_count,
232 link->preferred_link_setting.link_rate,
233 link->preferred_link_setting.link_spread);
234
235 while (size) {
236 if (*pos >= rd_buf_size)
237 break;
238
239 r = put_user(*(rd_buf + result), buf);
240 if (r) {
241 kfree(rd_buf);
242 return r; /* r = -EFAULT */
243 }
244
245 buf += 1;
246 size -= 1;
247 *pos += 1;
248 result += 1;
249 }
250
251 kfree(rd_buf);
252 return result;
253 }
254
dp_link_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)255 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
256 size_t size, loff_t *pos)
257 {
258 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
259 struct dc_link *link = connector->dc_link;
260 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
261 struct dc *dc = (struct dc *)link->dc;
262 struct dc_link_settings prefer_link_settings = {0};
263 char *wr_buf = NULL;
264 const uint32_t wr_buf_size = 40;
265 /* 0: lane_count; 1: link_rate */
266 int max_param_num = 2;
267 uint8_t param_nums = 0;
268 long param[2];
269 bool valid_input = true;
270
271 if (size == 0)
272 return -EINVAL;
273
274 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
275 if (!wr_buf)
276 return -ENOSPC;
277
278 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
279 (long *)param, buf,
280 max_param_num,
281 ¶m_nums)) {
282 kfree(wr_buf);
283 return -EINVAL;
284 }
285
286 if (param_nums <= 0) {
287 kfree(wr_buf);
288 DRM_DEBUG_DRIVER("user data not be read\n");
289 return -EINVAL;
290 }
291
292 switch (param[0]) {
293 case LANE_COUNT_ONE:
294 case LANE_COUNT_TWO:
295 case LANE_COUNT_FOUR:
296 break;
297 default:
298 valid_input = false;
299 break;
300 }
301
302 switch (param[1]) {
303 case LINK_RATE_LOW:
304 case LINK_RATE_HIGH:
305 case LINK_RATE_RBR2:
306 case LINK_RATE_HIGH2:
307 case LINK_RATE_HIGH3:
308 case LINK_RATE_UHBR10:
309 case LINK_RATE_UHBR13_5:
310 case LINK_RATE_UHBR20:
311 break;
312 default:
313 valid_input = false;
314 break;
315 }
316
317 if (!valid_input) {
318 kfree(wr_buf);
319 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
320 mutex_lock(&adev->dm.dc_lock);
321 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
322 mutex_unlock(&adev->dm.dc_lock);
323 return size;
324 }
325
326 /* save user force lane_count, link_rate to preferred settings
327 * spread spectrum will not be changed
328 */
329 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
330 prefer_link_settings.use_link_rate_set = false;
331 prefer_link_settings.lane_count = param[0];
332 prefer_link_settings.link_rate = param[1];
333
334 mutex_lock(&adev->dm.dc_lock);
335 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
336 mutex_unlock(&adev->dm.dc_lock);
337
338 kfree(wr_buf);
339 return size;
340 }
341
dp_mst_is_end_device(struct amdgpu_dm_connector * aconnector)342 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
343 {
344 bool is_end_device = false;
345 struct drm_dp_mst_topology_mgr *mgr = NULL;
346 struct drm_dp_mst_port *port = NULL;
347
348 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
349 mgr = &aconnector->mst_root->mst_mgr;
350 port = aconnector->mst_output_port;
351
352 drm_modeset_lock(&mgr->base.lock, NULL);
353 if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
354 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
355 is_end_device = true;
356 drm_modeset_unlock(&mgr->base.lock);
357 }
358
359 return is_end_device;
360 }
361
362 /* Change MST link setting
363 *
364 * valid lane count value: 1, 2, 4
365 * valid link rate value:
366 * 06h = 1.62Gbps per lane
367 * 0Ah = 2.7Gbps per lane
368 * 0Ch = 3.24Gbps per lane
369 * 14h = 5.4Gbps per lane
370 * 1Eh = 8.1Gbps per lane
371 * 3E8h = 10.0Gbps per lane
372 * 546h = 13.5Gbps per lane
373 * 7D0h = 20.0Gbps per lane
374 *
375 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
376 *
377 * for example, to force to 2 lane, 10.0GHz,
378 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
379 *
380 * Valid input will trigger hotplug event to get new link setting applied
381 * Invalid input will trigger training setting reset
382 *
383 * The usage can be referred to link_settings entry
384 *
385 */
dp_mst_link_setting(struct file * f,const char __user * buf,size_t size,loff_t * pos)386 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
387 size_t size, loff_t *pos)
388 {
389 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
390 struct dc_link *link = aconnector->dc_link;
391 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
392 struct dc *dc = (struct dc *)link->dc;
393 struct dc_link_settings prefer_link_settings = {0};
394 char *wr_buf = NULL;
395 const uint32_t wr_buf_size = 40;
396 /* 0: lane_count; 1: link_rate */
397 int max_param_num = 2;
398 uint8_t param_nums = 0;
399 long param[2];
400 bool valid_input = true;
401
402 if (!dp_mst_is_end_device(aconnector))
403 return -EINVAL;
404
405 if (size == 0)
406 return -EINVAL;
407
408 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
409 if (!wr_buf)
410 return -ENOSPC;
411
412 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
413 (long *)param, buf,
414 max_param_num,
415 ¶m_nums)) {
416 kfree(wr_buf);
417 return -EINVAL;
418 }
419
420 if (param_nums <= 0) {
421 kfree(wr_buf);
422 DRM_DEBUG_DRIVER("user data not be read\n");
423 return -EINVAL;
424 }
425
426 switch (param[0]) {
427 case LANE_COUNT_ONE:
428 case LANE_COUNT_TWO:
429 case LANE_COUNT_FOUR:
430 break;
431 default:
432 valid_input = false;
433 break;
434 }
435
436 switch (param[1]) {
437 case LINK_RATE_LOW:
438 case LINK_RATE_HIGH:
439 case LINK_RATE_RBR2:
440 case LINK_RATE_HIGH2:
441 case LINK_RATE_HIGH3:
442 case LINK_RATE_UHBR10:
443 case LINK_RATE_UHBR13_5:
444 case LINK_RATE_UHBR20:
445 break;
446 default:
447 valid_input = false;
448 break;
449 }
450
451 if (!valid_input) {
452 kfree(wr_buf);
453 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
454 mutex_lock(&adev->dm.dc_lock);
455 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
456 mutex_unlock(&adev->dm.dc_lock);
457 return -EINVAL;
458 }
459
460 /* save user force lane_count, link_rate to preferred settings
461 * spread spectrum will not be changed
462 */
463 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
464 prefer_link_settings.use_link_rate_set = false;
465 prefer_link_settings.lane_count = param[0];
466 prefer_link_settings.link_rate = param[1];
467
468 /* skip immediate retrain, and train to new link setting after hotplug event triggered */
469 mutex_lock(&adev->dm.dc_lock);
470 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
471 mutex_unlock(&adev->dm.dc_lock);
472
473 mutex_lock(&aconnector->base.dev->mode_config.mutex);
474 aconnector->base.force = DRM_FORCE_OFF;
475 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
476 drm_kms_helper_hotplug_event(aconnector->base.dev);
477
478 msleep(100);
479
480 mutex_lock(&aconnector->base.dev->mode_config.mutex);
481 aconnector->base.force = DRM_FORCE_UNSPECIFIED;
482 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
483 drm_kms_helper_hotplug_event(aconnector->base.dev);
484
485 kfree(wr_buf);
486 return size;
487 }
488
489 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
490 * post-cursor2 (defined by VESA DP specification)
491 *
492 * valid values
493 * voltage swing: 0,1,2,3
494 * pre-emphasis : 0,1,2,3
495 * post cursor2 : 0,1,2,3
496 *
497 *
498 * how to use this debugfs
499 *
500 * debugfs is located at /sys/kernel/debug/dri/0/DP-x
501 *
502 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
503 *
504 * To figure out which DP-x is the display for DP to be check,
505 * cd DP-x
506 * ls -ll
507 * There should be debugfs file, like link_settings, phy_settings.
508 * cat link_settings
509 * from lane_count, link_rate to figure which DP-x is for display to be worked
510 * on
511 *
512 * To get current DP PHY settings,
513 * cat phy_settings
514 *
515 * To change DP PHY settings,
516 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
517 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
518 * 0,
519 * echo 2 3 0 > phy_settings
520 *
521 * To check if change be applied, get current phy settings by
522 * cat phy_settings
523 *
524 * In case invalid values are set by user, like
525 * echo 1 4 0 > phy_settings
526 *
527 * HW will NOT be programmed by these settings.
528 * cat phy_settings will show the previous valid settings.
529 */
dp_phy_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)530 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
531 size_t size, loff_t *pos)
532 {
533 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
534 struct dc_link *link = connector->dc_link;
535 char *rd_buf = NULL;
536 const uint32_t rd_buf_size = 20;
537 uint32_t result = 0;
538 int r;
539
540 if (*pos & 3 || size & 3)
541 return -EINVAL;
542
543 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
544 if (!rd_buf)
545 return -EINVAL;
546
547 snprintf(rd_buf, rd_buf_size, " %d %d %d\n",
548 link->cur_lane_setting[0].VOLTAGE_SWING,
549 link->cur_lane_setting[0].PRE_EMPHASIS,
550 link->cur_lane_setting[0].POST_CURSOR2);
551
552 while (size) {
553 if (*pos >= rd_buf_size)
554 break;
555
556 r = put_user((*(rd_buf + result)), buf);
557 if (r) {
558 kfree(rd_buf);
559 return r; /* r = -EFAULT */
560 }
561
562 buf += 1;
563 size -= 1;
564 *pos += 1;
565 result += 1;
566 }
567
568 kfree(rd_buf);
569 return result;
570 }
571
dp_lttpr_status_show(struct seq_file * m,void * unused)572 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
573 {
574 struct drm_connector *connector = m->private;
575 struct amdgpu_dm_connector *aconnector =
576 to_amdgpu_dm_connector(connector);
577 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
578
579 if (connector->status != connector_status_connected)
580 return -ENODEV;
581
582 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
583 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
584 caps.phy_repeater_cnt);
585
586 seq_puts(m, "phy repeater mode: ");
587
588 switch (caps.mode) {
589 case DP_PHY_REPEATER_MODE_TRANSPARENT:
590 seq_puts(m, "transparent");
591 break;
592 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
593 seq_puts(m, "non-transparent");
594 break;
595 case 0x00:
596 seq_puts(m, "non lttpr");
597 break;
598 default:
599 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
600 break;
601 }
602
603 seq_puts(m, "\n");
604 return 0;
605 }
606
dp_phy_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)607 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
608 size_t size, loff_t *pos)
609 {
610 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
611 struct dc_link *link = connector->dc_link;
612 struct dc *dc = (struct dc *)link->dc;
613 char *wr_buf = NULL;
614 uint32_t wr_buf_size = 40;
615 long param[3];
616 bool use_prefer_link_setting;
617 struct link_training_settings link_lane_settings = {0};
618 int max_param_num = 3;
619 uint8_t param_nums = 0;
620 int r = 0;
621
622
623 if (size == 0)
624 return -EINVAL;
625
626 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
627 if (!wr_buf)
628 return -ENOSPC;
629
630 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
631 (long *)param, buf,
632 max_param_num,
633 ¶m_nums)) {
634 kfree(wr_buf);
635 return -EINVAL;
636 }
637
638 if (param_nums <= 0) {
639 kfree(wr_buf);
640 DRM_DEBUG_DRIVER("user data not be read\n");
641 return -EINVAL;
642 }
643
644 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
645 (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
646 (param[2] > POST_CURSOR2_MAX_LEVEL)) {
647 kfree(wr_buf);
648 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
649 return size;
650 }
651
652 /* get link settings: lane count, link rate */
653 use_prefer_link_setting =
654 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
655 (link->test_pattern_enabled));
656
657 memset(&link_lane_settings, 0, sizeof(link_lane_settings));
658
659 if (use_prefer_link_setting) {
660 link_lane_settings.link_settings.lane_count =
661 link->preferred_link_setting.lane_count;
662 link_lane_settings.link_settings.link_rate =
663 link->preferred_link_setting.link_rate;
664 link_lane_settings.link_settings.link_spread =
665 link->preferred_link_setting.link_spread;
666 } else {
667 link_lane_settings.link_settings.lane_count =
668 link->cur_link_settings.lane_count;
669 link_lane_settings.link_settings.link_rate =
670 link->cur_link_settings.link_rate;
671 link_lane_settings.link_settings.link_spread =
672 link->cur_link_settings.link_spread;
673 }
674
675 /* apply phy settings from user */
676 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
677 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
678 (enum dc_voltage_swing) (param[0]);
679 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
680 (enum dc_pre_emphasis) (param[1]);
681 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
682 (enum dc_post_cursor2) (param[2]);
683 }
684
685 /* program ASIC registers and DPCD registers */
686 dc_link_set_drive_settings(dc, &link_lane_settings, link);
687
688 kfree(wr_buf);
689 return size;
690 }
691
692 /* function description
693 *
694 * set PHY layer or Link layer test pattern
695 * PHY test pattern is used for PHY SI check.
696 * Link layer test will not affect PHY SI.
697 *
698 * Reset Test Pattern:
699 * 0 = DP_TEST_PATTERN_VIDEO_MODE
700 *
701 * PHY test pattern supported:
702 * 1 = DP_TEST_PATTERN_D102
703 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
704 * 3 = DP_TEST_PATTERN_PRBS7
705 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
706 * 5 = DP_TEST_PATTERN_CP2520_1
707 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
708 * 7 = DP_TEST_PATTERN_CP2520_3
709 *
710 * DP PHY Link Training Patterns
711 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
712 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
713 * a = DP_TEST_PATTERN_TRAINING_PATTERN3
714 * b = DP_TEST_PATTERN_TRAINING_PATTERN4
715 *
716 * DP Link Layer Test pattern
717 * c = DP_TEST_PATTERN_COLOR_SQUARES
718 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
719 * e = DP_TEST_PATTERN_VERTICAL_BARS
720 * f = DP_TEST_PATTERN_HORIZONTAL_BARS
721 * 10= DP_TEST_PATTERN_COLOR_RAMP
722 *
723 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
724 *
725 * --- set test pattern
726 * echo <test pattern #> > test_pattern
727 *
728 * If test pattern # is not supported, NO HW programming will be done.
729 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
730 * for the user pattern. input 10 bytes data are separated by space
731 *
732 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
733 *
734 * --- reset test pattern
735 * echo 0 > test_pattern
736 *
737 * --- HPD detection is disabled when set PHY test pattern
738 *
739 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
740 * is disable. User could unplug DP display from DP connected and plug scope to
741 * check test pattern PHY SI.
742 * If there is need unplug scope and plug DP display back, do steps below:
743 * echo 0 > phy_test_pattern
744 * unplug scope
745 * plug DP display.
746 *
747 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
748 * driver could detect "unplug scope" and "plug DP display"
749 */
dp_phy_test_pattern_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)750 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
751 size_t size, loff_t *pos)
752 {
753 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
754 struct dc_link *link = connector->dc_link;
755 char *wr_buf = NULL;
756 uint32_t wr_buf_size = 100;
757 long param[11] = {0x0};
758 int max_param_num = 11;
759 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
760 bool disable_hpd = false;
761 bool valid_test_pattern = false;
762 uint8_t param_nums = 0;
763 /* init with default 80bit custom pattern */
764 uint8_t custom_pattern[10] = {
765 0x1f, 0x7c, 0xf0, 0xc1, 0x07,
766 0x1f, 0x7c, 0xf0, 0xc1, 0x07
767 };
768 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
769 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
770 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
771 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
772 struct link_training_settings link_training_settings = {0};
773 int i;
774
775 if (size == 0)
776 return -EINVAL;
777
778 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
779 if (!wr_buf)
780 return -ENOSPC;
781
782 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
783 (long *)param, buf,
784 max_param_num,
785 ¶m_nums)) {
786 kfree(wr_buf);
787 return -EINVAL;
788 }
789
790 if (param_nums <= 0) {
791 kfree(wr_buf);
792 DRM_DEBUG_DRIVER("user data not be read\n");
793 return -EINVAL;
794 }
795
796
797 test_pattern = param[0];
798
799 switch (test_pattern) {
800 case DP_TEST_PATTERN_VIDEO_MODE:
801 case DP_TEST_PATTERN_COLOR_SQUARES:
802 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
803 case DP_TEST_PATTERN_VERTICAL_BARS:
804 case DP_TEST_PATTERN_HORIZONTAL_BARS:
805 case DP_TEST_PATTERN_COLOR_RAMP:
806 valid_test_pattern = true;
807 break;
808
809 case DP_TEST_PATTERN_D102:
810 case DP_TEST_PATTERN_SYMBOL_ERROR:
811 case DP_TEST_PATTERN_PRBS7:
812 case DP_TEST_PATTERN_80BIT_CUSTOM:
813 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
814 case DP_TEST_PATTERN_TRAINING_PATTERN4:
815 disable_hpd = true;
816 valid_test_pattern = true;
817 break;
818
819 default:
820 valid_test_pattern = false;
821 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
822 break;
823 }
824
825 if (!valid_test_pattern) {
826 kfree(wr_buf);
827 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
828 return size;
829 }
830
831 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
832 for (i = 0; i < 10; i++) {
833 if ((uint8_t) param[i + 1] != 0x0)
834 break;
835 }
836
837 if (i < 10) {
838 /* not use default value */
839 for (i = 0; i < 10; i++)
840 custom_pattern[i] = (uint8_t) param[i + 1];
841 }
842 }
843
844 /* Usage: set DP physical test pattern using debugfs with normal DP
845 * panel. Then plug out DP panel and connect a scope to measure
846 * For normal video mode and test pattern generated from CRCT,
847 * they are visibile to user. So do not disable HPD.
848 * Video Mode is also set to clear the test pattern, so enable HPD
849 * because it might have been disabled after a test pattern was set.
850 * AUX depends on HPD * sequence dependent, do not move!
851 */
852 if (!disable_hpd)
853 dc_link_enable_hpd(link);
854
855 prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
856 prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
857 prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
858
859 cur_link_settings.lane_count = link->cur_link_settings.lane_count;
860 cur_link_settings.link_rate = link->cur_link_settings.link_rate;
861 cur_link_settings.link_spread = link->cur_link_settings.link_spread;
862
863 link_training_settings.link_settings = cur_link_settings;
864
865
866 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
867 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
868 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN &&
869 (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
870 prefer_link_settings.link_rate != cur_link_settings.link_rate))
871 link_training_settings.link_settings = prefer_link_settings;
872 }
873
874 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
875 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
876
877 dc_link_dp_set_test_pattern(
878 link,
879 test_pattern,
880 DP_TEST_PATTERN_COLOR_SPACE_RGB,
881 &link_training_settings,
882 custom_pattern,
883 10);
884
885 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
886 * Then plug out DP panel and connect a scope to measure DP PHY signal.
887 * Need disable interrupt to avoid SW driver disable DP output. This is
888 * done after the test pattern is set.
889 */
890 if (valid_test_pattern && disable_hpd)
891 dc_link_disable_hpd(link);
892
893 kfree(wr_buf);
894
895 return size;
896 }
897
898 /*
899 * Returns the DMCUB tracebuffer contents.
900 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
901 */
dmub_tracebuffer_show(struct seq_file * m,void * data)902 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
903 {
904 struct amdgpu_device *adev = m->private;
905 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
906 struct dmub_fw_meta_info *fw_meta_info = NULL;
907 struct dmub_debugfs_trace_entry *entries;
908 uint8_t *tbuf_base;
909 uint32_t tbuf_size, max_entries, num_entries, first_entry, i;
910
911 if (!fb_info)
912 return 0;
913
914 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
915 if (!tbuf_base)
916 return 0;
917
918 if (adev->dm.dmub_srv)
919 fw_meta_info = &adev->dm.dmub_srv->meta_info;
920
921 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size :
922 DMUB_TRACE_BUFFER_SIZE;
923 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
924 sizeof(struct dmub_debugfs_trace_entry);
925
926 num_entries =
927 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
928
929 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that
930 * entries are being overwritten.
931 */
932 if (num_entries > max_entries)
933 seq_printf(m, "...\n");
934
935 first_entry = num_entries % max_entries;
936 num_entries = min(num_entries, max_entries);
937
938 entries = (struct dmub_debugfs_trace_entry
939 *)(tbuf_base +
940 sizeof(struct dmub_debugfs_trace_header));
941
942 /* To print entries chronologically, start from the first entry till the
943 * top of buffer, then from base of buffer to first entry.
944 */
945 for (i = first_entry; i < num_entries; ++i) {
946 struct dmub_debugfs_trace_entry *entry = &entries[i];
947
948 seq_printf(m,
949 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
950 entry->trace_code, entry->tick_count, entry->param0,
951 entry->param1);
952 }
953 for (i = 0; i < first_entry; ++i) {
954 struct dmub_debugfs_trace_entry *entry = &entries[i];
955
956 seq_printf(m,
957 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
958 entry->trace_code, entry->tick_count, entry->param0,
959 entry->param1);
960 }
961
962 return 0;
963 }
964
965 /*
966 * Returns the DMCUB firmware state contents.
967 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
968 */
dmub_fw_state_show(struct seq_file * m,void * data)969 static int dmub_fw_state_show(struct seq_file *m, void *data)
970 {
971 struct amdgpu_device *adev = m->private;
972 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
973 uint8_t *state_base;
974 uint32_t state_size;
975
976 if (!fb_info)
977 return 0;
978
979 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
980 if (!state_base)
981 return 0;
982
983 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
984
985 return seq_write(m, state_base, state_size);
986 }
987
988 /* replay_capability_show() - show eDP panel replay capability
989 *
990 * The read function: replay_capability_show
991 * Shows if sink and driver has Replay capability or not.
992 *
993 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability
994 *
995 * Expected output:
996 * "Sink support: no\n" - if panel doesn't support Replay
997 * "Sink support: yes\n" - if panel supports Replay
998 * "Driver support: no\n" - if driver doesn't support Replay
999 * "Driver support: yes\n" - if driver supports Replay
1000 */
replay_capability_show(struct seq_file * m,void * data)1001 static int replay_capability_show(struct seq_file *m, void *data)
1002 {
1003 struct drm_connector *connector = m->private;
1004 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1005 struct dc_link *link = aconnector->dc_link;
1006 bool sink_support_replay = false;
1007 bool driver_support_replay = false;
1008
1009 if (!link)
1010 return -ENODEV;
1011
1012 if (link->type == dc_connection_none)
1013 return -ENODEV;
1014
1015 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1016 return -ENODEV;
1017
1018 /* If Replay is already set to support, skip the checks */
1019 if (link->replay_settings.config.replay_supported) {
1020 sink_support_replay = true;
1021 driver_support_replay = true;
1022 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
1023 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1024 } else {
1025 struct dc *dc = link->ctx->dc;
1026
1027 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1028 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
1029 driver_support_replay =
1030 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
1031 }
1032
1033 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
1034 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));
1035 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));
1036
1037 return 0;
1038 }
1039
1040 /* psr_capability_show() - show eDP panel PSR capability
1041 *
1042 * The read function: sink_psr_capability_show
1043 * Shows if sink has PSR capability or not.
1044 * If yes - the PSR version is appended
1045 *
1046 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
1047 *
1048 * Expected output:
1049 * "Sink support: no\n" - if panel doesn't support PSR
1050 * "Sink support: yes [0x01]\n" - if panel supports PSR1
1051 * "Driver support: no\n" - if driver doesn't support PSR
1052 * "Driver support: yes [0x01]\n" - if driver supports PSR1
1053 */
psr_capability_show(struct seq_file * m,void * data)1054 static int psr_capability_show(struct seq_file *m, void *data)
1055 {
1056 struct drm_connector *connector = m->private;
1057 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1058 struct dc_link *link = aconnector->dc_link;
1059
1060 if (!link)
1061 return -ENODEV;
1062
1063 if (link->type == dc_connection_none)
1064 return -ENODEV;
1065
1066 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1067 return -ENODEV;
1068
1069 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
1070 if (link->dpcd_caps.psr_info.psr_version)
1071 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
1072 seq_puts(m, "\n");
1073
1074 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
1075 if (link->psr_settings.psr_version)
1076 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
1077 seq_puts(m, "\n");
1078
1079 return 0;
1080 }
1081
1082 /*
1083 * Returns the current bpc for the crtc.
1084 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1085 */
amdgpu_current_bpc_show(struct seq_file * m,void * data)1086 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1087 {
1088 struct drm_crtc *crtc = m->private;
1089 struct drm_device *dev = crtc->dev;
1090 struct dm_crtc_state *dm_crtc_state = NULL;
1091 int res = -ENODEV;
1092 unsigned int bpc;
1093
1094 mutex_lock(&dev->mode_config.mutex);
1095 drm_modeset_lock(&crtc->mutex, NULL);
1096 if (crtc->state == NULL)
1097 goto unlock;
1098
1099 dm_crtc_state = to_dm_crtc_state(crtc->state);
1100 if (dm_crtc_state->stream == NULL)
1101 goto unlock;
1102
1103 switch (dm_crtc_state->stream->timing.display_color_depth) {
1104 case COLOR_DEPTH_666:
1105 bpc = 6;
1106 break;
1107 case COLOR_DEPTH_888:
1108 bpc = 8;
1109 break;
1110 case COLOR_DEPTH_101010:
1111 bpc = 10;
1112 break;
1113 case COLOR_DEPTH_121212:
1114 bpc = 12;
1115 break;
1116 case COLOR_DEPTH_161616:
1117 bpc = 16;
1118 break;
1119 default:
1120 goto unlock;
1121 }
1122
1123 seq_printf(m, "Current: %u\n", bpc);
1124 res = 0;
1125
1126 unlock:
1127 drm_modeset_unlock(&crtc->mutex);
1128 mutex_unlock(&dev->mode_config.mutex);
1129
1130 return res;
1131 }
1132 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1133
1134 /*
1135 * Returns the current colorspace for the crtc.
1136 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1137 */
amdgpu_current_colorspace_show(struct seq_file * m,void * data)1138 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1139 {
1140 struct drm_crtc *crtc = m->private;
1141 struct drm_device *dev = crtc->dev;
1142 struct dm_crtc_state *dm_crtc_state = NULL;
1143 int res = -ENODEV;
1144
1145 mutex_lock(&dev->mode_config.mutex);
1146 drm_modeset_lock(&crtc->mutex, NULL);
1147 if (crtc->state == NULL)
1148 goto unlock;
1149
1150 dm_crtc_state = to_dm_crtc_state(crtc->state);
1151 if (dm_crtc_state->stream == NULL)
1152 goto unlock;
1153
1154 switch (dm_crtc_state->stream->output_color_space) {
1155 case COLOR_SPACE_SRGB:
1156 seq_puts(m, "sRGB");
1157 break;
1158 case COLOR_SPACE_YCBCR601:
1159 case COLOR_SPACE_YCBCR601_LIMITED:
1160 seq_puts(m, "BT601_YCC");
1161 break;
1162 case COLOR_SPACE_YCBCR709:
1163 case COLOR_SPACE_YCBCR709_LIMITED:
1164 seq_puts(m, "BT709_YCC");
1165 break;
1166 case COLOR_SPACE_ADOBERGB:
1167 seq_puts(m, "opRGB");
1168 break;
1169 case COLOR_SPACE_2020_RGB_FULLRANGE:
1170 seq_puts(m, "BT2020_RGB");
1171 break;
1172 case COLOR_SPACE_2020_YCBCR:
1173 seq_puts(m, "BT2020_YCC");
1174 break;
1175 default:
1176 goto unlock;
1177 }
1178 res = 0;
1179
1180 unlock:
1181 drm_modeset_unlock(&crtc->mutex);
1182 mutex_unlock(&dev->mode_config.mutex);
1183
1184 return res;
1185 }
1186 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1187
1188
1189 /*
1190 * Example usage:
1191 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1192 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1193 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1194 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1195 */
dp_dsc_passthrough_set(struct file * f,const char __user * buf,size_t size,loff_t * pos)1196 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1197 size_t size, loff_t *pos)
1198 {
1199 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1200 char *wr_buf = NULL;
1201 uint32_t wr_buf_size = 42;
1202 int max_param_num = 1;
1203 long param;
1204 uint8_t param_nums = 0;
1205
1206 if (size == 0)
1207 return -EINVAL;
1208
1209 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1210
1211 if (!wr_buf) {
1212 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1213 return -ENOSPC;
1214 }
1215
1216 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1217 ¶m, buf,
1218 max_param_num,
1219 ¶m_nums)) {
1220 kfree(wr_buf);
1221 return -EINVAL;
1222 }
1223
1224 aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1225
1226 kfree(wr_buf);
1227 return 0;
1228 }
1229
1230 /*
1231 * Returns the HDCP capability of the Display (1.4 for now).
1232 *
1233 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1234 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1235 *
1236 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1237 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1238 */
hdcp_sink_capability_show(struct seq_file * m,void * data)1239 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1240 {
1241 struct drm_connector *connector = m->private;
1242 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1243 bool hdcp_cap, hdcp2_cap;
1244
1245 if (connector->status != connector_status_connected)
1246 return -ENODEV;
1247
1248 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1249
1250 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1251 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1252
1253
1254 if (hdcp_cap)
1255 seq_printf(m, "%s ", "HDCP1.4");
1256 if (hdcp2_cap)
1257 seq_printf(m, "%s ", "HDCP2.2");
1258
1259 if (!hdcp_cap && !hdcp2_cap)
1260 seq_printf(m, "%s ", "None");
1261
1262 seq_puts(m, "\n");
1263
1264 return 0;
1265 }
1266
1267 /*
1268 * Returns whether the connected display is internal and not hotpluggable.
1269 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1270 */
internal_display_show(struct seq_file * m,void * data)1271 static int internal_display_show(struct seq_file *m, void *data)
1272 {
1273 struct drm_connector *connector = m->private;
1274 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1275 struct dc_link *link = aconnector->dc_link;
1276
1277 seq_printf(m, "Internal: %u\n", link->is_internal_display);
1278
1279 return 0;
1280 }
1281
1282 /*
1283 * Returns the number of segments used if ODM Combine mode is enabled.
1284 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1285 */
odm_combine_segments_show(struct seq_file * m,void * unused)1286 static int odm_combine_segments_show(struct seq_file *m, void *unused)
1287 {
1288 struct drm_connector *connector = m->private;
1289 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1290 struct dc_link *link = aconnector->dc_link;
1291 struct pipe_ctx *pipe_ctx = NULL;
1292 int i, segments = -EOPNOTSUPP;
1293
1294 for (i = 0; i < MAX_PIPES; i++) {
1295 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1296 if (pipe_ctx->stream &&
1297 pipe_ctx->stream->link == link)
1298 break;
1299 }
1300
1301 if (connector->status != connector_status_connected)
1302 return -ENODEV;
1303
1304 if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1305 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1306
1307 seq_printf(m, "%d\n", segments);
1308 return 0;
1309 }
1310
1311 /* function description
1312 *
1313 * generic SDP message access for testing
1314 *
1315 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1316 *
1317 * SDP header
1318 * Hb0 : Secondary-Data Packet ID
1319 * Hb1 : Secondary-Data Packet type
1320 * Hb2 : Secondary-Data-packet-specific header, Byte 0
1321 * Hb3 : Secondary-Data-packet-specific header, Byte 1
1322 *
1323 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1324 */
dp_sdp_message_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1325 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1326 size_t size, loff_t *pos)
1327 {
1328 int r;
1329 uint8_t data[36] = {0};
1330 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1331 struct dm_crtc_state *acrtc_state;
1332 uint32_t write_size = 36;
1333
1334 if (connector->base.status != connector_status_connected)
1335 return -ENODEV;
1336
1337 if (size == 0)
1338 return 0;
1339
1340 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1341
1342 r = copy_from_user(data, buf, write_size);
1343
1344 write_size -= r;
1345
1346 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1347
1348 return write_size;
1349 }
1350
1351 /* function: Read link's DSC & FEC capabilities
1352 *
1353 *
1354 * Access it with the following command (you need to specify
1355 * connector like DP-1):
1356 *
1357 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1358 *
1359 */
dp_dsc_fec_support_show(struct seq_file * m,void * data)1360 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1361 {
1362 struct drm_connector *connector = m->private;
1363 struct drm_modeset_acquire_ctx ctx;
1364 struct drm_device *dev = connector->dev;
1365 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1366 int ret = 0;
1367 bool try_again = false;
1368 bool is_fec_supported = false;
1369 bool is_dsc_supported = false;
1370 struct dpcd_caps dpcd_caps;
1371
1372 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1373 do {
1374 try_again = false;
1375 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1376 if (ret) {
1377 if (ret == -EDEADLK) {
1378 ret = drm_modeset_backoff(&ctx);
1379 if (!ret) {
1380 try_again = true;
1381 continue;
1382 }
1383 }
1384 break;
1385 }
1386 if (connector->status != connector_status_connected) {
1387 ret = -ENODEV;
1388 break;
1389 }
1390 dpcd_caps = aconnector->dc_link->dpcd_caps;
1391 if (aconnector->mst_output_port) {
1392 /* aconnector sets dsc_aux during get_modes call
1393 * if MST connector has it means it can either
1394 * enable DSC on the sink device or on MST branch
1395 * its connected to.
1396 */
1397 if (aconnector->dsc_aux) {
1398 is_fec_supported = true;
1399 is_dsc_supported = true;
1400 }
1401 } else {
1402 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1403 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1404 }
1405 } while (try_again);
1406
1407 drm_modeset_drop_locks(&ctx);
1408 drm_modeset_acquire_fini(&ctx);
1409
1410 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1411 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1412
1413 return ret;
1414 }
1415
1416 /* function: Trigger virtual HPD redetection on connector
1417 *
1418 * This function will perform link rediscovery, link disable
1419 * and enable, and dm connector state update.
1420 *
1421 * Retrigger HPD on an existing connector by echoing 1 into
1422 * its respectful "trigger_hotplug" debugfs entry:
1423 *
1424 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1425 *
1426 * This function can perform HPD unplug:
1427 *
1428 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1429 *
1430 */
trigger_hotplug(struct file * f,const char __user * buf,size_t size,loff_t * pos)1431 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1432 size_t size, loff_t *pos)
1433 {
1434 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1435 struct drm_connector *connector = &aconnector->base;
1436 struct dc_link *link = NULL;
1437 struct drm_device *dev = connector->dev;
1438 struct amdgpu_device *adev = drm_to_adev(dev);
1439 enum dc_connection_type new_connection_type = dc_connection_none;
1440 char *wr_buf = NULL;
1441 uint32_t wr_buf_size = 42;
1442 int max_param_num = 1;
1443 long param[1] = {0};
1444 uint8_t param_nums = 0;
1445 bool ret = false;
1446
1447 if (!aconnector->dc_link)
1448 return -EINVAL;
1449
1450 if (size == 0)
1451 return -EINVAL;
1452
1453 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1454
1455 if (!wr_buf) {
1456 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1457 return -ENOSPC;
1458 }
1459
1460 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1461 (long *)param, buf,
1462 max_param_num,
1463 ¶m_nums)) {
1464 kfree(wr_buf);
1465 return -EINVAL;
1466 }
1467
1468 kfree(wr_buf);
1469
1470 if (param_nums <= 0) {
1471 DRM_DEBUG_DRIVER("user data not be read\n");
1472 return -EINVAL;
1473 }
1474
1475 mutex_lock(&aconnector->hpd_lock);
1476
1477 /* Don't support for mst end device*/
1478 if (aconnector->mst_root) {
1479 mutex_unlock(&aconnector->hpd_lock);
1480 return -EINVAL;
1481 }
1482
1483 if (param[0] == 1) {
1484
1485 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1486 new_connection_type != dc_connection_none)
1487 goto unlock;
1488
1489 mutex_lock(&adev->dm.dc_lock);
1490 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1491 mutex_unlock(&adev->dm.dc_lock);
1492
1493 if (!ret)
1494 goto unlock;
1495
1496 amdgpu_dm_update_connector_after_detect(aconnector);
1497
1498 drm_modeset_lock_all(dev);
1499 dm_restore_drm_connector_state(dev, connector);
1500 drm_modeset_unlock_all(dev);
1501
1502 drm_kms_helper_connector_hotplug_event(connector);
1503 } else if (param[0] == 0) {
1504 if (!aconnector->dc_link)
1505 goto unlock;
1506
1507 link = aconnector->dc_link;
1508
1509 if (link->local_sink) {
1510 dc_sink_release(link->local_sink);
1511 link->local_sink = NULL;
1512 }
1513
1514 link->dpcd_sink_count = 0;
1515 link->type = dc_connection_none;
1516 link->dongle_max_pix_clk = 0;
1517
1518 amdgpu_dm_update_connector_after_detect(aconnector);
1519
1520 /* If the aconnector is the root node in mst topology */
1521 if (aconnector->mst_mgr.mst_state == true)
1522 dc_link_reset_cur_dp_mst_topology(link);
1523
1524 drm_modeset_lock_all(dev);
1525 dm_restore_drm_connector_state(dev, connector);
1526 drm_modeset_unlock_all(dev);
1527
1528 drm_kms_helper_connector_hotplug_event(connector);
1529 }
1530
1531 unlock:
1532 mutex_unlock(&aconnector->hpd_lock);
1533
1534 return size;
1535 }
1536
1537 /* function: read DSC status on the connector
1538 *
1539 * The read function: dp_dsc_clock_en_read
1540 * returns current status of DSC clock on the connector.
1541 * The return is a boolean flag: 1 or 0.
1542 *
1543 * Access it with the following command (you need to specify
1544 * connector like DP-1):
1545 *
1546 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1547 *
1548 * Expected output:
1549 * 1 - means that DSC is currently enabled
1550 * 0 - means that DSC is disabled
1551 */
dp_dsc_clock_en_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1552 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1553 size_t size, loff_t *pos)
1554 {
1555 char *rd_buf = NULL;
1556 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1557 struct display_stream_compressor *dsc;
1558 struct dcn_dsc_state dsc_state = {0};
1559 const uint32_t rd_buf_size = 10;
1560 struct pipe_ctx *pipe_ctx;
1561 ssize_t result = 0;
1562 int i, r, str_len = 10;
1563
1564 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1565
1566 if (!rd_buf)
1567 return -ENOMEM;
1568
1569 for (i = 0; i < MAX_PIPES; i++) {
1570 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1571 if (pipe_ctx->stream &&
1572 pipe_ctx->stream->link == aconnector->dc_link &&
1573 pipe_ctx->stream->sink &&
1574 pipe_ctx->stream->sink == aconnector->dc_sink)
1575 break;
1576 }
1577
1578 dsc = pipe_ctx->stream_res.dsc;
1579 if (dsc)
1580 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1581
1582 snprintf(rd_buf, str_len,
1583 "%d\n",
1584 dsc_state.dsc_clock_en);
1585
1586 while (size) {
1587 if (*pos >= rd_buf_size)
1588 break;
1589
1590 r = put_user(*(rd_buf + result), buf);
1591 if (r) {
1592 kfree(rd_buf);
1593 return r; /* r = -EFAULT */
1594 }
1595
1596 buf += 1;
1597 size -= 1;
1598 *pos += 1;
1599 result += 1;
1600 }
1601
1602 kfree(rd_buf);
1603 return result;
1604 }
1605
1606 /* function: write force DSC on the connector
1607 *
1608 * The write function: dp_dsc_clock_en_write
1609 * enables to force DSC on the connector.
1610 * User can write to either force enable or force disable DSC
1611 * on the next modeset or set it to driver default
1612 *
1613 * Accepted inputs:
1614 * 0 - default DSC enablement policy
1615 * 1 - force enable DSC on the connector
1616 * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1617 *
1618 * Writing DSC settings is done with the following command:
1619 * - To force enable DSC (you need to specify
1620 * connector like DP-1):
1621 *
1622 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1623 *
1624 * - To return to default state set the flag to zero and
1625 * let driver deal with DSC automatically
1626 * (you need to specify connector like DP-1):
1627 *
1628 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1629 *
1630 */
dp_dsc_clock_en_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1631 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1632 size_t size, loff_t *pos)
1633 {
1634 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1635 struct drm_connector *connector = &aconnector->base;
1636 struct drm_device *dev = connector->dev;
1637 struct drm_crtc *crtc = NULL;
1638 struct dm_crtc_state *dm_crtc_state = NULL;
1639 struct pipe_ctx *pipe_ctx;
1640 int i;
1641 char *wr_buf = NULL;
1642 uint32_t wr_buf_size = 42;
1643 int max_param_num = 1;
1644 long param[1] = {0};
1645 uint8_t param_nums = 0;
1646
1647 if (size == 0)
1648 return -EINVAL;
1649
1650 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1651
1652 if (!wr_buf) {
1653 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1654 return -ENOSPC;
1655 }
1656
1657 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1658 (long *)param, buf,
1659 max_param_num,
1660 ¶m_nums)) {
1661 kfree(wr_buf);
1662 return -EINVAL;
1663 }
1664
1665 if (param_nums <= 0) {
1666 DRM_DEBUG_DRIVER("user data not be read\n");
1667 kfree(wr_buf);
1668 return -EINVAL;
1669 }
1670
1671 for (i = 0; i < MAX_PIPES; i++) {
1672 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1673 if (pipe_ctx->stream &&
1674 pipe_ctx->stream->link == aconnector->dc_link &&
1675 pipe_ctx->stream->sink &&
1676 pipe_ctx->stream->sink == aconnector->dc_sink)
1677 break;
1678 }
1679
1680 if (!pipe_ctx->stream)
1681 goto done;
1682
1683 // Get CRTC state
1684 mutex_lock(&dev->mode_config.mutex);
1685 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1686
1687 if (connector->state == NULL)
1688 goto unlock;
1689
1690 crtc = connector->state->crtc;
1691 if (crtc == NULL)
1692 goto unlock;
1693
1694 drm_modeset_lock(&crtc->mutex, NULL);
1695 if (crtc->state == NULL)
1696 goto unlock;
1697
1698 dm_crtc_state = to_dm_crtc_state(crtc->state);
1699 if (dm_crtc_state->stream == NULL)
1700 goto unlock;
1701
1702 if (param[0] == 1)
1703 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1704 else if (param[0] == 2)
1705 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1706 else
1707 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1708
1709 dm_crtc_state->dsc_force_changed = true;
1710
1711 unlock:
1712 if (crtc)
1713 drm_modeset_unlock(&crtc->mutex);
1714 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1715 mutex_unlock(&dev->mode_config.mutex);
1716
1717 done:
1718 kfree(wr_buf);
1719 return size;
1720 }
1721
1722 /* function: read DSC slice width parameter on the connector
1723 *
1724 * The read function: dp_dsc_slice_width_read
1725 * returns dsc slice width used in the current configuration
1726 * The return is an integer: 0 or other positive number
1727 *
1728 * Access the status with the following command:
1729 *
1730 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1731 *
1732 * 0 - means that DSC is disabled
1733 *
1734 * Any other number more than zero represents the
1735 * slice width currently used by DSC in pixels
1736 *
1737 */
dp_dsc_slice_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1738 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1739 size_t size, loff_t *pos)
1740 {
1741 char *rd_buf = NULL;
1742 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1743 struct display_stream_compressor *dsc;
1744 struct dcn_dsc_state dsc_state = {0};
1745 const uint32_t rd_buf_size = 100;
1746 struct pipe_ctx *pipe_ctx;
1747 ssize_t result = 0;
1748 int i, r, str_len = 30;
1749
1750 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1751
1752 if (!rd_buf)
1753 return -ENOMEM;
1754
1755 for (i = 0; i < MAX_PIPES; i++) {
1756 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1757 if (pipe_ctx->stream &&
1758 pipe_ctx->stream->link == aconnector->dc_link &&
1759 pipe_ctx->stream->sink &&
1760 pipe_ctx->stream->sink == aconnector->dc_sink)
1761 break;
1762 }
1763
1764 dsc = pipe_ctx->stream_res.dsc;
1765 if (dsc)
1766 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1767
1768 snprintf(rd_buf, str_len,
1769 "%d\n",
1770 dsc_state.dsc_slice_width);
1771
1772 while (size) {
1773 if (*pos >= rd_buf_size)
1774 break;
1775
1776 r = put_user(*(rd_buf + result), buf);
1777 if (r) {
1778 kfree(rd_buf);
1779 return r; /* r = -EFAULT */
1780 }
1781
1782 buf += 1;
1783 size -= 1;
1784 *pos += 1;
1785 result += 1;
1786 }
1787
1788 kfree(rd_buf);
1789 return result;
1790 }
1791
1792 /* function: write DSC slice width parameter
1793 *
1794 * The write function: dp_dsc_slice_width_write
1795 * overwrites automatically generated DSC configuration
1796 * of slice width.
1797 *
1798 * The user has to write the slice width divisible by the
1799 * picture width.
1800 *
1801 * Also the user has to write width in hexidecimal
1802 * rather than in decimal.
1803 *
1804 * Writing DSC settings is done with the following command:
1805 * - To force overwrite slice width: (example sets to 1920 pixels)
1806 *
1807 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1808 *
1809 * - To stop overwriting and let driver find the optimal size,
1810 * set the width to zero:
1811 *
1812 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1813 *
1814 */
dp_dsc_slice_width_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1815 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1816 size_t size, loff_t *pos)
1817 {
1818 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1819 struct pipe_ctx *pipe_ctx;
1820 struct drm_connector *connector = &aconnector->base;
1821 struct drm_device *dev = connector->dev;
1822 struct drm_crtc *crtc = NULL;
1823 struct dm_crtc_state *dm_crtc_state = NULL;
1824 int i;
1825 char *wr_buf = NULL;
1826 uint32_t wr_buf_size = 42;
1827 int max_param_num = 1;
1828 long param[1] = {0};
1829 uint8_t param_nums = 0;
1830
1831 if (size == 0)
1832 return -EINVAL;
1833
1834 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1835
1836 if (!wr_buf) {
1837 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1838 return -ENOSPC;
1839 }
1840
1841 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1842 (long *)param, buf,
1843 max_param_num,
1844 ¶m_nums)) {
1845 kfree(wr_buf);
1846 return -EINVAL;
1847 }
1848
1849 if (param_nums <= 0) {
1850 DRM_DEBUG_DRIVER("user data not be read\n");
1851 kfree(wr_buf);
1852 return -EINVAL;
1853 }
1854
1855 for (i = 0; i < MAX_PIPES; i++) {
1856 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1857 if (pipe_ctx->stream &&
1858 pipe_ctx->stream->link == aconnector->dc_link &&
1859 pipe_ctx->stream->sink &&
1860 pipe_ctx->stream->sink == aconnector->dc_sink)
1861 break;
1862 }
1863
1864 if (!pipe_ctx->stream)
1865 goto done;
1866
1867 // Safely get CRTC state
1868 mutex_lock(&dev->mode_config.mutex);
1869 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1870
1871 if (connector->state == NULL)
1872 goto unlock;
1873
1874 crtc = connector->state->crtc;
1875 if (crtc == NULL)
1876 goto unlock;
1877
1878 drm_modeset_lock(&crtc->mutex, NULL);
1879 if (crtc->state == NULL)
1880 goto unlock;
1881
1882 dm_crtc_state = to_dm_crtc_state(crtc->state);
1883 if (dm_crtc_state->stream == NULL)
1884 goto unlock;
1885
1886 if (param[0] > 0)
1887 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1888 pipe_ctx->stream->timing.h_addressable,
1889 param[0]);
1890 else
1891 aconnector->dsc_settings.dsc_num_slices_h = 0;
1892
1893 dm_crtc_state->dsc_force_changed = true;
1894
1895 unlock:
1896 if (crtc)
1897 drm_modeset_unlock(&crtc->mutex);
1898 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1899 mutex_unlock(&dev->mode_config.mutex);
1900
1901 done:
1902 kfree(wr_buf);
1903 return size;
1904 }
1905
1906 /* function: read DSC slice height parameter on the connector
1907 *
1908 * The read function: dp_dsc_slice_height_read
1909 * returns dsc slice height used in the current configuration
1910 * The return is an integer: 0 or other positive number
1911 *
1912 * Access the status with the following command:
1913 *
1914 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1915 *
1916 * 0 - means that DSC is disabled
1917 *
1918 * Any other number more than zero represents the
1919 * slice height currently used by DSC in pixels
1920 *
1921 */
dp_dsc_slice_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1922 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1923 size_t size, loff_t *pos)
1924 {
1925 char *rd_buf = NULL;
1926 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1927 struct display_stream_compressor *dsc;
1928 struct dcn_dsc_state dsc_state = {0};
1929 const uint32_t rd_buf_size = 100;
1930 struct pipe_ctx *pipe_ctx;
1931 ssize_t result = 0;
1932 int i, r, str_len = 30;
1933
1934 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1935
1936 if (!rd_buf)
1937 return -ENOMEM;
1938
1939 for (i = 0; i < MAX_PIPES; i++) {
1940 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1941 if (pipe_ctx->stream &&
1942 pipe_ctx->stream->link == aconnector->dc_link &&
1943 pipe_ctx->stream->sink &&
1944 pipe_ctx->stream->sink == aconnector->dc_sink)
1945 break;
1946 }
1947
1948 dsc = pipe_ctx->stream_res.dsc;
1949 if (dsc)
1950 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1951
1952 snprintf(rd_buf, str_len,
1953 "%d\n",
1954 dsc_state.dsc_slice_height);
1955
1956 while (size) {
1957 if (*pos >= rd_buf_size)
1958 break;
1959
1960 r = put_user(*(rd_buf + result), buf);
1961 if (r) {
1962 kfree(rd_buf);
1963 return r; /* r = -EFAULT */
1964 }
1965
1966 buf += 1;
1967 size -= 1;
1968 *pos += 1;
1969 result += 1;
1970 }
1971
1972 kfree(rd_buf);
1973 return result;
1974 }
1975
1976 /* function: write DSC slice height parameter
1977 *
1978 * The write function: dp_dsc_slice_height_write
1979 * overwrites automatically generated DSC configuration
1980 * of slice height.
1981 *
1982 * The user has to write the slice height divisible by the
1983 * picture height.
1984 *
1985 * Also the user has to write height in hexidecimal
1986 * rather than in decimal.
1987 *
1988 * Writing DSC settings is done with the following command:
1989 * - To force overwrite slice height (example sets to 128 pixels):
1990 *
1991 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1992 *
1993 * - To stop overwriting and let driver find the optimal size,
1994 * set the height to zero:
1995 *
1996 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1997 *
1998 */
dp_dsc_slice_height_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1999 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
2000 size_t size, loff_t *pos)
2001 {
2002 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2003 struct drm_connector *connector = &aconnector->base;
2004 struct drm_device *dev = connector->dev;
2005 struct drm_crtc *crtc = NULL;
2006 struct dm_crtc_state *dm_crtc_state = NULL;
2007 struct pipe_ctx *pipe_ctx;
2008 int i;
2009 char *wr_buf = NULL;
2010 uint32_t wr_buf_size = 42;
2011 int max_param_num = 1;
2012 uint8_t param_nums = 0;
2013 long param[1] = {0};
2014
2015 if (size == 0)
2016 return -EINVAL;
2017
2018 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2019
2020 if (!wr_buf) {
2021 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2022 return -ENOSPC;
2023 }
2024
2025 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2026 (long *)param, buf,
2027 max_param_num,
2028 ¶m_nums)) {
2029 kfree(wr_buf);
2030 return -EINVAL;
2031 }
2032
2033 if (param_nums <= 0) {
2034 DRM_DEBUG_DRIVER("user data not be read\n");
2035 kfree(wr_buf);
2036 return -EINVAL;
2037 }
2038
2039 for (i = 0; i < MAX_PIPES; i++) {
2040 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2041 if (pipe_ctx->stream &&
2042 pipe_ctx->stream->link == aconnector->dc_link &&
2043 pipe_ctx->stream->sink &&
2044 pipe_ctx->stream->sink == aconnector->dc_sink)
2045 break;
2046 }
2047
2048 if (!pipe_ctx->stream)
2049 goto done;
2050
2051 // Get CRTC state
2052 mutex_lock(&dev->mode_config.mutex);
2053 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2054
2055 if (connector->state == NULL)
2056 goto unlock;
2057
2058 crtc = connector->state->crtc;
2059 if (crtc == NULL)
2060 goto unlock;
2061
2062 drm_modeset_lock(&crtc->mutex, NULL);
2063 if (crtc->state == NULL)
2064 goto unlock;
2065
2066 dm_crtc_state = to_dm_crtc_state(crtc->state);
2067 if (dm_crtc_state->stream == NULL)
2068 goto unlock;
2069
2070 if (param[0] > 0)
2071 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2072 pipe_ctx->stream->timing.v_addressable,
2073 param[0]);
2074 else
2075 aconnector->dsc_settings.dsc_num_slices_v = 0;
2076
2077 dm_crtc_state->dsc_force_changed = true;
2078
2079 unlock:
2080 if (crtc)
2081 drm_modeset_unlock(&crtc->mutex);
2082 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2083 mutex_unlock(&dev->mode_config.mutex);
2084
2085 done:
2086 kfree(wr_buf);
2087 return size;
2088 }
2089
2090 /* function: read DSC target rate on the connector in bits per pixel
2091 *
2092 * The read function: dp_dsc_bits_per_pixel_read
2093 * returns target rate of compression in bits per pixel
2094 * The return is an integer: 0 or other positive integer
2095 *
2096 * Access it with the following command:
2097 *
2098 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2099 *
2100 * 0 - means that DSC is disabled
2101 */
dp_dsc_bits_per_pixel_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2102 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2103 size_t size, loff_t *pos)
2104 {
2105 char *rd_buf = NULL;
2106 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2107 struct display_stream_compressor *dsc;
2108 struct dcn_dsc_state dsc_state = {0};
2109 const uint32_t rd_buf_size = 100;
2110 struct pipe_ctx *pipe_ctx;
2111 ssize_t result = 0;
2112 int i, r, str_len = 30;
2113
2114 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2115
2116 if (!rd_buf)
2117 return -ENOMEM;
2118
2119 for (i = 0; i < MAX_PIPES; i++) {
2120 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2121 if (pipe_ctx->stream &&
2122 pipe_ctx->stream->link == aconnector->dc_link &&
2123 pipe_ctx->stream->sink &&
2124 pipe_ctx->stream->sink == aconnector->dc_sink)
2125 break;
2126 }
2127
2128 dsc = pipe_ctx->stream_res.dsc;
2129 if (dsc)
2130 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2131
2132 snprintf(rd_buf, str_len,
2133 "%d\n",
2134 dsc_state.dsc_bits_per_pixel);
2135
2136 while (size) {
2137 if (*pos >= rd_buf_size)
2138 break;
2139
2140 r = put_user(*(rd_buf + result), buf);
2141 if (r) {
2142 kfree(rd_buf);
2143 return r; /* r = -EFAULT */
2144 }
2145
2146 buf += 1;
2147 size -= 1;
2148 *pos += 1;
2149 result += 1;
2150 }
2151
2152 kfree(rd_buf);
2153 return result;
2154 }
2155
2156 /* function: write DSC target rate in bits per pixel
2157 *
2158 * The write function: dp_dsc_bits_per_pixel_write
2159 * overwrites automatically generated DSC configuration
2160 * of DSC target bit rate.
2161 *
2162 * Also the user has to write bpp in hexidecimal
2163 * rather than in decimal.
2164 *
2165 * Writing DSC settings is done with the following command:
2166 * - To force overwrite rate (example sets to 256 bpp x 1/16):
2167 *
2168 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2169 *
2170 * - To stop overwriting and let driver find the optimal rate,
2171 * set the rate to zero:
2172 *
2173 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2174 *
2175 */
dp_dsc_bits_per_pixel_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2176 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2177 size_t size, loff_t *pos)
2178 {
2179 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2180 struct drm_connector *connector = &aconnector->base;
2181 struct drm_device *dev = connector->dev;
2182 struct drm_crtc *crtc = NULL;
2183 struct dm_crtc_state *dm_crtc_state = NULL;
2184 struct pipe_ctx *pipe_ctx;
2185 int i;
2186 char *wr_buf = NULL;
2187 uint32_t wr_buf_size = 42;
2188 int max_param_num = 1;
2189 uint8_t param_nums = 0;
2190 long param[1] = {0};
2191
2192 if (size == 0)
2193 return -EINVAL;
2194
2195 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2196
2197 if (!wr_buf) {
2198 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2199 return -ENOSPC;
2200 }
2201
2202 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2203 (long *)param, buf,
2204 max_param_num,
2205 ¶m_nums)) {
2206 kfree(wr_buf);
2207 return -EINVAL;
2208 }
2209
2210 if (param_nums <= 0) {
2211 DRM_DEBUG_DRIVER("user data not be read\n");
2212 kfree(wr_buf);
2213 return -EINVAL;
2214 }
2215
2216 for (i = 0; i < MAX_PIPES; i++) {
2217 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2218 if (pipe_ctx->stream &&
2219 pipe_ctx->stream->link == aconnector->dc_link &&
2220 pipe_ctx->stream->sink &&
2221 pipe_ctx->stream->sink == aconnector->dc_sink)
2222 break;
2223 }
2224
2225 if (!pipe_ctx->stream)
2226 goto done;
2227
2228 // Get CRTC state
2229 mutex_lock(&dev->mode_config.mutex);
2230 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2231
2232 if (connector->state == NULL)
2233 goto unlock;
2234
2235 crtc = connector->state->crtc;
2236 if (crtc == NULL)
2237 goto unlock;
2238
2239 drm_modeset_lock(&crtc->mutex, NULL);
2240 if (crtc->state == NULL)
2241 goto unlock;
2242
2243 dm_crtc_state = to_dm_crtc_state(crtc->state);
2244 if (dm_crtc_state->stream == NULL)
2245 goto unlock;
2246
2247 aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2248
2249 dm_crtc_state->dsc_force_changed = true;
2250
2251 unlock:
2252 if (crtc)
2253 drm_modeset_unlock(&crtc->mutex);
2254 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2255 mutex_unlock(&dev->mode_config.mutex);
2256
2257 done:
2258 kfree(wr_buf);
2259 return size;
2260 }
2261
2262 /* function: read DSC picture width parameter on the connector
2263 *
2264 * The read function: dp_dsc_pic_width_read
2265 * returns dsc picture width used in the current configuration
2266 * It is the same as h_addressable of the current
2267 * display's timing
2268 * The return is an integer: 0 or other positive integer
2269 * If 0 then DSC is disabled.
2270 *
2271 * Access it with the following command:
2272 *
2273 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2274 *
2275 * 0 - means that DSC is disabled
2276 */
dp_dsc_pic_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2277 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2278 size_t size, loff_t *pos)
2279 {
2280 char *rd_buf = NULL;
2281 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2282 struct display_stream_compressor *dsc;
2283 struct dcn_dsc_state dsc_state = {0};
2284 const uint32_t rd_buf_size = 100;
2285 struct pipe_ctx *pipe_ctx;
2286 ssize_t result = 0;
2287 int i, r, str_len = 30;
2288
2289 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2290
2291 if (!rd_buf)
2292 return -ENOMEM;
2293
2294 for (i = 0; i < MAX_PIPES; i++) {
2295 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2296 if (pipe_ctx->stream &&
2297 pipe_ctx->stream->link == aconnector->dc_link &&
2298 pipe_ctx->stream->sink &&
2299 pipe_ctx->stream->sink == aconnector->dc_sink)
2300 break;
2301 }
2302
2303 dsc = pipe_ctx->stream_res.dsc;
2304 if (dsc)
2305 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2306
2307 snprintf(rd_buf, str_len,
2308 "%d\n",
2309 dsc_state.dsc_pic_width);
2310
2311 while (size) {
2312 if (*pos >= rd_buf_size)
2313 break;
2314
2315 r = put_user(*(rd_buf + result), buf);
2316 if (r) {
2317 kfree(rd_buf);
2318 return r; /* r = -EFAULT */
2319 }
2320
2321 buf += 1;
2322 size -= 1;
2323 *pos += 1;
2324 result += 1;
2325 }
2326
2327 kfree(rd_buf);
2328 return result;
2329 }
2330
dp_dsc_pic_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2331 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2332 size_t size, loff_t *pos)
2333 {
2334 char *rd_buf = NULL;
2335 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2336 struct display_stream_compressor *dsc;
2337 struct dcn_dsc_state dsc_state = {0};
2338 const uint32_t rd_buf_size = 100;
2339 struct pipe_ctx *pipe_ctx;
2340 ssize_t result = 0;
2341 int i, r, str_len = 30;
2342
2343 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2344
2345 if (!rd_buf)
2346 return -ENOMEM;
2347
2348 for (i = 0; i < MAX_PIPES; i++) {
2349 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2350 if (pipe_ctx->stream &&
2351 pipe_ctx->stream->link == aconnector->dc_link &&
2352 pipe_ctx->stream->sink &&
2353 pipe_ctx->stream->sink == aconnector->dc_sink)
2354 break;
2355 }
2356
2357 dsc = pipe_ctx->stream_res.dsc;
2358 if (dsc)
2359 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2360
2361 snprintf(rd_buf, str_len,
2362 "%d\n",
2363 dsc_state.dsc_pic_height);
2364
2365 while (size) {
2366 if (*pos >= rd_buf_size)
2367 break;
2368
2369 r = put_user(*(rd_buf + result), buf);
2370 if (r) {
2371 kfree(rd_buf);
2372 return r; /* r = -EFAULT */
2373 }
2374
2375 buf += 1;
2376 size -= 1;
2377 *pos += 1;
2378 result += 1;
2379 }
2380
2381 kfree(rd_buf);
2382 return result;
2383 }
2384
2385 /* function: read DSC chunk size parameter on the connector
2386 *
2387 * The read function: dp_dsc_chunk_size_read
2388 * returns dsc chunk size set in the current configuration
2389 * The value is calculated automatically by DSC code
2390 * and depends on slice parameters and bpp target rate
2391 * The return is an integer: 0 or other positive integer
2392 * If 0 then DSC is disabled.
2393 *
2394 * Access it with the following command:
2395 *
2396 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2397 *
2398 * 0 - means that DSC is disabled
2399 */
dp_dsc_chunk_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2400 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2401 size_t size, loff_t *pos)
2402 {
2403 char *rd_buf = NULL;
2404 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2405 struct display_stream_compressor *dsc;
2406 struct dcn_dsc_state dsc_state = {0};
2407 const uint32_t rd_buf_size = 100;
2408 struct pipe_ctx *pipe_ctx;
2409 ssize_t result = 0;
2410 int i, r, str_len = 30;
2411
2412 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2413
2414 if (!rd_buf)
2415 return -ENOMEM;
2416
2417 for (i = 0; i < MAX_PIPES; i++) {
2418 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2419 if (pipe_ctx->stream &&
2420 pipe_ctx->stream->link == aconnector->dc_link &&
2421 pipe_ctx->stream->sink &&
2422 pipe_ctx->stream->sink == aconnector->dc_sink)
2423 break;
2424 }
2425
2426 dsc = pipe_ctx->stream_res.dsc;
2427 if (dsc)
2428 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2429
2430 snprintf(rd_buf, str_len,
2431 "%d\n",
2432 dsc_state.dsc_chunk_size);
2433
2434 while (size) {
2435 if (*pos >= rd_buf_size)
2436 break;
2437
2438 r = put_user(*(rd_buf + result), buf);
2439 if (r) {
2440 kfree(rd_buf);
2441 return r; /* r = -EFAULT */
2442 }
2443
2444 buf += 1;
2445 size -= 1;
2446 *pos += 1;
2447 result += 1;
2448 }
2449
2450 kfree(rd_buf);
2451 return result;
2452 }
2453
2454 /* function: read DSC slice bpg offset on the connector
2455 *
2456 * The read function: dp_dsc_slice_bpg_offset_read
2457 * returns dsc bpg slice offset set in the current configuration
2458 * The value is calculated automatically by DSC code
2459 * and depends on slice parameters and bpp target rate
2460 * The return is an integer: 0 or other positive integer
2461 * If 0 then DSC is disabled.
2462 *
2463 * Access it with the following command:
2464 *
2465 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2466 *
2467 * 0 - means that DSC is disabled
2468 */
dp_dsc_slice_bpg_offset_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2469 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2470 size_t size, loff_t *pos)
2471 {
2472 char *rd_buf = NULL;
2473 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2474 struct display_stream_compressor *dsc;
2475 struct dcn_dsc_state dsc_state = {0};
2476 const uint32_t rd_buf_size = 100;
2477 struct pipe_ctx *pipe_ctx;
2478 ssize_t result = 0;
2479 int i, r, str_len = 30;
2480
2481 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2482
2483 if (!rd_buf)
2484 return -ENOMEM;
2485
2486 for (i = 0; i < MAX_PIPES; i++) {
2487 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2488 if (pipe_ctx->stream &&
2489 pipe_ctx->stream->link == aconnector->dc_link &&
2490 pipe_ctx->stream->sink &&
2491 pipe_ctx->stream->sink == aconnector->dc_sink)
2492 break;
2493 }
2494
2495 dsc = pipe_ctx->stream_res.dsc;
2496 if (dsc)
2497 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2498
2499 snprintf(rd_buf, str_len,
2500 "%d\n",
2501 dsc_state.dsc_slice_bpg_offset);
2502
2503 while (size) {
2504 if (*pos >= rd_buf_size)
2505 break;
2506
2507 r = put_user(*(rd_buf + result), buf);
2508 if (r) {
2509 kfree(rd_buf);
2510 return r; /* r = -EFAULT */
2511 }
2512
2513 buf += 1;
2514 size -= 1;
2515 *pos += 1;
2516 result += 1;
2517 }
2518
2519 kfree(rd_buf);
2520 return result;
2521 }
2522
2523
2524 /*
2525 * function description: Read max_requested_bpc property from the connector
2526 *
2527 * Access it with the following command:
2528 *
2529 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2530 *
2531 */
dp_max_bpc_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2532 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2533 size_t size, loff_t *pos)
2534 {
2535 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2536 struct drm_connector *connector = &aconnector->base;
2537 struct drm_device *dev = connector->dev;
2538 struct dm_connector_state *state;
2539 ssize_t result = 0;
2540 char *rd_buf = NULL;
2541 char *rd_buf_ptr = NULL;
2542 const uint32_t rd_buf_size = 10;
2543 int r;
2544
2545 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2546
2547 if (!rd_buf)
2548 return -ENOMEM;
2549
2550 mutex_lock(&dev->mode_config.mutex);
2551 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2552
2553 if (connector->state == NULL)
2554 goto unlock;
2555
2556 state = to_dm_connector_state(connector->state);
2557
2558 rd_buf_ptr = rd_buf;
2559 snprintf(rd_buf_ptr, rd_buf_size,
2560 "%u\n",
2561 state->base.max_requested_bpc);
2562
2563 while (size) {
2564 if (*pos >= rd_buf_size)
2565 break;
2566
2567 r = put_user(*(rd_buf + result), buf);
2568 if (r) {
2569 result = r; /* r = -EFAULT */
2570 goto unlock;
2571 }
2572 buf += 1;
2573 size -= 1;
2574 *pos += 1;
2575 result += 1;
2576 }
2577 unlock:
2578 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2579 mutex_unlock(&dev->mode_config.mutex);
2580 kfree(rd_buf);
2581 return result;
2582 }
2583
2584
2585 /*
2586 * function description: Set max_requested_bpc property on the connector
2587 *
2588 * This function will not force the input BPC on connector, it will only
2589 * change the max value. This is equivalent to setting max_bpc through
2590 * xrandr.
2591 *
2592 * The BPC value written must be >= 6 and <= 16. Values outside of this
2593 * range will result in errors.
2594 *
2595 * BPC values:
2596 * 0x6 - 6 BPC
2597 * 0x8 - 8 BPC
2598 * 0xa - 10 BPC
2599 * 0xc - 12 BPC
2600 * 0x10 - 16 BPC
2601 *
2602 * Write the max_bpc in the following way:
2603 *
2604 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2605 *
2606 */
dp_max_bpc_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2607 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2608 size_t size, loff_t *pos)
2609 {
2610 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2611 struct drm_connector *connector = &aconnector->base;
2612 struct dm_connector_state *state;
2613 struct drm_device *dev = connector->dev;
2614 char *wr_buf = NULL;
2615 uint32_t wr_buf_size = 42;
2616 int max_param_num = 1;
2617 long param[1] = {0};
2618 uint8_t param_nums = 0;
2619
2620 if (size == 0)
2621 return -EINVAL;
2622
2623 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2624
2625 if (!wr_buf) {
2626 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2627 return -ENOSPC;
2628 }
2629
2630 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2631 (long *)param, buf,
2632 max_param_num,
2633 ¶m_nums)) {
2634 kfree(wr_buf);
2635 return -EINVAL;
2636 }
2637
2638 if (param_nums <= 0) {
2639 DRM_DEBUG_DRIVER("user data not be read\n");
2640 kfree(wr_buf);
2641 return -EINVAL;
2642 }
2643
2644 if (param[0] < 6 || param[0] > 16) {
2645 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2646 kfree(wr_buf);
2647 return -EINVAL;
2648 }
2649
2650 mutex_lock(&dev->mode_config.mutex);
2651 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2652
2653 if (connector->state == NULL)
2654 goto unlock;
2655
2656 state = to_dm_connector_state(connector->state);
2657 state->base.max_requested_bpc = param[0];
2658 unlock:
2659 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2660 mutex_unlock(&dev->mode_config.mutex);
2661
2662 kfree(wr_buf);
2663 return size;
2664 }
2665
2666 /*
2667 * IPS status. Read only.
2668 *
2669 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
2670 */
ips_status_show(struct seq_file * m,void * unused)2671 static int ips_status_show(struct seq_file *m, void *unused)
2672 {
2673 struct amdgpu_device *adev = m->private;
2674 struct dc *dc = adev->dm.dc;
2675 struct dc_dmub_srv *dc_dmub_srv;
2676
2677 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
2678 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
2679
2680 if (adev->dm.idle_workqueue) {
2681 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
2682 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
2683 }
2684
2685 dc_dmub_srv = dc->ctx->dmub_srv;
2686 if (dc_dmub_srv && dc_dmub_srv->dmub) {
2687 uint32_t rcg_count, ips1_count, ips2_count;
2688 volatile const struct dmub_shared_state_ips_fw *ips_fw =
2689 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
2690 rcg_count = ips_fw->rcg_entry_count;
2691 ips1_count = ips_fw->ips1_entry_count;
2692 ips2_count = ips_fw->ips2_entry_count;
2693 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",
2694 rcg_count,
2695 ips1_count,
2696 ips2_count);
2697 rcg_count = ips_fw->rcg_exit_count;
2698 ips1_count = ips_fw->ips1_exit_count;
2699 ips2_count = ips_fw->ips2_exit_count;
2700 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u",
2701 rcg_count,
2702 ips1_count,
2703 ips2_count);
2704 seq_puts(m, "\n");
2705 }
2706 return 0;
2707 }
2708
2709 /*
2710 * Backlight at this moment. Read only.
2711 * As written to display, taking ABM and backlight lut into account.
2712 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2713 *
2714 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2715 */
current_backlight_show(struct seq_file * m,void * unused)2716 static int current_backlight_show(struct seq_file *m, void *unused)
2717 {
2718 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2719 struct dc_link *link = aconnector->dc_link;
2720 unsigned int backlight;
2721
2722 backlight = dc_link_get_backlight_level(link);
2723 seq_printf(m, "0x%x\n", backlight);
2724
2725 return 0;
2726 }
2727
2728 /*
2729 * Backlight value that is being approached. Read only.
2730 * As written to display, taking ABM and backlight lut into account.
2731 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2732 *
2733 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2734 */
target_backlight_show(struct seq_file * m,void * unused)2735 static int target_backlight_show(struct seq_file *m, void *unused)
2736 {
2737 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2738 struct dc_link *link = aconnector->dc_link;
2739 unsigned int backlight;
2740
2741 backlight = dc_link_get_target_backlight_pwm(link);
2742 seq_printf(m, "0x%x\n", backlight);
2743
2744 return 0;
2745 }
2746
2747 /*
2748 * function description: Determine if the connector is mst connector
2749 *
2750 * This function helps to determine whether a connector is a mst connector.
2751 * - "root" stands for the root connector of the topology
2752 * - "branch" stands for branch device of the topology
2753 * - "end" stands for leaf node connector of the topology
2754 * - "no" stands for the connector is not a device of a mst topology
2755 * Access it with the following command:
2756 *
2757 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2758 *
2759 */
dp_is_mst_connector_show(struct seq_file * m,void * unused)2760 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2761 {
2762 struct drm_connector *connector = m->private;
2763 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2764 struct drm_dp_mst_topology_mgr *mgr = NULL;
2765 struct drm_dp_mst_port *port = NULL;
2766 char *role = NULL;
2767
2768 mutex_lock(&aconnector->hpd_lock);
2769
2770 if (aconnector->mst_mgr.mst_state) {
2771 role = "root";
2772 } else if (aconnector->mst_root &&
2773 aconnector->mst_root->mst_mgr.mst_state) {
2774
2775 role = "end";
2776
2777 mgr = &aconnector->mst_root->mst_mgr;
2778 port = aconnector->mst_output_port;
2779
2780 drm_modeset_lock(&mgr->base.lock, NULL);
2781 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2782 port->mcs)
2783 role = "branch";
2784 drm_modeset_unlock(&mgr->base.lock);
2785
2786 } else {
2787 role = "no";
2788 }
2789
2790 seq_printf(m, "%s\n", role);
2791
2792 mutex_unlock(&aconnector->hpd_lock);
2793
2794 return 0;
2795 }
2796
2797 /*
2798 * function description: Read out the mst progress status
2799 *
2800 * This function helps to determine the mst progress status of
2801 * a mst connector.
2802 *
2803 * Access it with the following command:
2804 *
2805 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2806 *
2807 */
dp_mst_progress_status_show(struct seq_file * m,void * unused)2808 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2809 {
2810 struct drm_connector *connector = m->private;
2811 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2812 struct amdgpu_device *adev = drm_to_adev(connector->dev);
2813 int i;
2814
2815 mutex_lock(&aconnector->hpd_lock);
2816 mutex_lock(&adev->dm.dc_lock);
2817
2818 if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2819 seq_puts(m, "disabled\n");
2820 } else {
2821 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2822 seq_printf(m, "%s:%s\n",
2823 mst_progress_status[i],
2824 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2825 }
2826
2827 mutex_unlock(&adev->dm.dc_lock);
2828 mutex_unlock(&aconnector->hpd_lock);
2829
2830 return 0;
2831 }
2832
2833 /*
2834 * Reports whether the connected display is a USB4 DPIA tunneled display
2835 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2836 */
is_dpia_link_show(struct seq_file * m,void * data)2837 static int is_dpia_link_show(struct seq_file *m, void *data)
2838 {
2839 struct drm_connector *connector = m->private;
2840 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2841 struct dc_link *link = aconnector->dc_link;
2842
2843 if (connector->status != connector_status_connected)
2844 return -ENODEV;
2845
2846 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2847 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2848
2849 return 0;
2850 }
2851
2852 /**
2853 * hdmi_cec_state_show - Read out the HDMI-CEC feature status
2854 * @m: sequence file.
2855 * @data: unused.
2856 *
2857 * Return 0 on success
2858 */
hdmi_cec_state_show(struct seq_file * m,void * data)2859 static int hdmi_cec_state_show(struct seq_file *m, void *data)
2860 {
2861 struct drm_connector *connector = m->private;
2862 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2863
2864 seq_printf(m, "%s:%d\n", connector->name, connector->base.id);
2865 seq_printf(m, "HDMI-CEC status: %d\n", aconnector->notifier ? 1 : 0);
2866
2867 return 0;
2868 }
2869
2870 /**
2871 * hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side
2872 * @f: file structure.
2873 * @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature.
2874 * @size: size of buffer from userpsace.
2875 * @pos: unused.
2876 *
2877 * Return size on success, error code on failure
2878 */
hdmi_cec_state_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2879 static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf,
2880 size_t size, loff_t *pos)
2881 {
2882 int ret;
2883 bool enable;
2884 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2885 struct drm_device *ddev = aconnector->base.dev;
2886
2887 if (size == 0)
2888 return -EINVAL;
2889
2890 ret = kstrtobool_from_user(buf, size, &enable);
2891 if (ret) {
2892 drm_dbg_driver(ddev, "invalid user data !\n");
2893 return ret;
2894 }
2895
2896 if (enable) {
2897 if (aconnector->notifier)
2898 return -EINVAL;
2899 ret = amdgpu_dm_initialize_hdmi_connector(aconnector);
2900 if (ret)
2901 return ret;
2902 hdmi_cec_set_edid(aconnector);
2903 } else {
2904 if (!aconnector->notifier)
2905 return -EINVAL;
2906 cec_notifier_conn_unregister(aconnector->notifier);
2907 aconnector->notifier = NULL;
2908 }
2909
2910 return size;
2911 }
2912
2913 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2914 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2915 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2916 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2917 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2918 DEFINE_SHOW_ATTRIBUTE(internal_display);
2919 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
2920 DEFINE_SHOW_ATTRIBUTE(replay_capability);
2921 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2922 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2923 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2924 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2925 DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state);
2926
2927 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2928 .owner = THIS_MODULE,
2929 .read = dp_dsc_clock_en_read,
2930 .write = dp_dsc_clock_en_write,
2931 .llseek = default_llseek
2932 };
2933
2934 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2935 .owner = THIS_MODULE,
2936 .read = dp_dsc_slice_width_read,
2937 .write = dp_dsc_slice_width_write,
2938 .llseek = default_llseek
2939 };
2940
2941 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2942 .owner = THIS_MODULE,
2943 .read = dp_dsc_slice_height_read,
2944 .write = dp_dsc_slice_height_write,
2945 .llseek = default_llseek
2946 };
2947
2948 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2949 .owner = THIS_MODULE,
2950 .read = dp_dsc_bits_per_pixel_read,
2951 .write = dp_dsc_bits_per_pixel_write,
2952 .llseek = default_llseek
2953 };
2954
2955 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2956 .owner = THIS_MODULE,
2957 .read = dp_dsc_pic_width_read,
2958 .llseek = default_llseek
2959 };
2960
2961 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2962 .owner = THIS_MODULE,
2963 .read = dp_dsc_pic_height_read,
2964 .llseek = default_llseek
2965 };
2966
2967 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2968 .owner = THIS_MODULE,
2969 .read = dp_dsc_chunk_size_read,
2970 .llseek = default_llseek
2971 };
2972
2973 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2974 .owner = THIS_MODULE,
2975 .read = dp_dsc_slice_bpg_offset_read,
2976 .llseek = default_llseek
2977 };
2978
2979 static const struct file_operations trigger_hotplug_debugfs_fops = {
2980 .owner = THIS_MODULE,
2981 .write = trigger_hotplug,
2982 .llseek = default_llseek
2983 };
2984
2985 static const struct file_operations dp_link_settings_debugfs_fops = {
2986 .owner = THIS_MODULE,
2987 .read = dp_link_settings_read,
2988 .write = dp_link_settings_write,
2989 .llseek = default_llseek
2990 };
2991
2992 static const struct file_operations dp_phy_settings_debugfs_fop = {
2993 .owner = THIS_MODULE,
2994 .read = dp_phy_settings_read,
2995 .write = dp_phy_settings_write,
2996 .llseek = default_llseek
2997 };
2998
2999 static const struct file_operations dp_phy_test_pattern_fops = {
3000 .owner = THIS_MODULE,
3001 .write = dp_phy_test_pattern_debugfs_write,
3002 .llseek = default_llseek
3003 };
3004
3005 static const struct file_operations sdp_message_fops = {
3006 .owner = THIS_MODULE,
3007 .write = dp_sdp_message_debugfs_write,
3008 .llseek = default_llseek
3009 };
3010
3011 static const struct file_operations dp_max_bpc_debugfs_fops = {
3012 .owner = THIS_MODULE,
3013 .read = dp_max_bpc_read,
3014 .write = dp_max_bpc_write,
3015 .llseek = default_llseek
3016 };
3017
3018 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
3019 .owner = THIS_MODULE,
3020 .write = dp_dsc_passthrough_set,
3021 .llseek = default_llseek
3022 };
3023
3024 static const struct file_operations dp_mst_link_settings_debugfs_fops = {
3025 .owner = THIS_MODULE,
3026 .write = dp_mst_link_setting,
3027 .llseek = default_llseek
3028 };
3029
3030 static const struct {
3031 char *name;
3032 const struct file_operations *fops;
3033 } dp_debugfs_entries[] = {
3034 {"link_settings", &dp_link_settings_debugfs_fops},
3035 {"phy_settings", &dp_phy_settings_debugfs_fop},
3036 {"lttpr_status", &dp_lttpr_status_fops},
3037 {"test_pattern", &dp_phy_test_pattern_fops},
3038 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3039 {"sdp_message", &sdp_message_fops},
3040 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
3041 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
3042 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
3043 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
3044 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
3045 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
3046 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
3047 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
3048 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
3049 {"max_bpc", &dp_max_bpc_debugfs_fops},
3050 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
3051 {"is_mst_connector", &dp_is_mst_connector_fops},
3052 {"mst_progress_status", &dp_mst_progress_status_fops},
3053 {"is_dpia_link", &is_dpia_link_fops},
3054 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
3055 };
3056
3057 static const struct {
3058 char *name;
3059 const struct file_operations *fops;
3060 } hdmi_debugfs_entries[] = {
3061 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3062 {"hdmi_cec_state", &hdmi_cec_state_fops}
3063 };
3064
3065 /*
3066 * Force YUV420 output if available from the given mode
3067 */
force_yuv420_output_set(void * data,u64 val)3068 static int force_yuv420_output_set(void *data, u64 val)
3069 {
3070 struct amdgpu_dm_connector *connector = data;
3071
3072 connector->force_yuv420_output = (bool)val;
3073
3074 return 0;
3075 }
3076
3077 /*
3078 * Check if YUV420 is forced when available from the given mode
3079 */
force_yuv420_output_get(void * data,u64 * val)3080 static int force_yuv420_output_get(void *data, u64 *val)
3081 {
3082 struct amdgpu_dm_connector *connector = data;
3083
3084 *val = connector->force_yuv420_output;
3085
3086 return 0;
3087 }
3088
3089 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
3090 force_yuv420_output_set, "%llu\n");
3091
3092 /*
3093 * Read Replay state
3094 */
replay_get_state(void * data,u64 * val)3095 static int replay_get_state(void *data, u64 *val)
3096 {
3097 struct amdgpu_dm_connector *connector = data;
3098 struct dc_link *link = connector->dc_link;
3099 uint64_t state = REPLAY_STATE_INVALID;
3100
3101 dc_link_get_replay_state(link, &state);
3102
3103 *val = state;
3104
3105 return 0;
3106 }
3107
3108 /*
3109 * Read PSR state
3110 */
psr_get(void * data,u64 * val)3111 static int psr_get(void *data, u64 *val)
3112 {
3113 struct amdgpu_dm_connector *connector = data;
3114 struct dc_link *link = connector->dc_link;
3115 enum dc_psr_state state = PSR_STATE0;
3116
3117 dc_link_get_psr_state(link, &state);
3118
3119 *val = state;
3120
3121 return 0;
3122 }
3123
3124 /*
3125 * Read PSR state residency
3126 */
psr_read_residency(void * data,u64 * val)3127 static int psr_read_residency(void *data, u64 *val)
3128 {
3129 struct amdgpu_dm_connector *connector = data;
3130 struct dc_link *link = connector->dc_link;
3131 u32 residency = 0;
3132
3133 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
3134
3135 *val = (u64)residency;
3136
3137 return 0;
3138 }
3139
3140 /* read allow_edp_hotplug_detection */
allow_edp_hotplug_detection_get(void * data,u64 * val)3141 static int allow_edp_hotplug_detection_get(void *data, u64 *val)
3142 {
3143 struct amdgpu_dm_connector *aconnector = data;
3144 struct drm_connector *connector = &aconnector->base;
3145 struct drm_device *dev = connector->dev;
3146 struct amdgpu_device *adev = drm_to_adev(dev);
3147
3148 *val = adev->dm.dc->config.allow_edp_hotplug_detection;
3149
3150 return 0;
3151 }
3152
3153 /* set allow_edp_hotplug_detection */
allow_edp_hotplug_detection_set(void * data,u64 val)3154 static int allow_edp_hotplug_detection_set(void *data, u64 val)
3155 {
3156 struct amdgpu_dm_connector *aconnector = data;
3157 struct drm_connector *connector = &aconnector->base;
3158 struct drm_device *dev = connector->dev;
3159 struct amdgpu_device *adev = drm_to_adev(dev);
3160
3161 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
3162
3163 return 0;
3164 }
3165
3166 /* check if kernel disallow eDP enter psr state
3167 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3168 * 0: allow edp enter psr; 1: disallow
3169 */
disallow_edp_enter_psr_get(void * data,u64 * val)3170 static int disallow_edp_enter_psr_get(void *data, u64 *val)
3171 {
3172 struct amdgpu_dm_connector *aconnector = data;
3173
3174 *val = (u64) aconnector->disallow_edp_enter_psr;
3175 return 0;
3176 }
3177
3178 /* set kernel disallow eDP enter psr state
3179 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3180 * 0: allow edp enter psr; 1: disallow
3181 *
3182 * usage: test app read crc from PSR eDP rx.
3183 *
3184 * during kernel boot up, kernel write dpcd 0x170 = 5.
3185 * this notify eDP rx psr enable and let rx check crc.
3186 * rx fw will start checking crc for rx internal logic.
3187 * crc read count within dpcd 0x246 is not updated and
3188 * value is 0. when eDP tx driver wants to read rx crc
3189 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3190 * timeout.
3191 *
3192 * to avoid this, we add this debugfs to let test app to disbable
3193 * rx crc checking for rx internal logic. then test app can read
3194 * non-zero crc read count.
3195 *
3196 * expected app sequence is as below:
3197 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3198 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3199 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3200 * without dpcd 0x170 = 5.
3201 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3202 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3203 * this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3204 */
disallow_edp_enter_psr_set(void * data,u64 val)3205 static int disallow_edp_enter_psr_set(void *data, u64 val)
3206 {
3207 struct amdgpu_dm_connector *aconnector = data;
3208
3209 aconnector->disallow_edp_enter_psr = val ? true : false;
3210 return 0;
3211 }
3212
dmub_trace_mask_set(void * data,u64 val)3213 static int dmub_trace_mask_set(void *data, u64 val)
3214 {
3215 struct amdgpu_device *adev = data;
3216 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3217 enum dmub_gpint_command cmd;
3218 u64 mask = 0xffff;
3219 u8 shift = 0;
3220 u32 res;
3221 int i;
3222
3223 if (!srv->fw_version)
3224 return -EINVAL;
3225
3226 for (i = 0; i < 4; i++) {
3227 res = (val & mask) >> shift;
3228
3229 switch (i) {
3230 case 0:
3231 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3232 break;
3233 case 1:
3234 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3235 break;
3236 case 2:
3237 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3238 break;
3239 case 3:
3240 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3241 break;
3242 }
3243
3244 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
3245 return -EIO;
3246
3247 usleep_range(100, 1000);
3248
3249 mask <<= 16;
3250 shift += 16;
3251 }
3252
3253 return 0;
3254 }
3255
dmub_trace_mask_show(void * data,u64 * val)3256 static int dmub_trace_mask_show(void *data, u64 *val)
3257 {
3258 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3259 struct amdgpu_device *adev = data;
3260 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3261 u8 shift = 0;
3262 u64 raw = 0;
3263 u64 res = 0;
3264 int i = 0;
3265
3266 if (!srv->fw_version)
3267 return -EINVAL;
3268
3269 while (i < 4) {
3270 uint32_t response;
3271
3272 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3273 return -EIO;
3274
3275 raw = response;
3276 usleep_range(100, 1000);
3277
3278 cmd++;
3279 res |= (raw << shift);
3280 shift += 16;
3281 i++;
3282 }
3283
3284 *val = res;
3285
3286 return 0;
3287 }
3288
3289 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3290 dmub_trace_mask_set, "0x%llx\n");
3291
3292 /*
3293 * Set dmcub trace event IRQ enable or disable.
3294 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3295 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3296 */
dmcub_trace_event_state_set(void * data,u64 val)3297 static int dmcub_trace_event_state_set(void *data, u64 val)
3298 {
3299 struct amdgpu_device *adev = data;
3300
3301 if (val == 1 || val == 0) {
3302 dc_dmub_trace_event_control(adev->dm.dc, val);
3303 adev->dm.dmcub_trace_event_en = (bool)val;
3304 } else
3305 return 0;
3306
3307 return 0;
3308 }
3309
3310 /*
3311 * The interface doesn't need get function, so it will return the
3312 * value of zero
3313 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3314 */
dmcub_trace_event_state_get(void * data,u64 * val)3315 static int dmcub_trace_event_state_get(void *data, u64 *val)
3316 {
3317 struct amdgpu_device *adev = data;
3318
3319 *val = adev->dm.dmcub_trace_event_en;
3320 return 0;
3321 }
3322
3323 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3324 dmcub_trace_event_state_set, "%llu\n");
3325
3326 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");
3327
3328 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3329 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3330 "%llu\n");
3331
3332 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3333 allow_edp_hotplug_detection_get,
3334 allow_edp_hotplug_detection_set, "%llu\n");
3335
3336 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3337 disallow_edp_enter_psr_get,
3338 disallow_edp_enter_psr_set, "%llu\n");
3339
3340 DEFINE_SHOW_ATTRIBUTE(current_backlight);
3341 DEFINE_SHOW_ATTRIBUTE(target_backlight);
3342 DEFINE_SHOW_ATTRIBUTE(ips_status);
3343
3344 static const struct {
3345 char *name;
3346 const struct file_operations *fops;
3347 } connector_debugfs_entries[] = {
3348 {"force_yuv420_output", &force_yuv420_output_fops},
3349 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3350 {"internal_display", &internal_display_fops},
3351 {"odm_combine_segments", &odm_combine_segments_fops}
3352 };
3353
3354 /*
3355 * Returns supported customized link rates by this eDP panel.
3356 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3357 */
edp_ilr_show(struct seq_file * m,void * unused)3358 static int edp_ilr_show(struct seq_file *m, void *unused)
3359 {
3360 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3361 struct dc_link *link = aconnector->dc_link;
3362 uint8_t supported_link_rates[16];
3363 uint32_t link_rate_in_khz;
3364 uint32_t entry = 0;
3365 uint8_t dpcd_rev;
3366
3367 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3368 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3369 supported_link_rates, sizeof(supported_link_rates));
3370
3371 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3372
3373 if (dpcd_rev >= DP_DPCD_REV_13 &&
3374 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3375
3376 for (entry = 0; entry < 16; entry += 2) {
3377 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3378 supported_link_rates[entry]) * 200;
3379 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3380 }
3381 } else {
3382 seq_puts(m, "ILR is not supported by this eDP panel.\n");
3383 }
3384
3385 return 0;
3386 }
3387
3388 /*
3389 * Set supported customized link rate to eDP panel.
3390 *
3391 * echo <lane_count> <link_rate option> > ilr_setting
3392 *
3393 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3394 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3395 * to set 4 lanes and 2.16 GHz
3396 */
edp_ilr_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)3397 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3398 size_t size, loff_t *pos)
3399 {
3400 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3401 struct dc_link *link = connector->dc_link;
3402 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3403 struct dc *dc = (struct dc *)link->dc;
3404 struct dc_link_settings prefer_link_settings;
3405 char *wr_buf = NULL;
3406 const uint32_t wr_buf_size = 40;
3407 /* 0: lane_count; 1: link_rate */
3408 int max_param_num = 2;
3409 uint8_t param_nums = 0;
3410 long param[2];
3411 bool valid_input = true;
3412
3413 if (size == 0)
3414 return -EINVAL;
3415
3416 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3417 if (!wr_buf)
3418 return -ENOMEM;
3419
3420 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3421 (long *)param, buf,
3422 max_param_num,
3423 ¶m_nums)) {
3424 kfree(wr_buf);
3425 return -EINVAL;
3426 }
3427
3428 if (param_nums <= 0) {
3429 kfree(wr_buf);
3430 return -EINVAL;
3431 }
3432
3433 switch (param[0]) {
3434 case LANE_COUNT_ONE:
3435 case LANE_COUNT_TWO:
3436 case LANE_COUNT_FOUR:
3437 break;
3438 default:
3439 valid_input = false;
3440 break;
3441 }
3442
3443 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3444 valid_input = false;
3445
3446 if (!valid_input) {
3447 kfree(wr_buf);
3448 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3449 prefer_link_settings.use_link_rate_set = false;
3450 mutex_lock(&adev->dm.dc_lock);
3451 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3452 mutex_unlock(&adev->dm.dc_lock);
3453 return size;
3454 }
3455
3456 /* save user force lane_count, link_rate to preferred settings
3457 * spread spectrum will not be changed
3458 */
3459 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3460 prefer_link_settings.lane_count = param[0];
3461 prefer_link_settings.use_link_rate_set = true;
3462 prefer_link_settings.link_rate_set = param[1];
3463 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
3464
3465 mutex_lock(&adev->dm.dc_lock);
3466 dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3467 NULL, link, false);
3468 mutex_unlock(&adev->dm.dc_lock);
3469
3470 kfree(wr_buf);
3471 return size;
3472 }
3473
edp_ilr_open(struct inode * inode,struct file * file)3474 static int edp_ilr_open(struct inode *inode, struct file *file)
3475 {
3476 return single_open(file, edp_ilr_show, inode->i_private);
3477 }
3478
3479 static const struct file_operations edp_ilr_debugfs_fops = {
3480 .owner = THIS_MODULE,
3481 .open = edp_ilr_open,
3482 .read = seq_read,
3483 .llseek = seq_lseek,
3484 .release = single_release,
3485 .write = edp_ilr_write
3486 };
3487
connector_debugfs_init(struct amdgpu_dm_connector * connector)3488 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3489 {
3490 int i;
3491 struct dentry *dir = connector->base.debugfs_entry;
3492
3493 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3494 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3495 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3496 debugfs_create_file(dp_debugfs_entries[i].name,
3497 0644, dir, connector,
3498 dp_debugfs_entries[i].fops);
3499 }
3500 }
3501 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3502 debugfs_create_file("replay_capability", 0444, dir, connector,
3503 &replay_capability_fops);
3504 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops);
3505 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3506 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3507 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3508 connector, &psr_residency_fops);
3509 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3510 ¤t_backlight_fops);
3511 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3512 &target_backlight_fops);
3513 debugfs_create_file("ilr_setting", 0644, dir, connector,
3514 &edp_ilr_debugfs_fops);
3515 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3516 &allow_edp_hotplug_detection_fops);
3517 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3518 &disallow_edp_enter_psr_fops);
3519 }
3520
3521 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3522 debugfs_create_file(connector_debugfs_entries[i].name,
3523 0644, dir, connector,
3524 connector_debugfs_entries[i].fops);
3525 }
3526
3527 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3528 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3529 debugfs_create_file(hdmi_debugfs_entries[i].name,
3530 0644, dir, connector,
3531 hdmi_debugfs_entries[i].fops);
3532 }
3533 }
3534 }
3535
3536 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3537 /*
3538 * Set crc window coordinate x start
3539 */
crc_win_x_start_set(void * data,u64 val)3540 static int crc_win_x_start_set(void *data, u64 val)
3541 {
3542 struct drm_crtc *crtc = data;
3543 struct drm_device *drm_dev = crtc->dev;
3544 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3545
3546 spin_lock_irq(&drm_dev->event_lock);
3547 acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
3548 acrtc->dm_irq_params.window_param[0].update_win = false;
3549 spin_unlock_irq(&drm_dev->event_lock);
3550
3551 return 0;
3552 }
3553
3554 /*
3555 * Get crc window coordinate x start
3556 */
crc_win_x_start_get(void * data,u64 * val)3557 static int crc_win_x_start_get(void *data, u64 *val)
3558 {
3559 struct drm_crtc *crtc = data;
3560 struct drm_device *drm_dev = crtc->dev;
3561 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3562
3563 spin_lock_irq(&drm_dev->event_lock);
3564 *val = acrtc->dm_irq_params.window_param[0].x_start;
3565 spin_unlock_irq(&drm_dev->event_lock);
3566
3567 return 0;
3568 }
3569
3570 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3571 crc_win_x_start_set, "%llu\n");
3572
3573
3574 /*
3575 * Set crc window coordinate y start
3576 */
crc_win_y_start_set(void * data,u64 val)3577 static int crc_win_y_start_set(void *data, u64 val)
3578 {
3579 struct drm_crtc *crtc = data;
3580 struct drm_device *drm_dev = crtc->dev;
3581 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3582
3583 spin_lock_irq(&drm_dev->event_lock);
3584 acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
3585 acrtc->dm_irq_params.window_param[0].update_win = false;
3586 spin_unlock_irq(&drm_dev->event_lock);
3587
3588 return 0;
3589 }
3590
3591 /*
3592 * Get crc window coordinate y start
3593 */
crc_win_y_start_get(void * data,u64 * val)3594 static int crc_win_y_start_get(void *data, u64 *val)
3595 {
3596 struct drm_crtc *crtc = data;
3597 struct drm_device *drm_dev = crtc->dev;
3598 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3599
3600 spin_lock_irq(&drm_dev->event_lock);
3601 *val = acrtc->dm_irq_params.window_param[0].y_start;
3602 spin_unlock_irq(&drm_dev->event_lock);
3603
3604 return 0;
3605 }
3606
3607 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3608 crc_win_y_start_set, "%llu\n");
3609
3610 /*
3611 * Set crc window coordinate x end
3612 */
crc_win_x_end_set(void * data,u64 val)3613 static int crc_win_x_end_set(void *data, u64 val)
3614 {
3615 struct drm_crtc *crtc = data;
3616 struct drm_device *drm_dev = crtc->dev;
3617 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3618
3619 spin_lock_irq(&drm_dev->event_lock);
3620 acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
3621 acrtc->dm_irq_params.window_param[0].update_win = false;
3622 spin_unlock_irq(&drm_dev->event_lock);
3623
3624 return 0;
3625 }
3626
3627 /*
3628 * Get crc window coordinate x end
3629 */
crc_win_x_end_get(void * data,u64 * val)3630 static int crc_win_x_end_get(void *data, u64 *val)
3631 {
3632 struct drm_crtc *crtc = data;
3633 struct drm_device *drm_dev = crtc->dev;
3634 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3635
3636 spin_lock_irq(&drm_dev->event_lock);
3637 *val = acrtc->dm_irq_params.window_param[0].x_end;
3638 spin_unlock_irq(&drm_dev->event_lock);
3639
3640 return 0;
3641 }
3642
3643 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3644 crc_win_x_end_set, "%llu\n");
3645
3646 /*
3647 * Set crc window coordinate y end
3648 */
crc_win_y_end_set(void * data,u64 val)3649 static int crc_win_y_end_set(void *data, u64 val)
3650 {
3651 struct drm_crtc *crtc = data;
3652 struct drm_device *drm_dev = crtc->dev;
3653 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3654
3655 spin_lock_irq(&drm_dev->event_lock);
3656 acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
3657 acrtc->dm_irq_params.window_param[0].update_win = false;
3658 spin_unlock_irq(&drm_dev->event_lock);
3659
3660 return 0;
3661 }
3662
3663 /*
3664 * Get crc window coordinate y end
3665 */
crc_win_y_end_get(void * data,u64 * val)3666 static int crc_win_y_end_get(void *data, u64 *val)
3667 {
3668 struct drm_crtc *crtc = data;
3669 struct drm_device *drm_dev = crtc->dev;
3670 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3671
3672 spin_lock_irq(&drm_dev->event_lock);
3673 *val = acrtc->dm_irq_params.window_param[0].y_end;
3674 spin_unlock_irq(&drm_dev->event_lock);
3675
3676 return 0;
3677 }
3678
3679 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3680 crc_win_y_end_set, "%llu\n");
3681 /*
3682 * Trigger to commit crc window
3683 */
crc_win_update_set(void * data,u64 val)3684 static int crc_win_update_set(void *data, u64 val)
3685 {
3686 struct drm_crtc *crtc = data;
3687 struct amdgpu_crtc *acrtc;
3688 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3689
3690 if (val) {
3691 acrtc = to_amdgpu_crtc(crtc);
3692 mutex_lock(&adev->dm.dc_lock);
3693 /* PSR may write to OTG CRC window control register,
3694 * so close it before starting secure_display.
3695 */
3696 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);
3697
3698 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3699
3700 acrtc->dm_irq_params.window_param[0].enable = true;
3701 acrtc->dm_irq_params.window_param[0].update_win = true;
3702 acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
3703 acrtc->dm_irq_params.crc_window_activated = true;
3704
3705 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3706 mutex_unlock(&adev->dm.dc_lock);
3707 }
3708
3709 return 0;
3710 }
3711
3712 /*
3713 * Get crc window update flag
3714 */
crc_win_update_get(void * data,u64 * val)3715 static int crc_win_update_get(void *data, u64 *val)
3716 {
3717 *val = 0;
3718 return 0;
3719 }
3720
3721 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3722 crc_win_update_set, "%llu\n");
3723 #endif
crtc_debugfs_init(struct drm_crtc * crtc)3724 void crtc_debugfs_init(struct drm_crtc *crtc)
3725 {
3726 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3727 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3728
3729 if (!dir)
3730 return;
3731
3732 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3733 &crc_win_x_start_fops);
3734 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3735 &crc_win_y_start_fops);
3736 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3737 &crc_win_x_end_fops);
3738 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3739 &crc_win_y_end_fops);
3740 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3741 &crc_win_update_fops);
3742 dput(dir);
3743 #endif
3744 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3745 crtc, &amdgpu_current_bpc_fops);
3746 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3747 crtc, &amdgpu_current_colorspace_fops);
3748 }
3749
3750 /*
3751 * Writes DTN log state to the user supplied buffer.
3752 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3753 */
dtn_log_read(struct file * f,char __user * buf,size_t size,loff_t * pos)3754 static ssize_t dtn_log_read(
3755 struct file *f,
3756 char __user *buf,
3757 size_t size,
3758 loff_t *pos)
3759 {
3760 struct amdgpu_device *adev = file_inode(f)->i_private;
3761 struct dc *dc = adev->dm.dc;
3762 struct dc_log_buffer_ctx log_ctx = { 0 };
3763 ssize_t result = 0;
3764
3765 if (!buf || !size)
3766 return -EINVAL;
3767
3768 if (!dc->hwss.log_hw_state)
3769 return 0;
3770
3771 dc->hwss.log_hw_state(dc, &log_ctx);
3772
3773 if (*pos < log_ctx.pos) {
3774 size_t to_copy = log_ctx.pos - *pos;
3775
3776 to_copy = min(to_copy, size);
3777
3778 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3779 *pos += to_copy;
3780 result = to_copy;
3781 }
3782 }
3783
3784 kfree(log_ctx.buf);
3785
3786 return result;
3787 }
3788
3789 /*
3790 * Writes DTN log state to dmesg when triggered via a write.
3791 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3792 */
dtn_log_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)3793 static ssize_t dtn_log_write(
3794 struct file *f,
3795 const char __user *buf,
3796 size_t size,
3797 loff_t *pos)
3798 {
3799 struct amdgpu_device *adev = file_inode(f)->i_private;
3800 struct dc *dc = adev->dm.dc;
3801
3802 /* Write triggers log output via dmesg. */
3803 if (size == 0)
3804 return 0;
3805
3806 if (dc->hwss.log_hw_state)
3807 dc->hwss.log_hw_state(dc, NULL);
3808
3809 return size;
3810 }
3811
mst_topo_show(struct seq_file * m,void * unused)3812 static int mst_topo_show(struct seq_file *m, void *unused)
3813 {
3814 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3815 struct drm_device *dev = adev_to_drm(adev);
3816 struct drm_connector *connector;
3817 struct drm_connector_list_iter conn_iter;
3818 struct amdgpu_dm_connector *aconnector;
3819
3820 drm_connector_list_iter_begin(dev, &conn_iter);
3821 drm_for_each_connector_iter(connector, &conn_iter) {
3822 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3823 continue;
3824
3825 aconnector = to_amdgpu_dm_connector(connector);
3826
3827 /* Ensure we're only dumping the topology of a root mst node */
3828 if (!aconnector->mst_mgr.mst_state)
3829 continue;
3830
3831 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3832 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3833 }
3834 drm_connector_list_iter_end(&conn_iter);
3835
3836 return 0;
3837 }
3838
3839 /*
3840 * Sets trigger hpd for MST topologies.
3841 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3842 * All topologies will be disconnected if val of 0 is set .
3843 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3844 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3845 */
trigger_hpd_mst_set(void * data,u64 val)3846 static int trigger_hpd_mst_set(void *data, u64 val)
3847 {
3848 struct amdgpu_device *adev = data;
3849 struct drm_device *dev = adev_to_drm(adev);
3850 struct drm_connector_list_iter iter;
3851 struct amdgpu_dm_connector *aconnector;
3852 struct drm_connector *connector;
3853 struct dc_link *link = NULL;
3854 int ret;
3855
3856 if (val == 1) {
3857 drm_connector_list_iter_begin(dev, &iter);
3858 drm_for_each_connector_iter(connector, &iter) {
3859 aconnector = to_amdgpu_dm_connector(connector);
3860 if (aconnector->dc_link->type == dc_connection_mst_branch &&
3861 aconnector->mst_mgr.aux) {
3862 mutex_lock(&adev->dm.dc_lock);
3863 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3864 mutex_unlock(&adev->dm.dc_lock);
3865
3866 if (!ret)
3867 DRM_ERROR("DM_MST: Failed to detect dc link!");
3868
3869 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3870 if (ret < 0)
3871 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
3872 }
3873 }
3874 } else if (val == 0) {
3875 drm_connector_list_iter_begin(dev, &iter);
3876 drm_for_each_connector_iter(connector, &iter) {
3877 aconnector = to_amdgpu_dm_connector(connector);
3878 if (!aconnector->dc_link)
3879 continue;
3880
3881 if (!aconnector->mst_root)
3882 continue;
3883
3884 link = aconnector->dc_link;
3885 dc_link_dp_receiver_power_ctrl(link, false);
3886 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
3887 link->mst_stream_alloc_table.stream_count = 0;
3888 memset(link->mst_stream_alloc_table.stream_allocations, 0,
3889 sizeof(link->mst_stream_alloc_table.stream_allocations));
3890 }
3891 } else {
3892 return 0;
3893 }
3894 drm_kms_helper_hotplug_event(dev);
3895
3896 return 0;
3897 }
3898
3899 /*
3900 * The interface doesn't need get function, so it will return the
3901 * value of zero
3902 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3903 */
trigger_hpd_mst_get(void * data,u64 * val)3904 static int trigger_hpd_mst_get(void *data, u64 *val)
3905 {
3906 *val = 0;
3907 return 0;
3908 }
3909
3910 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3911 trigger_hpd_mst_set, "%llu\n");
3912
3913
3914 /*
3915 * Sets the force_timing_sync debug option from the given string.
3916 * All connected displays will be force synchronized immediately.
3917 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3918 */
force_timing_sync_set(void * data,u64 val)3919 static int force_timing_sync_set(void *data, u64 val)
3920 {
3921 struct amdgpu_device *adev = data;
3922
3923 adev->dm.force_timing_sync = (bool)val;
3924
3925 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3926
3927 return 0;
3928 }
3929
3930 /*
3931 * Gets the force_timing_sync debug option value into the given buffer.
3932 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3933 */
force_timing_sync_get(void * data,u64 * val)3934 static int force_timing_sync_get(void *data, u64 *val)
3935 {
3936 struct amdgpu_device *adev = data;
3937
3938 *val = adev->dm.force_timing_sync;
3939
3940 return 0;
3941 }
3942
3943 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3944 force_timing_sync_set, "%llu\n");
3945
3946
3947 /*
3948 * Disables all HPD and HPD RX interrupt handling in the
3949 * driver when set to 1. Default is 0.
3950 */
disable_hpd_set(void * data,u64 val)3951 static int disable_hpd_set(void *data, u64 val)
3952 {
3953 struct amdgpu_device *adev = data;
3954
3955 adev->dm.disable_hpd_irq = (bool)val;
3956
3957 return 0;
3958 }
3959
3960
3961 /*
3962 * Returns 1 if HPD and HPRX interrupt handling is disabled,
3963 * 0 otherwise.
3964 */
disable_hpd_get(void * data,u64 * val)3965 static int disable_hpd_get(void *data, u64 *val)
3966 {
3967 struct amdgpu_device *adev = data;
3968
3969 *val = adev->dm.disable_hpd_irq;
3970
3971 return 0;
3972 }
3973
3974 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3975 disable_hpd_set, "%llu\n");
3976
3977 /*
3978 * Prints hardware capabilities. These are used for IGT testing.
3979 */
capabilities_show(struct seq_file * m,void * unused)3980 static int capabilities_show(struct seq_file *m, void *unused)
3981 {
3982 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3983 struct dc *dc = adev->dm.dc;
3984 bool mall_supported = dc->caps.mall_size_total;
3985 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
3986 unsigned int mall_in_use = false;
3987 unsigned int subvp_in_use = false;
3988
3989 struct hubbub *hubbub = dc->res_pool->hubbub;
3990
3991 if (hubbub->funcs->get_mall_en)
3992 hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
3993
3994 if (dc->cap_funcs.get_subvp_en)
3995 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
3996
3997 seq_printf(m, "mall supported: %s, enabled: %s\n",
3998 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
3999 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
4000 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
4001
4002 return 0;
4003 }
4004
4005 DEFINE_SHOW_ATTRIBUTE(capabilities);
4006
4007 /*
4008 * Temporary w/a to force sst sequence in M42D DP2 mst receiver
4009 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
4010 */
dp_force_sst_set(void * data,u64 val)4011 static int dp_force_sst_set(void *data, u64 val)
4012 {
4013 struct amdgpu_device *adev = data;
4014
4015 adev->dm.dc->debug.set_mst_en_for_sst = val;
4016
4017 return 0;
4018 }
4019
dp_force_sst_get(void * data,u64 * val)4020 static int dp_force_sst_get(void *data, u64 *val)
4021 {
4022 struct amdgpu_device *adev = data;
4023
4024 *val = adev->dm.dc->debug.set_mst_en_for_sst;
4025
4026 return 0;
4027 }
4028 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
4029 dp_force_sst_set, "%llu\n");
4030
4031 /*
4032 * Force DP2 sequence without VESA certified cable.
4033 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
4034 */
dp_ignore_cable_id_set(void * data,u64 val)4035 static int dp_ignore_cable_id_set(void *data, u64 val)
4036 {
4037 struct amdgpu_device *adev = data;
4038
4039 adev->dm.dc->debug.ignore_cable_id = val;
4040
4041 return 0;
4042 }
4043
dp_ignore_cable_id_get(void * data,u64 * val)4044 static int dp_ignore_cable_id_get(void *data, u64 *val)
4045 {
4046 struct amdgpu_device *adev = data;
4047
4048 *val = adev->dm.dc->debug.ignore_cable_id;
4049
4050 return 0;
4051 }
4052 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
4053 dp_ignore_cable_id_set, "%llu\n");
4054
4055 /*
4056 * Sets the DC visual confirm debug option from the given string.
4057 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
4058 */
visual_confirm_set(void * data,u64 val)4059 static int visual_confirm_set(void *data, u64 val)
4060 {
4061 struct amdgpu_device *adev = data;
4062
4063 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
4064
4065 return 0;
4066 }
4067
4068 /*
4069 * Reads the DC visual confirm debug option value into the given buffer.
4070 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
4071 */
visual_confirm_get(void * data,u64 * val)4072 static int visual_confirm_get(void *data, u64 *val)
4073 {
4074 struct amdgpu_device *adev = data;
4075
4076 *val = adev->dm.dc->debug.visual_confirm;
4077
4078 return 0;
4079 }
4080
4081 DEFINE_SHOW_ATTRIBUTE(mst_topo);
4082 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
4083 visual_confirm_set, "%llu\n");
4084
4085
4086 /*
4087 * Sets the DC skip_detection_link_training debug option from the given string.
4088 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
4089 */
skip_detection_link_training_set(void * data,u64 val)4090 static int skip_detection_link_training_set(void *data, u64 val)
4091 {
4092 struct amdgpu_device *adev = data;
4093
4094 if (val == 0)
4095 adev->dm.dc->debug.skip_detection_link_training = false;
4096 else
4097 adev->dm.dc->debug.skip_detection_link_training = true;
4098
4099 return 0;
4100 }
4101
4102 /*
4103 * Reads the DC skip_detection_link_training debug option value into the given buffer.
4104 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
4105 */
skip_detection_link_training_get(void * data,u64 * val)4106 static int skip_detection_link_training_get(void *data, u64 *val)
4107 {
4108 struct amdgpu_device *adev = data;
4109
4110 *val = adev->dm.dc->debug.skip_detection_link_training;
4111
4112 return 0;
4113 }
4114
4115 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
4116 skip_detection_link_training_get,
4117 skip_detection_link_training_set, "%llu\n");
4118
4119 /*
4120 * Dumps the DCC_EN bit for each pipe.
4121 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
4122 */
dcc_en_bits_read(struct file * f,char __user * buf,size_t size,loff_t * pos)4123 static ssize_t dcc_en_bits_read(
4124 struct file *f,
4125 char __user *buf,
4126 size_t size,
4127 loff_t *pos)
4128 {
4129 struct amdgpu_device *adev = file_inode(f)->i_private;
4130 struct dc *dc = adev->dm.dc;
4131 char *rd_buf = NULL;
4132 const uint32_t rd_buf_size = 32;
4133 uint32_t result = 0;
4134 int offset = 0;
4135 int num_pipes = dc->res_pool->pipe_count;
4136 int *dcc_en_bits;
4137 int i, r;
4138
4139 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
4140 if (!dcc_en_bits)
4141 return -ENOMEM;
4142
4143 if (!dc->hwss.get_dcc_en_bits) {
4144 kfree(dcc_en_bits);
4145 return 0;
4146 }
4147
4148 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
4149
4150 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
4151 if (!rd_buf) {
4152 kfree(dcc_en_bits);
4153 return -ENOMEM;
4154 }
4155
4156 for (i = 0; i < num_pipes; i++)
4157 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
4158 "%d ", dcc_en_bits[i]);
4159 rd_buf[strlen(rd_buf)] = '\n';
4160
4161 kfree(dcc_en_bits);
4162
4163 while (size) {
4164 if (*pos >= rd_buf_size)
4165 break;
4166 r = put_user(*(rd_buf + result), buf);
4167 if (r) {
4168 kfree(rd_buf);
4169 return r; /* r = -EFAULT */
4170 }
4171 buf += 1;
4172 size -= 1;
4173 *pos += 1;
4174 result += 1;
4175 }
4176
4177 kfree(rd_buf);
4178 return result;
4179 }
4180
dtn_debugfs_init(struct amdgpu_device * adev)4181 void dtn_debugfs_init(struct amdgpu_device *adev)
4182 {
4183 static const struct file_operations dtn_log_fops = {
4184 .owner = THIS_MODULE,
4185 .read = dtn_log_read,
4186 .write = dtn_log_write,
4187 .llseek = default_llseek
4188 };
4189 static const struct file_operations dcc_en_bits_fops = {
4190 .owner = THIS_MODULE,
4191 .read = dcc_en_bits_read,
4192 .llseek = default_llseek
4193 };
4194
4195 struct drm_minor *minor = adev_to_drm(adev)->primary;
4196 struct dentry *root = minor->debugfs_root;
4197
4198 debugfs_create_file("amdgpu_mst_topology", 0444, root,
4199 adev, &mst_topo_fops);
4200 debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4201 adev, &capabilities_fops);
4202 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4203 &dtn_log_fops);
4204 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4205 &dp_set_mst_en_for_sst_ops);
4206 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4207 &dp_ignore_cable_id_ops);
4208
4209 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
4210 &visual_confirm_fops);
4211
4212 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
4213 &skip_detection_link_training_fops);
4214
4215 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
4216 adev, &dmub_tracebuffer_fops);
4217
4218 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
4219 adev, &dmub_fw_state_fops);
4220
4221 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
4222 adev, &force_timing_sync_ops);
4223
4224 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,
4225 adev, &dmub_trace_mask_fops);
4226
4227 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
4228 adev, &dmcub_trace_event_state_fops);
4229
4230 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
4231 adev, &trigger_hpd_mst_ops);
4232
4233 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
4234 &dcc_en_bits_fops);
4235
4236 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
4237 &disable_hpd_ops);
4238
4239 if (adev->dm.dc->caps.ips_support)
4240 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
4241 &ips_status_fops);
4242 }
4243