1 /*
2 * Single-precision vector log2 function.
3 *
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "v_math.h"
9 #include "test_sig.h"
10 #include "test_defs.h"
11
12 static const struct data
13 {
14 float32x4_t c0, c2, c4, c6, c8;
15 uint32x4_t off, offset_lower_bound;
16 uint16x8_t special_bound;
17 uint32x4_t mantissa_mask;
18 float c1, c3, c5, c7;
19 } data = {
20 /* Coefficients generated using Remez algorithm approximate
21 log2(1+r)/r for r in [ -1/3, 1/3 ].
22 rel error: 0x1.c4c4b0cp-26. */
23 .c0 = V4 (0x1.715476p0f), /* (float)(1 / ln(2)). */
24 .c1 = -0x1.715458p-1f,
25 .c2 = V4 (0x1.ec701cp-2f),
26 .c3 = -0x1.7171a4p-2f,
27 .c4 = V4 (0x1.27a0b8p-2f),
28 .c5 = -0x1.e5143ep-3f,
29 .c6 = V4 (0x1.9d8ecap-3f),
30 .c7 = -0x1.c675bp-3f,
31 .c8 = V4 (0x1.9e495p-3f),
32 /* Lower bound is the smallest positive normal float 0x00800000. For
33 optimised register use subnormals are detected after offset has been
34 subtracted, so lower bound is 0x0080000 - offset (which wraps around). */
35 .offset_lower_bound = V4 (0x00800000 - 0x3f2aaaab),
36 .special_bound = V8 (0x7f00), /* top16(asuint32(inf) - 0x00800000). */
37 .off = V4 (0x3f2aaaab), /* 0.666667. */
38 .mantissa_mask = V4 (0x007fffff),
39 };
40
41 static float32x4_t VPCS_ATTR NOINLINE
special_case(float32x4_t n,uint32x4_t u_off,float32x4_t p,float32x4_t r,uint16x4_t cmp,const struct data * d)42 special_case (float32x4_t n, uint32x4_t u_off, float32x4_t p, float32x4_t r,
43 uint16x4_t cmp, const struct data *d)
44 {
45 /* Fall back to scalar code. */
46 return v_call_f32 (log2f, vreinterpretq_f32_u32 (vaddq_u32 (u_off, d->off)),
47 vfmaq_f32 (n, p, r), vmovl_u16 (cmp));
48 }
49
50 /* Fast implementation for single precision AdvSIMD log2,
51 relies on same argument reduction as AdvSIMD logf.
52 Maximum error: 2.48 ULPs
53 _ZGVnN4v_log2f(0x1.558174p+0) got 0x1.a9be84p-2
54 want 0x1.a9be8p-2. */
V_NAME_F1(log2)55 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (log2) (float32x4_t x)
56 {
57 const struct data *d = ptr_barrier (&data);
58
59 /* To avoid having to mov x out of the way, keep u after offset has been
60 applied, and recover x by adding the offset back in the special-case
61 handler. */
62 uint32x4_t u_off = vreinterpretq_u32_f32 (x);
63
64 /* x = 2^n * (1+r), where 2/3 < 1+r < 4/3. */
65 u_off = vsubq_u32 (u_off, d->off);
66 float32x4_t n = vcvtq_f32_s32 (
67 vshrq_n_s32 (vreinterpretq_s32_u32 (u_off), 23)); /* signextend. */
68
69 uint16x4_t special = vcge_u16 (vsubhn_u32 (u_off, d->offset_lower_bound),
70 vget_low_u16 (d->special_bound));
71
72 uint32x4_t u = vaddq_u32 (vandq_u32 (u_off, d->mantissa_mask), d->off);
73 float32x4_t r = vsubq_f32 (vreinterpretq_f32_u32 (u), v_f32 (1.0f));
74
75 /* y = log2(1+r) + n. */
76 float32x4_t r2 = vmulq_f32 (r, r);
77
78 float32x4_t c1357 = vld1q_f32 (&d->c1);
79 float32x4_t c01 = vfmaq_laneq_f32 (d->c0, r, c1357, 0);
80 float32x4_t c23 = vfmaq_laneq_f32 (d->c2, r, c1357, 1);
81 float32x4_t c45 = vfmaq_laneq_f32 (d->c4, r, c1357, 2);
82 float32x4_t c67 = vfmaq_laneq_f32 (d->c6, r, c1357, 3);
83 float32x4_t p68 = vfmaq_f32 (c67, r2, d->c8);
84 float32x4_t p48 = vfmaq_f32 (c45, r2, p68);
85 float32x4_t p28 = vfmaq_f32 (c23, r2, p48);
86 float32x4_t p = vfmaq_f32 (c01, r2, p28);
87
88 if (unlikely (v_any_u16h (special)))
89 return special_case (n, u_off, p, r, special, d);
90 return vfmaq_f32 (n, p, r);
91 }
92
93 HALF_WIDTH_ALIAS_F1 (log2)
94
95 TEST_SIG (V, F, 1, log2, 0.01, 11.1)
96 TEST_ULP (V_NAME_F1 (log2), 1.99)
97 TEST_INTERVAL (V_NAME_F1 (log2), -0.0, -0x1p126, 100)
98 TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-149, 0x1p-126, 4000)
99 TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-126, 0x1p-23, 50000)
100 TEST_INTERVAL (V_NAME_F1 (log2), 0x1p-23, 1.0, 50000)
101 TEST_INTERVAL (V_NAME_F1 (log2), 1.0, 100, 50000)
102 TEST_INTERVAL (V_NAME_F1 (log2), 100, inf, 50000)
103