1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/ib_user_verbs.h>
55 #include <rdma/ib_umem.h>
56 #include <rdma/ib_addr.h>
57 #include <linux/hashtable.h>
58
59 #include "bnxt_ulp.h"
60 #include "roce_hsi.h"
61 #include "qplib_res.h"
62 #include "qplib_sp.h"
63 #include "qplib_fp.h"
64 #include "qplib_rcfw.h"
65 #include "bnxt_re.h"
66 #include "ib_verbs.h"
67 #include <rdma/bnxt_re-abi.h>
68 #include "bnxt.h"
69 #include "hw_counters.h"
70
71 static char version[] =
72 BNXT_RE_DESC "\n";
73
74 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
75 MODULE_DESCRIPTION(BNXT_RE_DESC);
76 MODULE_LICENSE("Dual BSD/GPL");
77
78 /* globals */
79 static DEFINE_MUTEX(bnxt_re_mutex);
80
81 static void bnxt_re_stop_irq(void *handle);
82 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev);
83 static int bnxt_re_netdev_event(struct notifier_block *notifier,
84 unsigned long event, void *ptr);
85 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev);
86 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type);
87 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
88
89 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
90 u32 *offset);
91 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable);
bnxt_re_set_db_offset(struct bnxt_re_dev * rdev)92 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
93 {
94 struct bnxt_qplib_chip_ctx *cctx;
95 struct bnxt_en_dev *en_dev;
96 struct bnxt_qplib_res *res;
97 u32 l2db_len = 0;
98 u32 offset = 0;
99 u32 barlen;
100 int rc;
101
102 res = &rdev->qplib_res;
103 en_dev = rdev->en_dev;
104 cctx = rdev->chip_ctx;
105
106 /* Issue qcfg */
107 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
108 if (rc)
109 dev_info(rdev_to_dev(rdev),
110 "Couldn't get DB bar size, Low latency framework is disabled\n");
111 /* set register offsets for both UC and WC */
112 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
113 res->dpi_tbl.ucreg.offset = offset;
114 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
115 } else {
116 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
117 BNXT_QPLIB_DBR_PF_DB_OFFSET;
118 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
119 }
120
121 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
122 * is equal to the DB-Bar actual size. This indicates that L2
123 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
124 * in such cases and DB-push will be disabled.
125 */
126 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
127 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
128 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
129 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
130 }
131 }
132
bnxt_re_set_drv_mode(struct bnxt_re_dev * rdev)133 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev)
134 {
135 struct bnxt_qplib_chip_ctx *cctx;
136
137 cctx = rdev->chip_ctx;
138 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ?
139 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC;
140 if (bnxt_re_hwrm_qcaps(rdev))
141 dev_err(rdev_to_dev(rdev),
142 "Failed to query hwrm qcaps\n");
143 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) {
144 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;
145 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT;
146 }
147 }
148
bnxt_re_destroy_chip_ctx(struct bnxt_re_dev * rdev)149 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
150 {
151 struct bnxt_qplib_chip_ctx *chip_ctx;
152
153 if (!rdev->chip_ctx)
154 return;
155 chip_ctx = rdev->chip_ctx;
156 rdev->chip_ctx = NULL;
157 rdev->rcfw.res = NULL;
158 rdev->qplib_res.cctx = NULL;
159 rdev->qplib_res.pdev = NULL;
160 rdev->qplib_res.netdev = NULL;
161 kfree(chip_ctx);
162 }
163
bnxt_re_setup_chip_ctx(struct bnxt_re_dev * rdev)164 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
165 {
166 struct bnxt_qplib_chip_ctx *chip_ctx;
167 struct bnxt_en_dev *en_dev;
168 int rc;
169
170 en_dev = rdev->en_dev;
171
172 rdev->qplib_res.pdev = en_dev->pdev;
173 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
174 if (!chip_ctx)
175 return -ENOMEM;
176 chip_ctx->chip_num = en_dev->chip_num;
177 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
178
179 rdev->chip_ctx = chip_ctx;
180 /* rest members to follow eventually */
181
182 rdev->qplib_res.cctx = rdev->chip_ctx;
183 rdev->rcfw.res = &rdev->qplib_res;
184 rdev->qplib_res.dattr = &rdev->dev_attr;
185 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
186
187 bnxt_re_set_drv_mode(rdev);
188
189 bnxt_re_set_db_offset(rdev);
190 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
191 if (rc) {
192 kfree(rdev->chip_ctx);
193 rdev->chip_ctx = NULL;
194 return rc;
195 }
196
197 if (bnxt_qplib_determine_atomics(en_dev->pdev))
198 ibdev_info(&rdev->ibdev,
199 "platform doesn't support global atomics.");
200 return 0;
201 }
202
203 /* SR-IOV helper functions */
204
bnxt_re_get_sriov_func_type(struct bnxt_re_dev * rdev)205 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
206 {
207 if (BNXT_EN_VF(rdev->en_dev))
208 rdev->is_virtfn = 1;
209 }
210
211 /* Set the maximum number of each resource that the driver actually wants
212 * to allocate. This may be up to the maximum number the firmware has
213 * reserved for the function. The driver may choose to allocate fewer
214 * resources than the firmware maximum.
215 */
bnxt_re_limit_pf_res(struct bnxt_re_dev * rdev)216 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
217 {
218 struct bnxt_qplib_dev_attr *attr;
219 struct bnxt_qplib_ctx *ctx;
220 int i;
221
222 attr = &rdev->dev_attr;
223 ctx = &rdev->qplib_ctx;
224
225 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
226 attr->max_qp);
227 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
228 /* Use max_mr from fw since max_mrw does not get set */
229 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
230 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
231 attr->max_srq);
232 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
233 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
234 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
235 rdev->qplib_ctx.tqm_ctx.qcount[i] =
236 rdev->dev_attr.tqm_alloc_reqs[i];
237 }
238
bnxt_re_limit_vf_res(struct bnxt_qplib_ctx * qplib_ctx,u32 num_vf)239 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
240 {
241 struct bnxt_qplib_vf_res *vf_res;
242 u32 mrws = 0;
243 u32 vf_pct;
244 u32 nvfs;
245
246 vf_res = &qplib_ctx->vf_res;
247 /*
248 * Reserve a set of resources for the PF. Divide the remaining
249 * resources among the VFs
250 */
251 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
252 nvfs = num_vf;
253 num_vf = 100 * num_vf;
254 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
255 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
256 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
257 /*
258 * The driver allows many more MRs than other resources. If the
259 * firmware does also, then reserve a fixed amount for the PF and
260 * divide the rest among VFs. VFs may use many MRs for NFS
261 * mounts, ISER, NVME applications, etc. If the firmware severely
262 * restricts the number of MRs, then let PF have half and divide
263 * the rest among VFs, as for the other resource types.
264 */
265 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
266 mrws = qplib_ctx->mrw_count * vf_pct;
267 nvfs = num_vf;
268 } else {
269 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
270 }
271 vf_res->max_mrw_per_vf = (mrws / nvfs);
272 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
273 }
274
bnxt_re_set_resource_limits(struct bnxt_re_dev * rdev)275 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
276 {
277 u32 num_vfs;
278
279 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
280 bnxt_re_limit_pf_res(rdev);
281
282 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
283 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
284 if (num_vfs)
285 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
286 }
287
bnxt_re_vf_res_config(struct bnxt_re_dev * rdev)288 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
289 {
290 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
291 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
292 bnxt_re_set_resource_limits(rdev);
293 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
294 &rdev->qplib_ctx);
295 }
296 }
297
bnxt_re_shutdown(struct auxiliary_device * adev)298 static void bnxt_re_shutdown(struct auxiliary_device *adev)
299 {
300 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
301 struct bnxt_re_dev *rdev;
302
303 if (!en_info)
304 return;
305
306 rdev = en_info->rdev;
307 ib_unregister_device(&rdev->ibdev);
308 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
309 }
310
bnxt_re_stop_irq(void * handle)311 static void bnxt_re_stop_irq(void *handle)
312 {
313 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
314 struct bnxt_qplib_rcfw *rcfw;
315 struct bnxt_re_dev *rdev;
316 struct bnxt_qplib_nq *nq;
317 int indx;
318
319 if (!en_info)
320 return;
321
322 rdev = en_info->rdev;
323 rcfw = &rdev->rcfw;
324
325 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) {
326 nq = &rdev->nq[indx - 1];
327 bnxt_qplib_nq_stop_irq(nq, false);
328 }
329
330 bnxt_qplib_rcfw_stop_irq(rcfw, false);
331 }
332
bnxt_re_start_irq(void * handle,struct bnxt_msix_entry * ent)333 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
334 {
335 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
336 struct bnxt_msix_entry *msix_ent;
337 struct bnxt_qplib_rcfw *rcfw;
338 struct bnxt_re_dev *rdev;
339 struct bnxt_qplib_nq *nq;
340 int indx, rc;
341
342 if (!en_info)
343 return;
344
345 rdev = en_info->rdev;
346 msix_ent = rdev->en_dev->msix_entries;
347 rcfw = &rdev->rcfw;
348 if (!ent) {
349 /* Not setting the f/w timeout bit in rcfw.
350 * During the driver unload the first command
351 * to f/w will timeout and that will set the
352 * timeout bit.
353 */
354 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
355 return;
356 }
357
358 /* Vectors may change after restart, so update with new vectors
359 * in device sctructure.
360 */
361 for (indx = 0; indx < rdev->num_msix; indx++)
362 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector;
363
364 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
365 false);
366 if (rc) {
367 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
368 return;
369 }
370 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) {
371 nq = &rdev->nq[indx - 1];
372 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
373 msix_ent[indx].vector, false);
374 if (rc) {
375 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
376 indx - 1);
377 return;
378 }
379 }
380 }
381
382 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
383 .ulp_irq_stop = bnxt_re_stop_irq,
384 .ulp_irq_restart = bnxt_re_start_irq
385 };
386
387 /* RoCE -> Net driver */
388
bnxt_re_register_netdev(struct bnxt_re_dev * rdev)389 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
390 {
391 struct bnxt_en_dev *en_dev;
392
393 en_dev = rdev->en_dev;
394 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev);
395 }
396
bnxt_re_init_hwrm_hdr(struct input * hdr,u16 opcd)397 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
398 {
399 hdr->req_type = cpu_to_le16(opcd);
400 hdr->cmpl_ring = cpu_to_le16(-1);
401 hdr->target_id = cpu_to_le16(-1);
402 }
403
bnxt_re_fill_fw_msg(struct bnxt_fw_msg * fw_msg,void * msg,int msg_len,void * resp,int resp_max_len,int timeout)404 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
405 int msg_len, void *resp, int resp_max_len,
406 int timeout)
407 {
408 fw_msg->msg = msg;
409 fw_msg->msg_len = msg_len;
410 fw_msg->resp = resp;
411 fw_msg->resp_max_len = resp_max_len;
412 fw_msg->timeout = timeout;
413 }
414
415 /* Query device config using common hwrm */
bnxt_re_hwrm_qcfg(struct bnxt_re_dev * rdev,u32 * db_len,u32 * offset)416 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
417 u32 *offset)
418 {
419 struct bnxt_en_dev *en_dev = rdev->en_dev;
420 struct hwrm_func_qcfg_output resp = {0};
421 struct hwrm_func_qcfg_input req = {0};
422 struct bnxt_fw_msg fw_msg = {};
423 int rc;
424
425 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
426 req.fid = cpu_to_le16(0xffff);
427 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
428 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
429 rc = bnxt_send_msg(en_dev, &fw_msg);
430 if (!rc) {
431 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
432 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
433 }
434 return rc;
435 }
436
437 /* Query function capabilities using common hwrm */
bnxt_re_hwrm_qcaps(struct bnxt_re_dev * rdev)438 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
439 {
440 struct bnxt_en_dev *en_dev = rdev->en_dev;
441 struct hwrm_func_qcaps_output resp = {};
442 struct hwrm_func_qcaps_input req = {};
443 struct bnxt_qplib_chip_ctx *cctx;
444 struct bnxt_fw_msg fw_msg = {};
445 u32 flags_ext2;
446 int rc;
447
448 cctx = rdev->chip_ctx;
449 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
450 req.fid = cpu_to_le16(0xffff);
451 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
452 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
453
454 rc = bnxt_send_msg(en_dev, &fw_msg);
455 if (rc)
456 return rc;
457 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
458
459 flags_ext2 = le32_to_cpu(resp.flags_ext2);
460 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED ||
461 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED;
462 return 0;
463 }
464
bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev * rdev)465 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
466 {
467 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
468 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
469 struct hwrm_func_dbr_pacing_qcfg_input req = {};
470 struct bnxt_en_dev *en_dev = rdev->en_dev;
471 struct bnxt_qplib_chip_ctx *cctx;
472 struct bnxt_fw_msg fw_msg = {};
473 int rc;
474
475 cctx = rdev->chip_ctx;
476 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
477 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
478 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
479 rc = bnxt_send_msg(en_dev, &fw_msg);
480 if (rc)
481 return rc;
482
483 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
484 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
485 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
486 cctx->dbr_stat_db_fifo =
487 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
488 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
489
490 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth);
491 if (!pacing_data->fifo_max_depth)
492 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx);
493 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask);
494 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift;
495
496 return 0;
497 }
498
499 /* Update the pacing tunable parameters to the default values */
bnxt_re_set_default_pacing_data(struct bnxt_re_dev * rdev)500 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
501 {
502 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
503
504 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
505 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
506 pacing_data->alarm_th =
507 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
508 }
509
__get_fifo_occupancy(struct bnxt_re_dev * rdev)510 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev)
511 {
512 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
513 u32 read_val, fifo_occup;
514
515 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
516 fifo_occup = pacing_data->fifo_max_depth -
517 ((read_val & pacing_data->fifo_room_mask) >>
518 pacing_data->fifo_room_shift);
519 return fifo_occup;
520 }
521
is_dbr_fifo_full(struct bnxt_re_dev * rdev)522 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev)
523 {
524 u32 max_occup, fifo_occup;
525
526 fifo_occup = __get_fifo_occupancy(rdev);
527 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1;
528 if (fifo_occup == max_occup)
529 return true;
530
531 return false;
532 }
533
__wait_for_fifo_occupancy_below_th(struct bnxt_re_dev * rdev)534 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
535 {
536 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
537 u32 retry_fifo_check = 1000;
538 u32 fifo_occup;
539
540 /* loop shouldn't run infintely as the occupancy usually goes
541 * below pacing algo threshold as soon as pacing kicks in.
542 */
543 while (1) {
544 fifo_occup = __get_fifo_occupancy(rdev);
545 /* Fifo occupancy cannot be greater the MAX FIFO depth */
546 if (fifo_occup > pacing_data->fifo_max_depth)
547 break;
548
549 if (fifo_occup < pacing_data->pacing_th)
550 break;
551 if (!retry_fifo_check--) {
552 dev_info_once(rdev_to_dev(rdev),
553 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n",
554 __func__, fifo_occup, pacing_data->fifo_max_depth,
555 pacing_data->pacing_th);
556 break;
557 }
558
559 }
560 }
561
bnxt_re_db_fifo_check(struct work_struct * work)562 static void bnxt_re_db_fifo_check(struct work_struct *work)
563 {
564 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
565 dbq_fifo_check_work);
566 struct bnxt_qplib_db_pacing_data *pacing_data;
567 u32 pacing_save;
568
569 if (!mutex_trylock(&rdev->pacing.dbq_lock))
570 return;
571 pacing_data = rdev->qplib_res.pacing_data;
572 pacing_save = rdev->pacing.do_pacing_save;
573 __wait_for_fifo_occupancy_below_th(rdev);
574 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
575 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
576 /* Double the do_pacing value during the congestion */
577 pacing_save = pacing_save << 1;
578 } else {
579 /*
580 * when a new congestion is detected increase the do_pacing
581 * by 8 times. And also increase the pacing_th by 4 times. The
582 * reason to increase pacing_th is to give more space for the
583 * queue to oscillate down without getting empty, but also more
584 * room for the queue to increase without causing another alarm.
585 */
586 pacing_save = pacing_save << 3;
587 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
588 }
589
590 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
591 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
592
593 pacing_data->do_pacing = pacing_save;
594 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
595 pacing_data->alarm_th =
596 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
597 schedule_delayed_work(&rdev->dbq_pacing_work,
598 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
599 rdev->stats.pacing.alerts++;
600 mutex_unlock(&rdev->pacing.dbq_lock);
601 }
602
bnxt_re_pacing_timer_exp(struct work_struct * work)603 static void bnxt_re_pacing_timer_exp(struct work_struct *work)
604 {
605 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
606 dbq_pacing_work.work);
607 struct bnxt_qplib_db_pacing_data *pacing_data;
608 u32 fifo_occup;
609
610 if (!mutex_trylock(&rdev->pacing.dbq_lock))
611 return;
612
613 pacing_data = rdev->qplib_res.pacing_data;
614 fifo_occup = __get_fifo_occupancy(rdev);
615
616 if (fifo_occup > pacing_data->pacing_th)
617 goto restart_timer;
618
619 /*
620 * Instead of immediately going back to the default do_pacing
621 * reduce it by 1/8 times and restart the timer.
622 */
623 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
624 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
625 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
626 bnxt_re_set_default_pacing_data(rdev);
627 rdev->stats.pacing.complete++;
628 goto dbq_unlock;
629 }
630
631 restart_timer:
632 schedule_delayed_work(&rdev->dbq_pacing_work,
633 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
634 rdev->stats.pacing.resched++;
635 dbq_unlock:
636 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
637 mutex_unlock(&rdev->pacing.dbq_lock);
638 }
639
bnxt_re_pacing_alert(struct bnxt_re_dev * rdev)640 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
641 {
642 struct bnxt_qplib_db_pacing_data *pacing_data;
643
644 if (!rdev->pacing.dbr_pacing)
645 return;
646 mutex_lock(&rdev->pacing.dbq_lock);
647 pacing_data = rdev->qplib_res.pacing_data;
648
649 /*
650 * Increase the alarm_th to max so that other user lib instances do not
651 * keep alerting the driver.
652 */
653 pacing_data->alarm_th = pacing_data->fifo_max_depth;
654 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
655 cancel_work_sync(&rdev->dbq_fifo_check_work);
656 schedule_work(&rdev->dbq_fifo_check_work);
657 mutex_unlock(&rdev->pacing.dbq_lock);
658 }
659
bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev * rdev)660 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
661 {
662 /* Allocate a page for app use */
663 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
664 if (!rdev->pacing.dbr_page)
665 return -ENOMEM;
666
667 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
668 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
669
670 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) {
671 free_page((u64)rdev->pacing.dbr_page);
672 rdev->pacing.dbr_page = NULL;
673 return -EIO;
674 }
675
676 /* MAP HW window 2 for reading db fifo depth */
677 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
678 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
679 rdev->pacing.dbr_db_fifo_reg_off =
680 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
681 BNXT_RE_GRC_FIFO_REG_BASE;
682 rdev->pacing.dbr_bar_addr =
683 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
684
685 if (is_dbr_fifo_full(rdev)) {
686 free_page((u64)rdev->pacing.dbr_page);
687 rdev->pacing.dbr_page = NULL;
688 return -EIO;
689 }
690
691 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
692 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
693 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
694 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
695 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
696 bnxt_re_set_default_pacing_data(rdev);
697 /* Initialize worker for DBR Pacing */
698 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
699 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
700 return 0;
701 }
702
bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev * rdev)703 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
704 {
705 cancel_work_sync(&rdev->dbq_fifo_check_work);
706 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
707 if (rdev->pacing.dbr_page)
708 free_page((u64)rdev->pacing.dbr_page);
709
710 rdev->pacing.dbr_page = NULL;
711 rdev->pacing.dbr_pacing = false;
712 }
713
bnxt_re_net_ring_free(struct bnxt_re_dev * rdev,u16 fw_ring_id,int type)714 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
715 u16 fw_ring_id, int type)
716 {
717 struct bnxt_en_dev *en_dev;
718 struct hwrm_ring_free_input req = {};
719 struct hwrm_ring_free_output resp;
720 struct bnxt_fw_msg fw_msg = {};
721 int rc = -EINVAL;
722
723 if (!rdev)
724 return rc;
725
726 en_dev = rdev->en_dev;
727
728 if (!en_dev)
729 return rc;
730
731 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
732 return 0;
733
734 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
735 req.ring_type = type;
736 req.ring_id = cpu_to_le16(fw_ring_id);
737 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
738 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
739 rc = bnxt_send_msg(en_dev, &fw_msg);
740 if (rc)
741 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
742 req.ring_id, rc);
743 return rc;
744 }
745
bnxt_re_net_ring_alloc(struct bnxt_re_dev * rdev,struct bnxt_re_ring_attr * ring_attr,u16 * fw_ring_id)746 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
747 struct bnxt_re_ring_attr *ring_attr,
748 u16 *fw_ring_id)
749 {
750 struct bnxt_en_dev *en_dev = rdev->en_dev;
751 struct hwrm_ring_alloc_input req = {};
752 struct hwrm_ring_alloc_output resp;
753 struct bnxt_fw_msg fw_msg = {};
754 int rc = -EINVAL;
755
756 if (!en_dev)
757 return rc;
758
759 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
760 req.enables = 0;
761 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
762 if (ring_attr->pages > 1) {
763 /* Page size is in log2 units */
764 req.page_size = BNXT_PAGE_SHIFT;
765 req.page_tbl_depth = 1;
766 }
767 req.fbo = 0;
768 /* Association of ring index with doorbell index and MSIX number */
769 req.logical_id = cpu_to_le16(ring_attr->lrid);
770 req.length = cpu_to_le32(ring_attr->depth + 1);
771 req.ring_type = ring_attr->type;
772 req.int_mode = ring_attr->mode;
773 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
774 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
775 rc = bnxt_send_msg(en_dev, &fw_msg);
776 if (!rc)
777 *fw_ring_id = le16_to_cpu(resp.ring_id);
778
779 return rc;
780 }
781
bnxt_re_net_stats_ctx_free(struct bnxt_re_dev * rdev,u32 fw_stats_ctx_id)782 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
783 u32 fw_stats_ctx_id)
784 {
785 struct bnxt_en_dev *en_dev = rdev->en_dev;
786 struct hwrm_stat_ctx_free_input req = {};
787 struct hwrm_stat_ctx_free_output resp = {};
788 struct bnxt_fw_msg fw_msg = {};
789 int rc = -EINVAL;
790
791 if (!en_dev)
792 return rc;
793
794 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
795 return 0;
796
797 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
798 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
799 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
800 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
801 rc = bnxt_send_msg(en_dev, &fw_msg);
802 if (rc)
803 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
804 rc);
805
806 return rc;
807 }
808
bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev * rdev,dma_addr_t dma_map,u32 * fw_stats_ctx_id)809 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
810 dma_addr_t dma_map,
811 u32 *fw_stats_ctx_id)
812 {
813 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
814 struct hwrm_stat_ctx_alloc_output resp = {};
815 struct hwrm_stat_ctx_alloc_input req = {};
816 struct bnxt_en_dev *en_dev = rdev->en_dev;
817 struct bnxt_fw_msg fw_msg = {};
818 int rc = -EINVAL;
819
820 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
821
822 if (!en_dev)
823 return rc;
824
825 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
826 req.update_period_ms = cpu_to_le32(1000);
827 req.stats_dma_addr = cpu_to_le64(dma_map);
828 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
829 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
830 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
831 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
832 rc = bnxt_send_msg(en_dev, &fw_msg);
833 if (!rc)
834 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
835
836 return rc;
837 }
838
bnxt_re_disassociate_ucontext(struct ib_ucontext * ibcontext)839 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
840 {
841 }
842
843 /* Device */
844
bnxt_re_from_netdev(struct net_device * netdev)845 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
846 {
847 struct ib_device *ibdev =
848 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE);
849 if (!ibdev)
850 return NULL;
851
852 return container_of(ibdev, struct bnxt_re_dev, ibdev);
853 }
854
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)855 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
856 char *buf)
857 {
858 struct bnxt_re_dev *rdev =
859 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
860
861 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
862 }
863 static DEVICE_ATTR_RO(hw_rev);
864
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)865 static ssize_t hca_type_show(struct device *device,
866 struct device_attribute *attr, char *buf)
867 {
868 struct bnxt_re_dev *rdev =
869 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
870
871 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
872 }
873 static DEVICE_ATTR_RO(hca_type);
874
875 static struct attribute *bnxt_re_attributes[] = {
876 &dev_attr_hw_rev.attr,
877 &dev_attr_hca_type.attr,
878 NULL
879 };
880
881 static const struct attribute_group bnxt_re_dev_attr_group = {
882 .attrs = bnxt_re_attributes,
883 };
884
885 static const struct ib_device_ops bnxt_re_dev_ops = {
886 .owner = THIS_MODULE,
887 .driver_id = RDMA_DRIVER_BNXT_RE,
888 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
889
890 .add_gid = bnxt_re_add_gid,
891 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
892 .alloc_mr = bnxt_re_alloc_mr,
893 .alloc_pd = bnxt_re_alloc_pd,
894 .alloc_ucontext = bnxt_re_alloc_ucontext,
895 .create_ah = bnxt_re_create_ah,
896 .create_cq = bnxt_re_create_cq,
897 .create_qp = bnxt_re_create_qp,
898 .create_srq = bnxt_re_create_srq,
899 .create_user_ah = bnxt_re_create_ah,
900 .dealloc_pd = bnxt_re_dealloc_pd,
901 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
902 .del_gid = bnxt_re_del_gid,
903 .dereg_mr = bnxt_re_dereg_mr,
904 .destroy_ah = bnxt_re_destroy_ah,
905 .destroy_cq = bnxt_re_destroy_cq,
906 .destroy_qp = bnxt_re_destroy_qp,
907 .destroy_srq = bnxt_re_destroy_srq,
908 .device_group = &bnxt_re_dev_attr_group,
909 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
910 .get_dev_fw_str = bnxt_re_query_fw_str,
911 .get_dma_mr = bnxt_re_get_dma_mr,
912 .get_hw_stats = bnxt_re_ib_get_hw_stats,
913 .get_link_layer = bnxt_re_get_link_layer,
914 .get_port_immutable = bnxt_re_get_port_immutable,
915 .map_mr_sg = bnxt_re_map_mr_sg,
916 .mmap = bnxt_re_mmap,
917 .mmap_free = bnxt_re_mmap_free,
918 .modify_qp = bnxt_re_modify_qp,
919 .modify_srq = bnxt_re_modify_srq,
920 .poll_cq = bnxt_re_poll_cq,
921 .post_recv = bnxt_re_post_recv,
922 .post_send = bnxt_re_post_send,
923 .post_srq_recv = bnxt_re_post_srq_recv,
924 .query_ah = bnxt_re_query_ah,
925 .query_device = bnxt_re_query_device,
926 .query_pkey = bnxt_re_query_pkey,
927 .query_port = bnxt_re_query_port,
928 .query_qp = bnxt_re_query_qp,
929 .query_srq = bnxt_re_query_srq,
930 .reg_user_mr = bnxt_re_reg_user_mr,
931 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
932 .req_notify_cq = bnxt_re_req_notify_cq,
933 .resize_cq = bnxt_re_resize_cq,
934 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
935 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
936 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
937 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
938 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
939 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
940 };
941
bnxt_re_register_ib(struct bnxt_re_dev * rdev)942 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
943 {
944 struct ib_device *ibdev = &rdev->ibdev;
945 int ret;
946
947 /* ib device init */
948 ibdev->node_type = RDMA_NODE_IB_CA;
949 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
950 strlen(BNXT_RE_DESC) + 5);
951 ibdev->phys_port_cnt = 1;
952
953 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
954
955 ibdev->num_comp_vectors = rdev->num_msix - 1;
956 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
957 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
958
959 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
960 ibdev->driver_def = bnxt_re_uapi_defs;
961
962 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
963 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
964 if (ret)
965 return ret;
966
967 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
968 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
969 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
970 }
971
bnxt_re_dev_add(struct auxiliary_device * adev,struct bnxt_en_dev * en_dev)972 static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev,
973 struct bnxt_en_dev *en_dev)
974 {
975 struct bnxt_re_dev *rdev;
976
977 /* Allocate bnxt_re_dev instance here */
978 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
979 if (!rdev) {
980 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
981 ROCE_DRV_MODULE_NAME);
982 return NULL;
983 }
984 /* Default values */
985 rdev->nb.notifier_call = NULL;
986 rdev->netdev = en_dev->net;
987 rdev->en_dev = en_dev;
988 rdev->adev = adev;
989 rdev->id = rdev->en_dev->pdev->devfn;
990 INIT_LIST_HEAD(&rdev->qp_list);
991 mutex_init(&rdev->qp_lock);
992 mutex_init(&rdev->pacing.dbq_lock);
993 atomic_set(&rdev->stats.res.qp_count, 0);
994 atomic_set(&rdev->stats.res.cq_count, 0);
995 atomic_set(&rdev->stats.res.srq_count, 0);
996 atomic_set(&rdev->stats.res.mr_count, 0);
997 atomic_set(&rdev->stats.res.mw_count, 0);
998 atomic_set(&rdev->stats.res.ah_count, 0);
999 atomic_set(&rdev->stats.res.pd_count, 0);
1000 rdev->cosq[0] = 0xFFFF;
1001 rdev->cosq[1] = 0xFFFF;
1002
1003 return rdev;
1004 }
1005
bnxt_re_handle_unaffi_async_event(struct creq_func_event * unaffi_async)1006 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
1007 *unaffi_async)
1008 {
1009 switch (unaffi_async->event) {
1010 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
1011 break;
1012 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
1013 break;
1014 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
1015 break;
1016 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
1017 break;
1018 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
1019 break;
1020 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
1021 break;
1022 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
1023 break;
1024 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
1025 break;
1026 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
1027 break;
1028 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
1029 break;
1030 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035 return 0;
1036 }
1037
bnxt_re_handle_qp_async_event(struct creq_qp_event * qp_event,struct bnxt_re_qp * qp)1038 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
1039 struct bnxt_re_qp *qp)
1040 {
1041 struct creq_qp_error_notification *err_event;
1042 struct bnxt_re_srq *srq = NULL;
1043 struct ib_event event = {};
1044 unsigned int flags;
1045
1046 if (qp->qplib_qp.srq)
1047 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq,
1048 qplib_srq);
1049
1050 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
1051 rdma_is_kernel_res(&qp->ib_qp.res)) {
1052 flags = bnxt_re_lock_cqs(qp);
1053 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1054 bnxt_re_unlock_cqs(qp, flags);
1055 }
1056
1057 event.device = &qp->rdev->ibdev;
1058 event.element.qp = &qp->ib_qp;
1059 event.event = IB_EVENT_QP_FATAL;
1060
1061 err_event = (struct creq_qp_error_notification *)qp_event;
1062
1063 switch (err_event->req_err_state_reason) {
1064 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR:
1065 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT:
1066 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT:
1067 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2:
1068 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3:
1069 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP:
1070 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND:
1071 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG:
1072 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE:
1073 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR:
1074 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR:
1075 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR:
1076 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR:
1077 event.event = IB_EVENT_QP_ACCESS_ERR;
1078 break;
1079 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1:
1080 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4:
1081 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH:
1082 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR:
1083 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR:
1084 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR:
1085 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR:
1086 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR:
1087 event.event = IB_EVENT_QP_REQ_ERR;
1088 break;
1089 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR:
1090 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR:
1091 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR:
1092 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR:
1093 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR:
1094 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR:
1095 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR:
1096 event.event = IB_EVENT_QP_FATAL;
1097 break;
1098
1099 default:
1100 break;
1101 }
1102
1103 switch (err_event->res_err_state_reason) {
1104 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX:
1105 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH:
1106 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT:
1107 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY:
1108 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR:
1109 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION:
1110 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR:
1111 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY:
1112 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR:
1113 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION:
1114 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR:
1115 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC:
1116 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND:
1117 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY:
1118 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR:
1119 event.event = IB_EVENT_QP_ACCESS_ERR;
1120 break;
1121 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE:
1122 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR:
1123 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE:
1124 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE:
1125 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR:
1126 event.event = IB_EVENT_QP_REQ_ERR;
1127 break;
1128 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW:
1129 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR:
1130 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR:
1131 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR:
1132 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR:
1133 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR:
1134 event.event = IB_EVENT_QP_FATAL;
1135 break;
1136 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR:
1137 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR:
1138 if (srq)
1139 event.event = IB_EVENT_SRQ_ERR;
1140 break;
1141 default:
1142 break;
1143 }
1144
1145 if (err_event->res_err_state_reason || err_event->req_err_state_reason) {
1146 ibdev_dbg(&qp->rdev->ibdev,
1147 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n",
1148 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user",
1149 qp->qplib_qp.id,
1150 err_event->sq_cons_idx,
1151 err_event->rq_cons_idx,
1152 err_event->req_slow_path_state,
1153 err_event->req_err_state_reason,
1154 err_event->res_slow_path_state,
1155 err_event->res_err_state_reason);
1156 } else {
1157 if (srq)
1158 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
1159 }
1160
1161 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) {
1162 (*srq->ib_srq.event_handler)(&event,
1163 srq->ib_srq.srq_context);
1164 } else if (event.device && qp->ib_qp.event_handler) {
1165 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
1166 }
1167
1168 return 0;
1169 }
1170
bnxt_re_handle_cq_async_error(void * event,struct bnxt_re_cq * cq)1171 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq)
1172 {
1173 struct creq_cq_error_notification *cqerr;
1174 struct ib_event ibevent = {};
1175
1176 cqerr = event;
1177 switch (cqerr->cq_err_reason) {
1178 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR:
1179 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR:
1180 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR:
1181 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR:
1182 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR:
1183 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR:
1184 ibevent.event = IB_EVENT_CQ_ERR;
1185 break;
1186 default:
1187 break;
1188 }
1189
1190 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) {
1191 ibevent.element.cq = &cq->ib_cq;
1192 ibevent.device = &cq->rdev->ibdev;
1193
1194 ibdev_dbg(&cq->rdev->ibdev,
1195 "%s err reason %d\n", __func__, cqerr->cq_err_reason);
1196 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context);
1197 }
1198
1199 return 0;
1200 }
1201
bnxt_re_handle_affi_async_event(struct creq_qp_event * affi_async,void * obj)1202 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1203 void *obj)
1204 {
1205 struct bnxt_qplib_qp *lib_qp;
1206 struct bnxt_qplib_cq *lib_cq;
1207 struct bnxt_re_qp *qp;
1208 struct bnxt_re_cq *cq;
1209 int rc = 0;
1210 u8 event;
1211
1212 if (!obj)
1213 return rc; /* QP was already dead, still return success */
1214
1215 event = affi_async->event;
1216 switch (event) {
1217 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
1218 lib_qp = obj;
1219 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp);
1220 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1221 break;
1222 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION:
1223 lib_cq = obj;
1224 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq);
1225 rc = bnxt_re_handle_cq_async_error(affi_async, cq);
1226 break;
1227 default:
1228 rc = -EINVAL;
1229 }
1230 return rc;
1231 }
1232
bnxt_re_aeq_handler(struct bnxt_qplib_rcfw * rcfw,void * aeqe,void * obj)1233 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1234 void *aeqe, void *obj)
1235 {
1236 struct creq_qp_event *affi_async;
1237 struct creq_func_event *unaffi_async;
1238 u8 type;
1239 int rc;
1240
1241 type = ((struct creq_base *)aeqe)->type;
1242 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1243 unaffi_async = aeqe;
1244 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1245 } else {
1246 affi_async = aeqe;
1247 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1248 }
1249
1250 return rc;
1251 }
1252
bnxt_re_srqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_srq * handle,u8 event)1253 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1254 struct bnxt_qplib_srq *handle, u8 event)
1255 {
1256 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1257 qplib_srq);
1258 struct ib_event ib_event;
1259
1260 ib_event.device = &srq->rdev->ibdev;
1261 ib_event.element.srq = &srq->ib_srq;
1262
1263 if (srq->ib_srq.event_handler) {
1264 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1265 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1266 (*srq->ib_srq.event_handler)(&ib_event,
1267 srq->ib_srq.srq_context);
1268 }
1269 return 0;
1270 }
1271
bnxt_re_cqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_cq * handle)1272 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1273 struct bnxt_qplib_cq *handle)
1274 {
1275 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1276 qplib_cq);
1277
1278 if (cq->ib_cq.comp_handler)
1279 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1280
1281 return 0;
1282 }
1283
bnxt_re_cleanup_res(struct bnxt_re_dev * rdev)1284 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1285 {
1286 int i;
1287
1288 for (i = 1; i < rdev->num_msix; i++)
1289 bnxt_qplib_disable_nq(&rdev->nq[i - 1]);
1290
1291 if (rdev->qplib_res.rcfw)
1292 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1293 }
1294
bnxt_re_init_res(struct bnxt_re_dev * rdev)1295 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1296 {
1297 int num_vec_enabled = 0;
1298 int rc = 0, i;
1299 u32 db_offt;
1300
1301 bnxt_qplib_init_res(&rdev->qplib_res);
1302
1303 for (i = 1; i < rdev->num_msix ; i++) {
1304 db_offt = rdev->en_dev->msix_entries[i].db_offset;
1305 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
1306 i - 1, rdev->en_dev->msix_entries[i].vector,
1307 db_offt, &bnxt_re_cqn_handler,
1308 &bnxt_re_srqn_handler);
1309 if (rc) {
1310 ibdev_err(&rdev->ibdev,
1311 "Failed to enable NQ with rc = 0x%x", rc);
1312 goto fail;
1313 }
1314 num_vec_enabled++;
1315 }
1316 return 0;
1317 fail:
1318 for (i = num_vec_enabled; i >= 0; i--)
1319 bnxt_qplib_disable_nq(&rdev->nq[i]);
1320 return rc;
1321 }
1322
bnxt_re_free_nq_res(struct bnxt_re_dev * rdev)1323 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1324 {
1325 u8 type;
1326 int i;
1327
1328 for (i = 0; i < rdev->num_msix - 1; i++) {
1329 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1330 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1331 bnxt_qplib_free_nq(&rdev->nq[i]);
1332 rdev->nq[i].res = NULL;
1333 }
1334 }
1335
bnxt_re_free_res(struct bnxt_re_dev * rdev)1336 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1337 {
1338 bnxt_re_free_nq_res(rdev);
1339
1340 if (rdev->qplib_res.dpi_tbl.max) {
1341 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1342 &rdev->dpi_privileged);
1343 }
1344 if (rdev->qplib_res.rcfw) {
1345 bnxt_qplib_free_res(&rdev->qplib_res);
1346 rdev->qplib_res.rcfw = NULL;
1347 }
1348 }
1349
bnxt_re_alloc_res(struct bnxt_re_dev * rdev)1350 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1351 {
1352 struct bnxt_re_ring_attr rattr = {};
1353 int num_vec_created = 0;
1354 int rc, i;
1355 u8 type;
1356
1357 /* Configure and allocate resources for qplib */
1358 rdev->qplib_res.rcfw = &rdev->rcfw;
1359 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr);
1360 if (rc)
1361 goto fail;
1362
1363 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev,
1364 rdev->netdev, &rdev->dev_attr);
1365 if (rc)
1366 goto fail;
1367
1368 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1369 &rdev->dpi_privileged,
1370 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1371 if (rc)
1372 goto dealloc_res;
1373
1374 for (i = 0; i < rdev->num_msix - 1; i++) {
1375 struct bnxt_qplib_nq *nq;
1376
1377 nq = &rdev->nq[i];
1378 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1379 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]);
1380 if (rc) {
1381 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1382 i, rc);
1383 goto free_nq;
1384 }
1385 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1386 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1387 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count;
1388 rattr.type = type;
1389 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1390 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1391 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx;
1392 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1393 if (rc) {
1394 ibdev_err(&rdev->ibdev,
1395 "Failed to allocate NQ fw id with rc = 0x%x",
1396 rc);
1397 bnxt_qplib_free_nq(&rdev->nq[i]);
1398 goto free_nq;
1399 }
1400 num_vec_created++;
1401 }
1402 return 0;
1403 free_nq:
1404 for (i = num_vec_created - 1; i >= 0; i--) {
1405 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1406 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1407 bnxt_qplib_free_nq(&rdev->nq[i]);
1408 }
1409 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1410 &rdev->dpi_privileged);
1411 dealloc_res:
1412 bnxt_qplib_free_res(&rdev->qplib_res);
1413
1414 fail:
1415 rdev->qplib_res.rcfw = NULL;
1416 return rc;
1417 }
1418
bnxt_re_dispatch_event(struct ib_device * ibdev,struct ib_qp * qp,u8 port_num,enum ib_event_type event)1419 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1420 u8 port_num, enum ib_event_type event)
1421 {
1422 struct ib_event ib_event;
1423
1424 ib_event.device = ibdev;
1425 if (qp) {
1426 ib_event.element.qp = qp;
1427 ib_event.event = event;
1428 if (qp->event_handler)
1429 qp->event_handler(&ib_event, qp->qp_context);
1430
1431 } else {
1432 ib_event.element.port_num = port_num;
1433 ib_event.event = event;
1434 ib_dispatch_event(&ib_event);
1435 }
1436 }
1437
bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)1438 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1439 struct bnxt_re_qp *qp)
1440 {
1441 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1442 (qp == rdev->gsi_ctx.gsi_sqp);
1443 }
1444
bnxt_re_dev_stop(struct bnxt_re_dev * rdev)1445 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1446 {
1447 int mask = IB_QP_STATE;
1448 struct ib_qp_attr qp_attr;
1449 struct bnxt_re_qp *qp;
1450
1451 qp_attr.qp_state = IB_QPS_ERR;
1452 mutex_lock(&rdev->qp_lock);
1453 list_for_each_entry(qp, &rdev->qp_list, list) {
1454 /* Modify the state of all QPs except QP1/Shadow QP */
1455 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1456 if (qp->qplib_qp.state !=
1457 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1458 qp->qplib_qp.state !=
1459 CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1460 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1461 1, IB_EVENT_QP_FATAL);
1462 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask,
1463 NULL);
1464 }
1465 }
1466 }
1467 mutex_unlock(&rdev->qp_lock);
1468 }
1469
bnxt_re_update_gid(struct bnxt_re_dev * rdev)1470 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1471 {
1472 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1473 struct bnxt_qplib_gid gid;
1474 u16 gid_idx, index;
1475 int rc = 0;
1476
1477 if (!ib_device_try_get(&rdev->ibdev))
1478 return 0;
1479
1480 for (index = 0; index < sgid_tbl->active; index++) {
1481 gid_idx = sgid_tbl->hw_id[index];
1482
1483 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1484 sizeof(bnxt_qplib_gid_zero)))
1485 continue;
1486 /* need to modify the VLAN enable setting of non VLAN GID only
1487 * as setting is done for VLAN GID while adding GID
1488 */
1489 if (sgid_tbl->vlan[index])
1490 continue;
1491
1492 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1493
1494 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1495 rdev->qplib_res.netdev->dev_addr);
1496 }
1497
1498 ib_device_put(&rdev->ibdev);
1499 return rc;
1500 }
1501
bnxt_re_get_priority_mask(struct bnxt_re_dev * rdev)1502 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1503 {
1504 u32 prio_map = 0, tmp_map = 0;
1505 struct net_device *netdev;
1506 struct dcb_app app = {};
1507
1508 netdev = rdev->netdev;
1509
1510 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1511 app.protocol = ETH_P_IBOE;
1512 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1513 prio_map = tmp_map;
1514
1515 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1516 app.protocol = ROCE_V2_UDP_DPORT;
1517 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1518 prio_map |= tmp_map;
1519
1520 return prio_map;
1521 }
1522
bnxt_re_setup_qos(struct bnxt_re_dev * rdev)1523 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1524 {
1525 u8 prio_map = 0;
1526
1527 /* Get priority for roce */
1528 prio_map = bnxt_re_get_priority_mask(rdev);
1529
1530 if (prio_map == rdev->cur_prio_map)
1531 return 0;
1532 rdev->cur_prio_map = prio_map;
1533 /* Actual priorities are not programmed as they are already
1534 * done by L2 driver; just enable or disable priority vlan tagging
1535 */
1536 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1537 (prio_map != 0 && !rdev->qplib_res.prio)) {
1538 rdev->qplib_res.prio = prio_map;
1539 bnxt_re_update_gid(rdev);
1540 }
1541
1542 return 0;
1543 }
1544
bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev * rdev)1545 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1546 {
1547 struct bnxt_en_dev *en_dev = rdev->en_dev;
1548 struct hwrm_ver_get_output resp = {};
1549 struct hwrm_ver_get_input req = {};
1550 struct bnxt_qplib_chip_ctx *cctx;
1551 struct bnxt_fw_msg fw_msg = {};
1552 int rc;
1553
1554 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1555 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1556 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1557 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1558 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1559 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1560 rc = bnxt_send_msg(en_dev, &fw_msg);
1561 if (rc) {
1562 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1563 rc);
1564 return;
1565 }
1566
1567 cctx = rdev->chip_ctx;
1568 cctx->hwrm_intf_ver =
1569 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1570 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1571 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1572 le16_to_cpu(resp.hwrm_intf_patch);
1573
1574 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
1575
1576 if (!cctx->hwrm_cmd_max_timeout)
1577 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
1578 }
1579
bnxt_re_ib_init(struct bnxt_re_dev * rdev)1580 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1581 {
1582 int rc;
1583 u32 event;
1584
1585 /* Register ib dev */
1586 rc = bnxt_re_register_ib(rdev);
1587 if (rc) {
1588 pr_err("Failed to register with IB: %#x\n", rc);
1589 return rc;
1590 }
1591 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1592 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1593
1594 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1595 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1596
1597 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
1598
1599 return rc;
1600 }
1601
bnxt_re_dev_uninit(struct bnxt_re_dev * rdev,u8 op_type)1602 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type)
1603 {
1604 u8 type;
1605 int rc;
1606
1607 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1608 cancel_delayed_work_sync(&rdev->worker);
1609
1610 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1611 &rdev->flags))
1612 bnxt_re_cleanup_res(rdev);
1613 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1614 bnxt_re_free_res(rdev);
1615
1616 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1617 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1618 if (rc)
1619 ibdev_warn(&rdev->ibdev,
1620 "Failed to deinitialize RCFW: %#x", rc);
1621 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1622 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1623 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1624 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1625 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1626 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1627 }
1628
1629 rdev->num_msix = 0;
1630
1631 if (rdev->pacing.dbr_pacing)
1632 bnxt_re_deinitialize_dbr_pacing(rdev);
1633
1634 bnxt_re_destroy_chip_ctx(rdev);
1635 if (op_type == BNXT_RE_COMPLETE_REMOVE) {
1636 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
1637 bnxt_unregister_dev(rdev->en_dev);
1638 }
1639 }
1640
1641 /* worker thread for polling periodic events. Now used for QoS programming*/
bnxt_re_worker(struct work_struct * work)1642 static void bnxt_re_worker(struct work_struct *work)
1643 {
1644 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1645 worker.work);
1646
1647 bnxt_re_setup_qos(rdev);
1648 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1649 }
1650
bnxt_re_dev_init(struct bnxt_re_dev * rdev,u8 op_type)1651 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type)
1652 {
1653 struct bnxt_re_ring_attr rattr = {};
1654 struct bnxt_qplib_creq_ctx *creq;
1655 u32 db_offt;
1656 int vid;
1657 u8 type;
1658 int rc;
1659
1660 if (op_type == BNXT_RE_COMPLETE_INIT) {
1661 /* Registered a new RoCE device instance to netdev */
1662 rc = bnxt_re_register_netdev(rdev);
1663 if (rc) {
1664 ibdev_err(&rdev->ibdev,
1665 "Failed to register with netedev: %#x\n", rc);
1666 return -EINVAL;
1667 }
1668 }
1669 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1670
1671 rc = bnxt_re_setup_chip_ctx(rdev);
1672 if (rc) {
1673 bnxt_unregister_dev(rdev->en_dev);
1674 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1675 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
1676 return -EINVAL;
1677 }
1678
1679 /* Check whether VF or PF */
1680 bnxt_re_get_sriov_func_type(rdev);
1681
1682 if (!rdev->en_dev->ulp_tbl->msix_requested) {
1683 ibdev_err(&rdev->ibdev,
1684 "Failed to get MSI-X vectors: %#x\n", rc);
1685 rc = -EINVAL;
1686 goto fail;
1687 }
1688 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
1689 rdev->en_dev->ulp_tbl->msix_requested);
1690 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
1691
1692 bnxt_re_query_hwrm_intf_version(rdev);
1693
1694 /* Establish RCFW Communication Channel to initialize the context
1695 * memory for the function and all child VFs
1696 */
1697 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
1698 &rdev->qplib_ctx,
1699 BNXT_RE_MAX_QPC_COUNT);
1700 if (rc) {
1701 ibdev_err(&rdev->ibdev,
1702 "Failed to allocate RCFW Channel: %#x\n", rc);
1703 goto fail;
1704 }
1705
1706 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1707 creq = &rdev->rcfw.creq;
1708 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1709 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
1710 rattr.type = type;
1711 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1712 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
1713 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
1714 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
1715 if (rc) {
1716 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
1717 goto free_rcfw;
1718 }
1719 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
1720 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;
1721 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
1722 vid, db_offt,
1723 &bnxt_re_aeq_handler);
1724 if (rc) {
1725 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
1726 rc);
1727 goto free_ring;
1728 }
1729
1730 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
1731 rc = bnxt_re_initialize_dbr_pacing(rdev);
1732 if (!rc) {
1733 rdev->pacing.dbr_pacing = true;
1734 } else {
1735 ibdev_err(&rdev->ibdev,
1736 "DBR pacing disabled with error : %d\n", rc);
1737 rdev->pacing.dbr_pacing = false;
1738 }
1739 }
1740 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr);
1741 if (rc)
1742 goto disable_rcfw;
1743
1744 bnxt_re_set_resource_limits(rdev);
1745
1746 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
1747 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));
1748 if (rc) {
1749 ibdev_err(&rdev->ibdev,
1750 "Failed to allocate QPLIB context: %#x\n", rc);
1751 goto disable_rcfw;
1752 }
1753 rc = bnxt_re_net_stats_ctx_alloc(rdev,
1754 rdev->qplib_ctx.stats.dma_map,
1755 &rdev->qplib_ctx.stats.fw_id);
1756 if (rc) {
1757 ibdev_err(&rdev->ibdev,
1758 "Failed to allocate stats context: %#x\n", rc);
1759 goto free_ctx;
1760 }
1761
1762 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
1763 rdev->is_virtfn);
1764 if (rc) {
1765 ibdev_err(&rdev->ibdev,
1766 "Failed to initialize RCFW: %#x\n", rc);
1767 goto free_sctx;
1768 }
1769 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
1770
1771 /* Resources based on the 'new' device caps */
1772 rc = bnxt_re_alloc_res(rdev);
1773 if (rc) {
1774 ibdev_err(&rdev->ibdev,
1775 "Failed to allocate resources: %#x\n", rc);
1776 goto fail;
1777 }
1778 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
1779 rc = bnxt_re_init_res(rdev);
1780 if (rc) {
1781 ibdev_err(&rdev->ibdev,
1782 "Failed to initialize resources: %#x\n", rc);
1783 goto fail;
1784 }
1785
1786 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
1787
1788 if (!rdev->is_virtfn) {
1789 rc = bnxt_re_setup_qos(rdev);
1790 if (rc)
1791 ibdev_info(&rdev->ibdev,
1792 "RoCE priority not yet configured\n");
1793
1794 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
1795 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
1796 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1797 /*
1798 * Use the total VF count since the actual VF count may not be
1799 * available at this point.
1800 */
1801 bnxt_re_vf_res_config(rdev);
1802 }
1803 hash_init(rdev->cq_hash);
1804 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT)
1805 hash_init(rdev->srq_hash);
1806
1807 return 0;
1808 free_sctx:
1809 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1810 free_ctx:
1811 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1812 disable_rcfw:
1813 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1814 free_ring:
1815 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1816 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1817 free_rcfw:
1818 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1819 fail:
1820 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
1821
1822 return rc;
1823 }
1824
bnxt_re_update_en_info_rdev(struct bnxt_re_dev * rdev,struct bnxt_re_en_dev_info * en_info,struct auxiliary_device * adev)1825 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev,
1826 struct bnxt_re_en_dev_info *en_info,
1827 struct auxiliary_device *adev)
1828 {
1829 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure,
1830 * take the rtnl lock to avoid accessing invalid rdev pointer from
1831 * L2 ULP callbacks. This is applicable in all the places where rdev
1832 * pointer is updated in bnxt_re_en_dev_info.
1833 */
1834 rtnl_lock();
1835 en_info->rdev = rdev;
1836 rtnl_unlock();
1837 }
1838
bnxt_re_add_device(struct auxiliary_device * adev,u8 op_type)1839 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type)
1840 {
1841 struct bnxt_aux_priv *aux_priv =
1842 container_of(adev, struct bnxt_aux_priv, aux_dev);
1843 struct bnxt_re_en_dev_info *en_info;
1844 struct bnxt_en_dev *en_dev;
1845 struct bnxt_re_dev *rdev;
1846 int rc;
1847
1848 en_info = auxiliary_get_drvdata(adev);
1849 en_dev = en_info->en_dev;
1850
1851
1852 rdev = bnxt_re_dev_add(adev, en_dev);
1853 if (!rdev || !rdev_to_dev(rdev)) {
1854 rc = -ENOMEM;
1855 goto exit;
1856 }
1857
1858 bnxt_re_update_en_info_rdev(rdev, en_info, adev);
1859
1860 rc = bnxt_re_dev_init(rdev, op_type);
1861 if (rc)
1862 goto re_dev_dealloc;
1863
1864 rc = bnxt_re_ib_init(rdev);
1865 if (rc) {
1866 pr_err("Failed to register with IB: %s",
1867 aux_priv->aux_dev.name);
1868 goto re_dev_uninit;
1869 }
1870
1871 rdev->nb.notifier_call = bnxt_re_netdev_event;
1872 rc = register_netdevice_notifier(&rdev->nb);
1873 if (rc) {
1874 rdev->nb.notifier_call = NULL;
1875 pr_err("%s: Cannot register to netdevice_notifier",
1876 ROCE_DRV_MODULE_NAME);
1877 goto re_dev_unreg;
1878 }
1879 bnxt_re_setup_cc(rdev, true);
1880
1881 return 0;
1882
1883 re_dev_unreg:
1884 ib_unregister_device(&rdev->ibdev);
1885 re_dev_uninit:
1886 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
1887 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
1888 re_dev_dealloc:
1889 ib_dealloc_device(&rdev->ibdev);
1890 exit:
1891 return rc;
1892 }
1893
bnxt_re_setup_cc(struct bnxt_re_dev * rdev,bool enable)1894 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
1895 {
1896 struct bnxt_qplib_cc_param cc_param = {};
1897
1898 /* Do not enable congestion control on VFs */
1899 if (rdev->is_virtfn)
1900 return;
1901
1902 /* Currently enabling only for GenP5 adapters */
1903 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
1904 return;
1905
1906 if (enable) {
1907 cc_param.enable = 1;
1908 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE;
1909 }
1910
1911 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE |
1912 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
1913 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
1914
1915 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
1916 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
1917 }
1918
1919 /*
1920 * "Notifier chain callback can be invoked for the same chain from
1921 * different CPUs at the same time".
1922 *
1923 * For cases when the netdev is already present, our call to the
1924 * register_netdevice_notifier() will actually get the rtnl_lock()
1925 * before sending NETDEV_REGISTER and (if up) NETDEV_UP
1926 * events.
1927 *
1928 * But for cases when the netdev is not already present, the notifier
1929 * chain is subjected to be invoked from different CPUs simultaneously.
1930 *
1931 * This is protected by the netdev_mutex.
1932 */
bnxt_re_netdev_event(struct notifier_block * notifier,unsigned long event,void * ptr)1933 static int bnxt_re_netdev_event(struct notifier_block *notifier,
1934 unsigned long event, void *ptr)
1935 {
1936 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
1937 struct bnxt_re_dev *rdev;
1938
1939 real_dev = rdma_vlan_dev_real_dev(netdev);
1940 if (!real_dev)
1941 real_dev = netdev;
1942
1943 if (real_dev != netdev)
1944 goto exit;
1945
1946 rdev = bnxt_re_from_netdev(real_dev);
1947 if (!rdev)
1948 return NOTIFY_DONE;
1949
1950
1951 switch (event) {
1952 case NETDEV_UP:
1953 case NETDEV_DOWN:
1954 case NETDEV_CHANGE:
1955 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
1956 netif_carrier_ok(real_dev) ?
1957 IB_EVENT_PORT_ACTIVE :
1958 IB_EVENT_PORT_ERR);
1959 break;
1960 default:
1961 break;
1962 }
1963 ib_device_put(&rdev->ibdev);
1964 exit:
1965 return NOTIFY_DONE;
1966 }
1967
1968 #define BNXT_ADEV_NAME "bnxt_en"
1969
bnxt_re_remove_device(struct bnxt_re_dev * rdev,u8 op_type,struct auxiliary_device * aux_dev)1970 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type,
1971 struct auxiliary_device *aux_dev)
1972 {
1973 if (rdev->nb.notifier_call) {
1974 unregister_netdevice_notifier(&rdev->nb);
1975 rdev->nb.notifier_call = NULL;
1976 } else {
1977 /* If notifier is null, we should have already done a
1978 * clean up before coming here.
1979 */
1980 return;
1981 }
1982 bnxt_re_setup_cc(rdev, false);
1983 ib_unregister_device(&rdev->ibdev);
1984 bnxt_re_dev_uninit(rdev, op_type);
1985 ib_dealloc_device(&rdev->ibdev);
1986 }
1987
bnxt_re_remove(struct auxiliary_device * adev)1988 static void bnxt_re_remove(struct auxiliary_device *adev)
1989 {
1990 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
1991 struct bnxt_re_dev *rdev;
1992
1993 mutex_lock(&bnxt_re_mutex);
1994 if (!en_info) {
1995 mutex_unlock(&bnxt_re_mutex);
1996 return;
1997 }
1998 rdev = en_info->rdev;
1999
2000 if (rdev)
2001 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev);
2002 kfree(en_info);
2003 mutex_unlock(&bnxt_re_mutex);
2004 }
2005
bnxt_re_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)2006 static int bnxt_re_probe(struct auxiliary_device *adev,
2007 const struct auxiliary_device_id *id)
2008 {
2009 struct bnxt_aux_priv *aux_priv =
2010 container_of(adev, struct bnxt_aux_priv, aux_dev);
2011 struct bnxt_re_en_dev_info *en_info;
2012 struct bnxt_en_dev *en_dev;
2013 int rc;
2014
2015 en_dev = aux_priv->edev;
2016
2017 mutex_lock(&bnxt_re_mutex);
2018 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL);
2019 if (!en_info) {
2020 mutex_unlock(&bnxt_re_mutex);
2021 return -ENOMEM;
2022 }
2023 en_info->en_dev = en_dev;
2024
2025 auxiliary_set_drvdata(adev, en_info);
2026
2027 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT);
2028 mutex_unlock(&bnxt_re_mutex);
2029 return rc;
2030 }
2031
bnxt_re_suspend(struct auxiliary_device * adev,pm_message_t state)2032 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
2033 {
2034 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2035 struct bnxt_en_dev *en_dev;
2036 struct bnxt_re_dev *rdev;
2037
2038 if (!en_info)
2039 return 0;
2040
2041 rdev = en_info->rdev;
2042 en_dev = en_info->en_dev;
2043 mutex_lock(&bnxt_re_mutex);
2044 /* L2 driver may invoke this callback during device error/crash or device
2045 * reset. Current RoCE driver doesn't recover the device in case of
2046 * error. Handle the error by dispatching fatal events to all qps
2047 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
2048 * L2 driver want to modify the MSIx table.
2049 */
2050
2051 ibdev_info(&rdev->ibdev, "Handle device suspend call");
2052 /* Check the current device state from bnxt_en_dev and move the
2053 * device to detached state if FW_FATAL_COND is set.
2054 * This prevents more commands to HW during clean-up,
2055 * in case the device is already in error.
2056 */
2057 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state))
2058 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
2059
2060 bnxt_re_dev_stop(rdev);
2061 bnxt_re_stop_irq(adev);
2062 /* Move the device states to detached and avoid sending any more
2063 * commands to HW
2064 */
2065 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
2066 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
2067 wake_up_all(&rdev->rcfw.cmdq.waitq);
2068
2069 if (rdev->pacing.dbr_pacing)
2070 bnxt_re_set_pacing_dev_state(rdev);
2071
2072 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx",
2073 __func__, en_dev->en_state);
2074 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev);
2075 mutex_unlock(&bnxt_re_mutex);
2076
2077 return 0;
2078 }
2079
bnxt_re_resume(struct auxiliary_device * adev)2080 static int bnxt_re_resume(struct auxiliary_device *adev)
2081 {
2082 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2083 struct bnxt_re_dev *rdev;
2084
2085 if (!en_info)
2086 return 0;
2087
2088 mutex_lock(&bnxt_re_mutex);
2089 /* L2 driver may invoke this callback during device recovery, resume.
2090 * reset. Current RoCE driver doesn't recover the device in case of
2091 * error. Handle the error by dispatching fatal events to all qps
2092 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
2093 * L2 driver want to modify the MSIx table.
2094 */
2095
2096 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT);
2097 rdev = en_info->rdev;
2098 ibdev_info(&rdev->ibdev, "Device resume completed");
2099 mutex_unlock(&bnxt_re_mutex);
2100
2101 return 0;
2102 }
2103
2104 static const struct auxiliary_device_id bnxt_re_id_table[] = {
2105 { .name = BNXT_ADEV_NAME ".rdma", },
2106 {},
2107 };
2108
2109 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
2110
2111 static struct auxiliary_driver bnxt_re_driver = {
2112 .name = "rdma",
2113 .probe = bnxt_re_probe,
2114 .remove = bnxt_re_remove,
2115 .shutdown = bnxt_re_shutdown,
2116 .suspend = bnxt_re_suspend,
2117 .resume = bnxt_re_resume,
2118 .id_table = bnxt_re_id_table,
2119 };
2120
bnxt_re_mod_init(void)2121 static int __init bnxt_re_mod_init(void)
2122 {
2123 int rc;
2124
2125 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
2126 rc = auxiliary_driver_register(&bnxt_re_driver);
2127 if (rc) {
2128 pr_err("%s: Failed to register auxiliary driver\n",
2129 ROCE_DRV_MODULE_NAME);
2130 return rc;
2131 }
2132 return 0;
2133 }
2134
bnxt_re_mod_exit(void)2135 static void __exit bnxt_re_mod_exit(void)
2136 {
2137 auxiliary_driver_unregister(&bnxt_re_driver);
2138 }
2139
2140 module_init(bnxt_re_mod_init);
2141 module_exit(bnxt_re_mod_exit);
2142