1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006-2014 QLogic Corporation
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * The following controllers are supported by this driver:
32 * BCM5706C A2, A3
33 * BCM5706S A2, A3
34 * BCM5708C B1, B2
35 * BCM5708S B1, B2
36 * BCM5709C A1, C0
37 * BCM5709S A1, C0
38 * BCM5716C C0
39 * BCM5716S C0
40 *
41 * The following controllers are not supported by this driver:
42 * BCM5706C A0, A1 (pre-production)
43 * BCM5706S A0, A1 (pre-production)
44 * BCM5708C A0, B0 (pre-production)
45 * BCM5708S A0, B0 (pre-production)
46 * BCM5709C A0 B0, B1, B2 (pre-production)
47 * BCM5709S A0, B0, B1, B2 (pre-production)
48 */
49
50 #include "opt_bce.h"
51
52 #include <sys/param.h>
53 #include <sys/endian.h>
54 #include <sys/systm.h>
55 #include <sys/sockio.h>
56 #include <sys/lock.h>
57 #include <sys/mbuf.h>
58 #include <sys/malloc.h>
59 #include <sys/mutex.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
63 #include <sys/sysctl.h>
64 #include <sys/queue.h>
65
66 #include <net/bpf.h>
67 #include <net/ethernet.h>
68 #include <net/if.h>
69 #include <net/if_var.h>
70 #include <net/if_arp.h>
71 #include <net/if_dl.h>
72 #include <net/if_media.h>
73
74 #include <net/if_types.h>
75 #include <net/if_vlan_var.h>
76
77 #include <netinet/in_systm.h>
78 #include <netinet/in.h>
79 #include <netinet/if_ether.h>
80 #include <netinet/ip.h>
81 #include <netinet/ip6.h>
82 #include <netinet/tcp.h>
83 #include <netinet/udp.h>
84
85 #include <machine/bus.h>
86 #include <machine/resource.h>
87 #include <sys/bus.h>
88 #include <sys/rman.h>
89
90 #include <dev/mii/mii.h>
91 #include <dev/mii/miivar.h>
92 #include "miidevs.h"
93 #include <dev/mii/brgphyreg.h>
94
95 #include <dev/pci/pcireg.h>
96 #include <dev/pci/pcivar.h>
97
98 #include "miibus_if.h"
99
100 #include <dev/bce/if_bcereg.h>
101 #include <dev/bce/if_bcefw.h>
102
103 /****************************************************************************/
104 /* BCE Debug Options */
105 /****************************************************************************/
106 #ifdef BCE_DEBUG
107 u32 bce_debug = BCE_WARN;
108
109 /* 0 = Never */
110 /* 1 = 1 in 2,147,483,648 */
111 /* 256 = 1 in 8,388,608 */
112 /* 2048 = 1 in 1,048,576 */
113 /* 65536 = 1 in 32,768 */
114 /* 1048576 = 1 in 2,048 */
115 /* 268435456 = 1 in 8 */
116 /* 536870912 = 1 in 4 */
117 /* 1073741824 = 1 in 2 */
118
119 /* Controls how often the l2_fhdr frame error check will fail. */
120 int l2fhdr_error_sim_control = 0;
121
122 /* Controls how often the unexpected attention check will fail. */
123 int unexpected_attention_sim_control = 0;
124
125 /* Controls how often to simulate an mbuf allocation failure. */
126 int mbuf_alloc_failed_sim_control = 0;
127
128 /* Controls how often to simulate a DMA mapping failure. */
129 int dma_map_addr_failed_sim_control = 0;
130
131 /* Controls how often to simulate a bootcode failure. */
132 int bootcode_running_failure_sim_control = 0;
133 #endif
134
135 /****************************************************************************/
136 /* PCI Device ID Table */
137 /* */
138 /* Used by bce_probe() to identify the devices supported by this driver. */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX 64
141
142 static const struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "QLogic NetXtreme II BCM5706 1000Base-T" },
154
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "QLogic NetXtreme II BCM5706 1000Base-SX" },
160
161 /* BCM5708C controllers and OEM boards. */
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "QLogic NetXtreme II BCM5708 1000Base-T" },
170
171 /* BCM5708S controllers and OEM boards. */
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "QLogic NetXtreme II BCM5708 1000Base-SX" },
180
181 /* BCM5709C controllers and OEM boards. */
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "QLogic NetXtreme II BCM5709 1000Base-T" },
188
189 /* BCM5709S controllers and OEM boards. */
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "QLogic NetXtreme II BCM5709 1000Base-SX" },
196
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "QLogic NetXtreme II BCM5716 1000Base-T" },
200 { 0, 0, 0, 0, NULL }
201 };
202
203 /****************************************************************************/
204 /* Supported Flash NVRAM device data. */
205 /****************************************************************************/
206 static const struct flash_spec flash_table[] =
207 {
208 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
209 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
210
211 /* Slow EEPROM */
212 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
213 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
214 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
215 "EEPROM - slow"},
216 /* Expansion entry 0001 */
217 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 0001"},
221 /* Saifun SA25F010 (non-buffered flash) */
222 /* strap, cfg1, & write1 need updates */
223 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
226 "Non-buffered flash (128kB)"},
227 /* Saifun SA25F020 (non-buffered flash) */
228 /* strap, cfg1, & write1 need updates */
229 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
231 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
232 "Non-buffered flash (256kB)"},
233 /* Expansion entry 0100 */
234 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
235 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
236 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
237 "Entry 0100"},
238 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
239 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
240 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
241 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
242 "Entry 0101: ST M45PE10 (128kB non-buffered)"},
243 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
244 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
245 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
246 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
247 "Entry 0110: ST M45PE20 (256kB non-buffered)"},
248 /* Saifun SA25F005 (non-buffered flash) */
249 /* strap, cfg1, & write1 need updates */
250 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
252 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
253 "Non-buffered flash (64kB)"},
254 /* Fast EEPROM */
255 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
256 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
257 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
258 "EEPROM - fast"},
259 /* Expansion entry 1001 */
260 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
261 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
262 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
263 "Entry 1001"},
264 /* Expansion entry 1010 */
265 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
266 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
267 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
268 "Entry 1010"},
269 /* ATMEL AT45DB011B (buffered flash) */
270 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
271 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
272 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
273 "Buffered flash (128kB)"},
274 /* Expansion entry 1100 */
275 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
276 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
277 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
278 "Entry 1100"},
279 /* Expansion entry 1101 */
280 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
281 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
282 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
283 "Entry 1101"},
284 /* Ateml Expansion entry 1110 */
285 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
286 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
287 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
288 "Entry 1110 (Atmel)"},
289 /* ATMEL AT45DB021B (buffered flash) */
290 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
291 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
292 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
293 "Buffered flash (256kB)"},
294 };
295
296 /*
297 * The BCM5709 controllers transparently handle the
298 * differences between Atmel 264 byte pages and all
299 * flash devices which use 256 byte pages, so no
300 * logical-to-physical mapping is required in the
301 * driver.
302 */
303 static const struct flash_spec flash_5709 = {
304 .flags = BCE_NV_BUFFERED,
305 .page_bits = BCM5709_FLASH_PAGE_BITS,
306 .page_size = BCM5709_FLASH_PAGE_SIZE,
307 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
308 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
309 .name = "5709/5716 buffered flash (256kB)",
310 };
311
312 /****************************************************************************/
313 /* FreeBSD device entry points. */
314 /****************************************************************************/
315 static int bce_probe (device_t);
316 static int bce_attach (device_t);
317 static int bce_detach (device_t);
318 static int bce_shutdown (device_t);
319
320 /****************************************************************************/
321 /* BCE Debug Data Structure Dump Routines */
322 /****************************************************************************/
323 #ifdef BCE_DEBUG
324 static u32 bce_reg_rd (struct bce_softc *, u32);
325 static void bce_reg_wr (struct bce_softc *, u32, u32);
326 static void bce_reg_wr16 (struct bce_softc *, u32, u16);
327 static u32 bce_ctx_rd (struct bce_softc *, u32, u32);
328 static void bce_dump_enet (struct bce_softc *, struct mbuf *);
329 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *);
330 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int);
331 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int);
332 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int);
333 static void bce_dump_txbd (struct bce_softc *,
334 int, struct tx_bd *);
335 static void bce_dump_rxbd (struct bce_softc *,
336 int, struct rx_bd *);
337 static void bce_dump_pgbd (struct bce_softc *,
338 int, struct rx_bd *);
339 static void bce_dump_l2fhdr (struct bce_softc *,
340 int, struct l2_fhdr *);
341 static void bce_dump_ctx (struct bce_softc *, u16);
342 static void bce_dump_ftqs (struct bce_softc *);
343 static void bce_dump_tx_chain (struct bce_softc *, u16, int);
344 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int);
345 static void bce_dump_pg_chain (struct bce_softc *, u16, int);
346 static void bce_dump_status_block (struct bce_softc *);
347 static void bce_dump_stats_block (struct bce_softc *);
348 static void bce_dump_driver_state (struct bce_softc *);
349 static void bce_dump_hw_state (struct bce_softc *);
350 static void bce_dump_shmem_state (struct bce_softc *);
351 static void bce_dump_mq_regs (struct bce_softc *);
352 static void bce_dump_bc_state (struct bce_softc *);
353 static void bce_dump_txp_state (struct bce_softc *, int);
354 static void bce_dump_rxp_state (struct bce_softc *, int);
355 static void bce_dump_tpat_state (struct bce_softc *, int);
356 static void bce_dump_cp_state (struct bce_softc *, int);
357 static void bce_dump_com_state (struct bce_softc *, int);
358 static void bce_dump_rv2p_state (struct bce_softc *);
359 static void bce_breakpoint (struct bce_softc *);
360 #endif /*BCE_DEBUG */
361
362 /****************************************************************************/
363 /* BCE Register/Memory Access Routines */
364 /****************************************************************************/
365 static u32 bce_reg_rd_ind (struct bce_softc *, u32);
366 static void bce_reg_wr_ind (struct bce_softc *, u32, u32);
367 static void bce_shmem_wr (struct bce_softc *, u32, u32);
368 static u32 bce_shmem_rd (struct bce_softc *, u32);
369 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32);
370 static int bce_miibus_read_reg (device_t, int, int);
371 static int bce_miibus_write_reg (device_t, int, int, int);
372 static void bce_miibus_statchg (device_t);
373
374 #ifdef BCE_DEBUG
375 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
376 #ifdef BCE_NVRAM_WRITE_SUPPORT
377 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
378 #endif
379 #endif
380
381 /****************************************************************************/
382 /* BCE NVRAM Access Routines */
383 /****************************************************************************/
384 static int bce_acquire_nvram_lock (struct bce_softc *);
385 static int bce_release_nvram_lock (struct bce_softc *);
386 static void bce_enable_nvram_access(struct bce_softc *);
387 static void bce_disable_nvram_access(struct bce_softc *);
388 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32);
389 static int bce_init_nvram (struct bce_softc *);
390 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int);
391 static int bce_nvram_test (struct bce_softc *);
392 #ifdef BCE_NVRAM_WRITE_SUPPORT
393 static int bce_enable_nvram_write (struct bce_softc *);
394 static void bce_disable_nvram_write(struct bce_softc *);
395 static int bce_nvram_erase_page (struct bce_softc *, u32);
396 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32);
397 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int);
398 #endif
399
400 /****************************************************************************/
401 /* */
402 /****************************************************************************/
403 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
404 static void bce_get_media (struct bce_softc *);
405 static void bce_init_media (struct bce_softc *);
406 static u32 bce_get_rphy_link (struct bce_softc *);
407 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int);
408 static int bce_dma_alloc (device_t);
409 static void bce_dma_free (struct bce_softc *);
410 static void bce_release_resources (struct bce_softc *);
411
412 /****************************************************************************/
413 /* BCE Firmware Synchronization and Load */
414 /****************************************************************************/
415 static void bce_fw_cap_init (struct bce_softc *);
416 static int bce_fw_sync (struct bce_softc *, u32);
417 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32,
418 u32);
419 static void bce_load_cpu_fw (struct bce_softc *,
420 struct cpu_reg *, struct fw_info *);
421 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
422 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
423 static void bce_start_rxp_cpu (struct bce_softc *);
424 static void bce_init_rxp_cpu (struct bce_softc *);
425 static void bce_init_txp_cpu (struct bce_softc *);
426 static void bce_init_tpat_cpu (struct bce_softc *);
427 static void bce_init_cp_cpu (struct bce_softc *);
428 static void bce_init_com_cpu (struct bce_softc *);
429 static void bce_init_cpus (struct bce_softc *);
430
431 static void bce_print_adapter_info (struct bce_softc *);
432 static void bce_probe_pci_caps (device_t, struct bce_softc *);
433 static void bce_stop (struct bce_softc *);
434 static int bce_reset (struct bce_softc *, u32);
435 static int bce_chipinit (struct bce_softc *);
436 static int bce_blockinit (struct bce_softc *);
437
438 static int bce_init_tx_chain (struct bce_softc *);
439 static void bce_free_tx_chain (struct bce_softc *);
440
441 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *);
442 static int bce_init_rx_chain (struct bce_softc *);
443 static void bce_fill_rx_chain (struct bce_softc *);
444 static void bce_free_rx_chain (struct bce_softc *);
445
446 static int bce_get_pg_buf (struct bce_softc *, u16, u16);
447 static int bce_init_pg_chain (struct bce_softc *);
448 static void bce_fill_pg_chain (struct bce_softc *);
449 static void bce_free_pg_chain (struct bce_softc *);
450
451 static struct mbuf *bce_tso_setup (struct bce_softc *,
452 struct mbuf **, u16 *);
453 static int bce_tx_encap (struct bce_softc *, struct mbuf **);
454 static void bce_start_locked (if_t);
455 static void bce_start (if_t);
456 static int bce_ioctl (if_t, u_long, caddr_t);
457 static uint64_t bce_get_counter (if_t, ift_counter);
458 static void bce_watchdog (struct bce_softc *);
459 static int bce_ifmedia_upd (if_t);
460 static int bce_ifmedia_upd_locked (if_t);
461 static void bce_ifmedia_sts (if_t, struct ifmediareq *);
462 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *);
463 static void bce_init_locked (struct bce_softc *);
464 static void bce_init (void *);
465 static void bce_mgmt_init_locked (struct bce_softc *sc);
466
467 static int bce_init_ctx (struct bce_softc *);
468 static void bce_get_mac_addr (struct bce_softc *);
469 static void bce_set_mac_addr (struct bce_softc *);
470 static void bce_phy_intr (struct bce_softc *);
471 static inline u16 bce_get_hw_rx_cons (struct bce_softc *);
472 static void bce_rx_intr (struct bce_softc *);
473 static void bce_tx_intr (struct bce_softc *);
474 static void bce_disable_intr (struct bce_softc *);
475 static void bce_enable_intr (struct bce_softc *, int);
476
477 static void bce_intr (void *);
478 static void bce_set_rx_mode (struct bce_softc *);
479 static void bce_stats_update (struct bce_softc *);
480 static void bce_tick (void *);
481 static void bce_pulse (void *);
482 static void bce_add_sysctls (struct bce_softc *);
483
484 /****************************************************************************/
485 /* FreeBSD device dispatch table. */
486 /****************************************************************************/
487 static device_method_t bce_methods[] = {
488 /* Device interface (device_if.h) */
489 DEVMETHOD(device_probe, bce_probe),
490 DEVMETHOD(device_attach, bce_attach),
491 DEVMETHOD(device_detach, bce_detach),
492 DEVMETHOD(device_shutdown, bce_shutdown),
493 /* Supported by device interface but not used here. */
494 /* DEVMETHOD(device_identify, bce_identify), */
495 /* DEVMETHOD(device_suspend, bce_suspend), */
496 /* DEVMETHOD(device_resume, bce_resume), */
497 /* DEVMETHOD(device_quiesce, bce_quiesce), */
498
499 /* MII interface (miibus_if.h) */
500 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
501 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
502 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
503 /* Supported by MII interface but not used here. */
504 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */
505 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */
506
507 DEVMETHOD_END
508 };
509
510 static driver_t bce_driver = {
511 "bce",
512 bce_methods,
513 sizeof(struct bce_softc)
514 };
515
516 MODULE_DEPEND(bce, pci, 1, 1, 1);
517 MODULE_DEPEND(bce, ether, 1, 1, 1);
518 MODULE_DEPEND(bce, miibus, 1, 1, 1);
519
520 DRIVER_MODULE(bce, pci, bce_driver, NULL, NULL);
521 DRIVER_MODULE(miibus, bce, miibus_driver, NULL, NULL);
522 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce,
523 bce_devs, nitems(bce_devs) - 1);
524
525 /****************************************************************************/
526 /* Tunable device values */
527 /****************************************************************************/
528 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
529 "bce driver parameters");
530
531 /* Allowable values are TRUE or FALSE */
532 static int bce_verbose = TRUE;
533 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
534 "Verbose output enable/disable");
535
536 /* Allowable values are TRUE or FALSE */
537 static int bce_tso_enable = TRUE;
538 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
539 "TSO Enable/Disable");
540
541 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
542 /* ToDo: Add MSI-X support. */
543 static int bce_msi_enable = 1;
544 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
545 "MSI-X|MSI|INTx selector");
546
547 /* Allowable values are 1, 2, 4, 8. */
548 static int bce_rx_pages = DEFAULT_RX_PAGES;
549 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
550 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
551
552 /* Allowable values are 1, 2, 4, 8. */
553 static int bce_tx_pages = DEFAULT_TX_PAGES;
554 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
555 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
556
557 /* Allowable values are TRUE or FALSE. */
558 static int bce_hdr_split = TRUE;
559 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
560 "Frame header/payload splitting Enable/Disable");
561
562 /* Allowable values are TRUE or FALSE. */
563 static int bce_strict_rx_mtu = FALSE;
564 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN,
565 &bce_strict_rx_mtu, 0,
566 "Enable/Disable strict RX frame size checking");
567
568 /* Allowable values are 0 ... 100 */
569 #ifdef BCE_DEBUG
570 /* Generate 1 interrupt for every transmit completion. */
571 static int bce_tx_quick_cons_trip_int = 1;
572 #else
573 /* Generate 1 interrupt for every 20 transmit completions. */
574 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
575 #endif
576 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
577 &bce_tx_quick_cons_trip_int, 0,
578 "Transmit BD trip point during interrupts");
579
580 /* Allowable values are 0 ... 100 */
581 /* Generate 1 interrupt for every transmit completion. */
582 #ifdef BCE_DEBUG
583 static int bce_tx_quick_cons_trip = 1;
584 #else
585 /* Generate 1 interrupt for every 20 transmit completions. */
586 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
587 #endif
588 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
589 &bce_tx_quick_cons_trip, 0,
590 "Transmit BD trip point");
591
592 /* Allowable values are 0 ... 100 */
593 #ifdef BCE_DEBUG
594 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
595 static int bce_tx_ticks_int = 0;
596 #else
597 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
598 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
599 #endif
600 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
601 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
602
603 /* Allowable values are 0 ... 100 */
604 #ifdef BCE_DEBUG
605 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
606 static int bce_tx_ticks = 0;
607 #else
608 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
609 static int bce_tx_ticks = DEFAULT_TX_TICKS;
610 #endif
611 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
612 &bce_tx_ticks, 0, "Transmit ticks count");
613
614 /* Allowable values are 1 ... 100 */
615 #ifdef BCE_DEBUG
616 /* Generate 1 interrupt for every received frame. */
617 static int bce_rx_quick_cons_trip_int = 1;
618 #else
619 /* Generate 1 interrupt for every 6 received frames. */
620 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
621 #endif
622 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
623 &bce_rx_quick_cons_trip_int, 0,
624 "Receive BD trip point during interrupts");
625
626 /* Allowable values are 1 ... 100 */
627 #ifdef BCE_DEBUG
628 /* Generate 1 interrupt for every received frame. */
629 static int bce_rx_quick_cons_trip = 1;
630 #else
631 /* Generate 1 interrupt for every 6 received frames. */
632 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
633 #endif
634 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
635 &bce_rx_quick_cons_trip, 0,
636 "Receive BD trip point");
637
638 /* Allowable values are 0 ... 100 */
639 #ifdef BCE_DEBUG
640 /* Generate an int. if 0us have elapsed since the last received frame. */
641 static int bce_rx_ticks_int = 0;
642 #else
643 /* Generate an int. if 18us have elapsed since the last received frame. */
644 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
645 #endif
646 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
647 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
648
649 /* Allowable values are 0 ... 100 */
650 #ifdef BCE_DEBUG
651 /* Generate an int. if 0us have elapsed since the last received frame. */
652 static int bce_rx_ticks = 0;
653 #else
654 /* Generate an int. if 18us have elapsed since the last received frame. */
655 static int bce_rx_ticks = DEFAULT_RX_TICKS;
656 #endif
657 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
658 &bce_rx_ticks, 0, "Receive ticks count");
659
660 /****************************************************************************/
661 /* Device probe function. */
662 /* */
663 /* Compares the device to the driver's list of supported devices and */
664 /* reports back to the OS whether this is the right driver for the device. */
665 /* */
666 /* Returns: */
667 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
668 /****************************************************************************/
669 static int
bce_probe(device_t dev)670 bce_probe(device_t dev)
671 {
672 const struct bce_type *t;
673 struct bce_softc *sc;
674 u16 vid = 0, did = 0, svid = 0, sdid = 0;
675
676 t = bce_devs;
677
678 sc = device_get_softc(dev);
679 sc->bce_unit = device_get_unit(dev);
680 sc->bce_dev = dev;
681
682 /* Get the data for the device to be probed. */
683 vid = pci_get_vendor(dev);
684 did = pci_get_device(dev);
685 svid = pci_get_subvendor(dev);
686 sdid = pci_get_subdevice(dev);
687
688 DBPRINT(sc, BCE_EXTREME_LOAD,
689 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
690 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
691
692 /* Look through the list of known devices for a match. */
693 while(t->bce_name != NULL) {
694 if ((vid == t->bce_vid) && (did == t->bce_did) &&
695 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
696 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
697 device_set_descf(dev, "%s (%c%d)",
698 t->bce_name, (((pci_read_config(dev,
699 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
700 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
701 return(BUS_PROBE_DEFAULT);
702 }
703 t++;
704 }
705
706 return(ENXIO);
707 }
708
709 /****************************************************************************/
710 /* PCI Capabilities Probe Function. */
711 /* */
712 /* Walks the PCI capabiites list for the device to find what features are */
713 /* supported. */
714 /* */
715 /* Returns: */
716 /* None. */
717 /****************************************************************************/
718 static void
bce_print_adapter_info(struct bce_softc * sc)719 bce_print_adapter_info(struct bce_softc *sc)
720 {
721 int i = 0;
722
723 DBENTER(BCE_VERBOSE_LOAD);
724
725 if (bce_verbose || bootverbose) {
726 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
727 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
728 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
729
730 /* Bus info. */
731 if (sc->bce_flags & BCE_PCIE_FLAG) {
732 printf("Bus (PCIe x%d, ", sc->link_width);
733 switch (sc->link_speed) {
734 case 1: printf("2.5Gbps); "); break;
735 case 2: printf("5Gbps); "); break;
736 default: printf("Unknown link speed); ");
737 }
738 } else {
739 printf("Bus (PCI%s, %s, %dMHz); ",
740 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
741 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
742 "32-bit" : "64-bit"), sc->bus_speed_mhz);
743 }
744
745 /* Firmware version and device features. */
746 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
747 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages,
748 (bce_hdr_split == TRUE ? sc->pg_pages: 0));
749
750 if (bce_hdr_split == TRUE) {
751 printf("SPLT");
752 i++;
753 }
754
755 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
756 if (i > 0) printf("|");
757 printf("MSI"); i++;
758 }
759
760 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
761 if (i > 0) printf("|");
762 printf("MSI-X"); i++;
763 }
764
765 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
766 if (i > 0) printf("|");
767 printf("2.5G"); i++;
768 }
769
770 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
771 if (i > 0) printf("|");
772 printf("Remote PHY(%s)",
773 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
774 "FIBER" : "TP"); i++;
775 }
776
777 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
778 if (i > 0) printf("|");
779 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
780 } else {
781 printf(")\n");
782 }
783
784 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
785 sc->bce_rx_quick_cons_trip_int,
786 sc->bce_rx_quick_cons_trip,
787 sc->bce_rx_ticks_int,
788 sc->bce_rx_ticks,
789 sc->bce_tx_quick_cons_trip_int,
790 sc->bce_tx_quick_cons_trip,
791 sc->bce_tx_ticks_int,
792 sc->bce_tx_ticks);
793 }
794
795 DBEXIT(BCE_VERBOSE_LOAD);
796 }
797
798 /****************************************************************************/
799 /* PCI Capabilities Probe Function. */
800 /* */
801 /* Walks the PCI capabiites list for the device to find what features are */
802 /* supported. */
803 /* */
804 /* Returns: */
805 /* None. */
806 /****************************************************************************/
807 static void
bce_probe_pci_caps(device_t dev,struct bce_softc * sc)808 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
809 {
810 u32 reg;
811
812 DBENTER(BCE_VERBOSE_LOAD);
813
814 /* Check if PCI-X capability is enabled. */
815 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) {
816 if (reg != 0)
817 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
818 }
819
820 /* Check if PCIe capability is enabled. */
821 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
822 if (reg != 0) {
823 u16 link_status = pci_read_config(dev, reg + 0x12, 2);
824 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
825 "0x%08X\n", link_status);
826 sc->link_speed = link_status & 0xf;
827 sc->link_width = (link_status >> 4) & 0x3f;
828 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
829 sc->bce_flags |= BCE_PCIE_FLAG;
830 }
831 }
832
833 /* Check if MSI capability is enabled. */
834 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
835 if (reg != 0)
836 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
837 }
838
839 /* Check if MSI-X capability is enabled. */
840 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
841 if (reg != 0)
842 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
843 }
844
845 DBEXIT(BCE_VERBOSE_LOAD);
846 }
847
848 /****************************************************************************/
849 /* Load and validate user tunable settings. */
850 /* */
851 /* Returns: */
852 /* Nothing. */
853 /****************************************************************************/
854 static void
bce_set_tunables(struct bce_softc * sc)855 bce_set_tunables(struct bce_softc *sc)
856 {
857 /* Set sysctl values for RX page count. */
858 switch (bce_rx_pages) {
859 case 1:
860 /* fall-through */
861 case 2:
862 /* fall-through */
863 case 4:
864 /* fall-through */
865 case 8:
866 sc->rx_pages = bce_rx_pages;
867 break;
868 default:
869 sc->rx_pages = DEFAULT_RX_PAGES;
870 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
871 "hw.bce.rx_pages! Setting default of %d.\n",
872 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
873 }
874
875 /* ToDo: Consider allowing user setting for pg_pages. */
876 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
877
878 /* Set sysctl values for TX page count. */
879 switch (bce_tx_pages) {
880 case 1:
881 /* fall-through */
882 case 2:
883 /* fall-through */
884 case 4:
885 /* fall-through */
886 case 8:
887 sc->tx_pages = bce_tx_pages;
888 break;
889 default:
890 sc->tx_pages = DEFAULT_TX_PAGES;
891 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
892 "hw.bce.tx_pages! Setting default of %d.\n",
893 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
894 }
895
896 /*
897 * Validate the TX trip point (i.e. the number of
898 * TX completions before a status block update is
899 * generated and an interrupt is asserted.
900 */
901 if (bce_tx_quick_cons_trip_int <= 100) {
902 sc->bce_tx_quick_cons_trip_int =
903 bce_tx_quick_cons_trip_int;
904 } else {
905 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
906 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n",
907 __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
908 DEFAULT_TX_QUICK_CONS_TRIP_INT);
909 sc->bce_tx_quick_cons_trip_int =
910 DEFAULT_TX_QUICK_CONS_TRIP_INT;
911 }
912
913 if (bce_tx_quick_cons_trip <= 100) {
914 sc->bce_tx_quick_cons_trip =
915 bce_tx_quick_cons_trip;
916 } else {
917 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
918 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n",
919 __FILE__, __LINE__, bce_tx_quick_cons_trip,
920 DEFAULT_TX_QUICK_CONS_TRIP);
921 sc->bce_tx_quick_cons_trip =
922 DEFAULT_TX_QUICK_CONS_TRIP;
923 }
924
925 /*
926 * Validate the TX ticks count (i.e. the maximum amount
927 * of time to wait after the last TX completion has
928 * occurred before a status block update is generated
929 * and an interrupt is asserted.
930 */
931 if (bce_tx_ticks_int <= 100) {
932 sc->bce_tx_ticks_int =
933 bce_tx_ticks_int;
934 } else {
935 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
936 "hw.bce.tx_ticks_int! Setting default of %d.\n",
937 __FILE__, __LINE__, bce_tx_ticks_int,
938 DEFAULT_TX_TICKS_INT);
939 sc->bce_tx_ticks_int =
940 DEFAULT_TX_TICKS_INT;
941 }
942
943 if (bce_tx_ticks <= 100) {
944 sc->bce_tx_ticks =
945 bce_tx_ticks;
946 } else {
947 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
948 "hw.bce.tx_ticks! Setting default of %d.\n",
949 __FILE__, __LINE__, bce_tx_ticks,
950 DEFAULT_TX_TICKS);
951 sc->bce_tx_ticks =
952 DEFAULT_TX_TICKS;
953 }
954
955 /*
956 * Validate the RX trip point (i.e. the number of
957 * RX frames received before a status block update is
958 * generated and an interrupt is asserted.
959 */
960 if (bce_rx_quick_cons_trip_int <= 100) {
961 sc->bce_rx_quick_cons_trip_int =
962 bce_rx_quick_cons_trip_int;
963 } else {
964 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
965 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n",
966 __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
967 DEFAULT_RX_QUICK_CONS_TRIP_INT);
968 sc->bce_rx_quick_cons_trip_int =
969 DEFAULT_RX_QUICK_CONS_TRIP_INT;
970 }
971
972 if (bce_rx_quick_cons_trip <= 100) {
973 sc->bce_rx_quick_cons_trip =
974 bce_rx_quick_cons_trip;
975 } else {
976 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
977 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n",
978 __FILE__, __LINE__, bce_rx_quick_cons_trip,
979 DEFAULT_RX_QUICK_CONS_TRIP);
980 sc->bce_rx_quick_cons_trip =
981 DEFAULT_RX_QUICK_CONS_TRIP;
982 }
983
984 /*
985 * Validate the RX ticks count (i.e. the maximum amount
986 * of time to wait after the last RX frame has been
987 * received before a status block update is generated
988 * and an interrupt is asserted.
989 */
990 if (bce_rx_ticks_int <= 100) {
991 sc->bce_rx_ticks_int = bce_rx_ticks_int;
992 } else {
993 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
994 "hw.bce.rx_ticks_int! Setting default of %d.\n",
995 __FILE__, __LINE__, bce_rx_ticks_int,
996 DEFAULT_RX_TICKS_INT);
997 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
998 }
999
1000 if (bce_rx_ticks <= 100) {
1001 sc->bce_rx_ticks = bce_rx_ticks;
1002 } else {
1003 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1004 "hw.bce.rx_ticks! Setting default of %d.\n",
1005 __FILE__, __LINE__, bce_rx_ticks,
1006 DEFAULT_RX_TICKS);
1007 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1008 }
1009
1010 /* Disabling both RX ticks and RX trips will prevent interrupts. */
1011 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1012 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1013 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1014 __FILE__, __LINE__);
1015 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1016 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1017 }
1018
1019 /* Disabling both TX ticks and TX trips will prevent interrupts. */
1020 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1021 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1022 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1023 __FILE__, __LINE__);
1024 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1025 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1026 }
1027 }
1028
1029 /****************************************************************************/
1030 /* Device attach function. */
1031 /* */
1032 /* Allocates device resources, performs secondary chip identification, */
1033 /* resets and initializes the hardware, and initializes driver instance */
1034 /* variables. */
1035 /* */
1036 /* Returns: */
1037 /* 0 on success, positive value on failure. */
1038 /****************************************************************************/
1039 static int
bce_attach(device_t dev)1040 bce_attach(device_t dev)
1041 {
1042 struct bce_softc *sc;
1043 if_t ifp;
1044 u32 val;
1045 int count, error, rc = 0, rid;
1046
1047 sc = device_get_softc(dev);
1048 sc->bce_dev = dev;
1049
1050 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1051
1052 sc->bce_unit = device_get_unit(dev);
1053
1054 /* Set initial device and PHY flags */
1055 sc->bce_flags = 0;
1056 sc->bce_phy_flags = 0;
1057
1058 bce_set_tunables(sc);
1059
1060 pci_enable_busmaster(dev);
1061
1062 /* Allocate PCI memory resources. */
1063 rid = PCIR_BAR(0);
1064 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1065 &rid, RF_ACTIVE);
1066
1067 if (sc->bce_res_mem == NULL) {
1068 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1069 __FILE__, __LINE__);
1070 rc = ENXIO;
1071 goto bce_attach_fail;
1072 }
1073
1074 /* Get various resource handles. */
1075 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
1076 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1077 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1078
1079 bce_probe_pci_caps(dev, sc);
1080
1081 rid = 1;
1082 count = 0;
1083 #if 0
1084 /* Try allocating MSI-X interrupts. */
1085 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1086 (bce_msi_enable >= 2) &&
1087 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1088 &rid, RF_ACTIVE)) != NULL)) {
1089 msi_needed = count = 1;
1090
1091 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1092 (count != msi_needed)) {
1093 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1094 "Received = %d, error = %d\n", __FILE__, __LINE__,
1095 msi_needed, count, error);
1096 count = 0;
1097 pci_release_msi(dev);
1098 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1099 sc->bce_res_irq);
1100 sc->bce_res_irq = NULL;
1101 } else {
1102 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1103 __FUNCTION__);
1104 sc->bce_flags |= BCE_USING_MSIX_FLAG;
1105 }
1106 }
1107 #endif
1108
1109 /* Try allocating a MSI interrupt. */
1110 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1111 (bce_msi_enable >= 1) && (count == 0)) {
1112 count = 1;
1113 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1114 BCE_PRINTF("%s(%d): MSI allocation failed! "
1115 "error = %d\n", __FILE__, __LINE__, error);
1116 count = 0;
1117 pci_release_msi(dev);
1118 } else {
1119 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1120 "interrupt.\n", __FUNCTION__);
1121 sc->bce_flags |= BCE_USING_MSI_FLAG;
1122 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1123 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1124 rid = 1;
1125 }
1126 }
1127
1128 /* Try allocating a legacy interrupt. */
1129 if (count == 0) {
1130 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1131 __FUNCTION__);
1132 rid = 0;
1133 }
1134
1135 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1136 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1137
1138 /* Report any IRQ allocation errors. */
1139 if (sc->bce_res_irq == NULL) {
1140 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1141 __FILE__, __LINE__);
1142 rc = ENXIO;
1143 goto bce_attach_fail;
1144 }
1145
1146 /* Initialize mutex for the current device instance. */
1147 BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1148
1149 /*
1150 * Configure byte swap and enable indirect register access.
1151 * Rely on CPU to do target byte swapping on big endian systems.
1152 * Access to registers outside of PCI configurtion space are not
1153 * valid until this is done.
1154 */
1155 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1156 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1157 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1158
1159 /* Save ASIC revsion info. */
1160 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
1161
1162 /* Weed out any non-production controller revisions. */
1163 switch(BCE_CHIP_ID(sc)) {
1164 case BCE_CHIP_ID_5706_A0:
1165 case BCE_CHIP_ID_5706_A1:
1166 case BCE_CHIP_ID_5708_A0:
1167 case BCE_CHIP_ID_5708_B0:
1168 case BCE_CHIP_ID_5709_A0:
1169 case BCE_CHIP_ID_5709_B0:
1170 case BCE_CHIP_ID_5709_B1:
1171 case BCE_CHIP_ID_5709_B2:
1172 BCE_PRINTF("%s(%d): Unsupported controller "
1173 "revision (%c%d)!\n", __FILE__, __LINE__,
1174 (((pci_read_config(dev, PCIR_REVID, 4) &
1175 0xf0) >> 4) + 'A'), (pci_read_config(dev,
1176 PCIR_REVID, 4) & 0xf));
1177 rc = ENODEV;
1178 goto bce_attach_fail;
1179 }
1180
1181 /*
1182 * The embedded PCIe to PCI-X bridge (EPB)
1183 * in the 5708 cannot address memory above
1184 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1185 */
1186 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1187 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1188 else
1189 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1190
1191 /*
1192 * Find the base address for shared memory access.
1193 * Newer versions of bootcode use a signature and offset
1194 * while older versions use a fixed address.
1195 */
1196 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1197 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1198 /* Multi-port devices use different offsets in shared memory. */
1199 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1200 (pci_get_function(sc->bce_dev) << 2));
1201 else
1202 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1203
1204 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1205 __FUNCTION__, sc->bce_shmem_base);
1206
1207 /* Fetch the bootcode revision. */
1208 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1209 for (int i = 0, j = 0; i < 3; i++) {
1210 u8 num;
1211
1212 num = (u8) (val >> (24 - (i * 8)));
1213 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1214 if (num >= k || !skip0 || k == 1) {
1215 sc->bce_bc_ver[j++] = (num / k) + '0';
1216 skip0 = 0;
1217 }
1218 }
1219
1220 if (i != 2)
1221 sc->bce_bc_ver[j++] = '.';
1222 }
1223
1224 /* Check if any management firwmare is enabled. */
1225 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1226 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1227 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1228
1229 /* Allow time for firmware to enter the running state. */
1230 for (int i = 0; i < 30; i++) {
1231 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1232 if (val & BCE_CONDITION_MFW_RUN_MASK)
1233 break;
1234 DELAY(10000);
1235 }
1236
1237 /* Check if management firmware is running. */
1238 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1239 val &= BCE_CONDITION_MFW_RUN_MASK;
1240 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1241 (val != BCE_CONDITION_MFW_RUN_NONE)) {
1242 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1243 int i = 0;
1244
1245 /* Read the management firmware version string. */
1246 for (int j = 0; j < 3; j++) {
1247 val = bce_reg_rd_ind(sc, addr + j * 4);
1248 val = bswap32(val);
1249 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1250 i += 4;
1251 }
1252 } else {
1253 /* May cause firmware synchronization timeouts. */
1254 BCE_PRINTF("%s(%d): Management firmware enabled "
1255 "but not running!\n", __FILE__, __LINE__);
1256 strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1257
1258 /* ToDo: Any action the driver should take? */
1259 }
1260 }
1261
1262 /* Get PCI bus information (speed and type). */
1263 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1264 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1265 u32 clkreg;
1266
1267 sc->bce_flags |= BCE_PCIX_FLAG;
1268
1269 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1270
1271 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1272 switch (clkreg) {
1273 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1274 sc->bus_speed_mhz = 133;
1275 break;
1276
1277 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1278 sc->bus_speed_mhz = 100;
1279 break;
1280
1281 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1282 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1283 sc->bus_speed_mhz = 66;
1284 break;
1285
1286 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1287 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1288 sc->bus_speed_mhz = 50;
1289 break;
1290
1291 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1292 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1293 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1294 sc->bus_speed_mhz = 33;
1295 break;
1296 }
1297 } else {
1298 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1299 sc->bus_speed_mhz = 66;
1300 else
1301 sc->bus_speed_mhz = 33;
1302 }
1303
1304 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1305 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1306
1307 /* Find the media type for the adapter. */
1308 bce_get_media(sc);
1309
1310 /* Reset controller and announce to bootcode that driver is present. */
1311 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1312 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1313 __FILE__, __LINE__);
1314 rc = ENXIO;
1315 goto bce_attach_fail;
1316 }
1317
1318 /* Initialize the controller. */
1319 if (bce_chipinit(sc)) {
1320 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1321 __FILE__, __LINE__);
1322 rc = ENXIO;
1323 goto bce_attach_fail;
1324 }
1325
1326 /* Perform NVRAM test. */
1327 if (bce_nvram_test(sc)) {
1328 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1329 __FILE__, __LINE__);
1330 rc = ENXIO;
1331 goto bce_attach_fail;
1332 }
1333
1334 /* Fetch the permanent Ethernet MAC address. */
1335 bce_get_mac_addr(sc);
1336
1337 /* Update statistics once every second. */
1338 sc->bce_stats_ticks = 1000000 & 0xffff00;
1339
1340 /* Store data needed by PHY driver for backplane applications */
1341 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1342 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1343
1344 /* Allocate DMA memory resources. */
1345 if (bce_dma_alloc(dev)) {
1346 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1347 __FILE__, __LINE__);
1348 rc = ENXIO;
1349 goto bce_attach_fail;
1350 }
1351
1352 /* Allocate an ifnet structure. */
1353 ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1354
1355 /* Initialize the ifnet interface. */
1356 if_setsoftc(ifp, sc);
1357 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1358 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1359 if_setioctlfn(ifp, bce_ioctl);
1360 if_setstartfn(ifp, bce_start);
1361 if_setgetcounterfn(ifp, bce_get_counter);
1362 if_setinitfn(ifp, bce_init);
1363 if_setmtu(ifp, ETHERMTU);
1364
1365 if (bce_tso_enable) {
1366 if_sethwassist(ifp, BCE_IF_HWASSIST | CSUM_TSO);
1367 if_setcapabilities(ifp, BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1368 IFCAP_VLAN_HWTSO);
1369 } else {
1370 if_sethwassist(ifp, BCE_IF_HWASSIST);
1371 if_setcapabilities(ifp, BCE_IF_CAPABILITIES);
1372 }
1373
1374 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1375 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0);
1376
1377 if_setcapenable(ifp, if_getcapabilities(ifp));
1378
1379 /*
1380 * Assume standard mbuf sizes for buffer allocation.
1381 * This may change later if the MTU size is set to
1382 * something other than 1500.
1383 */
1384 bce_get_rx_buffer_sizes(sc,
1385 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1386
1387 /* Recalculate our buffer allocation sizes. */
1388 if_setsendqlen(ifp, USABLE_TX_BD_ALLOC);
1389 if_setsendqready(ifp);
1390
1391 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1392 if_setbaudrate(ifp, IF_Mbps(2500ULL));
1393 else
1394 if_setbaudrate(ifp, IF_Mbps(1000));
1395
1396 /* Handle any special PHY initialization for SerDes PHYs. */
1397 bce_init_media(sc);
1398
1399 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1400 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1401 bce_ifmedia_sts);
1402 /*
1403 * We can't manually override remote PHY's link and assume
1404 * PHY port configuration(Fiber or TP) is not changed after
1405 * device attach. This may not be correct though.
1406 */
1407 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1408 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1409 ifmedia_add(&sc->bce_ifmedia,
1410 IFM_ETHER | IFM_2500_SX, 0, NULL);
1411 ifmedia_add(&sc->bce_ifmedia,
1412 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1413 }
1414 ifmedia_add(&sc->bce_ifmedia,
1415 IFM_ETHER | IFM_1000_SX, 0, NULL);
1416 ifmedia_add(&sc->bce_ifmedia,
1417 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1418 } else {
1419 ifmedia_add(&sc->bce_ifmedia,
1420 IFM_ETHER | IFM_10_T, 0, NULL);
1421 ifmedia_add(&sc->bce_ifmedia,
1422 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1423 ifmedia_add(&sc->bce_ifmedia,
1424 IFM_ETHER | IFM_100_TX, 0, NULL);
1425 ifmedia_add(&sc->bce_ifmedia,
1426 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1427 ifmedia_add(&sc->bce_ifmedia,
1428 IFM_ETHER | IFM_1000_T, 0, NULL);
1429 ifmedia_add(&sc->bce_ifmedia,
1430 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1431 }
1432 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1433 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1434 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1435 } else {
1436 /* MII child bus by attaching the PHY. */
1437 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1438 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1439 MII_OFFSET_ANY, MIIF_DOPAUSE);
1440 if (rc != 0) {
1441 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1442 __LINE__);
1443 goto bce_attach_fail;
1444 }
1445 }
1446
1447 /* Attach to the Ethernet interface list. */
1448 ether_ifattach(ifp, sc->eaddr);
1449
1450 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1451 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1452
1453 /* Hookup IRQ last. */
1454 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1455 NULL, bce_intr, sc, &sc->bce_intrhand);
1456
1457 if (rc) {
1458 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1459 __FILE__, __LINE__);
1460 bce_detach(dev);
1461 goto bce_attach_exit;
1462 }
1463
1464 /*
1465 * At this point we've acquired all the resources
1466 * we need to run so there's no turning back, we're
1467 * cleared for launch.
1468 */
1469
1470 /* Print some important debugging info. */
1471 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1472
1473 /* Add the supported sysctls to the kernel. */
1474 bce_add_sysctls(sc);
1475
1476 BCE_LOCK(sc);
1477
1478 /*
1479 * The chip reset earlier notified the bootcode that
1480 * a driver is present. We now need to start our pulse
1481 * routine so that the bootcode is reminded that we're
1482 * still running.
1483 */
1484 bce_pulse(sc);
1485
1486 bce_mgmt_init_locked(sc);
1487 BCE_UNLOCK(sc);
1488
1489 /* Finally, print some useful adapter info */
1490 bce_print_adapter_info(sc);
1491 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1492 __FUNCTION__, sc);
1493
1494 goto bce_attach_exit;
1495
1496 bce_attach_fail:
1497 bce_release_resources(sc);
1498
1499 bce_attach_exit:
1500
1501 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1502
1503 return(rc);
1504 }
1505
1506 /****************************************************************************/
1507 /* Device detach function. */
1508 /* */
1509 /* Stops the controller, resets the controller, and releases resources. */
1510 /* */
1511 /* Returns: */
1512 /* 0 on success, positive value on failure. */
1513 /****************************************************************************/
1514 static int
bce_detach(device_t dev)1515 bce_detach(device_t dev)
1516 {
1517 struct bce_softc *sc = device_get_softc(dev);
1518 if_t ifp;
1519 u32 msg;
1520
1521 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1522
1523 ifp = sc->bce_ifp;
1524
1525 /* Stop and reset the controller. */
1526 BCE_LOCK(sc);
1527
1528 /* Stop the pulse so the bootcode can go to driver absent state. */
1529 callout_stop(&sc->bce_pulse_callout);
1530
1531 bce_stop(sc);
1532 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1533 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1534 else
1535 msg = BCE_DRV_MSG_CODE_UNLOAD;
1536 bce_reset(sc, msg);
1537
1538 BCE_UNLOCK(sc);
1539
1540 ether_ifdetach(ifp);
1541
1542 /* If we have a child device on the MII bus remove it too. */
1543 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1544 ifmedia_removeall(&sc->bce_ifmedia);
1545 else {
1546 bus_generic_detach(dev);
1547 device_delete_child(dev, sc->bce_miibus);
1548 }
1549
1550 /* Release all remaining resources. */
1551 bce_release_resources(sc);
1552
1553 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1554
1555 return(0);
1556 }
1557
1558 /****************************************************************************/
1559 /* Device shutdown function. */
1560 /* */
1561 /* Stops and resets the controller. */
1562 /* */
1563 /* Returns: */
1564 /* 0 on success, positive value on failure. */
1565 /****************************************************************************/
1566 static int
bce_shutdown(device_t dev)1567 bce_shutdown(device_t dev)
1568 {
1569 struct bce_softc *sc = device_get_softc(dev);
1570 u32 msg;
1571
1572 DBENTER(BCE_VERBOSE);
1573
1574 BCE_LOCK(sc);
1575 bce_stop(sc);
1576 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1577 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1578 else
1579 msg = BCE_DRV_MSG_CODE_UNLOAD;
1580 bce_reset(sc, msg);
1581 BCE_UNLOCK(sc);
1582
1583 DBEXIT(BCE_VERBOSE);
1584
1585 return (0);
1586 }
1587
1588 #ifdef BCE_DEBUG
1589 /****************************************************************************/
1590 /* Register read. */
1591 /* */
1592 /* Returns: */
1593 /* The value of the register. */
1594 /****************************************************************************/
1595 static u32
bce_reg_rd(struct bce_softc * sc,u32 offset)1596 bce_reg_rd(struct bce_softc *sc, u32 offset)
1597 {
1598 u32 val = REG_RD(sc, offset);
1599 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1600 __FUNCTION__, offset, val);
1601 return val;
1602 }
1603
1604 /****************************************************************************/
1605 /* Register write (16 bit). */
1606 /* */
1607 /* Returns: */
1608 /* Nothing. */
1609 /****************************************************************************/
1610 static void
bce_reg_wr16(struct bce_softc * sc,u32 offset,u16 val)1611 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1612 {
1613 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1614 __FUNCTION__, offset, val);
1615 REG_WR16(sc, offset, val);
1616 }
1617
1618 /****************************************************************************/
1619 /* Register write. */
1620 /* */
1621 /* Returns: */
1622 /* Nothing. */
1623 /****************************************************************************/
1624 static void
bce_reg_wr(struct bce_softc * sc,u32 offset,u32 val)1625 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1626 {
1627 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1628 __FUNCTION__, offset, val);
1629 REG_WR(sc, offset, val);
1630 }
1631 #endif
1632
1633 /****************************************************************************/
1634 /* Indirect register read. */
1635 /* */
1636 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1637 /* configuration space. Using this mechanism avoids issues with posted */
1638 /* reads but is much slower than memory-mapped I/O. */
1639 /* */
1640 /* Returns: */
1641 /* The value of the register. */
1642 /****************************************************************************/
1643 static u32
bce_reg_rd_ind(struct bce_softc * sc,u32 offset)1644 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1645 {
1646 device_t dev;
1647 dev = sc->bce_dev;
1648
1649 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1650 #ifdef BCE_DEBUG
1651 {
1652 u32 val;
1653 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1654 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1655 __FUNCTION__, offset, val);
1656 return val;
1657 }
1658 #else
1659 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1660 #endif
1661 }
1662
1663 /****************************************************************************/
1664 /* Indirect register write. */
1665 /* */
1666 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1667 /* configuration space. Using this mechanism avoids issues with posted */
1668 /* writes but is muchh slower than memory-mapped I/O. */
1669 /* */
1670 /* Returns: */
1671 /* Nothing. */
1672 /****************************************************************************/
1673 static void
bce_reg_wr_ind(struct bce_softc * sc,u32 offset,u32 val)1674 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1675 {
1676 device_t dev;
1677 dev = sc->bce_dev;
1678
1679 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1680 __FUNCTION__, offset, val);
1681
1682 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1683 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1684 }
1685
1686 /****************************************************************************/
1687 /* Shared memory write. */
1688 /* */
1689 /* Writes NetXtreme II shared memory region. */
1690 /* */
1691 /* Returns: */
1692 /* Nothing. */
1693 /****************************************************************************/
1694 static void
bce_shmem_wr(struct bce_softc * sc,u32 offset,u32 val)1695 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1696 {
1697 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to "
1698 "0x%08X\n", __FUNCTION__, val, offset);
1699
1700 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1701 }
1702
1703 /****************************************************************************/
1704 /* Shared memory read. */
1705 /* */
1706 /* Reads NetXtreme II shared memory region. */
1707 /* */
1708 /* Returns: */
1709 /* The 32 bit value read. */
1710 /****************************************************************************/
1711 static u32
bce_shmem_rd(struct bce_softc * sc,u32 offset)1712 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1713 {
1714 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1715
1716 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1717 "0x%08X\n", __FUNCTION__, val, offset);
1718
1719 return val;
1720 }
1721
1722 #ifdef BCE_DEBUG
1723 /****************************************************************************/
1724 /* Context memory read. */
1725 /* */
1726 /* The NetXtreme II controller uses context memory to track connection */
1727 /* information for L2 and higher network protocols. */
1728 /* */
1729 /* Returns: */
1730 /* The requested 32 bit value of context memory. */
1731 /****************************************************************************/
1732 static u32
bce_ctx_rd(struct bce_softc * sc,u32 cid_addr,u32 ctx_offset)1733 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1734 {
1735 u32 idx, offset, retry_cnt = 5, val;
1736
1737 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1738 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1739 "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1740
1741 offset = ctx_offset + cid_addr;
1742
1743 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1744 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1745
1746 for (idx = 0; idx < retry_cnt; idx++) {
1747 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1748 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1749 break;
1750 DELAY(5);
1751 }
1752
1753 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1754 BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1755 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1756 __FILE__, __LINE__, cid_addr, ctx_offset);
1757
1758 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1759 } else {
1760 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1761 val = REG_RD(sc, BCE_CTX_DATA);
1762 }
1763
1764 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1765 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1766
1767 return(val);
1768 }
1769 #endif
1770
1771 /****************************************************************************/
1772 /* Context memory write. */
1773 /* */
1774 /* The NetXtreme II controller uses context memory to track connection */
1775 /* information for L2 and higher network protocols. */
1776 /* */
1777 /* Returns: */
1778 /* Nothing. */
1779 /****************************************************************************/
1780 static void
bce_ctx_wr(struct bce_softc * sc,u32 cid_addr,u32 ctx_offset,u32 ctx_val)1781 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1782 {
1783 u32 idx, offset = ctx_offset + cid_addr;
1784 u32 val, retry_cnt = 5;
1785
1786 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1787 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1788
1789 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1790 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1791 __FUNCTION__, cid_addr));
1792
1793 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1794 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1795 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1796
1797 for (idx = 0; idx < retry_cnt; idx++) {
1798 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1799 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1800 break;
1801 DELAY(5);
1802 }
1803
1804 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1805 BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1806 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1807 __FILE__, __LINE__, cid_addr, ctx_offset);
1808
1809 } else {
1810 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1811 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1812 }
1813 }
1814
1815 /****************************************************************************/
1816 /* PHY register read. */
1817 /* */
1818 /* Implements register reads on the MII bus. */
1819 /* */
1820 /* Returns: */
1821 /* The value of the register. */
1822 /****************************************************************************/
1823 static int
bce_miibus_read_reg(device_t dev,int phy,int reg)1824 bce_miibus_read_reg(device_t dev, int phy, int reg)
1825 {
1826 struct bce_softc *sc;
1827 u32 val;
1828 int i;
1829
1830 sc = device_get_softc(dev);
1831
1832 /*
1833 * The 5709S PHY is an IEEE Clause 45 PHY
1834 * with special mappings to work with IEEE
1835 * Clause 22 register accesses.
1836 */
1837 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1838 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1839 reg += 0x10;
1840 }
1841
1842 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1843 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1844 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1845
1846 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1847 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1848
1849 DELAY(40);
1850 }
1851
1852 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1853 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1854 BCE_EMAC_MDIO_COMM_START_BUSY;
1855 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1856
1857 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1858 DELAY(10);
1859
1860 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1861 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1862 DELAY(5);
1863
1864 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1865 val &= BCE_EMAC_MDIO_COMM_DATA;
1866
1867 break;
1868 }
1869 }
1870
1871 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1872 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1873 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1874 val = 0x0;
1875 } else {
1876 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1877 }
1878
1879 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1880 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1881 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1882
1883 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1884 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1885
1886 DELAY(40);
1887 }
1888
1889 DB_PRINT_PHY_REG(reg, val);
1890 return (val & 0xffff);
1891 }
1892
1893 /****************************************************************************/
1894 /* PHY register write. */
1895 /* */
1896 /* Implements register writes on the MII bus. */
1897 /* */
1898 /* Returns: */
1899 /* The value of the register. */
1900 /****************************************************************************/
1901 static int
bce_miibus_write_reg(device_t dev,int phy,int reg,int val)1902 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1903 {
1904 struct bce_softc *sc;
1905 u32 val1;
1906 int i;
1907
1908 sc = device_get_softc(dev);
1909
1910 DB_PRINT_PHY_REG(reg, val);
1911
1912 /*
1913 * The 5709S PHY is an IEEE Clause 45 PHY
1914 * with special mappings to work with IEEE
1915 * Clause 22 register accesses.
1916 */
1917 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1918 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1919 reg += 0x10;
1920 }
1921
1922 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1923 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1924 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1925
1926 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1927 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1928
1929 DELAY(40);
1930 }
1931
1932 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1933 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1934 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1935 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1936
1937 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1938 DELAY(10);
1939
1940 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1941 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1942 DELAY(5);
1943 break;
1944 }
1945 }
1946
1947 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1948 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1949 __FILE__, __LINE__);
1950
1951 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1952 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1953 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1954
1955 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1956 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1957
1958 DELAY(40);
1959 }
1960
1961 return 0;
1962 }
1963
1964 /****************************************************************************/
1965 /* MII bus status change. */
1966 /* */
1967 /* Called by the MII bus driver when the PHY establishes link to set the */
1968 /* MAC interface registers. */
1969 /* */
1970 /* Returns: */
1971 /* Nothing. */
1972 /****************************************************************************/
1973 static void
bce_miibus_statchg(device_t dev)1974 bce_miibus_statchg(device_t dev)
1975 {
1976 struct bce_softc *sc;
1977 struct mii_data *mii;
1978 struct ifmediareq ifmr;
1979 int media_active, media_status, val;
1980
1981 sc = device_get_softc(dev);
1982
1983 DBENTER(BCE_VERBOSE_PHY);
1984
1985 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1986 bzero(&ifmr, sizeof(ifmr));
1987 bce_ifmedia_sts_rphy(sc, &ifmr);
1988 media_active = ifmr.ifm_active;
1989 media_status = ifmr.ifm_status;
1990 } else {
1991 mii = device_get_softc(sc->bce_miibus);
1992 media_active = mii->mii_media_active;
1993 media_status = mii->mii_media_status;
1994 }
1995
1996 /* Ignore invalid media status. */
1997 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
1998 (IFM_ACTIVE | IFM_AVALID))
1999 goto bce_miibus_statchg_exit;
2000
2001 val = REG_RD(sc, BCE_EMAC_MODE);
2002 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2003 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2004 BCE_EMAC_MODE_25G);
2005
2006 /* Set MII or GMII interface based on the PHY speed. */
2007 switch (IFM_SUBTYPE(media_active)) {
2008 case IFM_10_T:
2009 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2010 DBPRINT(sc, BCE_INFO_PHY,
2011 "Enabling 10Mb interface.\n");
2012 val |= BCE_EMAC_MODE_PORT_MII_10;
2013 break;
2014 }
2015 /* fall-through */
2016 case IFM_100_TX:
2017 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2018 val |= BCE_EMAC_MODE_PORT_MII;
2019 break;
2020 case IFM_2500_SX:
2021 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2022 val |= BCE_EMAC_MODE_25G;
2023 /* fall-through */
2024 case IFM_1000_T:
2025 case IFM_1000_SX:
2026 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2027 val |= BCE_EMAC_MODE_PORT_GMII;
2028 break;
2029 default:
2030 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2031 "default GMII interface.\n");
2032 val |= BCE_EMAC_MODE_PORT_GMII;
2033 }
2034
2035 /* Set half or full duplex based on PHY settings. */
2036 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2037 DBPRINT(sc, BCE_INFO_PHY,
2038 "Setting Half-Duplex interface.\n");
2039 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2040 } else
2041 DBPRINT(sc, BCE_INFO_PHY,
2042 "Setting Full-Duplex interface.\n");
2043
2044 REG_WR(sc, BCE_EMAC_MODE, val);
2045
2046 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2047 DBPRINT(sc, BCE_INFO_PHY,
2048 "%s(): Enabling RX flow control.\n", __FUNCTION__);
2049 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2050 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2051 } else {
2052 DBPRINT(sc, BCE_INFO_PHY,
2053 "%s(): Disabling RX flow control.\n", __FUNCTION__);
2054 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2055 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2056 }
2057
2058 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2059 DBPRINT(sc, BCE_INFO_PHY,
2060 "%s(): Enabling TX flow control.\n", __FUNCTION__);
2061 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2062 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2063 } else {
2064 DBPRINT(sc, BCE_INFO_PHY,
2065 "%s(): Disabling TX flow control.\n", __FUNCTION__);
2066 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2067 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2068 }
2069
2070 /* ToDo: Update watermarks in bce_init_rx_context(). */
2071
2072 bce_miibus_statchg_exit:
2073 DBEXIT(BCE_VERBOSE_PHY);
2074 }
2075
2076 /****************************************************************************/
2077 /* Acquire NVRAM lock. */
2078 /* */
2079 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
2080 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2081 /* for use by the driver. */
2082 /* */
2083 /* Returns: */
2084 /* 0 on success, positive value on failure. */
2085 /****************************************************************************/
2086 static int
bce_acquire_nvram_lock(struct bce_softc * sc)2087 bce_acquire_nvram_lock(struct bce_softc *sc)
2088 {
2089 u32 val;
2090 int j, rc = 0;
2091
2092 DBENTER(BCE_VERBOSE_NVRAM);
2093
2094 /* Request access to the flash interface. */
2095 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2096 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2097 val = REG_RD(sc, BCE_NVM_SW_ARB);
2098 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2099 break;
2100
2101 DELAY(5);
2102 }
2103
2104 if (j >= NVRAM_TIMEOUT_COUNT) {
2105 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2106 rc = EBUSY;
2107 }
2108
2109 DBEXIT(BCE_VERBOSE_NVRAM);
2110 return (rc);
2111 }
2112
2113 /****************************************************************************/
2114 /* Release NVRAM lock. */
2115 /* */
2116 /* When the caller is finished accessing NVRAM the lock must be released. */
2117 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2118 /* for use by the driver. */
2119 /* */
2120 /* Returns: */
2121 /* 0 on success, positive value on failure. */
2122 /****************************************************************************/
2123 static int
bce_release_nvram_lock(struct bce_softc * sc)2124 bce_release_nvram_lock(struct bce_softc *sc)
2125 {
2126 u32 val;
2127 int j, rc = 0;
2128
2129 DBENTER(BCE_VERBOSE_NVRAM);
2130
2131 /*
2132 * Relinquish nvram interface.
2133 */
2134 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2135
2136 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2137 val = REG_RD(sc, BCE_NVM_SW_ARB);
2138 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2139 break;
2140
2141 DELAY(5);
2142 }
2143
2144 if (j >= NVRAM_TIMEOUT_COUNT) {
2145 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2146 rc = EBUSY;
2147 }
2148
2149 DBEXIT(BCE_VERBOSE_NVRAM);
2150 return (rc);
2151 }
2152
2153 #ifdef BCE_NVRAM_WRITE_SUPPORT
2154 /****************************************************************************/
2155 /* Enable NVRAM write access. */
2156 /* */
2157 /* Before writing to NVRAM the caller must enable NVRAM writes. */
2158 /* */
2159 /* Returns: */
2160 /* 0 on success, positive value on failure. */
2161 /****************************************************************************/
2162 static int
bce_enable_nvram_write(struct bce_softc * sc)2163 bce_enable_nvram_write(struct bce_softc *sc)
2164 {
2165 u32 val;
2166 int rc = 0;
2167
2168 DBENTER(BCE_VERBOSE_NVRAM);
2169
2170 val = REG_RD(sc, BCE_MISC_CFG);
2171 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2172
2173 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2174 int j;
2175
2176 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2177 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2178
2179 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2180 DELAY(5);
2181
2182 val = REG_RD(sc, BCE_NVM_COMMAND);
2183 if (val & BCE_NVM_COMMAND_DONE)
2184 break;
2185 }
2186
2187 if (j >= NVRAM_TIMEOUT_COUNT) {
2188 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2189 rc = EBUSY;
2190 }
2191 }
2192
2193 DBENTER(BCE_VERBOSE_NVRAM);
2194 return (rc);
2195 }
2196
2197 /****************************************************************************/
2198 /* Disable NVRAM write access. */
2199 /* */
2200 /* When the caller is finished writing to NVRAM write access must be */
2201 /* disabled. */
2202 /* */
2203 /* Returns: */
2204 /* Nothing. */
2205 /****************************************************************************/
2206 static void
bce_disable_nvram_write(struct bce_softc * sc)2207 bce_disable_nvram_write(struct bce_softc *sc)
2208 {
2209 u32 val;
2210
2211 DBENTER(BCE_VERBOSE_NVRAM);
2212
2213 val = REG_RD(sc, BCE_MISC_CFG);
2214 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2215
2216 DBEXIT(BCE_VERBOSE_NVRAM);
2217
2218 }
2219 #endif
2220
2221 /****************************************************************************/
2222 /* Enable NVRAM access. */
2223 /* */
2224 /* Before accessing NVRAM for read or write operations the caller must */
2225 /* enabled NVRAM access. */
2226 /* */
2227 /* Returns: */
2228 /* Nothing. */
2229 /****************************************************************************/
2230 static void
bce_enable_nvram_access(struct bce_softc * sc)2231 bce_enable_nvram_access(struct bce_softc *sc)
2232 {
2233 u32 val;
2234
2235 DBENTER(BCE_VERBOSE_NVRAM);
2236
2237 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2238 /* Enable both bits, even on read. */
2239 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2240 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2241
2242 DBEXIT(BCE_VERBOSE_NVRAM);
2243 }
2244
2245 /****************************************************************************/
2246 /* Disable NVRAM access. */
2247 /* */
2248 /* When the caller is finished accessing NVRAM access must be disabled. */
2249 /* */
2250 /* Returns: */
2251 /* Nothing. */
2252 /****************************************************************************/
2253 static void
bce_disable_nvram_access(struct bce_softc * sc)2254 bce_disable_nvram_access(struct bce_softc *sc)
2255 {
2256 u32 val;
2257
2258 DBENTER(BCE_VERBOSE_NVRAM);
2259
2260 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2261
2262 /* Disable both bits, even after read. */
2263 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2264 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2265
2266 DBEXIT(BCE_VERBOSE_NVRAM);
2267 }
2268
2269 #ifdef BCE_NVRAM_WRITE_SUPPORT
2270 /****************************************************************************/
2271 /* Erase NVRAM page before writing. */
2272 /* */
2273 /* Non-buffered flash parts require that a page be erased before it is */
2274 /* written. */
2275 /* */
2276 /* Returns: */
2277 /* 0 on success, positive value on failure. */
2278 /****************************************************************************/
2279 static int
bce_nvram_erase_page(struct bce_softc * sc,u32 offset)2280 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2281 {
2282 u32 cmd;
2283 int j, rc = 0;
2284
2285 DBENTER(BCE_VERBOSE_NVRAM);
2286
2287 /* Buffered flash doesn't require an erase. */
2288 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2289 goto bce_nvram_erase_page_exit;
2290
2291 /* Build an erase command. */
2292 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2293 BCE_NVM_COMMAND_DOIT;
2294
2295 /*
2296 * Clear the DONE bit separately, set the NVRAM address to erase,
2297 * and issue the erase command.
2298 */
2299 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2300 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2301 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2302
2303 /* Wait for completion. */
2304 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2305 u32 val;
2306
2307 DELAY(5);
2308
2309 val = REG_RD(sc, BCE_NVM_COMMAND);
2310 if (val & BCE_NVM_COMMAND_DONE)
2311 break;
2312 }
2313
2314 if (j >= NVRAM_TIMEOUT_COUNT) {
2315 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2316 rc = EBUSY;
2317 }
2318
2319 bce_nvram_erase_page_exit:
2320 DBEXIT(BCE_VERBOSE_NVRAM);
2321 return (rc);
2322 }
2323 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2324
2325 /****************************************************************************/
2326 /* Read a dword (32 bits) from NVRAM. */
2327 /* */
2328 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
2329 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
2330 /* */
2331 /* Returns: */
2332 /* 0 on success and the 32 bit value read, positive value on failure. */
2333 /****************************************************************************/
2334 static int
bce_nvram_read_dword(struct bce_softc * sc,u32 offset,u8 * ret_val,u32 cmd_flags)2335 bce_nvram_read_dword(struct bce_softc *sc,
2336 u32 offset, u8 *ret_val, u32 cmd_flags)
2337 {
2338 u32 cmd;
2339 int i, rc = 0;
2340
2341 DBENTER(BCE_EXTREME_NVRAM);
2342
2343 /* Build the command word. */
2344 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2345
2346 /* Calculate the offset for buffered flash if translation is used. */
2347 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2348 offset = ((offset / sc->bce_flash_info->page_size) <<
2349 sc->bce_flash_info->page_bits) +
2350 (offset % sc->bce_flash_info->page_size);
2351 }
2352
2353 /*
2354 * Clear the DONE bit separately, set the address to read,
2355 * and issue the read.
2356 */
2357 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2358 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2359 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2360
2361 /* Wait for completion. */
2362 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2363 u32 val;
2364
2365 DELAY(5);
2366
2367 val = REG_RD(sc, BCE_NVM_COMMAND);
2368 if (val & BCE_NVM_COMMAND_DONE) {
2369 val = REG_RD(sc, BCE_NVM_READ);
2370
2371 val = bce_be32toh(val);
2372 memcpy(ret_val, &val, 4);
2373 break;
2374 }
2375 }
2376
2377 /* Check for errors. */
2378 if (i >= NVRAM_TIMEOUT_COUNT) {
2379 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2380 "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2381 rc = EBUSY;
2382 }
2383
2384 DBEXIT(BCE_EXTREME_NVRAM);
2385 return(rc);
2386 }
2387
2388 #ifdef BCE_NVRAM_WRITE_SUPPORT
2389 /****************************************************************************/
2390 /* Write a dword (32 bits) to NVRAM. */
2391 /* */
2392 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */
2393 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */
2394 /* enabled NVRAM write access. */
2395 /* */
2396 /* Returns: */
2397 /* 0 on success, positive value on failure. */
2398 /****************************************************************************/
2399 static int
bce_nvram_write_dword(struct bce_softc * sc,u32 offset,u8 * val,u32 cmd_flags)2400 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2401 u32 cmd_flags)
2402 {
2403 u32 cmd, val32;
2404 int j, rc = 0;
2405
2406 DBENTER(BCE_VERBOSE_NVRAM);
2407
2408 /* Build the command word. */
2409 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2410
2411 /* Calculate the offset for buffered flash if translation is used. */
2412 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2413 offset = ((offset / sc->bce_flash_info->page_size) <<
2414 sc->bce_flash_info->page_bits) +
2415 (offset % sc->bce_flash_info->page_size);
2416 }
2417
2418 /*
2419 * Clear the DONE bit separately, convert NVRAM data to big-endian,
2420 * set the NVRAM address to write, and issue the write command
2421 */
2422 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2423 memcpy(&val32, val, 4);
2424 val32 = htobe32(val32);
2425 REG_WR(sc, BCE_NVM_WRITE, val32);
2426 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2427 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2428
2429 /* Wait for completion. */
2430 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2431 DELAY(5);
2432
2433 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2434 break;
2435 }
2436 if (j >= NVRAM_TIMEOUT_COUNT) {
2437 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2438 "offset 0x%08X\n", __FILE__, __LINE__, offset);
2439 rc = EBUSY;
2440 }
2441
2442 DBEXIT(BCE_VERBOSE_NVRAM);
2443 return (rc);
2444 }
2445 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2446
2447 /****************************************************************************/
2448 /* Initialize NVRAM access. */
2449 /* */
2450 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
2451 /* access that device. */
2452 /* */
2453 /* Returns: */
2454 /* 0 on success, positive value on failure. */
2455 /****************************************************************************/
2456 static int
bce_init_nvram(struct bce_softc * sc)2457 bce_init_nvram(struct bce_softc *sc)
2458 {
2459 u32 val;
2460 int j, entry_count, rc = 0;
2461 const struct flash_spec *flash;
2462
2463 DBENTER(BCE_VERBOSE_NVRAM);
2464
2465 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2466 sc->bce_flash_info = &flash_5709;
2467 goto bce_init_nvram_get_flash_size;
2468 }
2469
2470 /* Determine the selected interface. */
2471 val = REG_RD(sc, BCE_NVM_CFG1);
2472
2473 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2474
2475 /*
2476 * Flash reconfiguration is required to support additional
2477 * NVRAM devices not directly supported in hardware.
2478 * Check if the flash interface was reconfigured
2479 * by the bootcode.
2480 */
2481
2482 if (val & 0x40000000) {
2483 /* Flash interface reconfigured by bootcode. */
2484
2485 DBPRINT(sc,BCE_INFO_LOAD,
2486 "bce_init_nvram(): Flash WAS reconfigured.\n");
2487
2488 for (j = 0, flash = &flash_table[0]; j < entry_count;
2489 j++, flash++) {
2490 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2491 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2492 sc->bce_flash_info = flash;
2493 break;
2494 }
2495 }
2496 } else {
2497 /* Flash interface not yet reconfigured. */
2498 u32 mask;
2499
2500 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2501 __FUNCTION__);
2502
2503 if (val & (1 << 23))
2504 mask = FLASH_BACKUP_STRAP_MASK;
2505 else
2506 mask = FLASH_STRAP_MASK;
2507
2508 /* Look for the matching NVRAM device configuration data. */
2509 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2510 /* Check if the device matches any of the known devices. */
2511 if ((val & mask) == (flash->strapping & mask)) {
2512 /* Found a device match. */
2513 sc->bce_flash_info = flash;
2514
2515 /* Request access to the flash interface. */
2516 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2517 return rc;
2518
2519 /* Reconfigure the flash interface. */
2520 bce_enable_nvram_access(sc);
2521 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2522 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2523 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2524 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2525 bce_disable_nvram_access(sc);
2526 bce_release_nvram_lock(sc);
2527
2528 break;
2529 }
2530 }
2531 }
2532
2533 /* Check if a matching device was found. */
2534 if (j == entry_count) {
2535 sc->bce_flash_info = NULL;
2536 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2537 __FILE__, __LINE__);
2538 DBEXIT(BCE_VERBOSE_NVRAM);
2539 return (ENODEV);
2540 }
2541
2542 bce_init_nvram_get_flash_size:
2543 /* Write the flash config data to the shared memory interface. */
2544 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2545 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2546 if (val)
2547 sc->bce_flash_size = val;
2548 else
2549 sc->bce_flash_size = sc->bce_flash_info->total_size;
2550
2551 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2552 __FUNCTION__, sc->bce_flash_info->name,
2553 sc->bce_flash_info->total_size);
2554
2555 DBEXIT(BCE_VERBOSE_NVRAM);
2556 return rc;
2557 }
2558
2559 /****************************************************************************/
2560 /* Read an arbitrary range of data from NVRAM. */
2561 /* */
2562 /* Prepares the NVRAM interface for access and reads the requested data */
2563 /* into the supplied buffer. */
2564 /* */
2565 /* Returns: */
2566 /* 0 on success and the data read, positive value on failure. */
2567 /****************************************************************************/
2568 static int
bce_nvram_read(struct bce_softc * sc,u32 offset,u8 * ret_buf,int buf_size)2569 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2570 int buf_size)
2571 {
2572 int rc = 0;
2573 u32 cmd_flags, offset32, len32, extra;
2574
2575 DBENTER(BCE_VERBOSE_NVRAM);
2576
2577 if (buf_size == 0)
2578 goto bce_nvram_read_exit;
2579
2580 /* Request access to the flash interface. */
2581 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2582 goto bce_nvram_read_exit;
2583
2584 /* Enable access to flash interface */
2585 bce_enable_nvram_access(sc);
2586
2587 len32 = buf_size;
2588 offset32 = offset;
2589 extra = 0;
2590
2591 cmd_flags = 0;
2592
2593 if (offset32 & 3) {
2594 u8 buf[4];
2595 u32 pre_len;
2596
2597 offset32 &= ~3;
2598 pre_len = 4 - (offset & 3);
2599
2600 if (pre_len >= len32) {
2601 pre_len = len32;
2602 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2603 }
2604 else {
2605 cmd_flags = BCE_NVM_COMMAND_FIRST;
2606 }
2607
2608 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2609
2610 if (rc)
2611 return rc;
2612
2613 memcpy(ret_buf, buf + (offset & 3), pre_len);
2614
2615 offset32 += 4;
2616 ret_buf += pre_len;
2617 len32 -= pre_len;
2618 }
2619
2620 if (len32 & 3) {
2621 extra = 4 - (len32 & 3);
2622 len32 = (len32 + 4) & ~3;
2623 }
2624
2625 if (len32 == 4) {
2626 u8 buf[4];
2627
2628 if (cmd_flags)
2629 cmd_flags = BCE_NVM_COMMAND_LAST;
2630 else
2631 cmd_flags = BCE_NVM_COMMAND_FIRST |
2632 BCE_NVM_COMMAND_LAST;
2633
2634 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2635
2636 memcpy(ret_buf, buf, 4 - extra);
2637 }
2638 else if (len32 > 0) {
2639 u8 buf[4];
2640
2641 /* Read the first word. */
2642 if (cmd_flags)
2643 cmd_flags = 0;
2644 else
2645 cmd_flags = BCE_NVM_COMMAND_FIRST;
2646
2647 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2648
2649 /* Advance to the next dword. */
2650 offset32 += 4;
2651 ret_buf += 4;
2652 len32 -= 4;
2653
2654 while (len32 > 4 && rc == 0) {
2655 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2656
2657 /* Advance to the next dword. */
2658 offset32 += 4;
2659 ret_buf += 4;
2660 len32 -= 4;
2661 }
2662
2663 if (rc)
2664 goto bce_nvram_read_locked_exit;
2665
2666 cmd_flags = BCE_NVM_COMMAND_LAST;
2667 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2668
2669 memcpy(ret_buf, buf, 4 - extra);
2670 }
2671
2672 bce_nvram_read_locked_exit:
2673 /* Disable access to flash interface and release the lock. */
2674 bce_disable_nvram_access(sc);
2675 bce_release_nvram_lock(sc);
2676
2677 bce_nvram_read_exit:
2678 DBEXIT(BCE_VERBOSE_NVRAM);
2679 return rc;
2680 }
2681
2682 #ifdef BCE_NVRAM_WRITE_SUPPORT
2683 /****************************************************************************/
2684 /* Write an arbitrary range of data from NVRAM. */
2685 /* */
2686 /* Prepares the NVRAM interface for write access and writes the requested */
2687 /* data from the supplied buffer. The caller is responsible for */
2688 /* calculating any appropriate CRCs. */
2689 /* */
2690 /* Returns: */
2691 /* 0 on success, positive value on failure. */
2692 /****************************************************************************/
2693 static int
bce_nvram_write(struct bce_softc * sc,u32 offset,u8 * data_buf,int buf_size)2694 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2695 int buf_size)
2696 {
2697 u32 written, offset32, len32;
2698 u8 *buf, start[4], end[4];
2699 int rc = 0;
2700 int align_start, align_end;
2701
2702 DBENTER(BCE_VERBOSE_NVRAM);
2703
2704 buf = data_buf;
2705 offset32 = offset;
2706 len32 = buf_size;
2707 align_start = align_end = 0;
2708
2709 if ((align_start = (offset32 & 3))) {
2710 offset32 &= ~3;
2711 len32 += align_start;
2712 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2713 goto bce_nvram_write_exit;
2714 }
2715
2716 if (len32 & 3) {
2717 if ((len32 > 4) || !align_start) {
2718 align_end = 4 - (len32 & 3);
2719 len32 += align_end;
2720 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2721 end, 4))) {
2722 goto bce_nvram_write_exit;
2723 }
2724 }
2725 }
2726
2727 if (align_start || align_end) {
2728 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2729 if (buf == NULL) {
2730 rc = ENOMEM;
2731 goto bce_nvram_write_exit;
2732 }
2733
2734 if (align_start) {
2735 memcpy(buf, start, 4);
2736 }
2737
2738 if (align_end) {
2739 memcpy(buf + len32 - 4, end, 4);
2740 }
2741 memcpy(buf + align_start, data_buf, buf_size);
2742 }
2743
2744 written = 0;
2745 while ((written < len32) && (rc == 0)) {
2746 u32 page_start, page_end, data_start, data_end;
2747 u32 addr, cmd_flags;
2748 int i;
2749 u8 flash_buffer[264];
2750
2751 /* Find the page_start addr */
2752 page_start = offset32 + written;
2753 page_start -= (page_start % sc->bce_flash_info->page_size);
2754 /* Find the page_end addr */
2755 page_end = page_start + sc->bce_flash_info->page_size;
2756 /* Find the data_start addr */
2757 data_start = (written == 0) ? offset32 : page_start;
2758 /* Find the data_end addr */
2759 data_end = (page_end > offset32 + len32) ?
2760 (offset32 + len32) : page_end;
2761
2762 /* Request access to the flash interface. */
2763 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2764 goto bce_nvram_write_exit;
2765
2766 /* Enable access to flash interface */
2767 bce_enable_nvram_access(sc);
2768
2769 cmd_flags = BCE_NVM_COMMAND_FIRST;
2770 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2771 int j;
2772
2773 /* Read the whole page into the buffer
2774 * (non-buffer flash only) */
2775 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2776 if (j == (sc->bce_flash_info->page_size - 4)) {
2777 cmd_flags |= BCE_NVM_COMMAND_LAST;
2778 }
2779 rc = bce_nvram_read_dword(sc,
2780 page_start + j,
2781 &flash_buffer[j],
2782 cmd_flags);
2783
2784 if (rc)
2785 goto bce_nvram_write_locked_exit;
2786
2787 cmd_flags = 0;
2788 }
2789 }
2790
2791 /* Enable writes to flash interface (unlock write-protect) */
2792 if ((rc = bce_enable_nvram_write(sc)) != 0)
2793 goto bce_nvram_write_locked_exit;
2794
2795 /* Erase the page */
2796 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2797 goto bce_nvram_write_locked_exit;
2798
2799 /* Re-enable the write again for the actual write */
2800 bce_enable_nvram_write(sc);
2801
2802 /* Loop to write back the buffer data from page_start to
2803 * data_start */
2804 i = 0;
2805 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2806 for (addr = page_start; addr < data_start;
2807 addr += 4, i += 4) {
2808 rc = bce_nvram_write_dword(sc, addr,
2809 &flash_buffer[i], cmd_flags);
2810
2811 if (rc != 0)
2812 goto bce_nvram_write_locked_exit;
2813
2814 cmd_flags = 0;
2815 }
2816 }
2817
2818 /* Loop to write the new data from data_start to data_end */
2819 for (addr = data_start; addr < data_end; addr += 4, i++) {
2820 if ((addr == page_end - 4) ||
2821 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2822 (addr == data_end - 4))) {
2823 cmd_flags |= BCE_NVM_COMMAND_LAST;
2824 }
2825 rc = bce_nvram_write_dword(sc, addr, buf,
2826 cmd_flags);
2827
2828 if (rc != 0)
2829 goto bce_nvram_write_locked_exit;
2830
2831 cmd_flags = 0;
2832 buf += 4;
2833 }
2834
2835 /* Loop to write back the buffer data from data_end
2836 * to page_end */
2837 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2838 for (addr = data_end; addr < page_end;
2839 addr += 4, i += 4) {
2840 if (addr == page_end-4) {
2841 cmd_flags = BCE_NVM_COMMAND_LAST;
2842 }
2843 rc = bce_nvram_write_dword(sc, addr,
2844 &flash_buffer[i], cmd_flags);
2845
2846 if (rc != 0)
2847 goto bce_nvram_write_locked_exit;
2848
2849 cmd_flags = 0;
2850 }
2851 }
2852
2853 /* Disable writes to flash interface (lock write-protect) */
2854 bce_disable_nvram_write(sc);
2855
2856 /* Disable access to flash interface */
2857 bce_disable_nvram_access(sc);
2858 bce_release_nvram_lock(sc);
2859
2860 /* Increment written */
2861 written += data_end - data_start;
2862 }
2863
2864 goto bce_nvram_write_exit;
2865
2866 bce_nvram_write_locked_exit:
2867 bce_disable_nvram_write(sc);
2868 bce_disable_nvram_access(sc);
2869 bce_release_nvram_lock(sc);
2870
2871 bce_nvram_write_exit:
2872 if (align_start || align_end)
2873 free(buf, M_DEVBUF);
2874
2875 DBEXIT(BCE_VERBOSE_NVRAM);
2876 return (rc);
2877 }
2878 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2879
2880 /****************************************************************************/
2881 /* Verifies that NVRAM is accessible and contains valid data. */
2882 /* */
2883 /* Reads the configuration data from NVRAM and verifies that the CRC is */
2884 /* correct. */
2885 /* */
2886 /* Returns: */
2887 /* 0 on success, positive value on failure. */
2888 /****************************************************************************/
2889 static int
bce_nvram_test(struct bce_softc * sc)2890 bce_nvram_test(struct bce_softc *sc)
2891 {
2892 u32 buf[BCE_NVRAM_SIZE / 4];
2893 u8 *data = (u8 *) buf;
2894 int rc = 0;
2895 u32 magic, csum;
2896
2897 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2898
2899 /*
2900 * Check that the device NVRAM is valid by reading
2901 * the magic value at offset 0.
2902 */
2903 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2904 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2905 __FILE__, __LINE__);
2906 goto bce_nvram_test_exit;
2907 }
2908
2909 /*
2910 * Verify that offset 0 of the NVRAM contains
2911 * a valid magic number.
2912 */
2913 magic = bce_be32toh(buf[0]);
2914 if (magic != BCE_NVRAM_MAGIC) {
2915 rc = ENODEV;
2916 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2917 "Expected: 0x%08X, Found: 0x%08X\n",
2918 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2919 goto bce_nvram_test_exit;
2920 }
2921
2922 /*
2923 * Verify that the device NVRAM includes valid
2924 * configuration data.
2925 */
2926 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2927 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2928 "Information from NVRAM!\n", __FILE__, __LINE__);
2929 goto bce_nvram_test_exit;
2930 }
2931
2932 csum = ether_crc32_le(data, 0x100);
2933 if (csum != BCE_CRC32_RESIDUAL) {
2934 rc = ENODEV;
2935 BCE_PRINTF("%s(%d): Invalid manufacturing information "
2936 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
2937 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2938 goto bce_nvram_test_exit;
2939 }
2940
2941 csum = ether_crc32_le(data + 0x100, 0x100);
2942 if (csum != BCE_CRC32_RESIDUAL) {
2943 rc = ENODEV;
2944 BCE_PRINTF("%s(%d): Invalid feature configuration "
2945 "information NVRAM CRC! Expected: 0x%08X, "
2946 "Found: 08%08X\n", __FILE__, __LINE__,
2947 BCE_CRC32_RESIDUAL, csum);
2948 }
2949
2950 bce_nvram_test_exit:
2951 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2952 return rc;
2953 }
2954
2955 /****************************************************************************/
2956 /* Calculates the size of the buffers to allocate based on the MTU. */
2957 /* */
2958 /* Returns: */
2959 /* Nothing. */
2960 /****************************************************************************/
2961 static void
bce_get_rx_buffer_sizes(struct bce_softc * sc,int mtu)2962 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
2963 {
2964 DBENTER(BCE_VERBOSE_LOAD);
2965
2966 /* Use a single allocation type when header splitting enabled. */
2967 if (bce_hdr_split == TRUE) {
2968 sc->rx_bd_mbuf_alloc_size = MHLEN;
2969 /* Make sure offset is 16 byte aligned for hardware. */
2970 sc->rx_bd_mbuf_align_pad =
2971 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN);
2972 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
2973 sc->rx_bd_mbuf_align_pad;
2974 } else {
2975 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2976 ETHER_CRC_LEN) > MCLBYTES) {
2977 /* Setup for jumbo RX buffer allocations. */
2978 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
2979 sc->rx_bd_mbuf_align_pad =
2980 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
2981 sc->rx_bd_mbuf_data_len =
2982 sc->rx_bd_mbuf_alloc_size -
2983 sc->rx_bd_mbuf_align_pad;
2984 } else {
2985 /* Setup for standard RX buffer allocations. */
2986 sc->rx_bd_mbuf_alloc_size = MCLBYTES;
2987 sc->rx_bd_mbuf_align_pad =
2988 roundup2(MCLBYTES, 16) - MCLBYTES;
2989 sc->rx_bd_mbuf_data_len =
2990 sc->rx_bd_mbuf_alloc_size -
2991 sc->rx_bd_mbuf_align_pad;
2992 }
2993 }
2994
2995 // DBPRINT(sc, BCE_INFO_LOAD,
2996 DBPRINT(sc, BCE_WARN,
2997 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
2998 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
2999 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3000 sc->rx_bd_mbuf_align_pad);
3001
3002 DBEXIT(BCE_VERBOSE_LOAD);
3003 }
3004
3005 /****************************************************************************/
3006 /* Identifies the current media type of the controller and sets the PHY */
3007 /* address. */
3008 /* */
3009 /* Returns: */
3010 /* Nothing. */
3011 /****************************************************************************/
3012 static void
bce_get_media(struct bce_softc * sc)3013 bce_get_media(struct bce_softc *sc)
3014 {
3015 u32 val;
3016
3017 DBENTER(BCE_VERBOSE_PHY);
3018
3019 /* Assume PHY address for copper controllers. */
3020 sc->bce_phy_addr = 1;
3021
3022 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3023 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3024 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3025 u32 strap;
3026
3027 /*
3028 * The BCM5709S is software configurable
3029 * for Copper or SerDes operation.
3030 */
3031 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3032 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3033 "for copper.\n");
3034 goto bce_get_media_exit;
3035 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3036 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3037 "for dual media.\n");
3038 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3039 goto bce_get_media_exit;
3040 }
3041
3042 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3043 strap = (val &
3044 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3045 else
3046 strap = (val &
3047 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3048
3049 if (pci_get_function(sc->bce_dev) == 0) {
3050 switch (strap) {
3051 case 0x4:
3052 case 0x5:
3053 case 0x6:
3054 DBPRINT(sc, BCE_INFO_LOAD,
3055 "BCM5709 s/w configured for SerDes.\n");
3056 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3057 break;
3058 default:
3059 DBPRINT(sc, BCE_INFO_LOAD,
3060 "BCM5709 s/w configured for Copper.\n");
3061 break;
3062 }
3063 } else {
3064 switch (strap) {
3065 case 0x1:
3066 case 0x2:
3067 case 0x4:
3068 DBPRINT(sc, BCE_INFO_LOAD,
3069 "BCM5709 s/w configured for SerDes.\n");
3070 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3071 break;
3072 default:
3073 DBPRINT(sc, BCE_INFO_LOAD,
3074 "BCM5709 s/w configured for Copper.\n");
3075 break;
3076 }
3077 }
3078
3079 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3080 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3081
3082 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3083 sc->bce_flags |= BCE_NO_WOL_FLAG;
3084
3085 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3086 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3087
3088 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3089 /* 5708S/09S/16S use a separate PHY for SerDes. */
3090 sc->bce_phy_addr = 2;
3091
3092 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3093 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3094 sc->bce_phy_flags |=
3095 BCE_PHY_2_5G_CAPABLE_FLAG;
3096 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3097 "capable adapter\n");
3098 }
3099 }
3100 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3101 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3102 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3103
3104 bce_get_media_exit:
3105 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3106 "Using PHY address %d.\n", sc->bce_phy_addr);
3107
3108 DBEXIT(BCE_VERBOSE_PHY);
3109 }
3110
3111 /****************************************************************************/
3112 /* Performs PHY initialization required before MII drivers access the */
3113 /* device. */
3114 /* */
3115 /* Returns: */
3116 /* Nothing. */
3117 /****************************************************************************/
3118 static void
bce_init_media(struct bce_softc * sc)3119 bce_init_media(struct bce_softc *sc)
3120 {
3121 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3122 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3123 /*
3124 * Configure 5709S/5716S PHYs to use traditional IEEE
3125 * Clause 22 method. Otherwise we have no way to attach
3126 * the PHY in mii(4) layer. PHY specific configuration
3127 * is done in mii layer.
3128 */
3129
3130 /* Select auto-negotiation MMD of the PHY. */
3131 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3132 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3133 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3134 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3135
3136 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3137 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3138 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3139 }
3140 }
3141
3142 /****************************************************************************/
3143 /* Free any DMA memory owned by the driver. */
3144 /* */
3145 /* Scans through each data structure that requires DMA memory and frees */
3146 /* the memory if allocated. */
3147 /* */
3148 /* Returns: */
3149 /* Nothing. */
3150 /****************************************************************************/
3151 static void
bce_dma_free(struct bce_softc * sc)3152 bce_dma_free(struct bce_softc *sc)
3153 {
3154 int i;
3155
3156 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3157
3158 /* Free, unmap, and destroy the status block. */
3159 if (sc->status_block_paddr != 0) {
3160 bus_dmamap_unload(
3161 sc->status_tag,
3162 sc->status_map);
3163 sc->status_block_paddr = 0;
3164 }
3165
3166 if (sc->status_block != NULL) {
3167 bus_dmamem_free(
3168 sc->status_tag,
3169 sc->status_block,
3170 sc->status_map);
3171 sc->status_block = NULL;
3172 }
3173
3174 if (sc->status_tag != NULL) {
3175 bus_dma_tag_destroy(sc->status_tag);
3176 sc->status_tag = NULL;
3177 }
3178
3179 /* Free, unmap, and destroy the statistics block. */
3180 if (sc->stats_block_paddr != 0) {
3181 bus_dmamap_unload(
3182 sc->stats_tag,
3183 sc->stats_map);
3184 sc->stats_block_paddr = 0;
3185 }
3186
3187 if (sc->stats_block != NULL) {
3188 bus_dmamem_free(
3189 sc->stats_tag,
3190 sc->stats_block,
3191 sc->stats_map);
3192 sc->stats_block = NULL;
3193 }
3194
3195 if (sc->stats_tag != NULL) {
3196 bus_dma_tag_destroy(sc->stats_tag);
3197 sc->stats_tag = NULL;
3198 }
3199
3200 /* Free, unmap and destroy all context memory pages. */
3201 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3202 for (i = 0; i < sc->ctx_pages; i++ ) {
3203 if (sc->ctx_paddr[i] != 0) {
3204 bus_dmamap_unload(
3205 sc->ctx_tag,
3206 sc->ctx_map[i]);
3207 sc->ctx_paddr[i] = 0;
3208 }
3209
3210 if (sc->ctx_block[i] != NULL) {
3211 bus_dmamem_free(
3212 sc->ctx_tag,
3213 sc->ctx_block[i],
3214 sc->ctx_map[i]);
3215 sc->ctx_block[i] = NULL;
3216 }
3217 }
3218
3219 /* Destroy the context memory tag. */
3220 if (sc->ctx_tag != NULL) {
3221 bus_dma_tag_destroy(sc->ctx_tag);
3222 sc->ctx_tag = NULL;
3223 }
3224 }
3225
3226 /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3227 for (i = 0; i < sc->tx_pages; i++ ) {
3228 if (sc->tx_bd_chain_paddr[i] != 0) {
3229 bus_dmamap_unload(
3230 sc->tx_bd_chain_tag,
3231 sc->tx_bd_chain_map[i]);
3232 sc->tx_bd_chain_paddr[i] = 0;
3233 }
3234
3235 if (sc->tx_bd_chain[i] != NULL) {
3236 bus_dmamem_free(
3237 sc->tx_bd_chain_tag,
3238 sc->tx_bd_chain[i],
3239 sc->tx_bd_chain_map[i]);
3240 sc->tx_bd_chain[i] = NULL;
3241 }
3242 }
3243
3244 /* Destroy the TX buffer descriptor tag. */
3245 if (sc->tx_bd_chain_tag != NULL) {
3246 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3247 sc->tx_bd_chain_tag = NULL;
3248 }
3249
3250 /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3251 for (i = 0; i < sc->rx_pages; i++ ) {
3252 if (sc->rx_bd_chain_paddr[i] != 0) {
3253 bus_dmamap_unload(
3254 sc->rx_bd_chain_tag,
3255 sc->rx_bd_chain_map[i]);
3256 sc->rx_bd_chain_paddr[i] = 0;
3257 }
3258
3259 if (sc->rx_bd_chain[i] != NULL) {
3260 bus_dmamem_free(
3261 sc->rx_bd_chain_tag,
3262 sc->rx_bd_chain[i],
3263 sc->rx_bd_chain_map[i]);
3264 sc->rx_bd_chain[i] = NULL;
3265 }
3266 }
3267
3268 /* Destroy the RX buffer descriptor tag. */
3269 if (sc->rx_bd_chain_tag != NULL) {
3270 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3271 sc->rx_bd_chain_tag = NULL;
3272 }
3273
3274 /* Free, unmap and destroy all page buffer descriptor chain pages. */
3275 if (bce_hdr_split == TRUE) {
3276 for (i = 0; i < sc->pg_pages; i++ ) {
3277 if (sc->pg_bd_chain_paddr[i] != 0) {
3278 bus_dmamap_unload(
3279 sc->pg_bd_chain_tag,
3280 sc->pg_bd_chain_map[i]);
3281 sc->pg_bd_chain_paddr[i] = 0;
3282 }
3283
3284 if (sc->pg_bd_chain[i] != NULL) {
3285 bus_dmamem_free(
3286 sc->pg_bd_chain_tag,
3287 sc->pg_bd_chain[i],
3288 sc->pg_bd_chain_map[i]);
3289 sc->pg_bd_chain[i] = NULL;
3290 }
3291 }
3292
3293 /* Destroy the page buffer descriptor tag. */
3294 if (sc->pg_bd_chain_tag != NULL) {
3295 bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3296 sc->pg_bd_chain_tag = NULL;
3297 }
3298 }
3299
3300 /* Unload and destroy the TX mbuf maps. */
3301 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3302 if (sc->tx_mbuf_map[i] != NULL) {
3303 bus_dmamap_unload(sc->tx_mbuf_tag,
3304 sc->tx_mbuf_map[i]);
3305 bus_dmamap_destroy(sc->tx_mbuf_tag,
3306 sc->tx_mbuf_map[i]);
3307 sc->tx_mbuf_map[i] = NULL;
3308 }
3309 }
3310
3311 /* Destroy the TX mbuf tag. */
3312 if (sc->tx_mbuf_tag != NULL) {
3313 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3314 sc->tx_mbuf_tag = NULL;
3315 }
3316
3317 /* Unload and destroy the RX mbuf maps. */
3318 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3319 if (sc->rx_mbuf_map[i] != NULL) {
3320 bus_dmamap_unload(sc->rx_mbuf_tag,
3321 sc->rx_mbuf_map[i]);
3322 bus_dmamap_destroy(sc->rx_mbuf_tag,
3323 sc->rx_mbuf_map[i]);
3324 sc->rx_mbuf_map[i] = NULL;
3325 }
3326 }
3327
3328 /* Destroy the RX mbuf tag. */
3329 if (sc->rx_mbuf_tag != NULL) {
3330 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3331 sc->rx_mbuf_tag = NULL;
3332 }
3333
3334 /* Unload and destroy the page mbuf maps. */
3335 if (bce_hdr_split == TRUE) {
3336 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3337 if (sc->pg_mbuf_map[i] != NULL) {
3338 bus_dmamap_unload(sc->pg_mbuf_tag,
3339 sc->pg_mbuf_map[i]);
3340 bus_dmamap_destroy(sc->pg_mbuf_tag,
3341 sc->pg_mbuf_map[i]);
3342 sc->pg_mbuf_map[i] = NULL;
3343 }
3344 }
3345
3346 /* Destroy the page mbuf tag. */
3347 if (sc->pg_mbuf_tag != NULL) {
3348 bus_dma_tag_destroy(sc->pg_mbuf_tag);
3349 sc->pg_mbuf_tag = NULL;
3350 }
3351 }
3352
3353 /* Destroy the parent tag */
3354 if (sc->parent_tag != NULL) {
3355 bus_dma_tag_destroy(sc->parent_tag);
3356 sc->parent_tag = NULL;
3357 }
3358
3359 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3360 }
3361
3362 /****************************************************************************/
3363 /* Get DMA memory from the OS. */
3364 /* */
3365 /* Validates that the OS has provided DMA buffers in response to a */
3366 /* bus_dmamap_load() call and saves the physical address of those buffers. */
3367 /* When the callback is used the OS will return 0 for the mapping function */
3368 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
3369 /* failures back to the caller. */
3370 /* */
3371 /* Returns: */
3372 /* Nothing. */
3373 /****************************************************************************/
3374 static void
bce_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)3375 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3376 {
3377 bus_addr_t *busaddr = arg;
3378
3379 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3380 __FUNCTION__, nseg));
3381 /* Simulate a mapping failure. */
3382 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3383 error = ENOMEM);
3384
3385 /* ToDo: How to increment debug sim_count variable here? */
3386
3387 /* Check for an error and signal the caller that an error occurred. */
3388 if (error) {
3389 *busaddr = 0;
3390 } else {
3391 *busaddr = segs->ds_addr;
3392 }
3393 }
3394
3395 /****************************************************************************/
3396 /* Allocate any DMA memory needed by the driver. */
3397 /* */
3398 /* Allocates DMA memory needed for the various global structures needed by */
3399 /* hardware. */
3400 /* */
3401 /* Memory alignment requirements: */
3402 /* +-----------------+----------+----------+----------+----------+ */
3403 /* | | 5706 | 5708 | 5709 | 5716 | */
3404 /* +-----------------+----------+----------+----------+----------+ */
3405 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
3406 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
3407 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
3408 /* |PG Buffers | none | none | none | none | */
3409 /* |TX Buffers | none | none | none | none | */
3410 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
3411 /* |Context Memory | | | | | */
3412 /* +-----------------+----------+----------+----------+----------+ */
3413 /* */
3414 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
3415 /* */
3416 /* Returns: */
3417 /* 0 for success, positive value for failure. */
3418 /****************************************************************************/
3419 static int
bce_dma_alloc(device_t dev)3420 bce_dma_alloc(device_t dev)
3421 {
3422 struct bce_softc *sc;
3423 int i, error, rc = 0;
3424 bus_size_t max_size, max_seg_size;
3425 int max_segments;
3426
3427 sc = device_get_softc(dev);
3428
3429 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3430
3431 /*
3432 * Allocate the parent bus DMA tag appropriate for PCI.
3433 */
3434 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3435 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3436 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3437 &sc->parent_tag)) {
3438 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3439 __FILE__, __LINE__);
3440 rc = ENOMEM;
3441 goto bce_dma_alloc_exit;
3442 }
3443
3444 /*
3445 * Create a DMA tag for the status block, allocate and clear the
3446 * memory, map the memory into DMA space, and fetch the physical
3447 * address of the block.
3448 */
3449 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3450 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3451 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3452 0, NULL, NULL, &sc->status_tag)) {
3453 BCE_PRINTF("%s(%d): Could not allocate status block "
3454 "DMA tag!\n", __FILE__, __LINE__);
3455 rc = ENOMEM;
3456 goto bce_dma_alloc_exit;
3457 }
3458
3459 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3460 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3461 &sc->status_map)) {
3462 BCE_PRINTF("%s(%d): Could not allocate status block "
3463 "DMA memory!\n", __FILE__, __LINE__);
3464 rc = ENOMEM;
3465 goto bce_dma_alloc_exit;
3466 }
3467
3468 error = bus_dmamap_load(sc->status_tag, sc->status_map,
3469 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3470 &sc->status_block_paddr, BUS_DMA_NOWAIT);
3471
3472 if (error || sc->status_block_paddr == 0) {
3473 BCE_PRINTF("%s(%d): Could not map status block "
3474 "DMA memory!\n", __FILE__, __LINE__);
3475 rc = ENOMEM;
3476 goto bce_dma_alloc_exit;
3477 }
3478
3479 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3480 __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3481
3482 /*
3483 * Create a DMA tag for the statistics block, allocate and clear the
3484 * memory, map the memory into DMA space, and fetch the physical
3485 * address of the block.
3486 */
3487 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3488 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3489 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3490 0, NULL, NULL, &sc->stats_tag)) {
3491 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3492 "DMA tag!\n", __FILE__, __LINE__);
3493 rc = ENOMEM;
3494 goto bce_dma_alloc_exit;
3495 }
3496
3497 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3498 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3499 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3500 "DMA memory!\n", __FILE__, __LINE__);
3501 rc = ENOMEM;
3502 goto bce_dma_alloc_exit;
3503 }
3504
3505 error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3506 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3507 &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3508
3509 if (error || sc->stats_block_paddr == 0) {
3510 BCE_PRINTF("%s(%d): Could not map statistics block "
3511 "DMA memory!\n", __FILE__, __LINE__);
3512 rc = ENOMEM;
3513 goto bce_dma_alloc_exit;
3514 }
3515
3516 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3517 __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3518
3519 /* BCM5709 uses host memory as cache for context memory. */
3520 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3521 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3522 if (sc->ctx_pages == 0)
3523 sc->ctx_pages = 1;
3524
3525 DBRUNIF((sc->ctx_pages > 512),
3526 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3527 __FILE__, __LINE__, sc->ctx_pages));
3528
3529 /*
3530 * Create a DMA tag for the context pages,
3531 * allocate and clear the memory, map the
3532 * memory into DMA space, and fetch the
3533 * physical address of the block.
3534 */
3535 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3536 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3537 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3538 0, NULL, NULL, &sc->ctx_tag)) {
3539 BCE_PRINTF("%s(%d): Could not allocate CTX "
3540 "DMA tag!\n", __FILE__, __LINE__);
3541 rc = ENOMEM;
3542 goto bce_dma_alloc_exit;
3543 }
3544
3545 for (i = 0; i < sc->ctx_pages; i++) {
3546 if(bus_dmamem_alloc(sc->ctx_tag,
3547 (void **)&sc->ctx_block[i],
3548 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3549 &sc->ctx_map[i])) {
3550 BCE_PRINTF("%s(%d): Could not allocate CTX "
3551 "DMA memory!\n", __FILE__, __LINE__);
3552 rc = ENOMEM;
3553 goto bce_dma_alloc_exit;
3554 }
3555
3556 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3557 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3558 &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3559
3560 if (error || sc->ctx_paddr[i] == 0) {
3561 BCE_PRINTF("%s(%d): Could not map CTX "
3562 "DMA memory!\n", __FILE__, __LINE__);
3563 rc = ENOMEM;
3564 goto bce_dma_alloc_exit;
3565 }
3566
3567 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3568 "= 0x%jX\n", __FUNCTION__, i,
3569 (uintmax_t) sc->ctx_paddr[i]);
3570 }
3571 }
3572
3573 /*
3574 * Create a DMA tag for the TX buffer descriptor chain,
3575 * allocate and clear the memory, and fetch the
3576 * physical address of the block.
3577 */
3578 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3579 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3580 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3581 NULL, NULL, &sc->tx_bd_chain_tag)) {
3582 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3583 "chain DMA tag!\n", __FILE__, __LINE__);
3584 rc = ENOMEM;
3585 goto bce_dma_alloc_exit;
3586 }
3587
3588 for (i = 0; i < sc->tx_pages; i++) {
3589 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3590 (void **)&sc->tx_bd_chain[i],
3591 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3592 &sc->tx_bd_chain_map[i])) {
3593 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3594 "chain DMA memory!\n", __FILE__, __LINE__);
3595 rc = ENOMEM;
3596 goto bce_dma_alloc_exit;
3597 }
3598
3599 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3600 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3601 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3602 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3603
3604 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3605 BCE_PRINTF("%s(%d): Could not map TX descriptor "
3606 "chain DMA memory!\n", __FILE__, __LINE__);
3607 rc = ENOMEM;
3608 goto bce_dma_alloc_exit;
3609 }
3610
3611 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3612 "0x%jX\n", __FUNCTION__, i,
3613 (uintmax_t) sc->tx_bd_chain_paddr[i]);
3614 }
3615
3616 /* Check the required size before mapping to conserve resources. */
3617 if (bce_tso_enable) {
3618 max_size = BCE_TSO_MAX_SIZE;
3619 max_segments = BCE_MAX_SEGMENTS;
3620 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3621 } else {
3622 max_size = MCLBYTES * BCE_MAX_SEGMENTS;
3623 max_segments = BCE_MAX_SEGMENTS;
3624 max_seg_size = MCLBYTES;
3625 }
3626
3627 /* Create a DMA tag for TX mbufs. */
3628 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3629 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3630 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3631 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3632 __FILE__, __LINE__);
3633 rc = ENOMEM;
3634 goto bce_dma_alloc_exit;
3635 }
3636
3637 /* Create DMA maps for the TX mbufs clusters. */
3638 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3639 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3640 &sc->tx_mbuf_map[i])) {
3641 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3642 "map!\n", __FILE__, __LINE__);
3643 rc = ENOMEM;
3644 goto bce_dma_alloc_exit;
3645 }
3646 }
3647
3648 /*
3649 * Create a DMA tag for the RX buffer descriptor chain,
3650 * allocate and clear the memory, and fetch the physical
3651 * address of the blocks.
3652 */
3653 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3654 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3655 sc->max_bus_addr, NULL, NULL,
3656 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3657 0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3658 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3659 "DMA tag!\n", __FILE__, __LINE__);
3660 rc = ENOMEM;
3661 goto bce_dma_alloc_exit;
3662 }
3663
3664 for (i = 0; i < sc->rx_pages; i++) {
3665 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3666 (void **)&sc->rx_bd_chain[i],
3667 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3668 &sc->rx_bd_chain_map[i])) {
3669 BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3670 "chain DMA memory!\n", __FILE__, __LINE__);
3671 rc = ENOMEM;
3672 goto bce_dma_alloc_exit;
3673 }
3674
3675 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3676 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3677 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3678 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3679
3680 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3681 BCE_PRINTF("%s(%d): Could not map RX descriptor "
3682 "chain DMA memory!\n", __FILE__, __LINE__);
3683 rc = ENOMEM;
3684 goto bce_dma_alloc_exit;
3685 }
3686
3687 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3688 "0x%jX\n", __FUNCTION__, i,
3689 (uintmax_t) sc->rx_bd_chain_paddr[i]);
3690 }
3691
3692 /*
3693 * Create a DMA tag for RX mbufs.
3694 */
3695 if (bce_hdr_split == TRUE)
3696 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3697 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3698 else
3699 max_size = MJUM9BYTES;
3700
3701 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3702 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3703
3704 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3705 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3706 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3707 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3708 __FILE__, __LINE__);
3709 rc = ENOMEM;
3710 goto bce_dma_alloc_exit;
3711 }
3712
3713 /* Create DMA maps for the RX mbuf clusters. */
3714 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3715 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3716 &sc->rx_mbuf_map[i])) {
3717 BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3718 "DMA map!\n", __FILE__, __LINE__);
3719 rc = ENOMEM;
3720 goto bce_dma_alloc_exit;
3721 }
3722 }
3723
3724 if (bce_hdr_split == TRUE) {
3725 /*
3726 * Create a DMA tag for the page buffer descriptor chain,
3727 * allocate and clear the memory, and fetch the physical
3728 * address of the blocks.
3729 */
3730 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3731 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3732 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3733 0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3734 BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3735 "chain DMA tag!\n", __FILE__, __LINE__);
3736 rc = ENOMEM;
3737 goto bce_dma_alloc_exit;
3738 }
3739
3740 for (i = 0; i < sc->pg_pages; i++) {
3741 if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3742 (void **)&sc->pg_bd_chain[i],
3743 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3744 &sc->pg_bd_chain_map[i])) {
3745 BCE_PRINTF("%s(%d): Could not allocate page "
3746 "descriptor chain DMA memory!\n",
3747 __FILE__, __LINE__);
3748 rc = ENOMEM;
3749 goto bce_dma_alloc_exit;
3750 }
3751
3752 error = bus_dmamap_load(sc->pg_bd_chain_tag,
3753 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3754 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3755 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3756
3757 if (error || sc->pg_bd_chain_paddr[i] == 0) {
3758 BCE_PRINTF("%s(%d): Could not map page descriptor "
3759 "chain DMA memory!\n", __FILE__, __LINE__);
3760 rc = ENOMEM;
3761 goto bce_dma_alloc_exit;
3762 }
3763
3764 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3765 "0x%jX\n", __FUNCTION__, i,
3766 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3767 }
3768
3769 /*
3770 * Create a DMA tag for page mbufs.
3771 */
3772 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3773 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3774 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3775 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3776 "DMA tag!\n", __FILE__, __LINE__);
3777 rc = ENOMEM;
3778 goto bce_dma_alloc_exit;
3779 }
3780
3781 /* Create DMA maps for the page mbuf clusters. */
3782 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3783 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3784 &sc->pg_mbuf_map[i])) {
3785 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3786 "DMA map!\n", __FILE__, __LINE__);
3787 rc = ENOMEM;
3788 goto bce_dma_alloc_exit;
3789 }
3790 }
3791 }
3792
3793 bce_dma_alloc_exit:
3794 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3795 return(rc);
3796 }
3797
3798 /****************************************************************************/
3799 /* Release all resources used by the driver. */
3800 /* */
3801 /* Releases all resources acquired by the driver including interrupts, */
3802 /* interrupt handler, interfaces, mutexes, and DMA memory. */
3803 /* */
3804 /* Returns: */
3805 /* Nothing. */
3806 /****************************************************************************/
3807 static void
bce_release_resources(struct bce_softc * sc)3808 bce_release_resources(struct bce_softc *sc)
3809 {
3810 device_t dev;
3811
3812 DBENTER(BCE_VERBOSE_RESET);
3813
3814 dev = sc->bce_dev;
3815
3816 bce_dma_free(sc);
3817
3818 if (sc->bce_intrhand != NULL) {
3819 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3820 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3821 }
3822
3823 if (sc->bce_res_irq != NULL) {
3824 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3825 bus_release_resource(dev, SYS_RES_IRQ,
3826 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3827 }
3828
3829 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3830 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3831 pci_release_msi(dev);
3832 }
3833
3834 if (sc->bce_res_mem != NULL) {
3835 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3836 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3837 sc->bce_res_mem);
3838 }
3839
3840 if (sc->bce_ifp != NULL) {
3841 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3842 if_free(sc->bce_ifp);
3843 }
3844
3845 if (mtx_initialized(&sc->bce_mtx))
3846 BCE_LOCK_DESTROY(sc);
3847
3848 DBEXIT(BCE_VERBOSE_RESET);
3849 }
3850
3851 /****************************************************************************/
3852 /* Firmware synchronization. */
3853 /* */
3854 /* Before performing certain events such as a chip reset, synchronize with */
3855 /* the firmware first. */
3856 /* */
3857 /* Returns: */
3858 /* 0 for success, positive value for failure. */
3859 /****************************************************************************/
3860 static int
bce_fw_sync(struct bce_softc * sc,u32 msg_data)3861 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3862 {
3863 int i, rc = 0;
3864 u32 val;
3865
3866 DBENTER(BCE_VERBOSE_RESET);
3867
3868 /* Don't waste any time if we've timed out before. */
3869 if (sc->bce_fw_timed_out == TRUE) {
3870 rc = EBUSY;
3871 goto bce_fw_sync_exit;
3872 }
3873
3874 /* Increment the message sequence number. */
3875 sc->bce_fw_wr_seq++;
3876 msg_data |= sc->bce_fw_wr_seq;
3877
3878 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3879 "0x%08X\n", msg_data);
3880
3881 /* Send the message to the bootcode driver mailbox. */
3882 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3883
3884 /* Wait for the bootcode to acknowledge the message. */
3885 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3886 /* Check for a response in the bootcode firmware mailbox. */
3887 val = bce_shmem_rd(sc, BCE_FW_MB);
3888 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3889 break;
3890 DELAY(1000);
3891 }
3892
3893 /* If we've timed out, tell bootcode that we've stopped waiting. */
3894 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3895 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3896 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3897 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3898
3899 msg_data &= ~BCE_DRV_MSG_CODE;
3900 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3901
3902 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3903
3904 sc->bce_fw_timed_out = TRUE;
3905 rc = EBUSY;
3906 }
3907
3908 bce_fw_sync_exit:
3909 DBEXIT(BCE_VERBOSE_RESET);
3910 return (rc);
3911 }
3912
3913 /****************************************************************************/
3914 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
3915 /* */
3916 /* Returns: */
3917 /* Nothing. */
3918 /****************************************************************************/
3919 static void
bce_load_rv2p_fw(struct bce_softc * sc,const u32 * rv2p_code,u32 rv2p_code_len,u32 rv2p_proc)3920 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
3921 u32 rv2p_code_len, u32 rv2p_proc)
3922 {
3923 int i;
3924 u32 val;
3925
3926 DBENTER(BCE_VERBOSE_RESET);
3927
3928 /* Set the page size used by RV2P. */
3929 if (rv2p_proc == RV2P_PROC2) {
3930 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
3931 }
3932
3933 for (i = 0; i < rv2p_code_len; i += 8) {
3934 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
3935 rv2p_code++;
3936 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
3937 rv2p_code++;
3938
3939 if (rv2p_proc == RV2P_PROC1) {
3940 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
3941 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
3942 }
3943 else {
3944 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
3945 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
3946 }
3947 }
3948
3949 /* Reset the processor, un-stall is done later. */
3950 if (rv2p_proc == RV2P_PROC1) {
3951 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
3952 }
3953 else {
3954 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
3955 }
3956
3957 DBEXIT(BCE_VERBOSE_RESET);
3958 }
3959
3960 /****************************************************************************/
3961 /* Load RISC processor firmware. */
3962 /* */
3963 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
3964 /* associated with a particular processor. */
3965 /* */
3966 /* Returns: */
3967 /* Nothing. */
3968 /****************************************************************************/
3969 static void
bce_load_cpu_fw(struct bce_softc * sc,struct cpu_reg * cpu_reg,struct fw_info * fw)3970 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3971 struct fw_info *fw)
3972 {
3973 u32 offset;
3974
3975 DBENTER(BCE_VERBOSE_RESET);
3976
3977 bce_halt_cpu(sc, cpu_reg);
3978
3979 /* Load the Text area. */
3980 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3981 if (fw->text) {
3982 int j;
3983
3984 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3985 REG_WR_IND(sc, offset, fw->text[j]);
3986 }
3987 }
3988
3989 /* Load the Data area. */
3990 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3991 if (fw->data) {
3992 int j;
3993
3994 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3995 REG_WR_IND(sc, offset, fw->data[j]);
3996 }
3997 }
3998
3999 /* Load the SBSS area. */
4000 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4001 if (fw->sbss) {
4002 int j;
4003
4004 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4005 REG_WR_IND(sc, offset, fw->sbss[j]);
4006 }
4007 }
4008
4009 /* Load the BSS area. */
4010 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4011 if (fw->bss) {
4012 int j;
4013
4014 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4015 REG_WR_IND(sc, offset, fw->bss[j]);
4016 }
4017 }
4018
4019 /* Load the Read-Only area. */
4020 offset = cpu_reg->spad_base +
4021 (fw->rodata_addr - cpu_reg->mips_view_base);
4022 if (fw->rodata) {
4023 int j;
4024
4025 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4026 REG_WR_IND(sc, offset, fw->rodata[j]);
4027 }
4028 }
4029
4030 /* Clear the pre-fetch instruction and set the FW start address. */
4031 REG_WR_IND(sc, cpu_reg->inst, 0);
4032 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4033
4034 DBEXIT(BCE_VERBOSE_RESET);
4035 }
4036
4037 /****************************************************************************/
4038 /* Starts the RISC processor. */
4039 /* */
4040 /* Assumes the CPU starting address has already been set. */
4041 /* */
4042 /* Returns: */
4043 /* Nothing. */
4044 /****************************************************************************/
4045 static void
bce_start_cpu(struct bce_softc * sc,struct cpu_reg * cpu_reg)4046 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4047 {
4048 u32 val;
4049
4050 DBENTER(BCE_VERBOSE_RESET);
4051
4052 /* Start the CPU. */
4053 val = REG_RD_IND(sc, cpu_reg->mode);
4054 val &= ~cpu_reg->mode_value_halt;
4055 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4056 REG_WR_IND(sc, cpu_reg->mode, val);
4057
4058 DBEXIT(BCE_VERBOSE_RESET);
4059 }
4060
4061 /****************************************************************************/
4062 /* Halts the RISC processor. */
4063 /* */
4064 /* Returns: */
4065 /* Nothing. */
4066 /****************************************************************************/
4067 static void
bce_halt_cpu(struct bce_softc * sc,struct cpu_reg * cpu_reg)4068 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4069 {
4070 u32 val;
4071
4072 DBENTER(BCE_VERBOSE_RESET);
4073
4074 /* Halt the CPU. */
4075 val = REG_RD_IND(sc, cpu_reg->mode);
4076 val |= cpu_reg->mode_value_halt;
4077 REG_WR_IND(sc, cpu_reg->mode, val);
4078 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4079
4080 DBEXIT(BCE_VERBOSE_RESET);
4081 }
4082
4083 /****************************************************************************/
4084 /* Initialize the RX CPU. */
4085 /* */
4086 /* Returns: */
4087 /* Nothing. */
4088 /****************************************************************************/
4089 static void
bce_start_rxp_cpu(struct bce_softc * sc)4090 bce_start_rxp_cpu(struct bce_softc *sc)
4091 {
4092 struct cpu_reg cpu_reg;
4093
4094 DBENTER(BCE_VERBOSE_RESET);
4095
4096 cpu_reg.mode = BCE_RXP_CPU_MODE;
4097 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4098 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4099 cpu_reg.state = BCE_RXP_CPU_STATE;
4100 cpu_reg.state_value_clear = 0xffffff;
4101 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4102 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4103 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4104 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4105 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4106 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4107 cpu_reg.mips_view_base = 0x8000000;
4108
4109 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4110 bce_start_cpu(sc, &cpu_reg);
4111
4112 DBEXIT(BCE_VERBOSE_RESET);
4113 }
4114
4115 /****************************************************************************/
4116 /* Initialize the RX CPU. */
4117 /* */
4118 /* Returns: */
4119 /* Nothing. */
4120 /****************************************************************************/
4121 static void
bce_init_rxp_cpu(struct bce_softc * sc)4122 bce_init_rxp_cpu(struct bce_softc *sc)
4123 {
4124 struct cpu_reg cpu_reg;
4125 struct fw_info fw;
4126
4127 DBENTER(BCE_VERBOSE_RESET);
4128
4129 cpu_reg.mode = BCE_RXP_CPU_MODE;
4130 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4131 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4132 cpu_reg.state = BCE_RXP_CPU_STATE;
4133 cpu_reg.state_value_clear = 0xffffff;
4134 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4135 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4136 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4137 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4138 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4139 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4140 cpu_reg.mips_view_base = 0x8000000;
4141
4142 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4143 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4144 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4145 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4146 fw.start_addr = bce_RXP_b09FwStartAddr;
4147
4148 fw.text_addr = bce_RXP_b09FwTextAddr;
4149 fw.text_len = bce_RXP_b09FwTextLen;
4150 fw.text_index = 0;
4151 fw.text = bce_RXP_b09FwText;
4152
4153 fw.data_addr = bce_RXP_b09FwDataAddr;
4154 fw.data_len = bce_RXP_b09FwDataLen;
4155 fw.data_index = 0;
4156 fw.data = bce_RXP_b09FwData;
4157
4158 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4159 fw.sbss_len = bce_RXP_b09FwSbssLen;
4160 fw.sbss_index = 0;
4161 fw.sbss = bce_RXP_b09FwSbss;
4162
4163 fw.bss_addr = bce_RXP_b09FwBssAddr;
4164 fw.bss_len = bce_RXP_b09FwBssLen;
4165 fw.bss_index = 0;
4166 fw.bss = bce_RXP_b09FwBss;
4167
4168 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4169 fw.rodata_len = bce_RXP_b09FwRodataLen;
4170 fw.rodata_index = 0;
4171 fw.rodata = bce_RXP_b09FwRodata;
4172 } else {
4173 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4174 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4175 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4176 fw.start_addr = bce_RXP_b06FwStartAddr;
4177
4178 fw.text_addr = bce_RXP_b06FwTextAddr;
4179 fw.text_len = bce_RXP_b06FwTextLen;
4180 fw.text_index = 0;
4181 fw.text = bce_RXP_b06FwText;
4182
4183 fw.data_addr = bce_RXP_b06FwDataAddr;
4184 fw.data_len = bce_RXP_b06FwDataLen;
4185 fw.data_index = 0;
4186 fw.data = bce_RXP_b06FwData;
4187
4188 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4189 fw.sbss_len = bce_RXP_b06FwSbssLen;
4190 fw.sbss_index = 0;
4191 fw.sbss = bce_RXP_b06FwSbss;
4192
4193 fw.bss_addr = bce_RXP_b06FwBssAddr;
4194 fw.bss_len = bce_RXP_b06FwBssLen;
4195 fw.bss_index = 0;
4196 fw.bss = bce_RXP_b06FwBss;
4197
4198 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4199 fw.rodata_len = bce_RXP_b06FwRodataLen;
4200 fw.rodata_index = 0;
4201 fw.rodata = bce_RXP_b06FwRodata;
4202 }
4203
4204 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4205 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4206
4207 /* Delay RXP start until initialization is complete. */
4208
4209 DBEXIT(BCE_VERBOSE_RESET);
4210 }
4211
4212 /****************************************************************************/
4213 /* Initialize the TX CPU. */
4214 /* */
4215 /* Returns: */
4216 /* Nothing. */
4217 /****************************************************************************/
4218 static void
bce_init_txp_cpu(struct bce_softc * sc)4219 bce_init_txp_cpu(struct bce_softc *sc)
4220 {
4221 struct cpu_reg cpu_reg;
4222 struct fw_info fw;
4223
4224 DBENTER(BCE_VERBOSE_RESET);
4225
4226 cpu_reg.mode = BCE_TXP_CPU_MODE;
4227 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4228 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4229 cpu_reg.state = BCE_TXP_CPU_STATE;
4230 cpu_reg.state_value_clear = 0xffffff;
4231 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4232 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4233 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4234 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4235 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4236 cpu_reg.spad_base = BCE_TXP_SCRATCH;
4237 cpu_reg.mips_view_base = 0x8000000;
4238
4239 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4240 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4241 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4242 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4243 fw.start_addr = bce_TXP_b09FwStartAddr;
4244
4245 fw.text_addr = bce_TXP_b09FwTextAddr;
4246 fw.text_len = bce_TXP_b09FwTextLen;
4247 fw.text_index = 0;
4248 fw.text = bce_TXP_b09FwText;
4249
4250 fw.data_addr = bce_TXP_b09FwDataAddr;
4251 fw.data_len = bce_TXP_b09FwDataLen;
4252 fw.data_index = 0;
4253 fw.data = bce_TXP_b09FwData;
4254
4255 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4256 fw.sbss_len = bce_TXP_b09FwSbssLen;
4257 fw.sbss_index = 0;
4258 fw.sbss = bce_TXP_b09FwSbss;
4259
4260 fw.bss_addr = bce_TXP_b09FwBssAddr;
4261 fw.bss_len = bce_TXP_b09FwBssLen;
4262 fw.bss_index = 0;
4263 fw.bss = bce_TXP_b09FwBss;
4264
4265 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4266 fw.rodata_len = bce_TXP_b09FwRodataLen;
4267 fw.rodata_index = 0;
4268 fw.rodata = bce_TXP_b09FwRodata;
4269 } else {
4270 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4271 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4272 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4273 fw.start_addr = bce_TXP_b06FwStartAddr;
4274
4275 fw.text_addr = bce_TXP_b06FwTextAddr;
4276 fw.text_len = bce_TXP_b06FwTextLen;
4277 fw.text_index = 0;
4278 fw.text = bce_TXP_b06FwText;
4279
4280 fw.data_addr = bce_TXP_b06FwDataAddr;
4281 fw.data_len = bce_TXP_b06FwDataLen;
4282 fw.data_index = 0;
4283 fw.data = bce_TXP_b06FwData;
4284
4285 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4286 fw.sbss_len = bce_TXP_b06FwSbssLen;
4287 fw.sbss_index = 0;
4288 fw.sbss = bce_TXP_b06FwSbss;
4289
4290 fw.bss_addr = bce_TXP_b06FwBssAddr;
4291 fw.bss_len = bce_TXP_b06FwBssLen;
4292 fw.bss_index = 0;
4293 fw.bss = bce_TXP_b06FwBss;
4294
4295 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4296 fw.rodata_len = bce_TXP_b06FwRodataLen;
4297 fw.rodata_index = 0;
4298 fw.rodata = bce_TXP_b06FwRodata;
4299 }
4300
4301 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4302 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4303 bce_start_cpu(sc, &cpu_reg);
4304
4305 DBEXIT(BCE_VERBOSE_RESET);
4306 }
4307
4308 /****************************************************************************/
4309 /* Initialize the TPAT CPU. */
4310 /* */
4311 /* Returns: */
4312 /* Nothing. */
4313 /****************************************************************************/
4314 static void
bce_init_tpat_cpu(struct bce_softc * sc)4315 bce_init_tpat_cpu(struct bce_softc *sc)
4316 {
4317 struct cpu_reg cpu_reg;
4318 struct fw_info fw;
4319
4320 DBENTER(BCE_VERBOSE_RESET);
4321
4322 cpu_reg.mode = BCE_TPAT_CPU_MODE;
4323 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4324 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4325 cpu_reg.state = BCE_TPAT_CPU_STATE;
4326 cpu_reg.state_value_clear = 0xffffff;
4327 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4328 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4329 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4330 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4331 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4332 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4333 cpu_reg.mips_view_base = 0x8000000;
4334
4335 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4336 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4337 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4338 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4339 fw.start_addr = bce_TPAT_b09FwStartAddr;
4340
4341 fw.text_addr = bce_TPAT_b09FwTextAddr;
4342 fw.text_len = bce_TPAT_b09FwTextLen;
4343 fw.text_index = 0;
4344 fw.text = bce_TPAT_b09FwText;
4345
4346 fw.data_addr = bce_TPAT_b09FwDataAddr;
4347 fw.data_len = bce_TPAT_b09FwDataLen;
4348 fw.data_index = 0;
4349 fw.data = bce_TPAT_b09FwData;
4350
4351 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4352 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4353 fw.sbss_index = 0;
4354 fw.sbss = bce_TPAT_b09FwSbss;
4355
4356 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4357 fw.bss_len = bce_TPAT_b09FwBssLen;
4358 fw.bss_index = 0;
4359 fw.bss = bce_TPAT_b09FwBss;
4360
4361 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4362 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4363 fw.rodata_index = 0;
4364 fw.rodata = bce_TPAT_b09FwRodata;
4365 } else {
4366 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4367 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4368 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4369 fw.start_addr = bce_TPAT_b06FwStartAddr;
4370
4371 fw.text_addr = bce_TPAT_b06FwTextAddr;
4372 fw.text_len = bce_TPAT_b06FwTextLen;
4373 fw.text_index = 0;
4374 fw.text = bce_TPAT_b06FwText;
4375
4376 fw.data_addr = bce_TPAT_b06FwDataAddr;
4377 fw.data_len = bce_TPAT_b06FwDataLen;
4378 fw.data_index = 0;
4379 fw.data = bce_TPAT_b06FwData;
4380
4381 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4382 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4383 fw.sbss_index = 0;
4384 fw.sbss = bce_TPAT_b06FwSbss;
4385
4386 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4387 fw.bss_len = bce_TPAT_b06FwBssLen;
4388 fw.bss_index = 0;
4389 fw.bss = bce_TPAT_b06FwBss;
4390
4391 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4392 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4393 fw.rodata_index = 0;
4394 fw.rodata = bce_TPAT_b06FwRodata;
4395 }
4396
4397 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4398 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4399 bce_start_cpu(sc, &cpu_reg);
4400
4401 DBEXIT(BCE_VERBOSE_RESET);
4402 }
4403
4404 /****************************************************************************/
4405 /* Initialize the CP CPU. */
4406 /* */
4407 /* Returns: */
4408 /* Nothing. */
4409 /****************************************************************************/
4410 static void
bce_init_cp_cpu(struct bce_softc * sc)4411 bce_init_cp_cpu(struct bce_softc *sc)
4412 {
4413 struct cpu_reg cpu_reg;
4414 struct fw_info fw;
4415
4416 DBENTER(BCE_VERBOSE_RESET);
4417
4418 cpu_reg.mode = BCE_CP_CPU_MODE;
4419 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4420 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4421 cpu_reg.state = BCE_CP_CPU_STATE;
4422 cpu_reg.state_value_clear = 0xffffff;
4423 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4424 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4425 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4426 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4427 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4428 cpu_reg.spad_base = BCE_CP_SCRATCH;
4429 cpu_reg.mips_view_base = 0x8000000;
4430
4431 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4432 fw.ver_major = bce_CP_b09FwReleaseMajor;
4433 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4434 fw.ver_fix = bce_CP_b09FwReleaseFix;
4435 fw.start_addr = bce_CP_b09FwStartAddr;
4436
4437 fw.text_addr = bce_CP_b09FwTextAddr;
4438 fw.text_len = bce_CP_b09FwTextLen;
4439 fw.text_index = 0;
4440 fw.text = bce_CP_b09FwText;
4441
4442 fw.data_addr = bce_CP_b09FwDataAddr;
4443 fw.data_len = bce_CP_b09FwDataLen;
4444 fw.data_index = 0;
4445 fw.data = bce_CP_b09FwData;
4446
4447 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4448 fw.sbss_len = bce_CP_b09FwSbssLen;
4449 fw.sbss_index = 0;
4450 fw.sbss = bce_CP_b09FwSbss;
4451
4452 fw.bss_addr = bce_CP_b09FwBssAddr;
4453 fw.bss_len = bce_CP_b09FwBssLen;
4454 fw.bss_index = 0;
4455 fw.bss = bce_CP_b09FwBss;
4456
4457 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4458 fw.rodata_len = bce_CP_b09FwRodataLen;
4459 fw.rodata_index = 0;
4460 fw.rodata = bce_CP_b09FwRodata;
4461 } else {
4462 fw.ver_major = bce_CP_b06FwReleaseMajor;
4463 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4464 fw.ver_fix = bce_CP_b06FwReleaseFix;
4465 fw.start_addr = bce_CP_b06FwStartAddr;
4466
4467 fw.text_addr = bce_CP_b06FwTextAddr;
4468 fw.text_len = bce_CP_b06FwTextLen;
4469 fw.text_index = 0;
4470 fw.text = bce_CP_b06FwText;
4471
4472 fw.data_addr = bce_CP_b06FwDataAddr;
4473 fw.data_len = bce_CP_b06FwDataLen;
4474 fw.data_index = 0;
4475 fw.data = bce_CP_b06FwData;
4476
4477 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4478 fw.sbss_len = bce_CP_b06FwSbssLen;
4479 fw.sbss_index = 0;
4480 fw.sbss = bce_CP_b06FwSbss;
4481
4482 fw.bss_addr = bce_CP_b06FwBssAddr;
4483 fw.bss_len = bce_CP_b06FwBssLen;
4484 fw.bss_index = 0;
4485 fw.bss = bce_CP_b06FwBss;
4486
4487 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4488 fw.rodata_len = bce_CP_b06FwRodataLen;
4489 fw.rodata_index = 0;
4490 fw.rodata = bce_CP_b06FwRodata;
4491 }
4492
4493 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4494 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4495 bce_start_cpu(sc, &cpu_reg);
4496
4497 DBEXIT(BCE_VERBOSE_RESET);
4498 }
4499
4500 /****************************************************************************/
4501 /* Initialize the COM CPU. */
4502 /* */
4503 /* Returns: */
4504 /* Nothing. */
4505 /****************************************************************************/
4506 static void
bce_init_com_cpu(struct bce_softc * sc)4507 bce_init_com_cpu(struct bce_softc *sc)
4508 {
4509 struct cpu_reg cpu_reg;
4510 struct fw_info fw;
4511
4512 DBENTER(BCE_VERBOSE_RESET);
4513
4514 cpu_reg.mode = BCE_COM_CPU_MODE;
4515 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4516 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4517 cpu_reg.state = BCE_COM_CPU_STATE;
4518 cpu_reg.state_value_clear = 0xffffff;
4519 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4520 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4521 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4522 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4523 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4524 cpu_reg.spad_base = BCE_COM_SCRATCH;
4525 cpu_reg.mips_view_base = 0x8000000;
4526
4527 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4528 fw.ver_major = bce_COM_b09FwReleaseMajor;
4529 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4530 fw.ver_fix = bce_COM_b09FwReleaseFix;
4531 fw.start_addr = bce_COM_b09FwStartAddr;
4532
4533 fw.text_addr = bce_COM_b09FwTextAddr;
4534 fw.text_len = bce_COM_b09FwTextLen;
4535 fw.text_index = 0;
4536 fw.text = bce_COM_b09FwText;
4537
4538 fw.data_addr = bce_COM_b09FwDataAddr;
4539 fw.data_len = bce_COM_b09FwDataLen;
4540 fw.data_index = 0;
4541 fw.data = bce_COM_b09FwData;
4542
4543 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4544 fw.sbss_len = bce_COM_b09FwSbssLen;
4545 fw.sbss_index = 0;
4546 fw.sbss = bce_COM_b09FwSbss;
4547
4548 fw.bss_addr = bce_COM_b09FwBssAddr;
4549 fw.bss_len = bce_COM_b09FwBssLen;
4550 fw.bss_index = 0;
4551 fw.bss = bce_COM_b09FwBss;
4552
4553 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4554 fw.rodata_len = bce_COM_b09FwRodataLen;
4555 fw.rodata_index = 0;
4556 fw.rodata = bce_COM_b09FwRodata;
4557 } else {
4558 fw.ver_major = bce_COM_b06FwReleaseMajor;
4559 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4560 fw.ver_fix = bce_COM_b06FwReleaseFix;
4561 fw.start_addr = bce_COM_b06FwStartAddr;
4562
4563 fw.text_addr = bce_COM_b06FwTextAddr;
4564 fw.text_len = bce_COM_b06FwTextLen;
4565 fw.text_index = 0;
4566 fw.text = bce_COM_b06FwText;
4567
4568 fw.data_addr = bce_COM_b06FwDataAddr;
4569 fw.data_len = bce_COM_b06FwDataLen;
4570 fw.data_index = 0;
4571 fw.data = bce_COM_b06FwData;
4572
4573 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4574 fw.sbss_len = bce_COM_b06FwSbssLen;
4575 fw.sbss_index = 0;
4576 fw.sbss = bce_COM_b06FwSbss;
4577
4578 fw.bss_addr = bce_COM_b06FwBssAddr;
4579 fw.bss_len = bce_COM_b06FwBssLen;
4580 fw.bss_index = 0;
4581 fw.bss = bce_COM_b06FwBss;
4582
4583 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4584 fw.rodata_len = bce_COM_b06FwRodataLen;
4585 fw.rodata_index = 0;
4586 fw.rodata = bce_COM_b06FwRodata;
4587 }
4588
4589 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4590 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4591 bce_start_cpu(sc, &cpu_reg);
4592
4593 DBEXIT(BCE_VERBOSE_RESET);
4594 }
4595
4596 /****************************************************************************/
4597 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
4598 /* */
4599 /* Loads the firmware for each CPU and starts the CPU. */
4600 /* */
4601 /* Returns: */
4602 /* Nothing. */
4603 /****************************************************************************/
4604 static void
bce_init_cpus(struct bce_softc * sc)4605 bce_init_cpus(struct bce_softc *sc)
4606 {
4607 DBENTER(BCE_VERBOSE_RESET);
4608
4609 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4610 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4611 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4612 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4613 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4614 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4615 } else {
4616 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4617 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4618 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4619 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4620 }
4621
4622 } else {
4623 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4624 sizeof(bce_rv2p_proc1), RV2P_PROC1);
4625 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4626 sizeof(bce_rv2p_proc2), RV2P_PROC2);
4627 }
4628
4629 bce_init_rxp_cpu(sc);
4630 bce_init_txp_cpu(sc);
4631 bce_init_tpat_cpu(sc);
4632 bce_init_com_cpu(sc);
4633 bce_init_cp_cpu(sc);
4634
4635 DBEXIT(BCE_VERBOSE_RESET);
4636 }
4637
4638 /****************************************************************************/
4639 /* Initialize context memory. */
4640 /* */
4641 /* Clears the memory associated with each Context ID (CID). */
4642 /* */
4643 /* Returns: */
4644 /* Nothing. */
4645 /****************************************************************************/
4646 static int
bce_init_ctx(struct bce_softc * sc)4647 bce_init_ctx(struct bce_softc *sc)
4648 {
4649 u32 offset, val, vcid_addr;
4650 int i, j, rc, retry_cnt;
4651
4652 rc = 0;
4653 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4654
4655 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4656 retry_cnt = CTX_INIT_RETRY_COUNT;
4657
4658 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4659
4660 /*
4661 * BCM5709 context memory may be cached
4662 * in host memory so prepare the host memory
4663 * for access.
4664 */
4665 val = BCE_CTX_COMMAND_ENABLED |
4666 BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4667 val |= (BCM_PAGE_BITS - 8) << 16;
4668 REG_WR(sc, BCE_CTX_COMMAND, val);
4669
4670 /* Wait for mem init command to complete. */
4671 for (i = 0; i < retry_cnt; i++) {
4672 val = REG_RD(sc, BCE_CTX_COMMAND);
4673 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4674 break;
4675 DELAY(2);
4676 }
4677 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4678 BCE_PRINTF("%s(): Context memory initialization failed!\n",
4679 __FUNCTION__);
4680 rc = EBUSY;
4681 goto init_ctx_fail;
4682 }
4683
4684 for (i = 0; i < sc->ctx_pages; i++) {
4685 /* Set the physical address of the context memory. */
4686 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4687 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4688 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4689 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4690 BCE_ADDR_HI(sc->ctx_paddr[i]));
4691 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4692 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4693
4694 /* Verify the context memory write was successful. */
4695 for (j = 0; j < retry_cnt; j++) {
4696 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4697 if ((val &
4698 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4699 break;
4700 DELAY(5);
4701 }
4702 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4703 BCE_PRINTF("%s(): Failed to initialize "
4704 "context page %d!\n", __FUNCTION__, i);
4705 rc = EBUSY;
4706 goto init_ctx_fail;
4707 }
4708 }
4709 } else {
4710 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4711
4712 /*
4713 * For the 5706/5708, context memory is local to
4714 * the controller, so initialize the controller
4715 * context memory.
4716 */
4717
4718 vcid_addr = GET_CID_ADDR(96);
4719 while (vcid_addr) {
4720 vcid_addr -= PHY_CTX_SIZE;
4721
4722 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4723 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4724
4725 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4726 CTX_WR(sc, 0x00, offset, 0);
4727 }
4728
4729 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4730 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4731 }
4732 }
4733 init_ctx_fail:
4734 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4735 return (rc);
4736 }
4737
4738 /****************************************************************************/
4739 /* Fetch the permanent MAC address of the controller. */
4740 /* */
4741 /* Returns: */
4742 /* Nothing. */
4743 /****************************************************************************/
4744 static void
bce_get_mac_addr(struct bce_softc * sc)4745 bce_get_mac_addr(struct bce_softc *sc)
4746 {
4747 u32 mac_lo = 0, mac_hi = 0;
4748
4749 DBENTER(BCE_VERBOSE_RESET);
4750
4751 /*
4752 * The NetXtreme II bootcode populates various NIC
4753 * power-on and runtime configuration items in a
4754 * shared memory area. The factory configured MAC
4755 * address is available from both NVRAM and the
4756 * shared memory area so we'll read the value from
4757 * shared memory for speed.
4758 */
4759
4760 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4761 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4762
4763 if ((mac_lo == 0) && (mac_hi == 0)) {
4764 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4765 __FILE__, __LINE__);
4766 } else {
4767 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4768 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4769 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4770 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4771 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4772 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4773 }
4774
4775 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4776 "address = %6D\n", sc->eaddr, ":");
4777 DBEXIT(BCE_VERBOSE_RESET);
4778 }
4779
4780 /****************************************************************************/
4781 /* Program the MAC address. */
4782 /* */
4783 /* Returns: */
4784 /* Nothing. */
4785 /****************************************************************************/
4786 static void
bce_set_mac_addr(struct bce_softc * sc)4787 bce_set_mac_addr(struct bce_softc *sc)
4788 {
4789 u32 val;
4790 u8 *mac_addr = sc->eaddr;
4791
4792 /* ToDo: Add support for setting multiple MAC addresses. */
4793
4794 DBENTER(BCE_VERBOSE_RESET);
4795 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4796 "%6D\n", sc->eaddr, ":");
4797
4798 val = (mac_addr[0] << 8) | mac_addr[1];
4799
4800 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4801
4802 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4803 (mac_addr[4] << 8) | mac_addr[5];
4804
4805 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4806
4807 DBEXIT(BCE_VERBOSE_RESET);
4808 }
4809
4810 /****************************************************************************/
4811 /* Stop the controller. */
4812 /* */
4813 /* Returns: */
4814 /* Nothing. */
4815 /****************************************************************************/
4816 static void
bce_stop(struct bce_softc * sc)4817 bce_stop(struct bce_softc *sc)
4818 {
4819 if_t ifp;
4820
4821 DBENTER(BCE_VERBOSE_RESET);
4822
4823 BCE_LOCK_ASSERT(sc);
4824
4825 ifp = sc->bce_ifp;
4826
4827 callout_stop(&sc->bce_tick_callout);
4828
4829 /* Disable the transmit/receive blocks. */
4830 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4831 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4832 DELAY(20);
4833
4834 bce_disable_intr(sc);
4835
4836 /* Free RX buffers. */
4837 if (bce_hdr_split == TRUE) {
4838 bce_free_pg_chain(sc);
4839 }
4840 bce_free_rx_chain(sc);
4841
4842 /* Free TX buffers. */
4843 bce_free_tx_chain(sc);
4844
4845 sc->watchdog_timer = 0;
4846
4847 sc->bce_link_up = FALSE;
4848
4849 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4850
4851 DBEXIT(BCE_VERBOSE_RESET);
4852 }
4853
4854 static int
bce_reset(struct bce_softc * sc,u32 reset_code)4855 bce_reset(struct bce_softc *sc, u32 reset_code)
4856 {
4857 u32 emac_mode_save, val;
4858 int i, rc = 0;
4859 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4860 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4861
4862 DBENTER(BCE_VERBOSE_RESET);
4863
4864 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4865 __FUNCTION__, reset_code);
4866
4867 /*
4868 * If ASF/IPMI is operational, then the EMAC Mode register already
4869 * contains appropriate values for the link settings that have
4870 * been auto-negotiated. Resetting the chip will clobber those
4871 * values. Save the important bits so we can restore them after
4872 * the reset.
4873 */
4874 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
4875
4876 /* Wait for pending PCI transactions to complete. */
4877 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4878 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4879 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4880 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4881 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4882 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4883 DELAY(5);
4884
4885 /* Disable DMA */
4886 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4887 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4888 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4889 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4890 }
4891
4892 /* Assume bootcode is running. */
4893 sc->bce_fw_timed_out = FALSE;
4894 sc->bce_drv_cardiac_arrest = FALSE;
4895
4896 /* Give the firmware a chance to prepare for the reset. */
4897 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
4898 if (rc)
4899 goto bce_reset_exit;
4900
4901 /* Set a firmware reminder that this is a soft reset. */
4902 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
4903
4904 /* Dummy read to force the chip to complete all current transactions. */
4905 val = REG_RD(sc, BCE_MISC_ID);
4906
4907 /* Chip reset. */
4908 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4909 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
4910 REG_RD(sc, BCE_MISC_COMMAND);
4911 DELAY(5);
4912
4913 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4914 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4915
4916 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
4917 } else {
4918 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4919 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4920 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4921 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
4922
4923 /* Allow up to 30us for reset to complete. */
4924 for (i = 0; i < 10; i++) {
4925 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
4926 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4927 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
4928 break;
4929 }
4930 DELAY(10);
4931 }
4932
4933 /* Check that reset completed successfully. */
4934 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4935 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4936 BCE_PRINTF("%s(%d): Reset failed!\n",
4937 __FILE__, __LINE__);
4938 rc = EBUSY;
4939 goto bce_reset_exit;
4940 }
4941 }
4942
4943 /* Make sure byte swapping is properly configured. */
4944 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
4945 if (val != 0x01020304) {
4946 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
4947 __FILE__, __LINE__);
4948 rc = ENODEV;
4949 goto bce_reset_exit;
4950 }
4951
4952 /* Just completed a reset, assume that firmware is running again. */
4953 sc->bce_fw_timed_out = FALSE;
4954 sc->bce_drv_cardiac_arrest = FALSE;
4955
4956 /* Wait for the firmware to finish its initialization. */
4957 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
4958 if (rc)
4959 BCE_PRINTF("%s(%d): Firmware did not complete "
4960 "initialization!\n", __FILE__, __LINE__);
4961 /* Get firmware capabilities. */
4962 bce_fw_cap_init(sc);
4963
4964 bce_reset_exit:
4965 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
4966 if (reset_code == BCE_DRV_MSG_CODE_RESET) {
4967 val = REG_RD(sc, BCE_EMAC_MODE);
4968 val = (val & ~emac_mode_mask) | emac_mode_save;
4969 REG_WR(sc, BCE_EMAC_MODE, val);
4970 }
4971
4972 DBEXIT(BCE_VERBOSE_RESET);
4973 return (rc);
4974 }
4975
4976 static int
bce_chipinit(struct bce_softc * sc)4977 bce_chipinit(struct bce_softc *sc)
4978 {
4979 u32 val;
4980 int rc = 0;
4981
4982 DBENTER(BCE_VERBOSE_RESET);
4983
4984 bce_disable_intr(sc);
4985
4986 /*
4987 * Initialize DMA byte/word swapping, configure the number of DMA
4988 * channels and PCI clock compensation delay.
4989 */
4990 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
4991 BCE_DMA_CONFIG_DATA_WORD_SWAP |
4992 #if BYTE_ORDER == BIG_ENDIAN
4993 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
4994 #endif
4995 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
4996 DMA_READ_CHANS << 12 |
4997 DMA_WRITE_CHANS << 16;
4998
4999 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5000
5001 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5002 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5003
5004 /*
5005 * This setting resolves a problem observed on certain Intel PCI
5006 * chipsets that cannot handle multiple outstanding DMA operations.
5007 * See errata E9_5706A1_65.
5008 */
5009 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5010 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5011 !(sc->bce_flags & BCE_PCIX_FLAG))
5012 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5013
5014 REG_WR(sc, BCE_DMA_CONFIG, val);
5015
5016 /* Enable the RX_V2P and Context state machines before access. */
5017 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5018 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5019 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5020 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5021
5022 /* Initialize context mapping and zero out the quick contexts. */
5023 if ((rc = bce_init_ctx(sc)) != 0)
5024 goto bce_chipinit_exit;
5025
5026 /* Initialize the on-boards CPUs */
5027 bce_init_cpus(sc);
5028
5029 /* Enable management frames (NC-SI) to flow to the MCP. */
5030 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5031 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5032 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5033 }
5034
5035 /* Prepare NVRAM for access. */
5036 if ((rc = bce_init_nvram(sc)) != 0)
5037 goto bce_chipinit_exit;
5038
5039 /* Set the kernel bypass block size */
5040 val = REG_RD(sc, BCE_MQ_CONFIG);
5041 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5042 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5043
5044 /* Enable bins used on the 5709. */
5045 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5046 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5047 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5048 val |= BCE_MQ_CONFIG_HALT_DIS;
5049 }
5050
5051 REG_WR(sc, BCE_MQ_CONFIG, val);
5052
5053 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5054 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5055 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5056
5057 /* Set the page size and clear the RV2P processor stall bits. */
5058 val = (BCM_PAGE_BITS - 8) << 24;
5059 REG_WR(sc, BCE_RV2P_CONFIG, val);
5060
5061 /* Configure page size. */
5062 val = REG_RD(sc, BCE_TBDR_CONFIG);
5063 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5064 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5065 REG_WR(sc, BCE_TBDR_CONFIG, val);
5066
5067 /* Set the perfect match control register to default. */
5068 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5069
5070 bce_chipinit_exit:
5071 DBEXIT(BCE_VERBOSE_RESET);
5072
5073 return(rc);
5074 }
5075
5076 /****************************************************************************/
5077 /* Initialize the controller in preparation to send/receive traffic. */
5078 /* */
5079 /* Returns: */
5080 /* 0 for success, positive value for failure. */
5081 /****************************************************************************/
5082 static int
bce_blockinit(struct bce_softc * sc)5083 bce_blockinit(struct bce_softc *sc)
5084 {
5085 u32 reg, val;
5086 int rc = 0;
5087
5088 DBENTER(BCE_VERBOSE_RESET);
5089
5090 /* Load the hardware default MAC address. */
5091 bce_set_mac_addr(sc);
5092
5093 /* Set the Ethernet backoff seed value */
5094 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
5095 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) +
5096 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
5097 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5098
5099 sc->last_status_idx = 0;
5100 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5101
5102 /* Set up link change interrupt generation. */
5103 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5104
5105 /* Program the physical address of the status block. */
5106 REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5107 BCE_ADDR_LO(sc->status_block_paddr));
5108 REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5109 BCE_ADDR_HI(sc->status_block_paddr));
5110
5111 /* Program the physical address of the statistics block. */
5112 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5113 BCE_ADDR_LO(sc->stats_block_paddr));
5114 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5115 BCE_ADDR_HI(sc->stats_block_paddr));
5116
5117 /*
5118 * Program various host coalescing parameters.
5119 * Trip points control how many BDs should be ready before generating
5120 * an interrupt while ticks control how long a BD can sit in the chain
5121 * before generating an interrupt.
5122 */
5123 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5124 (sc->bce_tx_quick_cons_trip_int << 16) |
5125 sc->bce_tx_quick_cons_trip);
5126 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5127 (sc->bce_rx_quick_cons_trip_int << 16) |
5128 sc->bce_rx_quick_cons_trip);
5129 REG_WR(sc, BCE_HC_TX_TICKS,
5130 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5131 REG_WR(sc, BCE_HC_RX_TICKS,
5132 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5133 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5134 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5135 /* Not used for L2. */
5136 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5137 REG_WR(sc, BCE_HC_COM_TICKS, 0);
5138 REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5139
5140 /* Configure the Host Coalescing block. */
5141 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5142 BCE_HC_CONFIG_COLLECT_STATS;
5143
5144 #if 0
5145 /* ToDo: Add MSI-X support. */
5146 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5147 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5148 BCE_HC_SB_CONFIG_1;
5149
5150 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5151
5152 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5153 BCE_HC_SB_CONFIG_1_ONE_SHOT);
5154
5155 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5156 (sc->tx_quick_cons_trip_int << 16) |
5157 sc->tx_quick_cons_trip);
5158
5159 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5160 (sc->tx_ticks_int << 16) | sc->tx_ticks);
5161
5162 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5163 }
5164
5165 /*
5166 * Tell the HC block to automatically set the
5167 * INT_MASK bit after an MSI/MSI-X interrupt
5168 * is generated so the driver doesn't have to.
5169 */
5170 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5171 val |= BCE_HC_CONFIG_ONE_SHOT;
5172
5173 /* Set the MSI-X status blocks to 128 byte boundaries. */
5174 if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5175 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5176 #endif
5177
5178 REG_WR(sc, BCE_HC_CONFIG, val);
5179
5180 /* Clear the internal statistics counters. */
5181 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5182
5183 /* Verify that bootcode is running. */
5184 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5185
5186 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5187 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5188 __FILE__, __LINE__);
5189 reg = 0);
5190
5191 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5192 BCE_DEV_INFO_SIGNATURE_MAGIC) {
5193 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5194 "Expected: 08%08X\n", __FILE__, __LINE__,
5195 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5196 BCE_DEV_INFO_SIGNATURE_MAGIC);
5197 rc = ENODEV;
5198 goto bce_blockinit_exit;
5199 }
5200
5201 /* Enable DMA */
5202 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5203 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5204 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5205 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5206 }
5207
5208 /* Allow bootcode to apply additional fixes before enabling MAC. */
5209 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5210 BCE_DRV_MSG_CODE_RESET);
5211
5212 /* Enable link state change interrupt generation. */
5213 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5214
5215 /* Enable the RXP. */
5216 bce_start_rxp_cpu(sc);
5217
5218 /* Disable management frames (NC-SI) from flowing to the MCP. */
5219 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5220 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5221 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5222 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5223 }
5224
5225 /* Enable all remaining blocks in the MAC. */
5226 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5227 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5228 BCE_MISC_ENABLE_DEFAULT_XI);
5229 else
5230 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5231 BCE_MISC_ENABLE_DEFAULT);
5232
5233 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5234 DELAY(20);
5235
5236 /* Save the current host coalescing block settings. */
5237 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5238
5239 bce_blockinit_exit:
5240 DBEXIT(BCE_VERBOSE_RESET);
5241
5242 return (rc);
5243 }
5244
5245 /****************************************************************************/
5246 /* Encapsulate an mbuf into the rx_bd chain. */
5247 /* */
5248 /* Returns: */
5249 /* 0 for success, positive value for failure. */
5250 /****************************************************************************/
5251 static int
bce_get_rx_buf(struct bce_softc * sc,u16 prod,u16 chain_prod,u32 * prod_bseq)5252 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5253 {
5254 bus_dma_segment_t segs[1];
5255 struct mbuf *m_new = NULL;
5256 struct rx_bd *rxbd;
5257 int nsegs, error, rc = 0;
5258 #ifdef BCE_DEBUG
5259 u16 debug_chain_prod = chain_prod;
5260 #endif
5261
5262 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5263
5264 /* Make sure the inputs are valid. */
5265 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5266 BCE_PRINTF("%s(%d): RX producer out of range: "
5267 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5268 chain_prod, (u16)MAX_RX_BD_ALLOC));
5269
5270 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5271 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5272 prod, chain_prod, *prod_bseq);
5273
5274 /* Update some debug statistic counters */
5275 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5276 sc->rx_low_watermark = sc->free_rx_bd);
5277 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5278 sc->rx_empty_count++);
5279
5280 /* Simulate an mbuf allocation failure. */
5281 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5282 sc->mbuf_alloc_failed_count++;
5283 sc->mbuf_alloc_failed_sim_count++;
5284 rc = ENOBUFS;
5285 goto bce_get_rx_buf_exit);
5286
5287 /* This is a new mbuf allocation. */
5288 if (bce_hdr_split == TRUE)
5289 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5290 else
5291 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5292 sc->rx_bd_mbuf_alloc_size);
5293
5294 if (m_new == NULL) {
5295 sc->mbuf_alloc_failed_count++;
5296 rc = ENOBUFS;
5297 goto bce_get_rx_buf_exit;
5298 }
5299
5300 DBRUN(sc->debug_rx_mbuf_alloc++);
5301
5302 /* Make sure we have a valid packet header. */
5303 M_ASSERTPKTHDR(m_new);
5304
5305 /* Initialize the mbuf size and pad if necessary for alignment. */
5306 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5307 m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5308
5309 /* ToDo: Consider calling m_fragment() to test error handling. */
5310
5311 /* Map the mbuf cluster into device memory. */
5312 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5313 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5314
5315 /* Handle any mapping errors. */
5316 if (error) {
5317 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5318 "chain (%d)!\n", __FILE__, __LINE__, error);
5319
5320 sc->dma_map_addr_rx_failed_count++;
5321 m_freem(m_new);
5322
5323 DBRUN(sc->debug_rx_mbuf_alloc--);
5324
5325 rc = ENOBUFS;
5326 goto bce_get_rx_buf_exit;
5327 }
5328
5329 /* All mbufs must map to a single segment. */
5330 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5331 __FUNCTION__, nsegs));
5332
5333 /* Setup the rx_bd for the segment. */
5334 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5335
5336 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5337 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5338 rxbd->rx_bd_len = htole32(segs[0].ds_len);
5339 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5340 *prod_bseq += segs[0].ds_len;
5341
5342 /* Save the mbuf and update our counter. */
5343 sc->rx_mbuf_ptr[chain_prod] = m_new;
5344 sc->free_rx_bd -= nsegs;
5345
5346 DBRUNMSG(BCE_INSANE_RECV,
5347 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5348
5349 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5350 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5351 chain_prod, *prod_bseq);
5352
5353 bce_get_rx_buf_exit:
5354 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5355
5356 return(rc);
5357 }
5358
5359 /****************************************************************************/
5360 /* Encapsulate an mbuf cluster into the page chain. */
5361 /* */
5362 /* Returns: */
5363 /* 0 for success, positive value for failure. */
5364 /****************************************************************************/
5365 static int
bce_get_pg_buf(struct bce_softc * sc,u16 prod,u16 prod_idx)5366 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5367 {
5368 bus_dma_segment_t segs[1];
5369 struct mbuf *m_new = NULL;
5370 struct rx_bd *pgbd;
5371 int error, nsegs, rc = 0;
5372 #ifdef BCE_DEBUG
5373 u16 debug_prod_idx = prod_idx;
5374 #endif
5375
5376 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5377
5378 /* Make sure the inputs are valid. */
5379 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5380 BCE_PRINTF("%s(%d): page producer out of range: "
5381 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5382 prod_idx, (u16)MAX_PG_BD_ALLOC));
5383
5384 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5385 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5386
5387 /* Update counters if we've hit a new low or run out of pages. */
5388 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5389 sc->pg_low_watermark = sc->free_pg_bd);
5390 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5391
5392 /* Simulate an mbuf allocation failure. */
5393 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5394 sc->mbuf_alloc_failed_count++;
5395 sc->mbuf_alloc_failed_sim_count++;
5396 rc = ENOBUFS;
5397 goto bce_get_pg_buf_exit);
5398
5399 /* This is a new mbuf allocation. */
5400 m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5401 if (m_new == NULL) {
5402 sc->mbuf_alloc_failed_count++;
5403 rc = ENOBUFS;
5404 goto bce_get_pg_buf_exit;
5405 }
5406
5407 DBRUN(sc->debug_pg_mbuf_alloc++);
5408
5409 m_new->m_len = MCLBYTES;
5410
5411 /* ToDo: Consider calling m_fragment() to test error handling. */
5412
5413 /* Map the mbuf cluster into device memory. */
5414 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5415 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5416
5417 /* Handle any mapping errors. */
5418 if (error) {
5419 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5420 __FILE__, __LINE__);
5421
5422 m_freem(m_new);
5423 DBRUN(sc->debug_pg_mbuf_alloc--);
5424
5425 rc = ENOBUFS;
5426 goto bce_get_pg_buf_exit;
5427 }
5428
5429 /* All mbufs must map to a single segment. */
5430 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5431 __FUNCTION__, nsegs));
5432
5433 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5434
5435 /*
5436 * The page chain uses the same rx_bd data structure
5437 * as the receive chain but doesn't require a byte sequence (bseq).
5438 */
5439 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5440
5441 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5442 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5443 pgbd->rx_bd_len = htole32(MCLBYTES);
5444 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5445
5446 /* Save the mbuf and update our counter. */
5447 sc->pg_mbuf_ptr[prod_idx] = m_new;
5448 sc->free_pg_bd--;
5449
5450 DBRUNMSG(BCE_INSANE_RECV,
5451 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5452
5453 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5454 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5455
5456 bce_get_pg_buf_exit:
5457 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5458
5459 return(rc);
5460 }
5461
5462 /****************************************************************************/
5463 /* Initialize the TX context memory. */
5464 /* */
5465 /* Returns: */
5466 /* Nothing */
5467 /****************************************************************************/
5468 static void
bce_init_tx_context(struct bce_softc * sc)5469 bce_init_tx_context(struct bce_softc *sc)
5470 {
5471 u32 val;
5472
5473 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5474
5475 /* Initialize the context ID for an L2 TX chain. */
5476 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5477 /* Set the CID type to support an L2 connection. */
5478 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5479 BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5480 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5481 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5482 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5483 BCE_L2CTX_TX_CMD_TYPE_XI, val);
5484
5485 /* Point the hardware to the first page in the chain. */
5486 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5487 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5488 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5489 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5490 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5491 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5492 } else {
5493 /* Set the CID type to support an L2 connection. */
5494 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5495 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5496 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5497 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5498
5499 /* Point the hardware to the first page in the chain. */
5500 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5501 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5502 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5503 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5504 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5505 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5506 }
5507
5508 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5509 }
5510
5511 /****************************************************************************/
5512 /* Allocate memory and initialize the TX data structures. */
5513 /* */
5514 /* Returns: */
5515 /* 0 for success, positive value for failure. */
5516 /****************************************************************************/
5517 static int
bce_init_tx_chain(struct bce_softc * sc)5518 bce_init_tx_chain(struct bce_softc *sc)
5519 {
5520 struct tx_bd *txbd;
5521 int i, rc = 0;
5522
5523 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5524
5525 /* Set the initial TX producer/consumer indices. */
5526 sc->tx_prod = 0;
5527 sc->tx_cons = 0;
5528 sc->tx_prod_bseq = 0;
5529 sc->used_tx_bd = 0;
5530 sc->max_tx_bd = USABLE_TX_BD_ALLOC;
5531 DBRUN(sc->tx_hi_watermark = 0);
5532 DBRUN(sc->tx_full_count = 0);
5533
5534 /*
5535 * The NetXtreme II supports a linked-list structure called
5536 * a Buffer Descriptor Chain (or BD chain). A BD chain
5537 * consists of a series of 1 or more chain pages, each of which
5538 * consists of a fixed number of BD entries.
5539 * The last BD entry on each page is a pointer to the next page
5540 * in the chain, and the last pointer in the BD chain
5541 * points back to the beginning of the chain.
5542 */
5543
5544 /* Set the TX next pointer chain entries. */
5545 for (i = 0; i < sc->tx_pages; i++) {
5546 int j;
5547
5548 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5549
5550 /* Check if we've reached the last page. */
5551 if (i == (sc->tx_pages - 1))
5552 j = 0;
5553 else
5554 j = i + 1;
5555
5556 txbd->tx_bd_haddr_hi =
5557 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5558 txbd->tx_bd_haddr_lo =
5559 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5560 }
5561
5562 bce_init_tx_context(sc);
5563
5564 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5565 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5566
5567 return(rc);
5568 }
5569
5570 /****************************************************************************/
5571 /* Free memory and clear the TX data structures. */
5572 /* */
5573 /* Returns: */
5574 /* Nothing. */
5575 /****************************************************************************/
5576 static void
bce_free_tx_chain(struct bce_softc * sc)5577 bce_free_tx_chain(struct bce_softc *sc)
5578 {
5579 int i;
5580
5581 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5582
5583 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5584 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5585 if (sc->tx_mbuf_ptr[i] != NULL) {
5586 if (sc->tx_mbuf_map[i] != NULL)
5587 bus_dmamap_sync(sc->tx_mbuf_tag,
5588 sc->tx_mbuf_map[i],
5589 BUS_DMASYNC_POSTWRITE);
5590 m_freem(sc->tx_mbuf_ptr[i]);
5591 sc->tx_mbuf_ptr[i] = NULL;
5592 DBRUN(sc->debug_tx_mbuf_alloc--);
5593 }
5594 }
5595
5596 /* Clear each TX chain page. */
5597 for (i = 0; i < sc->tx_pages; i++)
5598 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5599
5600 sc->used_tx_bd = 0;
5601
5602 /* Check if we lost any mbufs in the process. */
5603 DBRUNIF((sc->debug_tx_mbuf_alloc),
5604 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5605 "from tx chain!\n", __FILE__, __LINE__,
5606 sc->debug_tx_mbuf_alloc));
5607
5608 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5609 }
5610
5611 /****************************************************************************/
5612 /* Initialize the RX context memory. */
5613 /* */
5614 /* Returns: */
5615 /* Nothing */
5616 /****************************************************************************/
5617 static void
bce_init_rx_context(struct bce_softc * sc)5618 bce_init_rx_context(struct bce_softc *sc)
5619 {
5620 u32 val;
5621
5622 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5623
5624 /* Init the type, size, and BD cache levels for the RX context. */
5625 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5626 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5627 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5628
5629 /*
5630 * Set the level for generating pause frames
5631 * when the number of available rx_bd's gets
5632 * too low (the low watermark) and the level
5633 * when pause frames can be stopped (the high
5634 * watermark).
5635 */
5636 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5637 u32 lo_water, hi_water;
5638
5639 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5640 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5641 } else {
5642 lo_water = 0;
5643 }
5644
5645 if (lo_water >= USABLE_RX_BD_ALLOC) {
5646 lo_water = 0;
5647 }
5648
5649 hi_water = USABLE_RX_BD_ALLOC / 4;
5650
5651 if (hi_water <= lo_water) {
5652 lo_water = 0;
5653 }
5654
5655 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5656 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5657
5658 if (hi_water > 0xf)
5659 hi_water = 0xf;
5660 else if (hi_water == 0)
5661 lo_water = 0;
5662
5663 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5664 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5665 }
5666
5667 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5668
5669 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5670 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5671 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5672 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5673 }
5674
5675 /* Point the hardware to the first page in the chain. */
5676 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5677 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5678 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5679 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5680
5681 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5682 }
5683
5684 /****************************************************************************/
5685 /* Allocate memory and initialize the RX data structures. */
5686 /* */
5687 /* Returns: */
5688 /* 0 for success, positive value for failure. */
5689 /****************************************************************************/
5690 static int
bce_init_rx_chain(struct bce_softc * sc)5691 bce_init_rx_chain(struct bce_softc *sc)
5692 {
5693 struct rx_bd *rxbd;
5694 int i, rc = 0;
5695
5696 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5697 BCE_VERBOSE_CTX);
5698
5699 /* Initialize the RX producer and consumer indices. */
5700 sc->rx_prod = 0;
5701 sc->rx_cons = 0;
5702 sc->rx_prod_bseq = 0;
5703 sc->free_rx_bd = USABLE_RX_BD_ALLOC;
5704 sc->max_rx_bd = USABLE_RX_BD_ALLOC;
5705
5706 /* Initialize the RX next pointer chain entries. */
5707 for (i = 0; i < sc->rx_pages; i++) {
5708 int j;
5709
5710 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5711
5712 /* Check if we've reached the last page. */
5713 if (i == (sc->rx_pages - 1))
5714 j = 0;
5715 else
5716 j = i + 1;
5717
5718 /* Setup the chain page pointers. */
5719 rxbd->rx_bd_haddr_hi =
5720 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5721 rxbd->rx_bd_haddr_lo =
5722 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5723 }
5724
5725 /* Fill up the RX chain. */
5726 bce_fill_rx_chain(sc);
5727
5728 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5729 DBRUN(sc->rx_empty_count = 0);
5730 for (i = 0; i < sc->rx_pages; i++) {
5731 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5733 }
5734
5735 bce_init_rx_context(sc);
5736
5737 DBRUNMSG(BCE_EXTREME_RECV,
5738 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5739 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5740 BCE_VERBOSE_CTX);
5741
5742 /* ToDo: Are there possible failure modes here? */
5743
5744 return(rc);
5745 }
5746
5747 /****************************************************************************/
5748 /* Add mbufs to the RX chain until its full or an mbuf allocation error */
5749 /* occurs. */
5750 /* */
5751 /* Returns: */
5752 /* Nothing */
5753 /****************************************************************************/
5754 static void
bce_fill_rx_chain(struct bce_softc * sc)5755 bce_fill_rx_chain(struct bce_softc *sc)
5756 {
5757 u16 prod, prod_idx;
5758 u32 prod_bseq;
5759
5760 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5761 BCE_VERBOSE_CTX);
5762
5763 /* Get the RX chain producer indices. */
5764 prod = sc->rx_prod;
5765 prod_bseq = sc->rx_prod_bseq;
5766
5767 /* Keep filling the RX chain until it's full. */
5768 while (sc->free_rx_bd > 0) {
5769 prod_idx = RX_CHAIN_IDX(prod);
5770 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5771 /* Bail out if we can't add an mbuf to the chain. */
5772 break;
5773 }
5774 prod = NEXT_RX_BD(prod);
5775 }
5776
5777 /* Save the RX chain producer indices. */
5778 sc->rx_prod = prod;
5779 sc->rx_prod_bseq = prod_bseq;
5780
5781 /* We should never end up pointing to a next page pointer. */
5782 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5783 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5784 __FUNCTION__, rx_prod));
5785
5786 /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5787 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5788 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5789
5790 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5791 BCE_VERBOSE_CTX);
5792 }
5793
5794 /****************************************************************************/
5795 /* Free memory and clear the RX data structures. */
5796 /* */
5797 /* Returns: */
5798 /* Nothing. */
5799 /****************************************************************************/
5800 static void
bce_free_rx_chain(struct bce_softc * sc)5801 bce_free_rx_chain(struct bce_softc *sc)
5802 {
5803 int i;
5804
5805 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5806
5807 /* Free any mbufs still in the RX mbuf chain. */
5808 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5809 if (sc->rx_mbuf_ptr[i] != NULL) {
5810 if (sc->rx_mbuf_map[i] != NULL)
5811 bus_dmamap_sync(sc->rx_mbuf_tag,
5812 sc->rx_mbuf_map[i],
5813 BUS_DMASYNC_POSTREAD);
5814 m_freem(sc->rx_mbuf_ptr[i]);
5815 sc->rx_mbuf_ptr[i] = NULL;
5816 DBRUN(sc->debug_rx_mbuf_alloc--);
5817 }
5818 }
5819
5820 /* Clear each RX chain page. */
5821 for (i = 0; i < sc->rx_pages; i++)
5822 if (sc->rx_bd_chain[i] != NULL)
5823 bzero((char *)sc->rx_bd_chain[i],
5824 BCE_RX_CHAIN_PAGE_SZ);
5825
5826 sc->free_rx_bd = sc->max_rx_bd;
5827
5828 /* Check if we lost any mbufs in the process. */
5829 DBRUNIF((sc->debug_rx_mbuf_alloc),
5830 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5831 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5832
5833 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5834 }
5835
5836 /****************************************************************************/
5837 /* Allocate memory and initialize the page data structures. */
5838 /* Assumes that bce_init_rx_chain() has not already been called. */
5839 /* */
5840 /* Returns: */
5841 /* 0 for success, positive value for failure. */
5842 /****************************************************************************/
5843 static int
bce_init_pg_chain(struct bce_softc * sc)5844 bce_init_pg_chain(struct bce_softc *sc)
5845 {
5846 struct rx_bd *pgbd;
5847 int i, rc = 0;
5848 u32 val;
5849
5850 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5851 BCE_VERBOSE_CTX);
5852
5853 /* Initialize the page producer and consumer indices. */
5854 sc->pg_prod = 0;
5855 sc->pg_cons = 0;
5856 sc->free_pg_bd = USABLE_PG_BD_ALLOC;
5857 sc->max_pg_bd = USABLE_PG_BD_ALLOC;
5858 DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5859 DBRUN(sc->pg_empty_count = 0);
5860
5861 /* Initialize the page next pointer chain entries. */
5862 for (i = 0; i < sc->pg_pages; i++) {
5863 int j;
5864
5865 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5866
5867 /* Check if we've reached the last page. */
5868 if (i == (sc->pg_pages - 1))
5869 j = 0;
5870 else
5871 j = i + 1;
5872
5873 /* Setup the chain page pointers. */
5874 pgbd->rx_bd_haddr_hi =
5875 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5876 pgbd->rx_bd_haddr_lo =
5877 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5878 }
5879
5880 /* Setup the MQ BIN mapping for host_pg_bidx. */
5881 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5882 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
5883
5884 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5885
5886 /* Configure the rx_bd and page chain mbuf cluster size. */
5887 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
5888 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
5889
5890 /* Configure the context reserved for jumbo support. */
5891 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
5892 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
5893
5894 /* Point the hardware to the first page in the page chain. */
5895 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5896 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
5897 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5898 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
5899
5900 /* Fill up the page chain. */
5901 bce_fill_pg_chain(sc);
5902
5903 for (i = 0; i < sc->pg_pages; i++) {
5904 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
5905 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5906 }
5907
5908 DBRUNMSG(BCE_EXTREME_RECV,
5909 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
5910 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5911 BCE_VERBOSE_CTX);
5912 return(rc);
5913 }
5914
5915 /****************************************************************************/
5916 /* Add mbufs to the page chain until its full or an mbuf allocation error */
5917 /* occurs. */
5918 /* */
5919 /* Returns: */
5920 /* Nothing */
5921 /****************************************************************************/
5922 static void
bce_fill_pg_chain(struct bce_softc * sc)5923 bce_fill_pg_chain(struct bce_softc *sc)
5924 {
5925 u16 prod, prod_idx;
5926
5927 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5928 BCE_VERBOSE_CTX);
5929
5930 /* Get the page chain prodcuer index. */
5931 prod = sc->pg_prod;
5932
5933 /* Keep filling the page chain until it's full. */
5934 while (sc->free_pg_bd > 0) {
5935 prod_idx = PG_CHAIN_IDX(prod);
5936 if (bce_get_pg_buf(sc, prod, prod_idx)) {
5937 /* Bail out if we can't add an mbuf to the chain. */
5938 break;
5939 }
5940 prod = NEXT_PG_BD(prod);
5941 }
5942
5943 /* Save the page chain producer index. */
5944 sc->pg_prod = prod;
5945
5946 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5947 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
5948 __FUNCTION__, pg_prod));
5949
5950 /*
5951 * Write the mailbox and tell the chip about
5952 * the new rx_bd's in the page chain.
5953 */
5954 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
5955 prod);
5956
5957 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5958 BCE_VERBOSE_CTX);
5959 }
5960
5961 /****************************************************************************/
5962 /* Free memory and clear the RX data structures. */
5963 /* */
5964 /* Returns: */
5965 /* Nothing. */
5966 /****************************************************************************/
5967 static void
bce_free_pg_chain(struct bce_softc * sc)5968 bce_free_pg_chain(struct bce_softc *sc)
5969 {
5970 int i;
5971
5972 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5973
5974 /* Free any mbufs still in the mbuf page chain. */
5975 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
5976 if (sc->pg_mbuf_ptr[i] != NULL) {
5977 if (sc->pg_mbuf_map[i] != NULL)
5978 bus_dmamap_sync(sc->pg_mbuf_tag,
5979 sc->pg_mbuf_map[i],
5980 BUS_DMASYNC_POSTREAD);
5981 m_freem(sc->pg_mbuf_ptr[i]);
5982 sc->pg_mbuf_ptr[i] = NULL;
5983 DBRUN(sc->debug_pg_mbuf_alloc--);
5984 }
5985 }
5986
5987 /* Clear each page chain pages. */
5988 for (i = 0; i < sc->pg_pages; i++)
5989 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
5990
5991 sc->free_pg_bd = sc->max_pg_bd;
5992
5993 /* Check if we lost any mbufs in the process. */
5994 DBRUNIF((sc->debug_pg_mbuf_alloc),
5995 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
5996 __FUNCTION__, sc->debug_pg_mbuf_alloc));
5997
5998 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5999 }
6000
6001 static u32
bce_get_rphy_link(struct bce_softc * sc)6002 bce_get_rphy_link(struct bce_softc *sc)
6003 {
6004 u32 advertise, link;
6005 int fdpx;
6006
6007 advertise = 0;
6008 fdpx = 0;
6009 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6010 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6011 else
6012 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6013 if (link & BCE_NETLINK_ANEG_ENB)
6014 advertise |= BCE_NETLINK_ANEG_ENB;
6015 if (link & BCE_NETLINK_SPEED_10HALF)
6016 advertise |= BCE_NETLINK_SPEED_10HALF;
6017 if (link & BCE_NETLINK_SPEED_10FULL) {
6018 advertise |= BCE_NETLINK_SPEED_10FULL;
6019 fdpx++;
6020 }
6021 if (link & BCE_NETLINK_SPEED_100HALF)
6022 advertise |= BCE_NETLINK_SPEED_100HALF;
6023 if (link & BCE_NETLINK_SPEED_100FULL) {
6024 advertise |= BCE_NETLINK_SPEED_100FULL;
6025 fdpx++;
6026 }
6027 if (link & BCE_NETLINK_SPEED_1000HALF)
6028 advertise |= BCE_NETLINK_SPEED_1000HALF;
6029 if (link & BCE_NETLINK_SPEED_1000FULL) {
6030 advertise |= BCE_NETLINK_SPEED_1000FULL;
6031 fdpx++;
6032 }
6033 if (link & BCE_NETLINK_SPEED_2500HALF)
6034 advertise |= BCE_NETLINK_SPEED_2500HALF;
6035 if (link & BCE_NETLINK_SPEED_2500FULL) {
6036 advertise |= BCE_NETLINK_SPEED_2500FULL;
6037 fdpx++;
6038 }
6039 if (fdpx)
6040 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6041 BCE_NETLINK_FC_PAUSE_ASYM;
6042 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6043 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6044 BCE_NETLINK_ETH_AT_WIRESPEED;
6045
6046 return (advertise);
6047 }
6048
6049 /****************************************************************************/
6050 /* Set media options. */
6051 /* */
6052 /* Returns: */
6053 /* 0 for success, positive value for failure. */
6054 /****************************************************************************/
6055 static int
bce_ifmedia_upd(if_t ifp)6056 bce_ifmedia_upd(if_t ifp)
6057 {
6058 struct bce_softc *sc = if_getsoftc(ifp);
6059 int error;
6060
6061 DBENTER(BCE_VERBOSE);
6062
6063 BCE_LOCK(sc);
6064 error = bce_ifmedia_upd_locked(ifp);
6065 BCE_UNLOCK(sc);
6066
6067 DBEXIT(BCE_VERBOSE);
6068 return (error);
6069 }
6070
6071 /****************************************************************************/
6072 /* Set media options. */
6073 /* */
6074 /* Returns: */
6075 /* Nothing. */
6076 /****************************************************************************/
6077 static int
bce_ifmedia_upd_locked(if_t ifp)6078 bce_ifmedia_upd_locked(if_t ifp)
6079 {
6080 struct bce_softc *sc = if_getsoftc(ifp);
6081 struct mii_data *mii;
6082 struct mii_softc *miisc;
6083 struct ifmedia *ifm;
6084 u32 link;
6085 int error, fdx;
6086
6087 DBENTER(BCE_VERBOSE_PHY);
6088
6089 error = 0;
6090 BCE_LOCK_ASSERT(sc);
6091
6092 sc->bce_link_up = FALSE;
6093 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6094 ifm = &sc->bce_ifmedia;
6095 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6096 return (EINVAL);
6097 link = 0;
6098 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6099 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6100 case IFM_AUTO:
6101 /*
6102 * Check advertised link of remote PHY by reading
6103 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6104 * Always use the same link type of remote PHY.
6105 */
6106 link = bce_get_rphy_link(sc);
6107 break;
6108 case IFM_2500_SX:
6109 if ((sc->bce_phy_flags &
6110 (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6111 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6112 return (EINVAL);
6113 /*
6114 * XXX
6115 * Have to enable forced 2.5Gbps configuration.
6116 */
6117 if (fdx != 0)
6118 link |= BCE_NETLINK_SPEED_2500FULL;
6119 else
6120 link |= BCE_NETLINK_SPEED_2500HALF;
6121 break;
6122 case IFM_1000_SX:
6123 if ((sc->bce_phy_flags &
6124 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6125 return (EINVAL);
6126 /*
6127 * XXX
6128 * Have to disable 2.5Gbps configuration.
6129 */
6130 if (fdx != 0)
6131 link = BCE_NETLINK_SPEED_1000FULL;
6132 else
6133 link = BCE_NETLINK_SPEED_1000HALF;
6134 break;
6135 case IFM_1000_T:
6136 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6137 return (EINVAL);
6138 if (fdx != 0)
6139 link = BCE_NETLINK_SPEED_1000FULL;
6140 else
6141 link = BCE_NETLINK_SPEED_1000HALF;
6142 break;
6143 case IFM_100_TX:
6144 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6145 return (EINVAL);
6146 if (fdx != 0)
6147 link = BCE_NETLINK_SPEED_100FULL;
6148 else
6149 link = BCE_NETLINK_SPEED_100HALF;
6150 break;
6151 case IFM_10_T:
6152 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6153 return (EINVAL);
6154 if (fdx != 0)
6155 link = BCE_NETLINK_SPEED_10FULL;
6156 else
6157 link = BCE_NETLINK_SPEED_10HALF;
6158 break;
6159 default:
6160 return (EINVAL);
6161 }
6162 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6163 /*
6164 * XXX
6165 * Advertise pause capability for full-duplex media.
6166 */
6167 if (fdx != 0)
6168 link |= BCE_NETLINK_FC_PAUSE_SYM |
6169 BCE_NETLINK_FC_PAUSE_ASYM;
6170 if ((sc->bce_phy_flags &
6171 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6172 link |= BCE_NETLINK_PHY_APP_REMOTE |
6173 BCE_NETLINK_ETH_AT_WIRESPEED;
6174 }
6175
6176 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6177 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6178 } else {
6179 mii = device_get_softc(sc->bce_miibus);
6180
6181 /* Make sure the MII bus has been enumerated. */
6182 if (mii) {
6183 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6184 PHY_RESET(miisc);
6185 error = mii_mediachg(mii);
6186 }
6187 }
6188
6189 DBEXIT(BCE_VERBOSE_PHY);
6190 return (error);
6191 }
6192
6193 static void
bce_ifmedia_sts_rphy(struct bce_softc * sc,struct ifmediareq * ifmr)6194 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6195 {
6196 if_t ifp;
6197 u32 link;
6198
6199 ifp = sc->bce_ifp;
6200 BCE_LOCK_ASSERT(sc);
6201
6202 ifmr->ifm_status = IFM_AVALID;
6203 ifmr->ifm_active = IFM_ETHER;
6204 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6205 /* XXX Handle heart beat status? */
6206 if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6207 ifmr->ifm_status |= IFM_ACTIVE;
6208 else {
6209 ifmr->ifm_active |= IFM_NONE;
6210 if_setbaudrate(ifp, 0);
6211 return;
6212 }
6213 switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6214 case BCE_LINK_STATUS_10HALF:
6215 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6216 if_setbaudrate(ifp, IF_Mbps(10UL));
6217 break;
6218 case BCE_LINK_STATUS_10FULL:
6219 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6220 if_setbaudrate(ifp, IF_Mbps(10UL));
6221 break;
6222 case BCE_LINK_STATUS_100HALF:
6223 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6224 if_setbaudrate(ifp, IF_Mbps(100UL));
6225 break;
6226 case BCE_LINK_STATUS_100FULL:
6227 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6228 if_setbaudrate(ifp, IF_Mbps(100UL));
6229 break;
6230 case BCE_LINK_STATUS_1000HALF:
6231 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6232 ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6233 else
6234 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6235 if_setbaudrate(ifp, IF_Mbps(1000UL));
6236 break;
6237 case BCE_LINK_STATUS_1000FULL:
6238 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6239 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6240 else
6241 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6242 if_setbaudrate(ifp, IF_Mbps(1000UL));
6243 break;
6244 case BCE_LINK_STATUS_2500HALF:
6245 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6246 ifmr->ifm_active |= IFM_NONE;
6247 return;
6248 } else
6249 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6250 if_setbaudrate(ifp, IF_Mbps(2500UL));
6251 break;
6252 case BCE_LINK_STATUS_2500FULL:
6253 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6254 ifmr->ifm_active |= IFM_NONE;
6255 return;
6256 } else
6257 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6258 if_setbaudrate(ifp, IF_Mbps(2500UL));
6259 break;
6260 default:
6261 ifmr->ifm_active |= IFM_NONE;
6262 return;
6263 }
6264
6265 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6266 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6267 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6268 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6269 }
6270
6271 /****************************************************************************/
6272 /* Reports current media status. */
6273 /* */
6274 /* Returns: */
6275 /* Nothing. */
6276 /****************************************************************************/
6277 static void
bce_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)6278 bce_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
6279 {
6280 struct bce_softc *sc = if_getsoftc(ifp);
6281 struct mii_data *mii;
6282
6283 DBENTER(BCE_VERBOSE_PHY);
6284
6285 BCE_LOCK(sc);
6286
6287 if ((if_getflags(ifp) & IFF_UP) == 0) {
6288 BCE_UNLOCK(sc);
6289 return;
6290 }
6291
6292 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6293 bce_ifmedia_sts_rphy(sc, ifmr);
6294 else {
6295 mii = device_get_softc(sc->bce_miibus);
6296 mii_pollstat(mii);
6297 ifmr->ifm_active = mii->mii_media_active;
6298 ifmr->ifm_status = mii->mii_media_status;
6299 }
6300
6301 BCE_UNLOCK(sc);
6302
6303 DBEXIT(BCE_VERBOSE_PHY);
6304 }
6305
6306 /****************************************************************************/
6307 /* Handles PHY generated interrupt events. */
6308 /* */
6309 /* Returns: */
6310 /* Nothing. */
6311 /****************************************************************************/
6312 static void
bce_phy_intr(struct bce_softc * sc)6313 bce_phy_intr(struct bce_softc *sc)
6314 {
6315 u32 new_link_state, old_link_state;
6316
6317 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6318
6319 DBRUN(sc->phy_interrupts++);
6320
6321 new_link_state = sc->status_block->status_attn_bits &
6322 STATUS_ATTN_BITS_LINK_STATE;
6323 old_link_state = sc->status_block->status_attn_bits_ack &
6324 STATUS_ATTN_BITS_LINK_STATE;
6325
6326 /* Handle any changes if the link state has changed. */
6327 if (new_link_state != old_link_state) {
6328 /* Update the status_attn_bits_ack field. */
6329 if (new_link_state) {
6330 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6331 STATUS_ATTN_BITS_LINK_STATE);
6332 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6333 __FUNCTION__);
6334 } else {
6335 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6336 STATUS_ATTN_BITS_LINK_STATE);
6337 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6338 __FUNCTION__);
6339 }
6340
6341 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6342 if (new_link_state) {
6343 if (bootverbose)
6344 if_printf(sc->bce_ifp, "link UP\n");
6345 if_link_state_change(sc->bce_ifp,
6346 LINK_STATE_UP);
6347 } else {
6348 if (bootverbose)
6349 if_printf(sc->bce_ifp, "link DOWN\n");
6350 if_link_state_change(sc->bce_ifp,
6351 LINK_STATE_DOWN);
6352 }
6353 }
6354 /*
6355 * Assume link is down and allow
6356 * tick routine to update the state
6357 * based on the actual media state.
6358 */
6359 sc->bce_link_up = FALSE;
6360 callout_stop(&sc->bce_tick_callout);
6361 bce_tick(sc);
6362 }
6363
6364 /* Acknowledge the link change interrupt. */
6365 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6366
6367 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6368 }
6369
6370 /****************************************************************************/
6371 /* Reads the receive consumer value from the status block (skipping over */
6372 /* chain page pointer if necessary). */
6373 /* */
6374 /* Returns: */
6375 /* hw_cons */
6376 /****************************************************************************/
6377 static inline u16
bce_get_hw_rx_cons(struct bce_softc * sc)6378 bce_get_hw_rx_cons(struct bce_softc *sc)
6379 {
6380 u16 hw_cons;
6381
6382 rmb();
6383 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6384 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6385 hw_cons++;
6386
6387 return hw_cons;
6388 }
6389
6390 /****************************************************************************/
6391 /* Handles received frame interrupt events. */
6392 /* */
6393 /* Returns: */
6394 /* Nothing. */
6395 /****************************************************************************/
6396 static void
bce_rx_intr(struct bce_softc * sc)6397 bce_rx_intr(struct bce_softc *sc)
6398 {
6399 if_t ifp = sc->bce_ifp;
6400 struct l2_fhdr *l2fhdr;
6401 struct ether_vlan_header *vh;
6402 unsigned int pkt_len;
6403 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6404 u32 status;
6405 unsigned int rem_len;
6406 u16 sw_pg_cons, sw_pg_cons_idx;
6407
6408 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6409 DBRUN(sc->interrupts_rx++);
6410 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6411 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6412 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6413
6414 /* Prepare the RX chain pages to be accessed by the host CPU. */
6415 for (int i = 0; i < sc->rx_pages; i++)
6416 bus_dmamap_sync(sc->rx_bd_chain_tag,
6417 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6418
6419 /* Prepare the page chain pages to be accessed by the host CPU. */
6420 if (bce_hdr_split == TRUE) {
6421 for (int i = 0; i < sc->pg_pages; i++)
6422 bus_dmamap_sync(sc->pg_bd_chain_tag,
6423 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6424 }
6425
6426 /* Get the hardware's view of the RX consumer index. */
6427 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6428
6429 /* Get working copies of the driver's view of the consumer indices. */
6430 sw_rx_cons = sc->rx_cons;
6431 sw_pg_cons = sc->pg_cons;
6432
6433 /* Update some debug statistics counters */
6434 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6435 sc->rx_low_watermark = sc->free_rx_bd);
6436 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6437 sc->rx_empty_count++);
6438
6439 /* Scan through the receive chain as long as there is work to do */
6440 /* ToDo: Consider setting a limit on the number of packets processed. */
6441 rmb();
6442 while (sw_rx_cons != hw_rx_cons) {
6443 struct mbuf *m0;
6444
6445 /* Convert the producer/consumer indices to an actual rx_bd index. */
6446 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6447
6448 /* Unmap the mbuf from DMA space. */
6449 bus_dmamap_sync(sc->rx_mbuf_tag,
6450 sc->rx_mbuf_map[sw_rx_cons_idx],
6451 BUS_DMASYNC_POSTREAD);
6452 bus_dmamap_unload(sc->rx_mbuf_tag,
6453 sc->rx_mbuf_map[sw_rx_cons_idx]);
6454
6455 /* Remove the mbuf from the RX chain. */
6456 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6457 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6458 DBRUN(sc->debug_rx_mbuf_alloc--);
6459 sc->free_rx_bd++;
6460
6461 /*
6462 * Frames received on the NetXteme II are prepended
6463 * with an l2_fhdr structure which provides status
6464 * information about the received frame (including
6465 * VLAN tags and checksum info). The frames are
6466 * also automatically adjusted to word align the IP
6467 * header (i.e. two null bytes are inserted before
6468 * the Ethernet header). As a result the data
6469 * DMA'd by the controller into the mbuf looks
6470 * like this:
6471 *
6472 * +---------+-----+---------------------+-----+
6473 * | l2_fhdr | pad | packet data | FCS |
6474 * +---------+-----+---------------------+-----+
6475 *
6476 * The l2_fhdr needs to be checked and skipped and
6477 * the FCS needs to be stripped before sending the
6478 * packet up the stack.
6479 */
6480 l2fhdr = mtod(m0, struct l2_fhdr *);
6481
6482 /* Get the packet data + FCS length and the status. */
6483 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6484 status = l2fhdr->l2_fhdr_status;
6485
6486 /*
6487 * Skip over the l2_fhdr and pad, resulting in the
6488 * following data in the mbuf:
6489 * +---------------------+-----+
6490 * | packet data | FCS |
6491 * +---------------------+-----+
6492 */
6493 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6494
6495 /*
6496 * When split header mode is used, an ethernet frame
6497 * may be split across the receive chain and the
6498 * page chain. If that occurs an mbuf cluster must be
6499 * reassembled from the individual mbuf pieces.
6500 */
6501 if (bce_hdr_split == TRUE) {
6502 /*
6503 * Check whether the received frame fits in a single
6504 * mbuf or not (i.e. packet data + FCS <=
6505 * sc->rx_bd_mbuf_data_len bytes).
6506 */
6507 if (pkt_len > m0->m_len) {
6508 /*
6509 * The received frame is larger than a single mbuf.
6510 * If the frame was a TCP frame then only the TCP
6511 * header is placed in the mbuf, the remaining
6512 * payload (including FCS) is placed in the page
6513 * chain, the SPLIT flag is set, and the header
6514 * length is placed in the IP checksum field.
6515 * If the frame is not a TCP frame then the mbuf
6516 * is filled and the remaining bytes are placed
6517 * in the page chain.
6518 */
6519
6520 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6521 "packet.\n", __FUNCTION__);
6522 DBRUN(sc->split_header_frames_rcvd++);
6523
6524 /*
6525 * When the page chain is enabled and the TCP
6526 * header has been split from the TCP payload,
6527 * the ip_xsum structure will reflect the length
6528 * of the TCP header, not the IP checksum. Set
6529 * the packet length of the mbuf accordingly.
6530 */
6531 if (status & L2_FHDR_STATUS_SPLIT) {
6532 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6533 DBRUN(sc->split_header_tcp_frames_rcvd++);
6534 }
6535
6536 rem_len = pkt_len - m0->m_len;
6537
6538 /* Pull mbufs off the page chain for any remaining data. */
6539 while (rem_len > 0) {
6540 struct mbuf *m_pg;
6541
6542 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6543
6544 /* Remove the mbuf from the page chain. */
6545 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6546 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6547 DBRUN(sc->debug_pg_mbuf_alloc--);
6548 sc->free_pg_bd++;
6549
6550 /* Unmap the page chain mbuf from DMA space. */
6551 bus_dmamap_sync(sc->pg_mbuf_tag,
6552 sc->pg_mbuf_map[sw_pg_cons_idx],
6553 BUS_DMASYNC_POSTREAD);
6554 bus_dmamap_unload(sc->pg_mbuf_tag,
6555 sc->pg_mbuf_map[sw_pg_cons_idx]);
6556
6557 /* Adjust the mbuf length. */
6558 if (rem_len < m_pg->m_len) {
6559 /* The mbuf chain is complete. */
6560 m_pg->m_len = rem_len;
6561 rem_len = 0;
6562 } else {
6563 /* More packet data is waiting. */
6564 rem_len -= m_pg->m_len;
6565 }
6566
6567 /* Concatenate the mbuf cluster to the mbuf. */
6568 m_cat(m0, m_pg);
6569
6570 sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6571 }
6572
6573 /* Set the total packet length. */
6574 m0->m_pkthdr.len = pkt_len;
6575
6576 } else {
6577 /*
6578 * The received packet is small and fits in a
6579 * single mbuf (i.e. the l2_fhdr + pad + packet +
6580 * FCS <= MHLEN). In other words, the packet is
6581 * 154 bytes or less in size.
6582 */
6583
6584 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6585 "packet.\n", __FUNCTION__);
6586
6587 /* Set the total packet length. */
6588 m0->m_pkthdr.len = m0->m_len = pkt_len;
6589 }
6590 } else
6591 /* Set the total packet length. */
6592 m0->m_pkthdr.len = m0->m_len = pkt_len;
6593
6594 /* Remove the trailing Ethernet FCS. */
6595 m_adj(m0, -ETHER_CRC_LEN);
6596
6597 /* Check that the resulting mbuf chain is valid. */
6598 DBRUN(m_sanity(m0, FALSE));
6599 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6600 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6601 BCE_PRINTF("Invalid Ethernet frame size!\n");
6602 m_print(m0, 128));
6603
6604 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6605 sc->l2fhdr_error_sim_count++;
6606 status = status | L2_FHDR_ERRORS_PHY_DECODE);
6607
6608 /* Check the received frame for errors. */
6609 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6610 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6611 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
6612 /* Log the error and release the mbuf. */
6613 sc->l2fhdr_error_count++;
6614 m_freem(m0);
6615 m0 = NULL;
6616 goto bce_rx_intr_next_rx;
6617 }
6618
6619 /* Send the packet to the appropriate interface. */
6620 m0->m_pkthdr.rcvif = ifp;
6621
6622 /* Assume no hardware checksum. */
6623 m0->m_pkthdr.csum_flags = 0;
6624
6625 /* Validate the checksum if offload enabled. */
6626 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
6627 /* Check for an IP datagram. */
6628 if (!(status & L2_FHDR_STATUS_SPLIT) &&
6629 (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6630 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6631 DBRUN(sc->csum_offload_ip++);
6632 /* Check if the IP checksum is valid. */
6633 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6634 m0->m_pkthdr.csum_flags |=
6635 CSUM_IP_VALID;
6636 }
6637
6638 /* Check for a valid TCP/UDP frame. */
6639 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6640 L2_FHDR_STATUS_UDP_DATAGRAM)) {
6641 /* Check for a good TCP/UDP checksum. */
6642 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6643 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6644 DBRUN(sc->csum_offload_tcp_udp++);
6645 m0->m_pkthdr.csum_data =
6646 l2fhdr->l2_fhdr_tcp_udp_xsum;
6647 m0->m_pkthdr.csum_flags |=
6648 (CSUM_DATA_VALID
6649 | CSUM_PSEUDO_HDR);
6650 }
6651 }
6652 }
6653
6654 /* Attach the VLAN tag. */
6655 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6656 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6657 DBRUN(sc->vlan_tagged_frames_rcvd++);
6658 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
6659 DBRUN(sc->vlan_tagged_frames_stripped++);
6660 m0->m_pkthdr.ether_vtag =
6661 l2fhdr->l2_fhdr_vlan_tag;
6662 m0->m_flags |= M_VLANTAG;
6663 } else {
6664 /*
6665 * bce(4) controllers can't disable VLAN
6666 * tag stripping if management firmware
6667 * (ASF/IPMI/UMP) is running. So we always
6668 * strip VLAN tag and manually reconstruct
6669 * the VLAN frame by appending stripped
6670 * VLAN tag in driver if VLAN tag stripping
6671 * was disabled.
6672 *
6673 * TODO: LLC SNAP handling.
6674 */
6675 bcopy(mtod(m0, uint8_t *),
6676 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6677 ETHER_ADDR_LEN * 2);
6678 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6679 vh = mtod(m0, struct ether_vlan_header *);
6680 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6681 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6682 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6683 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6684 }
6685 }
6686
6687 /* Increment received packet statistics. */
6688 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
6689
6690 bce_rx_intr_next_rx:
6691 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6692
6693 /* If we have a packet, pass it up the stack */
6694 if (m0) {
6695 /* Make sure we don't lose our place when we release the lock. */
6696 sc->rx_cons = sw_rx_cons;
6697 sc->pg_cons = sw_pg_cons;
6698
6699 BCE_UNLOCK(sc);
6700 if_input(ifp, m0);
6701 BCE_LOCK(sc);
6702
6703 /* Recover our place. */
6704 sw_rx_cons = sc->rx_cons;
6705 sw_pg_cons = sc->pg_cons;
6706 }
6707
6708 /* Refresh hw_cons to see if there's new work */
6709 if (sw_rx_cons == hw_rx_cons)
6710 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6711 }
6712
6713 /* No new packets. Refill the page chain. */
6714 if (bce_hdr_split == TRUE) {
6715 sc->pg_cons = sw_pg_cons;
6716 bce_fill_pg_chain(sc);
6717 }
6718
6719 /* No new packets. Refill the RX chain. */
6720 sc->rx_cons = sw_rx_cons;
6721 bce_fill_rx_chain(sc);
6722
6723 /* Prepare the page chain pages to be accessed by the NIC. */
6724 for (int i = 0; i < sc->rx_pages; i++)
6725 bus_dmamap_sync(sc->rx_bd_chain_tag,
6726 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6727
6728 if (bce_hdr_split == TRUE) {
6729 for (int i = 0; i < sc->pg_pages; i++)
6730 bus_dmamap_sync(sc->pg_bd_chain_tag,
6731 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6732 }
6733
6734 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6735 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6736 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6737 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6738 }
6739
6740 /****************************************************************************/
6741 /* Reads the transmit consumer value from the status block (skipping over */
6742 /* chain page pointer if necessary). */
6743 /* */
6744 /* Returns: */
6745 /* hw_cons */
6746 /****************************************************************************/
6747 static inline u16
bce_get_hw_tx_cons(struct bce_softc * sc)6748 bce_get_hw_tx_cons(struct bce_softc *sc)
6749 {
6750 u16 hw_cons;
6751
6752 mb();
6753 hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6754 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6755 hw_cons++;
6756
6757 return hw_cons;
6758 }
6759
6760 /****************************************************************************/
6761 /* Handles transmit completion interrupt events. */
6762 /* */
6763 /* Returns: */
6764 /* Nothing. */
6765 /****************************************************************************/
6766 static void
bce_tx_intr(struct bce_softc * sc)6767 bce_tx_intr(struct bce_softc *sc)
6768 {
6769 if_t ifp = sc->bce_ifp;
6770 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6771
6772 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6773 DBRUN(sc->interrupts_tx++);
6774 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6775 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6776 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6777
6778 BCE_LOCK_ASSERT(sc);
6779
6780 /* Get the hardware's view of the TX consumer index. */
6781 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6782 sw_tx_cons = sc->tx_cons;
6783
6784 /* Prevent speculative reads of the status block. */
6785 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6786 BUS_SPACE_BARRIER_READ);
6787
6788 /* Cycle through any completed TX chain page entries. */
6789 while (sw_tx_cons != hw_tx_cons) {
6790 #ifdef BCE_DEBUG
6791 struct tx_bd *txbd = NULL;
6792 #endif
6793 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6794
6795 DBPRINT(sc, BCE_INFO_SEND,
6796 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6797 "sw_tx_chain_cons = 0x%04X\n",
6798 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6799
6800 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6801 BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6802 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6803 (int) MAX_TX_BD_ALLOC);
6804 bce_breakpoint(sc));
6805
6806 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6807 [TX_IDX(sw_tx_chain_cons)]);
6808
6809 DBRUNIF((txbd == NULL),
6810 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6811 __FILE__, __LINE__, sw_tx_chain_cons);
6812 bce_breakpoint(sc));
6813
6814 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6815 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6816
6817 /*
6818 * Free the associated mbuf. Remember
6819 * that only the last tx_bd of a packet
6820 * has an mbuf pointer and DMA map.
6821 */
6822 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6823 /* Validate that this is the last tx_bd. */
6824 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6825 BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6826 "txmbuf == NULL!\n", __FILE__, __LINE__);
6827 bce_breakpoint(sc));
6828
6829 DBRUNMSG(BCE_INFO_SEND,
6830 BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6831 "from tx_bd[0x%04X]\n", __FUNCTION__,
6832 sw_tx_chain_cons));
6833
6834 /* Unmap the mbuf. */
6835 bus_dmamap_unload(sc->tx_mbuf_tag,
6836 sc->tx_mbuf_map[sw_tx_chain_cons]);
6837
6838 /* Free the mbuf. */
6839 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6840 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6841 DBRUN(sc->debug_tx_mbuf_alloc--);
6842
6843 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
6844 }
6845
6846 sc->used_tx_bd--;
6847 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6848
6849 /* Refresh hw_cons to see if there's new work. */
6850 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6851
6852 /* Prevent speculative reads of the status block. */
6853 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6854 BUS_SPACE_BARRIER_READ);
6855 }
6856
6857 /* Clear the TX timeout timer. */
6858 sc->watchdog_timer = 0;
6859
6860 /* Clear the tx hardware queue full flag. */
6861 if (sc->used_tx_bd < sc->max_tx_bd) {
6862 DBRUNIF((if_getdrvflags(ifp) & IFF_DRV_OACTIVE),
6863 DBPRINT(sc, BCE_INFO_SEND,
6864 "%s(): Open TX chain! %d/%d (used/total)\n",
6865 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6866 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
6867 }
6868
6869 sc->tx_cons = sw_tx_cons;
6870
6871 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
6872 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6873 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6874 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6875 }
6876
6877 /****************************************************************************/
6878 /* Disables interrupt generation. */
6879 /* */
6880 /* Returns: */
6881 /* Nothing. */
6882 /****************************************************************************/
6883 static void
bce_disable_intr(struct bce_softc * sc)6884 bce_disable_intr(struct bce_softc *sc)
6885 {
6886 DBENTER(BCE_VERBOSE_INTR);
6887
6888 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
6889 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
6890
6891 DBEXIT(BCE_VERBOSE_INTR);
6892 }
6893
6894 /****************************************************************************/
6895 /* Enables interrupt generation. */
6896 /* */
6897 /* Returns: */
6898 /* Nothing. */
6899 /****************************************************************************/
6900 static void
bce_enable_intr(struct bce_softc * sc,int coal_now)6901 bce_enable_intr(struct bce_softc *sc, int coal_now)
6902 {
6903 DBENTER(BCE_VERBOSE_INTR);
6904
6905 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6906 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
6907 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
6908
6909 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6910 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
6911
6912 /* Force an immediate interrupt (whether there is new data or not). */
6913 if (coal_now)
6914 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
6915
6916 DBEXIT(BCE_VERBOSE_INTR);
6917 }
6918
6919 /****************************************************************************/
6920 /* Handles controller initialization. */
6921 /* */
6922 /* Returns: */
6923 /* Nothing. */
6924 /****************************************************************************/
6925 static void
bce_init_locked(struct bce_softc * sc)6926 bce_init_locked(struct bce_softc *sc)
6927 {
6928 if_t ifp;
6929 u32 ether_mtu = 0;
6930
6931 DBENTER(BCE_VERBOSE_RESET);
6932
6933 BCE_LOCK_ASSERT(sc);
6934
6935 ifp = sc->bce_ifp;
6936
6937 /* Check if the driver is still running and bail out if it is. */
6938 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6939 goto bce_init_locked_exit;
6940
6941 bce_stop(sc);
6942
6943 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
6944 BCE_PRINTF("%s(%d): Controller reset failed!\n",
6945 __FILE__, __LINE__);
6946 goto bce_init_locked_exit;
6947 }
6948
6949 if (bce_chipinit(sc)) {
6950 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
6951 __FILE__, __LINE__);
6952 goto bce_init_locked_exit;
6953 }
6954
6955 if (bce_blockinit(sc)) {
6956 BCE_PRINTF("%s(%d): Block initialization failed!\n",
6957 __FILE__, __LINE__);
6958 goto bce_init_locked_exit;
6959 }
6960
6961 /* Load our MAC address. */
6962 bcopy(if_getlladdr(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
6963 bce_set_mac_addr(sc);
6964
6965 if (bce_hdr_split == FALSE)
6966 bce_get_rx_buffer_sizes(sc, if_getmtu(ifp));
6967 /*
6968 * Calculate and program the hardware Ethernet MTU
6969 * size. Be generous on the receive if we have room
6970 * and allowed by the user.
6971 */
6972 if (bce_strict_rx_mtu == TRUE)
6973 ether_mtu = if_getmtu(ifp);
6974 else {
6975 if (bce_hdr_split == TRUE) {
6976 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len + MCLBYTES)
6977 ether_mtu = sc->rx_bd_mbuf_data_len +
6978 MCLBYTES;
6979 else
6980 ether_mtu = if_getmtu(ifp);
6981 } else {
6982 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len)
6983 ether_mtu = sc->rx_bd_mbuf_data_len;
6984 else
6985 ether_mtu = if_getmtu(ifp);
6986 }
6987 }
6988
6989 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
6990
6991 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
6992 __FUNCTION__, ether_mtu);
6993
6994 /* Program the mtu, enabling jumbo frame support if necessary. */
6995 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
6996 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6997 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6998 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6999 else
7000 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7001
7002 /* Program appropriate promiscuous/multicast filtering. */
7003 bce_set_rx_mode(sc);
7004
7005 if (bce_hdr_split == TRUE) {
7006 /* Init page buffer descriptor chain. */
7007 bce_init_pg_chain(sc);
7008 }
7009
7010 /* Init RX buffer descriptor chain. */
7011 bce_init_rx_chain(sc);
7012
7013 /* Init TX buffer descriptor chain. */
7014 bce_init_tx_chain(sc);
7015
7016 /* Enable host interrupts. */
7017 bce_enable_intr(sc, 1);
7018
7019 bce_ifmedia_upd_locked(ifp);
7020
7021 /* Let the OS know the driver is up and running. */
7022 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
7023 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
7024
7025 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7026
7027 bce_init_locked_exit:
7028 DBEXIT(BCE_VERBOSE_RESET);
7029 }
7030
7031 /****************************************************************************/
7032 /* Initialize the controller just enough so that any management firmware */
7033 /* running on the device will continue to operate correctly. */
7034 /* */
7035 /* Returns: */
7036 /* Nothing. */
7037 /****************************************************************************/
7038 static void
bce_mgmt_init_locked(struct bce_softc * sc)7039 bce_mgmt_init_locked(struct bce_softc *sc)
7040 {
7041 if_t ifp;
7042
7043 DBENTER(BCE_VERBOSE_RESET);
7044
7045 BCE_LOCK_ASSERT(sc);
7046
7047 /* Bail out if management firmware is not running. */
7048 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7049 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7050 "No management firmware running...\n");
7051 goto bce_mgmt_init_locked_exit;
7052 }
7053
7054 ifp = sc->bce_ifp;
7055
7056 /* Enable all critical blocks in the MAC. */
7057 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7058 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7059 DELAY(20);
7060
7061 bce_ifmedia_upd_locked(ifp);
7062
7063 bce_mgmt_init_locked_exit:
7064 DBEXIT(BCE_VERBOSE_RESET);
7065 }
7066
7067 /****************************************************************************/
7068 /* Handles controller initialization when called from an unlocked routine. */
7069 /* */
7070 /* Returns: */
7071 /* Nothing. */
7072 /****************************************************************************/
7073 static void
bce_init(void * xsc)7074 bce_init(void *xsc)
7075 {
7076 struct bce_softc *sc = xsc;
7077
7078 DBENTER(BCE_VERBOSE_RESET);
7079
7080 BCE_LOCK(sc);
7081 bce_init_locked(sc);
7082 BCE_UNLOCK(sc);
7083
7084 DBEXIT(BCE_VERBOSE_RESET);
7085 }
7086
7087 /****************************************************************************/
7088 /* Modifies an mbuf for TSO on the hardware. */
7089 /* */
7090 /* Returns: */
7091 /* Pointer to a modified mbuf. */
7092 /****************************************************************************/
7093 static struct mbuf *
bce_tso_setup(struct bce_softc * sc,struct mbuf ** m_head,u16 * flags)7094 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7095 {
7096 struct mbuf *m;
7097 struct ether_header *eh;
7098 struct ip *ip;
7099 struct tcphdr *th;
7100 u16 etype;
7101 int hdr_len __unused, ip_len __unused, ip_hlen = 0, tcp_hlen = 0;
7102
7103 DBRUN(sc->tso_frames_requested++);
7104
7105 ip_len = 0;
7106 /* Controller may modify mbuf chains. */
7107 if (M_WRITABLE(*m_head) == 0) {
7108 m = m_dup(*m_head, M_NOWAIT);
7109 m_freem(*m_head);
7110 if (m == NULL) {
7111 sc->mbuf_alloc_failed_count++;
7112 *m_head = NULL;
7113 return (NULL);
7114 }
7115 *m_head = m;
7116 }
7117
7118 /*
7119 * For TSO the controller needs two pieces of info,
7120 * the MSS and the IP+TCP options length.
7121 */
7122 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7123 if (m == NULL) {
7124 *m_head = NULL;
7125 return (NULL);
7126 }
7127 eh = mtod(m, struct ether_header *);
7128 etype = ntohs(eh->ether_type);
7129
7130 /* Check for supported TSO Ethernet types (only IPv4 for now) */
7131 switch (etype) {
7132 case ETHERTYPE_IP:
7133 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7134 /* TSO only supported for TCP protocol. */
7135 if (ip->ip_p != IPPROTO_TCP) {
7136 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7137 __FILE__, __LINE__);
7138 m_freem(*m_head);
7139 *m_head = NULL;
7140 return (NULL);
7141 }
7142
7143 /* Get IP header length in bytes (min 20) */
7144 ip_hlen = ip->ip_hl << 2;
7145 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7146 sizeof(struct tcphdr));
7147 if (m == NULL) {
7148 *m_head = NULL;
7149 return (NULL);
7150 }
7151
7152 /* Get the TCP header length in bytes (min 20) */
7153 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7154 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7155 tcp_hlen = (th->th_off << 2);
7156
7157 /* Make sure all IP/TCP options live in the same buffer. */
7158 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen +
7159 tcp_hlen);
7160 if (m == NULL) {
7161 *m_head = NULL;
7162 return (NULL);
7163 }
7164
7165 /* Clear IP header length and checksum, will be calc'd by h/w. */
7166 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7167 ip_len = ip->ip_len;
7168 ip->ip_len = 0;
7169 ip->ip_sum = 0;
7170 break;
7171 case ETHERTYPE_IPV6:
7172 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7173 __FILE__, __LINE__);
7174 m_freem(*m_head);
7175 *m_head = NULL;
7176 return (NULL);
7177 /* NOT REACHED */
7178 default:
7179 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7180 __FILE__, __LINE__);
7181 m_freem(*m_head);
7182 *m_head = NULL;
7183 return (NULL);
7184 }
7185
7186 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7187
7188 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7189 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7190 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7191 tcp_hlen, ip_len);
7192
7193 /* Set the LSO flag in the TX BD */
7194 *flags |= TX_BD_FLAGS_SW_LSO;
7195
7196 /* Set the length of IP + TCP options (in 32 bit words) */
7197 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7198 sizeof(struct tcphdr)) >> 2) << 8);
7199
7200 DBRUN(sc->tso_frames_completed++);
7201 return (*m_head);
7202 }
7203
7204 /****************************************************************************/
7205 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7206 /* memory visible to the controller. */
7207 /* */
7208 /* Returns: */
7209 /* 0 for success, positive value for failure. */
7210 /* Modified: */
7211 /* m_head: May be set to NULL if MBUF is excessively fragmented. */
7212 /****************************************************************************/
7213 static int
bce_tx_encap(struct bce_softc * sc,struct mbuf ** m_head)7214 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7215 {
7216 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7217 bus_dmamap_t map;
7218 struct tx_bd *txbd = NULL;
7219 struct mbuf *m0;
7220 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7221 u32 prod_bseq;
7222
7223 #ifdef BCE_DEBUG
7224 u16 debug_prod;
7225 #endif
7226
7227 int i, error, nsegs, rc = 0;
7228
7229 DBENTER(BCE_VERBOSE_SEND);
7230
7231 /* Make sure we have room in the TX chain. */
7232 if (sc->used_tx_bd >= sc->max_tx_bd)
7233 goto bce_tx_encap_exit;
7234
7235 /* Transfer any checksum offload flags to the bd. */
7236 m0 = *m_head;
7237 if (m0->m_pkthdr.csum_flags) {
7238 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7239 m0 = bce_tso_setup(sc, m_head, &flags);
7240 if (m0 == NULL) {
7241 DBRUN(sc->tso_frames_failed++);
7242 goto bce_tx_encap_exit;
7243 }
7244 mss = htole16(m0->m_pkthdr.tso_segsz);
7245 } else {
7246 if (m0->m_pkthdr.csum_flags & CSUM_IP)
7247 flags |= TX_BD_FLAGS_IP_CKSUM;
7248 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7249 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7250 }
7251 }
7252
7253 /* Transfer any VLAN tags to the bd. */
7254 if (m0->m_flags & M_VLANTAG) {
7255 flags |= TX_BD_FLAGS_VLAN_TAG;
7256 vlan_tag = m0->m_pkthdr.ether_vtag;
7257 }
7258
7259 /* Map the mbuf into DMAable memory. */
7260 prod = sc->tx_prod;
7261 chain_prod = TX_CHAIN_IDX(prod);
7262 map = sc->tx_mbuf_map[chain_prod];
7263
7264 /* Map the mbuf into our DMA address space. */
7265 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7266 segs, &nsegs, BUS_DMA_NOWAIT);
7267
7268 /* Check if the DMA mapping was successful */
7269 if (error == EFBIG) {
7270 sc->mbuf_frag_count++;
7271
7272 /* Try to defrag the mbuf. */
7273 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7274 if (m0 == NULL) {
7275 /* Defrag was unsuccessful */
7276 m_freem(*m_head);
7277 *m_head = NULL;
7278 sc->mbuf_alloc_failed_count++;
7279 rc = ENOBUFS;
7280 goto bce_tx_encap_exit;
7281 }
7282
7283 /* Defrag was successful, try mapping again */
7284 *m_head = m0;
7285 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7286 map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7287
7288 /* Still getting an error after a defrag. */
7289 if (error == ENOMEM) {
7290 /* Insufficient DMA buffers available. */
7291 sc->dma_map_addr_tx_failed_count++;
7292 rc = error;
7293 goto bce_tx_encap_exit;
7294 } else if (error != 0) {
7295 /* Release it and return an error. */
7296 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7297 "TX chain!\n", __FILE__, __LINE__);
7298 m_freem(m0);
7299 *m_head = NULL;
7300 sc->dma_map_addr_tx_failed_count++;
7301 rc = ENOBUFS;
7302 goto bce_tx_encap_exit;
7303 }
7304 } else if (error == ENOMEM) {
7305 /* Insufficient DMA buffers available. */
7306 sc->dma_map_addr_tx_failed_count++;
7307 rc = error;
7308 goto bce_tx_encap_exit;
7309 } else if (error != 0) {
7310 m_freem(m0);
7311 *m_head = NULL;
7312 sc->dma_map_addr_tx_failed_count++;
7313 rc = error;
7314 goto bce_tx_encap_exit;
7315 }
7316
7317 /* Make sure there's room in the chain */
7318 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7319 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7320 rc = ENOBUFS;
7321 goto bce_tx_encap_exit;
7322 }
7323
7324 /* prod points to an empty tx_bd at this point. */
7325 prod_bseq = sc->tx_prod_bseq;
7326
7327 #ifdef BCE_DEBUG
7328 debug_prod = chain_prod;
7329 #endif
7330
7331 DBPRINT(sc, BCE_INFO_SEND,
7332 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7333 "prod_bseq = 0x%08X\n",
7334 __FUNCTION__, prod, chain_prod, prod_bseq);
7335
7336 /*
7337 * Cycle through each mbuf segment that makes up
7338 * the outgoing frame, gathering the mapping info
7339 * for that segment and creating a tx_bd for
7340 * the mbuf.
7341 */
7342 for (i = 0; i < nsegs ; i++) {
7343 chain_prod = TX_CHAIN_IDX(prod);
7344 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7345 [TX_IDX(chain_prod)];
7346
7347 txbd->tx_bd_haddr_lo =
7348 htole32(BCE_ADDR_LO(segs[i].ds_addr));
7349 txbd->tx_bd_haddr_hi =
7350 htole32(BCE_ADDR_HI(segs[i].ds_addr));
7351 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7352 htole16(segs[i].ds_len);
7353 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7354 txbd->tx_bd_flags = htole16(flags);
7355 prod_bseq += segs[i].ds_len;
7356 if (i == 0)
7357 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7358 prod = NEXT_TX_BD(prod);
7359 }
7360
7361 /* Set the END flag on the last TX buffer descriptor. */
7362 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7363
7364 DBRUNMSG(BCE_EXTREME_SEND,
7365 bce_dump_tx_chain(sc, debug_prod, nsegs));
7366
7367 /*
7368 * Ensure that the mbuf pointer for this transmission
7369 * is placed at the array index of the last
7370 * descriptor in this chain. This is done
7371 * because a single map is used for all
7372 * segments of the mbuf and we don't want to
7373 * unload the map before all of the segments
7374 * have been freed.
7375 */
7376 sc->tx_mbuf_ptr[chain_prod] = m0;
7377 sc->used_tx_bd += nsegs;
7378
7379 /* Update some debug statistic counters */
7380 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7381 sc->tx_hi_watermark = sc->used_tx_bd);
7382 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7383 DBRUNIF(sc->debug_tx_mbuf_alloc++);
7384
7385 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7386
7387 /* prod points to the next free tx_bd at this point. */
7388 sc->tx_prod = prod;
7389 sc->tx_prod_bseq = prod_bseq;
7390
7391 /* Tell the chip about the waiting TX frames. */
7392 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7393 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7394 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7395 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7396
7397 bce_tx_encap_exit:
7398 DBEXIT(BCE_VERBOSE_SEND);
7399 return(rc);
7400 }
7401
7402 /****************************************************************************/
7403 /* Main transmit routine when called from another routine with a lock. */
7404 /* */
7405 /* Returns: */
7406 /* Nothing. */
7407 /****************************************************************************/
7408 static void
bce_start_locked(if_t ifp)7409 bce_start_locked(if_t ifp)
7410 {
7411 struct bce_softc *sc = if_getsoftc(ifp);
7412 struct mbuf *m_head = NULL;
7413 int count = 0;
7414 u16 tx_prod, tx_chain_prod __unused;
7415
7416 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7417
7418 BCE_LOCK_ASSERT(sc);
7419
7420 /* prod points to the next free tx_bd. */
7421 tx_prod = sc->tx_prod;
7422 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7423
7424 DBPRINT(sc, BCE_INFO_SEND,
7425 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7426 "tx_prod_bseq = 0x%08X\n",
7427 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7428
7429 /* If there's no link or the transmit queue is empty then just exit. */
7430 if (sc->bce_link_up == FALSE) {
7431 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7432 __FUNCTION__);
7433 goto bce_start_locked_exit;
7434 }
7435
7436 if (if_sendq_empty(ifp)) {
7437 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7438 __FUNCTION__);
7439 goto bce_start_locked_exit;
7440 }
7441
7442 /*
7443 * Keep adding entries while there is space in the ring.
7444 */
7445 while (sc->used_tx_bd < sc->max_tx_bd) {
7446 /* Check for any frames to send. */
7447 m_head = if_dequeue(ifp);
7448
7449 /* Stop when the transmit queue is empty. */
7450 if (m_head == NULL)
7451 break;
7452
7453 /*
7454 * Pack the data into the transmit ring. If we
7455 * don't have room, place the mbuf back at the
7456 * head of the queue and set the OACTIVE flag
7457 * to wait for the NIC to drain the chain.
7458 */
7459 if (bce_tx_encap(sc, &m_head)) {
7460 if (m_head != NULL)
7461 if_sendq_prepend(ifp, m_head);
7462 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
7463 DBPRINT(sc, BCE_INFO_SEND,
7464 "TX chain is closed for business! Total "
7465 "tx_bd used = %d\n", sc->used_tx_bd);
7466 break;
7467 }
7468
7469 count++;
7470
7471 /* Send a copy of the frame to any BPF listeners. */
7472 ETHER_BPF_MTAP(ifp, m_head);
7473 }
7474
7475 /* Exit if no packets were dequeued. */
7476 if (count == 0) {
7477 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7478 "dequeued\n", __FUNCTION__);
7479 goto bce_start_locked_exit;
7480 }
7481
7482 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7483 "send queue.\n", __FUNCTION__, count);
7484
7485 /* Set the tx timeout. */
7486 sc->watchdog_timer = BCE_TX_TIMEOUT;
7487
7488 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7489 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7490
7491 bce_start_locked_exit:
7492 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7493 }
7494
7495 /****************************************************************************/
7496 /* Main transmit routine when called from another routine without a lock. */
7497 /* */
7498 /* Returns: */
7499 /* Nothing. */
7500 /****************************************************************************/
7501 static void
bce_start(if_t ifp)7502 bce_start(if_t ifp)
7503 {
7504 struct bce_softc *sc = if_getsoftc(ifp);
7505
7506 DBENTER(BCE_VERBOSE_SEND);
7507
7508 BCE_LOCK(sc);
7509 bce_start_locked(ifp);
7510 BCE_UNLOCK(sc);
7511
7512 DBEXIT(BCE_VERBOSE_SEND);
7513 }
7514
7515 /****************************************************************************/
7516 /* Handles any IOCTL calls from the operating system. */
7517 /* */
7518 /* Returns: */
7519 /* 0 for success, positive value for failure. */
7520 /****************************************************************************/
7521 static int
bce_ioctl(if_t ifp,u_long command,caddr_t data)7522 bce_ioctl(if_t ifp, u_long command, caddr_t data)
7523 {
7524 struct bce_softc *sc = if_getsoftc(ifp);
7525 struct ifreq *ifr = (struct ifreq *) data;
7526 struct mii_data *mii;
7527 int mask, error = 0;
7528
7529 DBENTER(BCE_VERBOSE_MISC);
7530
7531 switch(command) {
7532 /* Set the interface MTU. */
7533 case SIOCSIFMTU:
7534 /* Check that the MTU setting is supported. */
7535 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7536 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7537 error = EINVAL;
7538 break;
7539 }
7540
7541 DBPRINT(sc, BCE_INFO_MISC,
7542 "SIOCSIFMTU: Changing MTU from %d to %d\n",
7543 (int) if_getmtu(ifp), (int) ifr->ifr_mtu);
7544
7545 BCE_LOCK(sc);
7546 if_setmtu(ifp, ifr->ifr_mtu);
7547 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
7548 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
7549 bce_init_locked(sc);
7550 }
7551 BCE_UNLOCK(sc);
7552 break;
7553
7554 /* Set interface flags. */
7555 case SIOCSIFFLAGS:
7556 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7557
7558 BCE_LOCK(sc);
7559
7560 /* Check if the interface is up. */
7561 if (if_getflags(ifp) & IFF_UP) {
7562 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
7563 /* Change promiscuous/multicast flags as necessary. */
7564 bce_set_rx_mode(sc);
7565 } else {
7566 /* Start the HW */
7567 bce_init_locked(sc);
7568 }
7569 } else {
7570 /* The interface is down, check if driver is running. */
7571 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
7572 bce_stop(sc);
7573
7574 /* If MFW is running, restart the controller a bit. */
7575 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7576 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7577 bce_chipinit(sc);
7578 bce_mgmt_init_locked(sc);
7579 }
7580 }
7581 }
7582
7583 BCE_UNLOCK(sc);
7584 break;
7585
7586 /* Add/Delete multicast address */
7587 case SIOCADDMULTI:
7588 case SIOCDELMULTI:
7589 DBPRINT(sc, BCE_VERBOSE_MISC,
7590 "Received SIOCADDMULTI/SIOCDELMULTI\n");
7591
7592 BCE_LOCK(sc);
7593 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
7594 bce_set_rx_mode(sc);
7595 BCE_UNLOCK(sc);
7596
7597 break;
7598
7599 /* Set/Get Interface media */
7600 case SIOCSIFMEDIA:
7601 case SIOCGIFMEDIA:
7602 DBPRINT(sc, BCE_VERBOSE_MISC,
7603 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7604 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7605 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7606 command);
7607 else {
7608 mii = device_get_softc(sc->bce_miibus);
7609 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7610 command);
7611 }
7612 break;
7613
7614 /* Set interface capability */
7615 case SIOCSIFCAP:
7616 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
7617 DBPRINT(sc, BCE_INFO_MISC,
7618 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7619
7620 /* Toggle the TX checksum capabilities enable flag. */
7621 if (mask & IFCAP_TXCSUM &&
7622 if_getcapabilities(ifp) & IFCAP_TXCSUM) {
7623 if_togglecapenable(ifp, IFCAP_TXCSUM);
7624 if (IFCAP_TXCSUM & if_getcapenable(ifp))
7625 if_sethwassistbits(ifp, BCE_IF_HWASSIST, 0);
7626 else
7627 if_sethwassistbits(ifp, 0, BCE_IF_HWASSIST);
7628 }
7629
7630 /* Toggle the RX checksum capabilities enable flag. */
7631 if (mask & IFCAP_RXCSUM &&
7632 if_getcapabilities(ifp) & IFCAP_RXCSUM)
7633 if_togglecapenable(ifp, IFCAP_RXCSUM);
7634
7635 /* Toggle the TSO capabilities enable flag. */
7636 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7637 if_getcapabilities(ifp) & IFCAP_TSO4) {
7638 if_togglecapenable(ifp, IFCAP_TSO4);
7639 if (IFCAP_TSO4 & if_getcapenable(ifp))
7640 if_sethwassistbits(ifp, CSUM_TSO, 0);
7641 else
7642 if_sethwassistbits(ifp, 0, CSUM_TSO);
7643 }
7644
7645 if (mask & IFCAP_VLAN_HWCSUM &&
7646 if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM)
7647 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
7648
7649 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7650 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
7651 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
7652 /*
7653 * Don't actually disable VLAN tag stripping as
7654 * management firmware (ASF/IPMI/UMP) requires the
7655 * feature. If VLAN tag stripping is disabled driver
7656 * will manually reconstruct the VLAN frame by
7657 * appending stripped VLAN tag.
7658 */
7659 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7660 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)) {
7661 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
7662 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
7663 == 0)
7664 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
7665 }
7666 VLAN_CAPABILITIES(ifp);
7667 break;
7668 default:
7669 /* We don't know how to handle the IOCTL, pass it on. */
7670 error = ether_ioctl(ifp, command, data);
7671 break;
7672 }
7673
7674 DBEXIT(BCE_VERBOSE_MISC);
7675 return(error);
7676 }
7677
7678 /****************************************************************************/
7679 /* Transmit timeout handler. */
7680 /* */
7681 /* Returns: */
7682 /* Nothing. */
7683 /****************************************************************************/
7684 static void
bce_watchdog(struct bce_softc * sc)7685 bce_watchdog(struct bce_softc *sc)
7686 {
7687 uint32_t status;
7688
7689 DBENTER(BCE_EXTREME_SEND);
7690
7691 BCE_LOCK_ASSERT(sc);
7692
7693 status = 0;
7694 /* If the watchdog timer hasn't expired then just exit. */
7695 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7696 goto bce_watchdog_exit;
7697
7698 status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7699 /* If pause frames are active then don't reset the hardware. */
7700 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7701 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7702 /*
7703 * If link partner has us in XOFF state then wait for
7704 * the condition to clear.
7705 */
7706 sc->watchdog_timer = BCE_TX_TIMEOUT;
7707 goto bce_watchdog_exit;
7708 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7709 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7710 /*
7711 * If we're not currently XOFF'ed but have recently
7712 * been XOFF'd/XON'd then assume that's delaying TX
7713 * this time around.
7714 */
7715 sc->watchdog_timer = BCE_TX_TIMEOUT;
7716 goto bce_watchdog_exit;
7717 }
7718 /*
7719 * Any other condition is unexpected and the controller
7720 * should be reset.
7721 */
7722 }
7723
7724 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7725 __FILE__, __LINE__);
7726
7727 DBRUNMSG(BCE_INFO,
7728 bce_dump_driver_state(sc);
7729 bce_dump_status_block(sc);
7730 bce_dump_stats_block(sc);
7731 bce_dump_ftqs(sc);
7732 bce_dump_txp_state(sc, 0);
7733 bce_dump_rxp_state(sc, 0);
7734 bce_dump_tpat_state(sc, 0);
7735 bce_dump_cp_state(sc, 0);
7736 bce_dump_com_state(sc, 0));
7737
7738 DBRUN(bce_breakpoint(sc));
7739
7740 if_setdrvflagbits(sc->bce_ifp, 0, IFF_DRV_RUNNING);
7741
7742 bce_init_locked(sc);
7743 sc->watchdog_timeouts++;
7744
7745 bce_watchdog_exit:
7746 REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7747 DBEXIT(BCE_EXTREME_SEND);
7748 }
7749
7750 /*
7751 * Interrupt handler.
7752 */
7753 /****************************************************************************/
7754 /* Main interrupt entry point. Verifies that the controller generated the */
7755 /* interrupt and then calls a separate routine for handle the various */
7756 /* interrupt causes (PHY, TX, RX). */
7757 /* */
7758 /* Returns: */
7759 /* Nothing. */
7760 /****************************************************************************/
7761 static void
bce_intr(void * xsc)7762 bce_intr(void *xsc)
7763 {
7764 struct bce_softc *sc;
7765 if_t ifp;
7766 u32 status_attn_bits;
7767 u16 hw_rx_cons, hw_tx_cons;
7768
7769 sc = xsc;
7770 ifp = sc->bce_ifp;
7771
7772 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7773 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7774 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7775
7776 BCE_LOCK(sc);
7777
7778 DBRUN(sc->interrupts_generated++);
7779
7780 /* Synchnorize before we read from interface's status block */
7781 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7782
7783 /*
7784 * If the hardware status block index matches the last value read
7785 * by the driver and we haven't asserted our interrupt then there's
7786 * nothing to do. This may only happen in case of INTx due to the
7787 * interrupt arriving at the CPU before the status block is updated.
7788 */
7789 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7790 sc->status_block->status_idx == sc->last_status_idx &&
7791 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7792 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7793 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7794 __FUNCTION__);
7795 goto bce_intr_exit;
7796 }
7797
7798 /* Ack the interrupt and stop others from occurring. */
7799 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7800 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7801 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7802
7803 /* Check if the hardware has finished any work. */
7804 hw_rx_cons = bce_get_hw_rx_cons(sc);
7805 hw_tx_cons = bce_get_hw_tx_cons(sc);
7806
7807 /* Keep processing data as long as there is work to do. */
7808 for (;;) {
7809 status_attn_bits = sc->status_block->status_attn_bits;
7810
7811 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7812 BCE_PRINTF("Simulating unexpected status attention "
7813 "bit set.");
7814 sc->unexpected_attention_sim_count++;
7815 status_attn_bits = status_attn_bits |
7816 STATUS_ATTN_BITS_PARITY_ERROR);
7817
7818 /* Was it a link change interrupt? */
7819 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7820 (sc->status_block->status_attn_bits_ack &
7821 STATUS_ATTN_BITS_LINK_STATE)) {
7822 bce_phy_intr(sc);
7823
7824 /* Clear transient updates during link state change. */
7825 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7826 BCE_HC_COMMAND_COAL_NOW_WO_INT);
7827 REG_RD(sc, BCE_HC_COMMAND);
7828 }
7829
7830 /* If any other attention is asserted, the chip is toast. */
7831 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7832 (sc->status_block->status_attn_bits_ack &
7833 ~STATUS_ATTN_BITS_LINK_STATE))) {
7834 sc->unexpected_attention_count++;
7835
7836 BCE_PRINTF("%s(%d): Fatal attention detected: "
7837 "0x%08X\n", __FILE__, __LINE__,
7838 sc->status_block->status_attn_bits);
7839
7840 DBRUNMSG(BCE_FATAL,
7841 if (unexpected_attention_sim_control == 0)
7842 bce_breakpoint(sc));
7843
7844 bce_init_locked(sc);
7845 goto bce_intr_exit;
7846 }
7847
7848 /* Check for any completed RX frames. */
7849 if (hw_rx_cons != sc->hw_rx_cons)
7850 bce_rx_intr(sc);
7851
7852 /* Check for any completed TX frames. */
7853 if (hw_tx_cons != sc->hw_tx_cons)
7854 bce_tx_intr(sc);
7855
7856 /* Save status block index value for the next interrupt. */
7857 sc->last_status_idx = sc->status_block->status_idx;
7858
7859 /*
7860 * Prevent speculative reads from getting
7861 * ahead of the status block.
7862 */
7863 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7864 BUS_SPACE_BARRIER_READ);
7865
7866 /*
7867 * If there's no work left then exit the
7868 * interrupt service routine.
7869 */
7870 hw_rx_cons = bce_get_hw_rx_cons(sc);
7871 hw_tx_cons = bce_get_hw_tx_cons(sc);
7872
7873 if ((hw_rx_cons == sc->hw_rx_cons) &&
7874 (hw_tx_cons == sc->hw_tx_cons))
7875 break;
7876 }
7877
7878 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
7879
7880 /* Re-enable interrupts. */
7881 bce_enable_intr(sc, 0);
7882
7883 /* Handle any frames that arrived while handling the interrupt. */
7884 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
7885 !if_sendq_empty(ifp))
7886 bce_start_locked(ifp);
7887
7888 bce_intr_exit:
7889 BCE_UNLOCK(sc);
7890
7891 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7892 }
7893
7894 /****************************************************************************/
7895 /* Programs the various packet receive modes (broadcast and multicast). */
7896 /* */
7897 /* Returns: */
7898 /* Nothing. */
7899 /****************************************************************************/
7900 static u_int
bce_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)7901 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
7902 {
7903 u32 *hashes = arg;
7904 int h;
7905
7906 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
7907 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
7908
7909 return (1);
7910 }
7911
7912 static void
bce_set_rx_mode(struct bce_softc * sc)7913 bce_set_rx_mode(struct bce_softc *sc)
7914 {
7915 if_t ifp;
7916 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
7917 u32 rx_mode, sort_mode;
7918 int i;
7919
7920 DBENTER(BCE_VERBOSE_MISC);
7921
7922 BCE_LOCK_ASSERT(sc);
7923
7924 ifp = sc->bce_ifp;
7925
7926 /* Initialize receive mode default settings. */
7927 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
7928 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
7929 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
7930
7931 /*
7932 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
7933 * be enbled.
7934 */
7935 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
7936 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
7937 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
7938
7939 /*
7940 * Check for promiscuous, all multicast, or selected
7941 * multicast address filtering.
7942 */
7943 if (if_getflags(ifp) & IFF_PROMISC) {
7944 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
7945
7946 /* Enable promiscuous mode. */
7947 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
7948 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
7949 } else if (if_getflags(ifp) & IFF_ALLMULTI) {
7950 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
7951
7952 /* Enable all multicast addresses. */
7953 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
7954 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
7955 0xffffffff);
7956 }
7957 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
7958 } else {
7959 /* Accept one or more multicast(s). */
7960 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
7961 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes);
7962
7963 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
7964 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
7965
7966 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
7967 }
7968
7969 /* Only make changes if the recive mode has actually changed. */
7970 if (rx_mode != sc->rx_mode) {
7971 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
7972 "0x%08X\n", rx_mode);
7973
7974 sc->rx_mode = rx_mode;
7975 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
7976 }
7977
7978 /* Disable and clear the existing sort before enabling a new sort. */
7979 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
7980 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
7981 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
7982
7983 DBEXIT(BCE_VERBOSE_MISC);
7984 }
7985
7986 /****************************************************************************/
7987 /* Called periodically to updates statistics from the controllers */
7988 /* statistics block. */
7989 /* */
7990 /* Returns: */
7991 /* Nothing. */
7992 /****************************************************************************/
7993 static void
bce_stats_update(struct bce_softc * sc)7994 bce_stats_update(struct bce_softc *sc)
7995 {
7996 struct statistics_block *stats;
7997
7998 DBENTER(BCE_EXTREME_MISC);
7999
8000 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8001
8002 stats = (struct statistics_block *) sc->stats_block;
8003
8004 /*
8005 * Update the sysctl statistics from the
8006 * hardware statistics.
8007 */
8008 sc->stat_IfHCInOctets =
8009 ((u64) stats->stat_IfHCInOctets_hi << 32) +
8010 (u64) stats->stat_IfHCInOctets_lo;
8011
8012 sc->stat_IfHCInBadOctets =
8013 ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8014 (u64) stats->stat_IfHCInBadOctets_lo;
8015
8016 sc->stat_IfHCOutOctets =
8017 ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8018 (u64) stats->stat_IfHCOutOctets_lo;
8019
8020 sc->stat_IfHCOutBadOctets =
8021 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8022 (u64) stats->stat_IfHCOutBadOctets_lo;
8023
8024 sc->stat_IfHCInUcastPkts =
8025 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8026 (u64) stats->stat_IfHCInUcastPkts_lo;
8027
8028 sc->stat_IfHCInMulticastPkts =
8029 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8030 (u64) stats->stat_IfHCInMulticastPkts_lo;
8031
8032 sc->stat_IfHCInBroadcastPkts =
8033 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8034 (u64) stats->stat_IfHCInBroadcastPkts_lo;
8035
8036 sc->stat_IfHCOutUcastPkts =
8037 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8038 (u64) stats->stat_IfHCOutUcastPkts_lo;
8039
8040 sc->stat_IfHCOutMulticastPkts =
8041 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8042 (u64) stats->stat_IfHCOutMulticastPkts_lo;
8043
8044 sc->stat_IfHCOutBroadcastPkts =
8045 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8046 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8047
8048 /* ToDo: Preserve counters beyond 32 bits? */
8049 /* ToDo: Read the statistics from auto-clear regs? */
8050
8051 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8052 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8053
8054 sc->stat_Dot3StatsCarrierSenseErrors =
8055 stats->stat_Dot3StatsCarrierSenseErrors;
8056
8057 sc->stat_Dot3StatsFCSErrors =
8058 stats->stat_Dot3StatsFCSErrors;
8059
8060 sc->stat_Dot3StatsAlignmentErrors =
8061 stats->stat_Dot3StatsAlignmentErrors;
8062
8063 sc->stat_Dot3StatsSingleCollisionFrames =
8064 stats->stat_Dot3StatsSingleCollisionFrames;
8065
8066 sc->stat_Dot3StatsMultipleCollisionFrames =
8067 stats->stat_Dot3StatsMultipleCollisionFrames;
8068
8069 sc->stat_Dot3StatsDeferredTransmissions =
8070 stats->stat_Dot3StatsDeferredTransmissions;
8071
8072 sc->stat_Dot3StatsExcessiveCollisions =
8073 stats->stat_Dot3StatsExcessiveCollisions;
8074
8075 sc->stat_Dot3StatsLateCollisions =
8076 stats->stat_Dot3StatsLateCollisions;
8077
8078 sc->stat_EtherStatsCollisions =
8079 stats->stat_EtherStatsCollisions;
8080
8081 sc->stat_EtherStatsFragments =
8082 stats->stat_EtherStatsFragments;
8083
8084 sc->stat_EtherStatsJabbers =
8085 stats->stat_EtherStatsJabbers;
8086
8087 sc->stat_EtherStatsUndersizePkts =
8088 stats->stat_EtherStatsUndersizePkts;
8089
8090 sc->stat_EtherStatsOversizePkts =
8091 stats->stat_EtherStatsOversizePkts;
8092
8093 sc->stat_EtherStatsPktsRx64Octets =
8094 stats->stat_EtherStatsPktsRx64Octets;
8095
8096 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8097 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8098
8099 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8100 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8101
8102 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8103 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8104
8105 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8106 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8107
8108 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8109 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8110
8111 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8112 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8113
8114 sc->stat_EtherStatsPktsTx64Octets =
8115 stats->stat_EtherStatsPktsTx64Octets;
8116
8117 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8118 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8119
8120 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8121 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8122
8123 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8124 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8125
8126 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8127 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8128
8129 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8130 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8131
8132 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8133 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8134
8135 sc->stat_XonPauseFramesReceived =
8136 stats->stat_XonPauseFramesReceived;
8137
8138 sc->stat_XoffPauseFramesReceived =
8139 stats->stat_XoffPauseFramesReceived;
8140
8141 sc->stat_OutXonSent =
8142 stats->stat_OutXonSent;
8143
8144 sc->stat_OutXoffSent =
8145 stats->stat_OutXoffSent;
8146
8147 sc->stat_FlowControlDone =
8148 stats->stat_FlowControlDone;
8149
8150 sc->stat_MacControlFramesReceived =
8151 stats->stat_MacControlFramesReceived;
8152
8153 sc->stat_XoffStateEntered =
8154 stats->stat_XoffStateEntered;
8155
8156 sc->stat_IfInFramesL2FilterDiscards =
8157 stats->stat_IfInFramesL2FilterDiscards;
8158
8159 sc->stat_IfInRuleCheckerDiscards =
8160 stats->stat_IfInRuleCheckerDiscards;
8161
8162 sc->stat_IfInFTQDiscards =
8163 stats->stat_IfInFTQDiscards;
8164
8165 sc->stat_IfInMBUFDiscards =
8166 stats->stat_IfInMBUFDiscards;
8167
8168 sc->stat_IfInRuleCheckerP4Hit =
8169 stats->stat_IfInRuleCheckerP4Hit;
8170
8171 sc->stat_CatchupInRuleCheckerDiscards =
8172 stats->stat_CatchupInRuleCheckerDiscards;
8173
8174 sc->stat_CatchupInFTQDiscards =
8175 stats->stat_CatchupInFTQDiscards;
8176
8177 sc->stat_CatchupInMBUFDiscards =
8178 stats->stat_CatchupInMBUFDiscards;
8179
8180 sc->stat_CatchupInRuleCheckerP4Hit =
8181 stats->stat_CatchupInRuleCheckerP4Hit;
8182
8183 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8184
8185 /* ToDo: Add additional statistics? */
8186
8187 DBEXIT(BCE_EXTREME_MISC);
8188 }
8189
8190 static uint64_t
bce_get_counter(if_t ifp,ift_counter cnt)8191 bce_get_counter(if_t ifp, ift_counter cnt)
8192 {
8193 struct bce_softc *sc;
8194 uint64_t rv;
8195
8196 sc = if_getsoftc(ifp);
8197
8198 switch (cnt) {
8199 case IFCOUNTER_COLLISIONS:
8200 return (sc->stat_EtherStatsCollisions);
8201 case IFCOUNTER_IERRORS:
8202 return (sc->stat_EtherStatsUndersizePkts +
8203 sc->stat_EtherStatsOversizePkts +
8204 sc->stat_IfInMBUFDiscards +
8205 sc->stat_Dot3StatsAlignmentErrors +
8206 sc->stat_Dot3StatsFCSErrors +
8207 sc->stat_IfInRuleCheckerDiscards +
8208 sc->stat_IfInFTQDiscards +
8209 sc->l2fhdr_error_count +
8210 sc->com_no_buffers);
8211 case IFCOUNTER_OERRORS:
8212 rv = sc->stat_Dot3StatsExcessiveCollisions +
8213 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8214 sc->stat_Dot3StatsLateCollisions +
8215 sc->watchdog_timeouts;
8216 /*
8217 * Certain controllers don't report
8218 * carrier sense errors correctly.
8219 * See errata E11_5708CA0_1165.
8220 */
8221 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8222 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8223 rv += sc->stat_Dot3StatsCarrierSenseErrors;
8224 return (rv);
8225 default:
8226 return (if_get_counter_default(ifp, cnt));
8227 }
8228 }
8229
8230 /****************************************************************************/
8231 /* Periodic function to notify the bootcode that the driver is still */
8232 /* present. */
8233 /* */
8234 /* Returns: */
8235 /* Nothing. */
8236 /****************************************************************************/
8237 static void
bce_pulse(void * xsc)8238 bce_pulse(void *xsc)
8239 {
8240 struct bce_softc *sc = xsc;
8241 u32 msg;
8242
8243 DBENTER(BCE_EXTREME_MISC);
8244
8245 BCE_LOCK_ASSERT(sc);
8246
8247 /* Tell the firmware that the driver is still running. */
8248 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8249 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8250
8251 /* Update the bootcode condition. */
8252 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8253
8254 /* Report whether the bootcode still knows the driver is running. */
8255 if (bce_verbose || bootverbose) {
8256 if (sc->bce_drv_cardiac_arrest == FALSE) {
8257 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8258 sc->bce_drv_cardiac_arrest = TRUE;
8259 BCE_PRINTF("%s(): Warning: bootcode "
8260 "thinks driver is absent! "
8261 "(bc_state = 0x%08X)\n",
8262 __FUNCTION__, sc->bc_state);
8263 }
8264 } else {
8265 /*
8266 * Not supported by all bootcode versions.
8267 * (v5.0.11+ and v5.2.1+) Older bootcode
8268 * will require the driver to reset the
8269 * controller to clear this condition.
8270 */
8271 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8272 sc->bce_drv_cardiac_arrest = FALSE;
8273 BCE_PRINTF("%s(): Bootcode found the "
8274 "driver pulse! (bc_state = 0x%08X)\n",
8275 __FUNCTION__, sc->bc_state);
8276 }
8277 }
8278 }
8279
8280 /* Schedule the next pulse. */
8281 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8282
8283 DBEXIT(BCE_EXTREME_MISC);
8284 }
8285
8286 /****************************************************************************/
8287 /* Periodic function to perform maintenance tasks. */
8288 /* */
8289 /* Returns: */
8290 /* Nothing. */
8291 /****************************************************************************/
8292 static void
bce_tick(void * xsc)8293 bce_tick(void *xsc)
8294 {
8295 struct bce_softc *sc = xsc;
8296 struct mii_data *mii;
8297 if_t ifp;
8298 struct ifmediareq ifmr;
8299
8300 ifp = sc->bce_ifp;
8301
8302 DBENTER(BCE_EXTREME_MISC);
8303
8304 BCE_LOCK_ASSERT(sc);
8305
8306 /* Schedule the next tick. */
8307 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8308
8309 /* Update the statistics from the hardware statistics block. */
8310 bce_stats_update(sc);
8311
8312 /* Ensure page and RX chains get refilled in low-memory situations. */
8313 if (bce_hdr_split == TRUE)
8314 bce_fill_pg_chain(sc);
8315 bce_fill_rx_chain(sc);
8316
8317 /* Check that chip hasn't hung. */
8318 bce_watchdog(sc);
8319
8320 /* If link is up already up then we're done. */
8321 if (sc->bce_link_up == TRUE)
8322 goto bce_tick_exit;
8323
8324 /* Link is down. Check what the PHY's doing. */
8325 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8326 bzero(&ifmr, sizeof(ifmr));
8327 bce_ifmedia_sts_rphy(sc, &ifmr);
8328 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8329 (IFM_ACTIVE | IFM_AVALID)) {
8330 sc->bce_link_up = TRUE;
8331 bce_miibus_statchg(sc->bce_dev);
8332 }
8333 } else {
8334 mii = device_get_softc(sc->bce_miibus);
8335 mii_tick(mii);
8336 /* Check if the link has come up. */
8337 if ((mii->mii_media_status & IFM_ACTIVE) &&
8338 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8339 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8340 __FUNCTION__);
8341 sc->bce_link_up = TRUE;
8342 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8343 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8344 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8345 (bce_verbose || bootverbose))
8346 BCE_PRINTF("Gigabit link up!\n");
8347 }
8348 }
8349 if (sc->bce_link_up == TRUE) {
8350 /* Now that link is up, handle any outstanding TX traffic. */
8351 if (!if_sendq_empty(ifp)) {
8352 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8353 "pending TX traffic.\n", __FUNCTION__);
8354 bce_start_locked(ifp);
8355 }
8356 }
8357
8358 bce_tick_exit:
8359 DBEXIT(BCE_EXTREME_MISC);
8360 }
8361
8362 static void
bce_fw_cap_init(struct bce_softc * sc)8363 bce_fw_cap_init(struct bce_softc *sc)
8364 {
8365 u32 ack, cap, link;
8366
8367 ack = 0;
8368 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8369 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8370 BCE_FW_CAP_SIGNATURE_MAGIC)
8371 return;
8372 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8373 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8374 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8375 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8376 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8377 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8378 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8379 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8380 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8381 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8382 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8383 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8384 BCE_FW_CAP_REMOTE_PHY_CAP;
8385 }
8386
8387 if (ack != 0)
8388 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8389 }
8390
8391 #ifdef BCE_DEBUG
8392 /****************************************************************************/
8393 /* Allows the driver state to be dumped through the sysctl interface. */
8394 /* */
8395 /* Returns: */
8396 /* 0 for success, positive value for failure. */
8397 /****************************************************************************/
8398 static int
bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)8399 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8400 {
8401 int error;
8402 int result;
8403 struct bce_softc *sc;
8404
8405 result = -1;
8406 error = sysctl_handle_int(oidp, &result, 0, req);
8407
8408 if (error || !req->newptr)
8409 return (error);
8410
8411 if (result == 1) {
8412 sc = (struct bce_softc *)arg1;
8413 bce_dump_driver_state(sc);
8414 }
8415
8416 return error;
8417 }
8418
8419 /****************************************************************************/
8420 /* Allows the hardware state to be dumped through the sysctl interface. */
8421 /* */
8422 /* Returns: */
8423 /* 0 for success, positive value for failure. */
8424 /****************************************************************************/
8425 static int
bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)8426 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8427 {
8428 int error;
8429 int result;
8430 struct bce_softc *sc;
8431
8432 result = -1;
8433 error = sysctl_handle_int(oidp, &result, 0, req);
8434
8435 if (error || !req->newptr)
8436 return (error);
8437
8438 if (result == 1) {
8439 sc = (struct bce_softc *)arg1;
8440 bce_dump_hw_state(sc);
8441 }
8442
8443 return error;
8444 }
8445
8446 /****************************************************************************/
8447 /* Allows the status block to be dumped through the sysctl interface. */
8448 /* */
8449 /* Returns: */
8450 /* 0 for success, positive value for failure. */
8451 /****************************************************************************/
8452 static int
bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)8453 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8454 {
8455 int error;
8456 int result;
8457 struct bce_softc *sc;
8458
8459 result = -1;
8460 error = sysctl_handle_int(oidp, &result, 0, req);
8461
8462 if (error || !req->newptr)
8463 return (error);
8464
8465 if (result == 1) {
8466 sc = (struct bce_softc *)arg1;
8467 bce_dump_status_block(sc);
8468 }
8469
8470 return error;
8471 }
8472
8473 /****************************************************************************/
8474 /* Allows the stats block to be dumped through the sysctl interface. */
8475 /* */
8476 /* Returns: */
8477 /* 0 for success, positive value for failure. */
8478 /****************************************************************************/
8479 static int
bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)8480 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8481 {
8482 int error;
8483 int result;
8484 struct bce_softc *sc;
8485
8486 result = -1;
8487 error = sysctl_handle_int(oidp, &result, 0, req);
8488
8489 if (error || !req->newptr)
8490 return (error);
8491
8492 if (result == 1) {
8493 sc = (struct bce_softc *)arg1;
8494 bce_dump_stats_block(sc);
8495 }
8496
8497 return error;
8498 }
8499
8500 /****************************************************************************/
8501 /* Allows the stat counters to be cleared without unloading/reloading the */
8502 /* driver. */
8503 /* */
8504 /* Returns: */
8505 /* 0 for success, positive value for failure. */
8506 /****************************************************************************/
8507 static int
bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)8508 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8509 {
8510 int error;
8511 int result;
8512 struct bce_softc *sc;
8513
8514 result = -1;
8515 error = sysctl_handle_int(oidp, &result, 0, req);
8516
8517 if (error || !req->newptr)
8518 return (error);
8519
8520 if (result == 1) {
8521 sc = (struct bce_softc *)arg1;
8522 struct statistics_block *stats;
8523
8524 stats = (struct statistics_block *) sc->stats_block;
8525 bzero(stats, sizeof(struct statistics_block));
8526 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8528
8529 /* Clear the internal H/W statistics counters. */
8530 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8531
8532 /* Reset the driver maintained statistics. */
8533 sc->interrupts_rx =
8534 sc->interrupts_tx = 0;
8535 sc->tso_frames_requested =
8536 sc->tso_frames_completed =
8537 sc->tso_frames_failed = 0;
8538 sc->rx_empty_count =
8539 sc->tx_full_count = 0;
8540 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8541 sc->tx_hi_watermark = 0;
8542 sc->l2fhdr_error_count =
8543 sc->l2fhdr_error_sim_count = 0;
8544 sc->mbuf_alloc_failed_count =
8545 sc->mbuf_alloc_failed_sim_count = 0;
8546 sc->dma_map_addr_rx_failed_count =
8547 sc->dma_map_addr_tx_failed_count = 0;
8548 sc->mbuf_frag_count = 0;
8549 sc->csum_offload_tcp_udp =
8550 sc->csum_offload_ip = 0;
8551 sc->vlan_tagged_frames_rcvd =
8552 sc->vlan_tagged_frames_stripped = 0;
8553 sc->split_header_frames_rcvd =
8554 sc->split_header_tcp_frames_rcvd = 0;
8555
8556 /* Clear firmware maintained statistics. */
8557 REG_WR_IND(sc, 0x120084, 0);
8558 }
8559
8560 return error;
8561 }
8562
8563 /****************************************************************************/
8564 /* Allows the shared memory contents to be dumped through the sysctl . */
8565 /* interface. */
8566 /* */
8567 /* Returns: */
8568 /* 0 for success, positive value for failure. */
8569 /****************************************************************************/
8570 static int
bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)8571 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8572 {
8573 int error;
8574 int result;
8575 struct bce_softc *sc;
8576
8577 result = -1;
8578 error = sysctl_handle_int(oidp, &result, 0, req);
8579
8580 if (error || !req->newptr)
8581 return (error);
8582
8583 if (result == 1) {
8584 sc = (struct bce_softc *)arg1;
8585 bce_dump_shmem_state(sc);
8586 }
8587
8588 return error;
8589 }
8590
8591 /****************************************************************************/
8592 /* Allows the bootcode state to be dumped through the sysctl interface. */
8593 /* */
8594 /* Returns: */
8595 /* 0 for success, positive value for failure. */
8596 /****************************************************************************/
8597 static int
bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)8598 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8599 {
8600 int error;
8601 int result;
8602 struct bce_softc *sc;
8603
8604 result = -1;
8605 error = sysctl_handle_int(oidp, &result, 0, req);
8606
8607 if (error || !req->newptr)
8608 return (error);
8609
8610 if (result == 1) {
8611 sc = (struct bce_softc *)arg1;
8612 bce_dump_bc_state(sc);
8613 }
8614
8615 return error;
8616 }
8617
8618 /****************************************************************************/
8619 /* Provides a sysctl interface to allow dumping the RX BD chain. */
8620 /* */
8621 /* Returns: */
8622 /* 0 for success, positive value for failure. */
8623 /****************************************************************************/
8624 static int
bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)8625 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8626 {
8627 int error;
8628 int result;
8629 struct bce_softc *sc;
8630
8631 result = -1;
8632 error = sysctl_handle_int(oidp, &result, 0, req);
8633
8634 if (error || !req->newptr)
8635 return (error);
8636
8637 if (result == 1) {
8638 sc = (struct bce_softc *)arg1;
8639 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8640 }
8641
8642 return error;
8643 }
8644
8645 /****************************************************************************/
8646 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */
8647 /* */
8648 /* Returns: */
8649 /* 0 for success, positive value for failure. */
8650 /****************************************************************************/
8651 static int
bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)8652 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8653 {
8654 int error;
8655 int result;
8656 struct bce_softc *sc;
8657
8658 result = -1;
8659 error = sysctl_handle_int(oidp, &result, 0, req);
8660
8661 if (error || !req->newptr)
8662 return (error);
8663
8664 if (result == 1) {
8665 sc = (struct bce_softc *)arg1;
8666 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8667 }
8668
8669 return error;
8670 }
8671
8672 /****************************************************************************/
8673 /* Provides a sysctl interface to allow dumping the TX chain. */
8674 /* */
8675 /* Returns: */
8676 /* 0 for success, positive value for failure. */
8677 /****************************************************************************/
8678 static int
bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)8679 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8680 {
8681 int error;
8682 int result;
8683 struct bce_softc *sc;
8684
8685 result = -1;
8686 error = sysctl_handle_int(oidp, &result, 0, req);
8687
8688 if (error || !req->newptr)
8689 return (error);
8690
8691 if (result == 1) {
8692 sc = (struct bce_softc *)arg1;
8693 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8694 }
8695
8696 return error;
8697 }
8698
8699 /****************************************************************************/
8700 /* Provides a sysctl interface to allow dumping the page chain. */
8701 /* */
8702 /* Returns: */
8703 /* 0 for success, positive value for failure. */
8704 /****************************************************************************/
8705 static int
bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)8706 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8707 {
8708 int error;
8709 int result;
8710 struct bce_softc *sc;
8711
8712 result = -1;
8713 error = sysctl_handle_int(oidp, &result, 0, req);
8714
8715 if (error || !req->newptr)
8716 return (error);
8717
8718 if (result == 1) {
8719 sc = (struct bce_softc *)arg1;
8720 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8721 }
8722
8723 return error;
8724 }
8725
8726 /****************************************************************************/
8727 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */
8728 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8729 /* */
8730 /* Returns: */
8731 /* 0 for success, positive value for failure. */
8732 /****************************************************************************/
8733 static int
bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)8734 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8735 {
8736 struct bce_softc *sc = (struct bce_softc *)arg1;
8737 int error;
8738 u32 result;
8739 u32 val[1];
8740 u8 *data = (u8 *) val;
8741
8742 result = -1;
8743 error = sysctl_handle_int(oidp, &result, 0, req);
8744 if (error || (req->newptr == NULL))
8745 return (error);
8746
8747 error = bce_nvram_read(sc, result, data, 4);
8748
8749 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8750
8751 return (error);
8752 }
8753
8754 /****************************************************************************/
8755 /* Provides a sysctl interface to allow reading arbitrary registers in the */
8756 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8757 /* */
8758 /* Returns: */
8759 /* 0 for success, positive value for failure. */
8760 /****************************************************************************/
8761 static int
bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)8762 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8763 {
8764 struct bce_softc *sc = (struct bce_softc *)arg1;
8765 int error;
8766 u32 val, result;
8767
8768 result = -1;
8769 error = sysctl_handle_int(oidp, &result, 0, req);
8770 if (error || (req->newptr == NULL))
8771 return (error);
8772
8773 /* Make sure the register is accessible. */
8774 if (result < 0x8000) {
8775 val = REG_RD(sc, result);
8776 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8777 } else if (result < 0x0280000) {
8778 val = REG_RD_IND(sc, result);
8779 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8780 }
8781
8782 return (error);
8783 }
8784
8785 /****************************************************************************/
8786 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
8787 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8788 /* */
8789 /* Returns: */
8790 /* 0 for success, positive value for failure. */
8791 /****************************************************************************/
8792 static int
bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)8793 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8794 {
8795 struct bce_softc *sc;
8796 device_t dev;
8797 int error, result;
8798 u16 val;
8799
8800 result = -1;
8801 error = sysctl_handle_int(oidp, &result, 0, req);
8802 if (error || (req->newptr == NULL))
8803 return (error);
8804
8805 /* Make sure the register is accessible. */
8806 if (result < 0x20) {
8807 sc = (struct bce_softc *)arg1;
8808 dev = sc->bce_dev;
8809 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8810 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8811 }
8812 return (error);
8813 }
8814
8815 /****************************************************************************/
8816 /* Provides a sysctl interface for dumping the nvram contents. */
8817 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8818 /* */
8819 /* Returns: */
8820 /* 0 for success, positive errno for failure. */
8821 /****************************************************************************/
8822 static int
bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)8823 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
8824 {
8825 struct bce_softc *sc = (struct bce_softc *)arg1;
8826 int error, i;
8827
8828 if (sc->nvram_buf == NULL)
8829 sc->nvram_buf = malloc(sc->bce_flash_size,
8830 M_TEMP, M_ZERO | M_WAITOK);
8831
8832 error = 0;
8833 if (req->oldlen == sc->bce_flash_size) {
8834 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
8835 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
8836 }
8837
8838 if (error == 0)
8839 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
8840
8841 return error;
8842 }
8843
8844 #ifdef BCE_NVRAM_WRITE_SUPPORT
8845 /****************************************************************************/
8846 /* Provides a sysctl interface for writing to nvram. */
8847 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8848 /* */
8849 /* Returns: */
8850 /* 0 for success, positive errno for failure. */
8851 /****************************************************************************/
8852 static int
bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)8853 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
8854 {
8855 struct bce_softc *sc = (struct bce_softc *)arg1;
8856 int error;
8857
8858 if (sc->nvram_buf == NULL)
8859 sc->nvram_buf = malloc(sc->bce_flash_size,
8860 M_TEMP, M_ZERO | M_WAITOK);
8861 else
8862 bzero(sc->nvram_buf, sc->bce_flash_size);
8863
8864 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
8865 if (error == 0)
8866 return (error);
8867
8868 if (req->newlen == sc->bce_flash_size)
8869 error = bce_nvram_write(sc, 0, sc->nvram_buf,
8870 sc->bce_flash_size);
8871
8872 return error;
8873 }
8874 #endif
8875
8876 /****************************************************************************/
8877 /* Provides a sysctl interface to allow reading a CID. */
8878 /* */
8879 /* Returns: */
8880 /* 0 for success, positive value for failure. */
8881 /****************************************************************************/
8882 static int
bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)8883 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
8884 {
8885 struct bce_softc *sc;
8886 int error, result;
8887
8888 result = -1;
8889 error = sysctl_handle_int(oidp, &result, 0, req);
8890 if (error || (req->newptr == NULL))
8891 return (error);
8892
8893 /* Make sure the register is accessible. */
8894 if (result <= TX_CID) {
8895 sc = (struct bce_softc *)arg1;
8896 bce_dump_ctx(sc, result);
8897 }
8898
8899 return (error);
8900 }
8901
8902 /****************************************************************************/
8903 /* Provides a sysctl interface to forcing the driver to dump state and */
8904 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8905 /* */
8906 /* Returns: */
8907 /* 0 for success, positive value for failure. */
8908 /****************************************************************************/
8909 static int
bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)8910 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
8911 {
8912 int error;
8913 int result;
8914 struct bce_softc *sc;
8915
8916 result = -1;
8917 error = sysctl_handle_int(oidp, &result, 0, req);
8918
8919 if (error || !req->newptr)
8920 return (error);
8921
8922 if (result == 1) {
8923 sc = (struct bce_softc *)arg1;
8924 bce_breakpoint(sc);
8925 }
8926
8927 return error;
8928 }
8929 #endif
8930
8931 /****************************************************************************/
8932 /* Adds any sysctl parameters for tuning or debugging purposes. */
8933 /* */
8934 /* Returns: */
8935 /* 0 for success, positive value for failure. */
8936 /****************************************************************************/
8937 static void
bce_add_sysctls(struct bce_softc * sc)8938 bce_add_sysctls(struct bce_softc *sc)
8939 {
8940 struct sysctl_ctx_list *ctx;
8941 struct sysctl_oid_list *children;
8942
8943 DBENTER(BCE_VERBOSE_MISC);
8944
8945 ctx = device_get_sysctl_ctx(sc->bce_dev);
8946 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
8947
8948 #ifdef BCE_DEBUG
8949 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8950 "l2fhdr_error_sim_control",
8951 CTLFLAG_RW, &l2fhdr_error_sim_control,
8952 0, "Debug control to force l2fhdr errors");
8953
8954 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8955 "l2fhdr_error_sim_count",
8956 CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
8957 0, "Number of simulated l2_fhdr errors");
8958 #endif
8959
8960 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8961 "l2fhdr_error_count",
8962 CTLFLAG_RD, &sc->l2fhdr_error_count,
8963 0, "Number of l2_fhdr errors");
8964
8965 #ifdef BCE_DEBUG
8966 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8967 "mbuf_alloc_failed_sim_control",
8968 CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
8969 0, "Debug control to force mbuf allocation failures");
8970
8971 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8972 "mbuf_alloc_failed_sim_count",
8973 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
8974 0, "Number of simulated mbuf cluster allocation failures");
8975 #endif
8976
8977 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8978 "mbuf_alloc_failed_count",
8979 CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
8980 0, "Number of mbuf allocation failures");
8981
8982 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8983 "mbuf_frag_count",
8984 CTLFLAG_RD, &sc->mbuf_frag_count,
8985 0, "Number of fragmented mbufs");
8986
8987 #ifdef BCE_DEBUG
8988 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8989 "dma_map_addr_failed_sim_control",
8990 CTLFLAG_RW, &dma_map_addr_failed_sim_control,
8991 0, "Debug control to force DMA mapping failures");
8992
8993 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
8994 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8995 "dma_map_addr_failed_sim_count",
8996 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
8997 0, "Number of simulated DMA mapping failures");
8998
8999 #endif
9000
9001 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9002 "dma_map_addr_rx_failed_count",
9003 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9004 0, "Number of RX DMA mapping failures");
9005
9006 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9007 "dma_map_addr_tx_failed_count",
9008 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9009 0, "Number of TX DMA mapping failures");
9010
9011 #ifdef BCE_DEBUG
9012 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9013 "unexpected_attention_sim_control",
9014 CTLFLAG_RW, &unexpected_attention_sim_control,
9015 0, "Debug control to simulate unexpected attentions");
9016
9017 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9018 "unexpected_attention_sim_count",
9019 CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9020 0, "Number of simulated unexpected attentions");
9021 #endif
9022
9023 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9024 "unexpected_attention_count",
9025 CTLFLAG_RW, &sc->unexpected_attention_count,
9026 0, "Number of unexpected attentions");
9027
9028 #ifdef BCE_DEBUG
9029 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9030 "debug_bootcode_running_failure",
9031 CTLFLAG_RW, &bootcode_running_failure_sim_control,
9032 0, "Debug control to force bootcode running failures");
9033
9034 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9035 "rx_low_watermark",
9036 CTLFLAG_RD, &sc->rx_low_watermark,
9037 0, "Lowest level of free rx_bd's");
9038
9039 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9040 "rx_empty_count",
9041 CTLFLAG_RD, &sc->rx_empty_count,
9042 "Number of times the RX chain was empty");
9043
9044 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9045 "tx_hi_watermark",
9046 CTLFLAG_RD, &sc->tx_hi_watermark,
9047 0, "Highest level of used tx_bd's");
9048
9049 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9050 "tx_full_count",
9051 CTLFLAG_RD, &sc->tx_full_count,
9052 "Number of times the TX chain was full");
9053
9054 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9055 "tso_frames_requested",
9056 CTLFLAG_RD, &sc->tso_frames_requested,
9057 "Number of TSO frames requested");
9058
9059 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9060 "tso_frames_completed",
9061 CTLFLAG_RD, &sc->tso_frames_completed,
9062 "Number of TSO frames completed");
9063
9064 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9065 "tso_frames_failed",
9066 CTLFLAG_RD, &sc->tso_frames_failed,
9067 "Number of TSO frames failed");
9068
9069 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9070 "csum_offload_ip",
9071 CTLFLAG_RD, &sc->csum_offload_ip,
9072 "Number of IP checksum offload frames");
9073
9074 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9075 "csum_offload_tcp_udp",
9076 CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9077 "Number of TCP/UDP checksum offload frames");
9078
9079 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9080 "vlan_tagged_frames_rcvd",
9081 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9082 "Number of VLAN tagged frames received");
9083
9084 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9085 "vlan_tagged_frames_stripped",
9086 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9087 "Number of VLAN tagged frames stripped");
9088
9089 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9090 "interrupts_rx",
9091 CTLFLAG_RD, &sc->interrupts_rx,
9092 "Number of RX interrupts");
9093
9094 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9095 "interrupts_tx",
9096 CTLFLAG_RD, &sc->interrupts_tx,
9097 "Number of TX interrupts");
9098
9099 if (bce_hdr_split == TRUE) {
9100 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9101 "split_header_frames_rcvd",
9102 CTLFLAG_RD, &sc->split_header_frames_rcvd,
9103 "Number of split header frames received");
9104
9105 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9106 "split_header_tcp_frames_rcvd",
9107 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9108 "Number of split header TCP frames received");
9109 }
9110
9111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9112 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
9113 (void *)sc, 0,
9114 bce_sysctl_nvram_dump, "S", "");
9115
9116 #ifdef BCE_NVRAM_WRITE_SUPPORT
9117 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9118 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT,
9119 (void *)sc, 0,
9120 bce_sysctl_nvram_write, "S", "");
9121 #endif
9122 #endif /* BCE_DEBUG */
9123
9124 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9125 "stat_IfHcInOctets",
9126 CTLFLAG_RD, &sc->stat_IfHCInOctets,
9127 "Bytes received");
9128
9129 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9130 "stat_IfHCInBadOctets",
9131 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9132 "Bad bytes received");
9133
9134 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9135 "stat_IfHCOutOctets",
9136 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9137 "Bytes sent");
9138
9139 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9140 "stat_IfHCOutBadOctets",
9141 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9142 "Bad bytes sent");
9143
9144 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9145 "stat_IfHCInUcastPkts",
9146 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9147 "Unicast packets received");
9148
9149 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9150 "stat_IfHCInMulticastPkts",
9151 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9152 "Multicast packets received");
9153
9154 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9155 "stat_IfHCInBroadcastPkts",
9156 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9157 "Broadcast packets received");
9158
9159 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9160 "stat_IfHCOutUcastPkts",
9161 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9162 "Unicast packets sent");
9163
9164 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9165 "stat_IfHCOutMulticastPkts",
9166 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9167 "Multicast packets sent");
9168
9169 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9170 "stat_IfHCOutBroadcastPkts",
9171 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9172 "Broadcast packets sent");
9173
9174 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9175 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9176 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9177 0, "Internal MAC transmit errors");
9178
9179 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9180 "stat_Dot3StatsCarrierSenseErrors",
9181 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9182 0, "Carrier sense errors");
9183
9184 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9185 "stat_Dot3StatsFCSErrors",
9186 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9187 0, "Frame check sequence errors");
9188
9189 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9190 "stat_Dot3StatsAlignmentErrors",
9191 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9192 0, "Alignment errors");
9193
9194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9195 "stat_Dot3StatsSingleCollisionFrames",
9196 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9197 0, "Single Collision Frames");
9198
9199 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9200 "stat_Dot3StatsMultipleCollisionFrames",
9201 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9202 0, "Multiple Collision Frames");
9203
9204 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9205 "stat_Dot3StatsDeferredTransmissions",
9206 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9207 0, "Deferred Transmissions");
9208
9209 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9210 "stat_Dot3StatsExcessiveCollisions",
9211 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9212 0, "Excessive Collisions");
9213
9214 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9215 "stat_Dot3StatsLateCollisions",
9216 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9217 0, "Late Collisions");
9218
9219 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9220 "stat_EtherStatsCollisions",
9221 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9222 0, "Collisions");
9223
9224 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9225 "stat_EtherStatsFragments",
9226 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9227 0, "Fragments");
9228
9229 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9230 "stat_EtherStatsJabbers",
9231 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9232 0, "Jabbers");
9233
9234 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9235 "stat_EtherStatsUndersizePkts",
9236 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9237 0, "Undersize packets");
9238
9239 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9240 "stat_EtherStatsOversizePkts",
9241 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9242 0, "stat_EtherStatsOversizePkts");
9243
9244 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9245 "stat_EtherStatsPktsRx64Octets",
9246 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9247 0, "Bytes received in 64 byte packets");
9248
9249 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9250 "stat_EtherStatsPktsRx65Octetsto127Octets",
9251 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9252 0, "Bytes received in 65 to 127 byte packets");
9253
9254 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9255 "stat_EtherStatsPktsRx128Octetsto255Octets",
9256 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9257 0, "Bytes received in 128 to 255 byte packets");
9258
9259 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9260 "stat_EtherStatsPktsRx256Octetsto511Octets",
9261 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9262 0, "Bytes received in 256 to 511 byte packets");
9263
9264 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9265 "stat_EtherStatsPktsRx512Octetsto1023Octets",
9266 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9267 0, "Bytes received in 512 to 1023 byte packets");
9268
9269 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9270 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9271 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9272 0, "Bytes received in 1024 t0 1522 byte packets");
9273
9274 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9275 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9276 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9277 0, "Bytes received in 1523 to 9022 byte packets");
9278
9279 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9280 "stat_EtherStatsPktsTx64Octets",
9281 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9282 0, "Bytes sent in 64 byte packets");
9283
9284 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9285 "stat_EtherStatsPktsTx65Octetsto127Octets",
9286 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9287 0, "Bytes sent in 65 to 127 byte packets");
9288
9289 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9290 "stat_EtherStatsPktsTx128Octetsto255Octets",
9291 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9292 0, "Bytes sent in 128 to 255 byte packets");
9293
9294 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9295 "stat_EtherStatsPktsTx256Octetsto511Octets",
9296 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9297 0, "Bytes sent in 256 to 511 byte packets");
9298
9299 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9300 "stat_EtherStatsPktsTx512Octetsto1023Octets",
9301 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9302 0, "Bytes sent in 512 to 1023 byte packets");
9303
9304 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9305 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9306 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9307 0, "Bytes sent in 1024 to 1522 byte packets");
9308
9309 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9310 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9311 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9312 0, "Bytes sent in 1523 to 9022 byte packets");
9313
9314 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9315 "stat_XonPauseFramesReceived",
9316 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9317 0, "XON pause frames receved");
9318
9319 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9320 "stat_XoffPauseFramesReceived",
9321 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9322 0, "XOFF pause frames received");
9323
9324 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9325 "stat_OutXonSent",
9326 CTLFLAG_RD, &sc->stat_OutXonSent,
9327 0, "XON pause frames sent");
9328
9329 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9330 "stat_OutXoffSent",
9331 CTLFLAG_RD, &sc->stat_OutXoffSent,
9332 0, "XOFF pause frames sent");
9333
9334 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9335 "stat_FlowControlDone",
9336 CTLFLAG_RD, &sc->stat_FlowControlDone,
9337 0, "Flow control done");
9338
9339 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9340 "stat_MacControlFramesReceived",
9341 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9342 0, "MAC control frames received");
9343
9344 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9345 "stat_XoffStateEntered",
9346 CTLFLAG_RD, &sc->stat_XoffStateEntered,
9347 0, "XOFF state entered");
9348
9349 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9350 "stat_IfInFramesL2FilterDiscards",
9351 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9352 0, "Received L2 packets discarded");
9353
9354 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9355 "stat_IfInRuleCheckerDiscards",
9356 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9357 0, "Received packets discarded by rule");
9358
9359 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9360 "stat_IfInFTQDiscards",
9361 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9362 0, "Received packet FTQ discards");
9363
9364 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9365 "stat_IfInMBUFDiscards",
9366 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9367 0, "Received packets discarded due to lack "
9368 "of controller buffer memory");
9369
9370 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9371 "stat_IfInRuleCheckerP4Hit",
9372 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9373 0, "Received packets rule checker hits");
9374
9375 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9376 "stat_CatchupInRuleCheckerDiscards",
9377 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9378 0, "Received packets discarded in Catchup path");
9379
9380 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9381 "stat_CatchupInFTQDiscards",
9382 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9383 0, "Received packets discarded in FTQ in Catchup path");
9384
9385 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9386 "stat_CatchupInMBUFDiscards",
9387 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9388 0, "Received packets discarded in controller "
9389 "buffer memory in Catchup path");
9390
9391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9392 "stat_CatchupInRuleCheckerP4Hit",
9393 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9394 0, "Received packets rule checker hits in Catchup path");
9395
9396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9397 "com_no_buffers",
9398 CTLFLAG_RD, &sc->com_no_buffers,
9399 0, "Valid packets received but no RX buffers available");
9400
9401 #ifdef BCE_DEBUG
9402 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9403 "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9404 (void *)sc, 0,
9405 bce_sysctl_driver_state, "I", "Drive state information");
9406
9407 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9408 "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9409 (void *)sc, 0,
9410 bce_sysctl_hw_state, "I", "Hardware state information");
9411
9412 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9413 "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9414 (void *)sc, 0,
9415 bce_sysctl_status_block, "I", "Dump status block");
9416
9417 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9418 "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9419 (void *)sc, 0,
9420 bce_sysctl_stats_block, "I", "Dump statistics block");
9421
9422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9423 "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9424 (void *)sc, 0,
9425 bce_sysctl_stats_clear, "I", "Clear statistics block");
9426
9427 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9428 "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9429 (void *)sc, 0,
9430 bce_sysctl_shmem_state, "I", "Shared memory state information");
9431
9432 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9433 "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9434 (void *)sc, 0,
9435 bce_sysctl_bc_state, "I", "Bootcode state information");
9436
9437 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9438 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9439 (void *)sc, 0,
9440 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9441
9442 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9443 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9444 (void *)sc, 0,
9445 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9446
9447 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9448 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9449 (void *)sc, 0,
9450 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9451
9452 if (bce_hdr_split == TRUE) {
9453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9454 "dump_pg_chain",
9455 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9456 (void *)sc, 0,
9457 bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9458 }
9459
9460 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9461 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9462 (void *)sc, 0,
9463 bce_sysctl_dump_ctx, "I", "Dump context memory");
9464
9465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9466 "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9467 (void *)sc, 0,
9468 bce_sysctl_breakpoint, "I", "Driver breakpoint");
9469
9470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9471 "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT,
9472 (void *)sc, 0,
9473 bce_sysctl_reg_read, "I", "Register read");
9474
9475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9476 "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9477 (void *)sc, 0,
9478 bce_sysctl_nvram_read, "I", "NVRAM read");
9479
9480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9481 "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9482 (void *)sc, 0,
9483 bce_sysctl_phy_read, "I", "PHY register read");
9484
9485 #endif
9486
9487 DBEXIT(BCE_VERBOSE_MISC);
9488 }
9489
9490 /****************************************************************************/
9491 /* BCE Debug Routines */
9492 /****************************************************************************/
9493 #ifdef BCE_DEBUG
9494
9495 /****************************************************************************/
9496 /* Freezes the controller to allow for a cohesive state dump. */
9497 /* */
9498 /* Returns: */
9499 /* Nothing. */
9500 /****************************************************************************/
9501 static __attribute__ ((noinline)) void
bce_freeze_controller(struct bce_softc * sc)9502 bce_freeze_controller(struct bce_softc *sc)
9503 {
9504 u32 val;
9505 val = REG_RD(sc, BCE_MISC_COMMAND);
9506 val |= BCE_MISC_COMMAND_DISABLE_ALL;
9507 REG_WR(sc, BCE_MISC_COMMAND, val);
9508 }
9509
9510 /****************************************************************************/
9511 /* Unfreezes the controller after a freeze operation. This may not always */
9512 /* work and the controller will require a reset! */
9513 /* */
9514 /* Returns: */
9515 /* Nothing. */
9516 /****************************************************************************/
9517 static __attribute__ ((noinline)) void
bce_unfreeze_controller(struct bce_softc * sc)9518 bce_unfreeze_controller(struct bce_softc *sc)
9519 {
9520 u32 val;
9521 val = REG_RD(sc, BCE_MISC_COMMAND);
9522 val |= BCE_MISC_COMMAND_ENABLE_ALL;
9523 REG_WR(sc, BCE_MISC_COMMAND, val);
9524 }
9525
9526 /****************************************************************************/
9527 /* Prints out Ethernet frame information from an mbuf. */
9528 /* */
9529 /* Partially decode an Ethernet frame to look at some important headers. */
9530 /* */
9531 /* Returns: */
9532 /* Nothing. */
9533 /****************************************************************************/
9534 static __attribute__ ((noinline)) void
bce_dump_enet(struct bce_softc * sc,struct mbuf * m)9535 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9536 {
9537 struct ether_vlan_header *eh;
9538 u16 etype;
9539 int ehlen;
9540 struct ip *ip;
9541 struct tcphdr *th;
9542 struct udphdr *uh;
9543 struct arphdr *ah;
9544
9545 BCE_PRINTF(
9546 "-----------------------------"
9547 " Frame Decode "
9548 "-----------------------------\n");
9549
9550 eh = mtod(m, struct ether_vlan_header *);
9551
9552 /* Handle VLAN encapsulation if present. */
9553 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9554 etype = ntohs(eh->evl_proto);
9555 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9556 } else {
9557 etype = ntohs(eh->evl_encap_proto);
9558 ehlen = ETHER_HDR_LEN;
9559 }
9560
9561 /* ToDo: Add VLAN output. */
9562 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9563 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9564
9565 switch (etype) {
9566 case ETHERTYPE_IP:
9567 ip = (struct ip *)(m->m_data + ehlen);
9568 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9569 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9570 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9571 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9572
9573 switch (ip->ip_p) {
9574 case IPPROTO_TCP:
9575 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9576 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9577 "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9578 ntohs(th->th_dport), ntohs(th->th_sport),
9579 (th->th_off << 2), th->th_flags,
9580 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9581 "\02SYN\01FIN", ntohs(th->th_sum));
9582 break;
9583 case IPPROTO_UDP:
9584 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9585 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9586 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9587 ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9588 ntohs(uh->uh_sum));
9589 break;
9590 case IPPROTO_ICMP:
9591 BCE_PRINTF("icmp:\n");
9592 break;
9593 default:
9594 BCE_PRINTF("----: Other IP protocol.\n");
9595 }
9596 break;
9597 case ETHERTYPE_IPV6:
9598 BCE_PRINTF("ipv6: No decode supported.\n");
9599 break;
9600 case ETHERTYPE_ARP:
9601 BCE_PRINTF("-arp: ");
9602 ah = (struct arphdr *) (m->m_data + ehlen);
9603 switch (ntohs(ah->ar_op)) {
9604 case ARPOP_REVREQUEST:
9605 printf("reverse ARP request\n");
9606 break;
9607 case ARPOP_REVREPLY:
9608 printf("reverse ARP reply\n");
9609 break;
9610 case ARPOP_REQUEST:
9611 printf("ARP request\n");
9612 break;
9613 case ARPOP_REPLY:
9614 printf("ARP reply\n");
9615 break;
9616 default:
9617 printf("other ARP operation\n");
9618 }
9619 break;
9620 default:
9621 BCE_PRINTF("----: Other protocol.\n");
9622 }
9623
9624 BCE_PRINTF(
9625 "-----------------------------"
9626 "--------------"
9627 "-----------------------------\n");
9628 }
9629
9630 /****************************************************************************/
9631 /* Prints out information about an mbuf. */
9632 /* */
9633 /* Returns: */
9634 /* Nothing. */
9635 /****************************************************************************/
9636 static __attribute__ ((noinline)) void
bce_dump_mbuf(struct bce_softc * sc,struct mbuf * m)9637 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9638 {
9639 struct mbuf *mp = m;
9640
9641 if (m == NULL) {
9642 BCE_PRINTF("mbuf: null pointer\n");
9643 return;
9644 }
9645
9646 while (mp) {
9647 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9648 "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9649 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9650
9651 if (mp->m_flags & M_PKTHDR) {
9652 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9653 "csum_flags = %b\n", mp->m_pkthdr.len,
9654 mp->m_flags, M_FLAG_PRINTF,
9655 mp->m_pkthdr.csum_flags, CSUM_BITS);
9656 }
9657
9658 if (mp->m_flags & M_EXT) {
9659 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9660 mp->m_ext.ext_buf, mp->m_ext.ext_size);
9661 switch (mp->m_ext.ext_type) {
9662 case EXT_CLUSTER:
9663 printf("EXT_CLUSTER\n"); break;
9664 case EXT_SFBUF:
9665 printf("EXT_SFBUF\n"); break;
9666 case EXT_JUMBO9:
9667 printf("EXT_JUMBO9\n"); break;
9668 case EXT_JUMBO16:
9669 printf("EXT_JUMBO16\n"); break;
9670 case EXT_PACKET:
9671 printf("EXT_PACKET\n"); break;
9672 case EXT_MBUF:
9673 printf("EXT_MBUF\n"); break;
9674 case EXT_NET_DRV:
9675 printf("EXT_NET_DRV\n"); break;
9676 case EXT_MOD_TYPE:
9677 printf("EXT_MDD_TYPE\n"); break;
9678 case EXT_DISPOSABLE:
9679 printf("EXT_DISPOSABLE\n"); break;
9680 case EXT_EXTREF:
9681 printf("EXT_EXTREF\n"); break;
9682 default:
9683 printf("UNKNOWN\n");
9684 }
9685 }
9686
9687 mp = mp->m_next;
9688 }
9689 }
9690
9691 /****************************************************************************/
9692 /* Prints out the mbufs in the TX mbuf chain. */
9693 /* */
9694 /* Returns: */
9695 /* Nothing. */
9696 /****************************************************************************/
9697 static __attribute__ ((noinline)) void
bce_dump_tx_mbuf_chain(struct bce_softc * sc,u16 chain_prod,int count)9698 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9699 {
9700 struct mbuf *m;
9701
9702 BCE_PRINTF(
9703 "----------------------------"
9704 " tx mbuf data "
9705 "----------------------------\n");
9706
9707 for (int i = 0; i < count; i++) {
9708 m = sc->tx_mbuf_ptr[chain_prod];
9709 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9710 bce_dump_mbuf(sc, m);
9711 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9712 }
9713
9714 BCE_PRINTF(
9715 "----------------------------"
9716 "----------------"
9717 "----------------------------\n");
9718 }
9719
9720 /****************************************************************************/
9721 /* Prints out the mbufs in the RX mbuf chain. */
9722 /* */
9723 /* Returns: */
9724 /* Nothing. */
9725 /****************************************************************************/
9726 static __attribute__ ((noinline)) void
bce_dump_rx_mbuf_chain(struct bce_softc * sc,u16 chain_prod,int count)9727 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9728 {
9729 struct mbuf *m;
9730
9731 BCE_PRINTF(
9732 "----------------------------"
9733 " rx mbuf data "
9734 "----------------------------\n");
9735
9736 for (int i = 0; i < count; i++) {
9737 m = sc->rx_mbuf_ptr[chain_prod];
9738 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9739 bce_dump_mbuf(sc, m);
9740 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9741 }
9742
9743 BCE_PRINTF(
9744 "----------------------------"
9745 "----------------"
9746 "----------------------------\n");
9747 }
9748
9749 /****************************************************************************/
9750 /* Prints out the mbufs in the mbuf page chain. */
9751 /* */
9752 /* Returns: */
9753 /* Nothing. */
9754 /****************************************************************************/
9755 static __attribute__ ((noinline)) void
bce_dump_pg_mbuf_chain(struct bce_softc * sc,u16 chain_prod,int count)9756 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9757 {
9758 struct mbuf *m;
9759
9760 BCE_PRINTF(
9761 "----------------------------"
9762 " pg mbuf data "
9763 "----------------------------\n");
9764
9765 for (int i = 0; i < count; i++) {
9766 m = sc->pg_mbuf_ptr[chain_prod];
9767 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9768 bce_dump_mbuf(sc, m);
9769 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9770 }
9771
9772 BCE_PRINTF(
9773 "----------------------------"
9774 "----------------"
9775 "----------------------------\n");
9776 }
9777
9778 /****************************************************************************/
9779 /* Prints out a tx_bd structure. */
9780 /* */
9781 /* Returns: */
9782 /* Nothing. */
9783 /****************************************************************************/
9784 static __attribute__ ((noinline)) void
bce_dump_txbd(struct bce_softc * sc,int idx,struct tx_bd * txbd)9785 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9786 {
9787 int i = 0;
9788
9789 if (idx > MAX_TX_BD_ALLOC)
9790 /* Index out of range. */
9791 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9792 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9793 /* TX Chain page pointer. */
9794 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9795 "pointer\n", idx, txbd->tx_bd_haddr_hi,
9796 txbd->tx_bd_haddr_lo);
9797 else {
9798 /* Normal tx_bd entry. */
9799 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9800 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9801 "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9802 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9803 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9804
9805 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9806 if (i>0)
9807 printf("|");
9808 printf("CONN_FAULT");
9809 i++;
9810 }
9811
9812 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9813 if (i>0)
9814 printf("|");
9815 printf("TCP_UDP_CKSUM");
9816 i++;
9817 }
9818
9819 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
9820 if (i>0)
9821 printf("|");
9822 printf("IP_CKSUM");
9823 i++;
9824 }
9825
9826 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
9827 if (i>0)
9828 printf("|");
9829 printf("VLAN");
9830 i++;
9831 }
9832
9833 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
9834 if (i>0)
9835 printf("|");
9836 printf("COAL_NOW");
9837 i++;
9838 }
9839
9840 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
9841 if (i>0)
9842 printf("|");
9843 printf("DONT_GEN_CRC");
9844 i++;
9845 }
9846
9847 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
9848 if (i>0)
9849 printf("|");
9850 printf("START");
9851 i++;
9852 }
9853
9854 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
9855 if (i>0)
9856 printf("|");
9857 printf("END");
9858 i++;
9859 }
9860
9861 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
9862 if (i>0)
9863 printf("|");
9864 printf("LSO");
9865 i++;
9866 }
9867
9868 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
9869 if (i>0)
9870 printf("|");
9871 printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
9872 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
9873 }
9874
9875 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
9876 if (i>0)
9877 printf("|");
9878 printf("SW_FLAGS");
9879 i++;
9880 }
9881
9882 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
9883 if (i>0)
9884 printf("|");
9885 printf("SNAP)");
9886 } else {
9887 printf(")\n");
9888 }
9889 }
9890 }
9891
9892 /****************************************************************************/
9893 /* Prints out a rx_bd structure. */
9894 /* */
9895 /* Returns: */
9896 /* Nothing. */
9897 /****************************************************************************/
9898 static __attribute__ ((noinline)) void
bce_dump_rxbd(struct bce_softc * sc,int idx,struct rx_bd * rxbd)9899 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
9900 {
9901 if (idx > MAX_RX_BD_ALLOC)
9902 /* Index out of range. */
9903 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
9904 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
9905 /* RX Chain page pointer. */
9906 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9907 "pointer\n", idx, rxbd->rx_bd_haddr_hi,
9908 rxbd->rx_bd_haddr_lo);
9909 else
9910 /* Normal rx_bd entry. */
9911 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
9912 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
9913 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
9914 rxbd->rx_bd_flags);
9915 }
9916
9917 /****************************************************************************/
9918 /* Prints out a rx_bd structure in the page chain. */
9919 /* */
9920 /* Returns: */
9921 /* Nothing. */
9922 /****************************************************************************/
9923 static __attribute__ ((noinline)) void
bce_dump_pgbd(struct bce_softc * sc,int idx,struct rx_bd * pgbd)9924 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
9925 {
9926 if (idx > MAX_PG_BD_ALLOC)
9927 /* Index out of range. */
9928 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
9929 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
9930 /* Page Chain page pointer. */
9931 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
9932 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
9933 else
9934 /* Normal rx_bd entry. */
9935 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
9936 "flags = 0x%08X\n", idx,
9937 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
9938 pgbd->rx_bd_len, pgbd->rx_bd_flags);
9939 }
9940
9941 /****************************************************************************/
9942 /* Prints out a l2_fhdr structure. */
9943 /* */
9944 /* Returns: */
9945 /* Nothing. */
9946 /****************************************************************************/
9947 static __attribute__ ((noinline)) void
bce_dump_l2fhdr(struct bce_softc * sc,int idx,struct l2_fhdr * l2fhdr)9948 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
9949 {
9950 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
9951 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
9952 "tcp_udp_xsum = 0x%04X\n", idx,
9953 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
9954 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
9955 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
9956 }
9957
9958 /****************************************************************************/
9959 /* Prints out context memory info. (Only useful for CID 0 to 16.) */
9960 /* */
9961 /* Returns: */
9962 /* Nothing. */
9963 /****************************************************************************/
9964 static __attribute__ ((noinline)) void
bce_dump_ctx(struct bce_softc * sc,u16 cid)9965 bce_dump_ctx(struct bce_softc *sc, u16 cid)
9966 {
9967 if (cid > TX_CID) {
9968 BCE_PRINTF(" Unknown CID\n");
9969 return;
9970 }
9971
9972 BCE_PRINTF(
9973 "----------------------------"
9974 " CTX Data "
9975 "----------------------------\n");
9976
9977 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
9978
9979 if (cid == RX_CID) {
9980 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
9981 "producer index\n",
9982 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
9983 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
9984 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
9985 BCE_L2CTX_RX_HOST_BSEQ));
9986 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
9987 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
9988 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
9989 "descriptor address\n",
9990 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
9991 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
9992 "descriptor address\n",
9993 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
9994 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
9995 "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9996 BCE_L2CTX_RX_NX_BDIDX));
9997 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
9998 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9999 BCE_L2CTX_RX_HOST_PG_BDIDX));
10000 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10001 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10002 BCE_L2CTX_RX_PG_BUF_SIZE));
10003 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10004 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10005 BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10006 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10007 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10008 BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10009 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10010 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10011 BCE_L2CTX_RX_NX_PG_BDIDX));
10012 } else if (cid == TX_CID) {
10013 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10014 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10015 CTX_RD(sc, GET_CID_ADDR(cid),
10016 BCE_L2CTX_TX_TYPE_XI));
10017 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10018 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10019 BCE_L2CTX_TX_CMD_TYPE_XI));
10020 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10021 "h/w buffer descriptor address\n",
10022 CTX_RD(sc, GET_CID_ADDR(cid),
10023 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10024 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10025 "h/w buffer descriptor address\n",
10026 CTX_RD(sc, GET_CID_ADDR(cid),
10027 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10028 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10029 "host producer index\n",
10030 CTX_RD(sc, GET_CID_ADDR(cid),
10031 BCE_L2CTX_TX_HOST_BIDX_XI));
10032 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10033 "host byte sequence\n",
10034 CTX_RD(sc, GET_CID_ADDR(cid),
10035 BCE_L2CTX_TX_HOST_BSEQ_XI));
10036 } else {
10037 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10038 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10039 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10040 CTX_RD(sc, GET_CID_ADDR(cid),
10041 BCE_L2CTX_TX_CMD_TYPE));
10042 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10043 "h/w buffer descriptor address\n",
10044 CTX_RD(sc, GET_CID_ADDR(cid),
10045 BCE_L2CTX_TX_TBDR_BHADDR_HI));
10046 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10047 "h/w buffer descriptor address\n",
10048 CTX_RD(sc, GET_CID_ADDR(cid),
10049 BCE_L2CTX_TX_TBDR_BHADDR_LO));
10050 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10051 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10052 BCE_L2CTX_TX_HOST_BIDX));
10053 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10054 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10055 BCE_L2CTX_TX_HOST_BSEQ));
10056 }
10057 }
10058
10059 BCE_PRINTF(
10060 "----------------------------"
10061 " Raw CTX "
10062 "----------------------------\n");
10063
10064 for (int i = 0x0; i < 0x300; i += 0x10) {
10065 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10066 CTX_RD(sc, GET_CID_ADDR(cid), i),
10067 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10068 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10069 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10070 }
10071
10072 BCE_PRINTF(
10073 "----------------------------"
10074 "----------------"
10075 "----------------------------\n");
10076 }
10077
10078 /****************************************************************************/
10079 /* Prints out the FTQ data. */
10080 /* */
10081 /* Returns: */
10082 /* Nothing. */
10083 /****************************************************************************/
10084 static __attribute__ ((noinline)) void
bce_dump_ftqs(struct bce_softc * sc)10085 bce_dump_ftqs(struct bce_softc *sc)
10086 {
10087 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10088
10089 BCE_PRINTF(
10090 "----------------------------"
10091 " FTQ Data "
10092 "----------------------------\n");
10093
10094 BCE_PRINTF(" FTQ Command Control Depth_Now "
10095 "Max_Depth Valid_Cnt \n");
10096 BCE_PRINTF(" ------- ---------- ---------- ---------- "
10097 "---------- ----------\n");
10098
10099 /* Setup the generic statistic counters for the FTQ valid count. */
10100 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10101 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) |
10102 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) |
10103 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10104 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10105
10106 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) |
10107 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) |
10108 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) |
10109 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10110 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10111
10112 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) |
10113 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) |
10114 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
10115 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10116 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10117
10118 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
10119 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
10120 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
10121 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10122 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10123
10124 /* Input queue to the Receive Lookup state machine */
10125 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10126 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10127 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10128 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10129 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10130 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10131 cmd, ctl, cur_depth, max_depth, valid_cnt);
10132
10133 /* Input queue to the Receive Processor */
10134 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10135 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10136 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10137 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10138 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10139 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10140 cmd, ctl, cur_depth, max_depth, valid_cnt);
10141
10142 /* Input queue to the Recevie Processor */
10143 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10144 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10145 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10146 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10147 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10148 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10149 cmd, ctl, cur_depth, max_depth, valid_cnt);
10150
10151 /* Input queue to the Receive Virtual to Physical state machine */
10152 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10153 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10154 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10155 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10156 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10157 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10158 cmd, ctl, cur_depth, max_depth, valid_cnt);
10159
10160 /* Input queue to the Recevie Virtual to Physical state machine */
10161 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10162 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10163 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10164 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10165 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10166 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10167 cmd, ctl, cur_depth, max_depth, valid_cnt);
10168
10169 /* Input queue to the Receive Virtual to Physical state machine */
10170 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10171 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10172 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10173 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10174 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10175 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10176 cmd, ctl, cur_depth, max_depth, valid_cnt);
10177
10178 /* Input queue to the Receive DMA state machine */
10179 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10180 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10181 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10182 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10183 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10184 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10185 cmd, ctl, cur_depth, max_depth, valid_cnt);
10186
10187 /* Input queue to the Transmit Scheduler state machine */
10188 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10189 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10190 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10191 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10192 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10193 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10194 cmd, ctl, cur_depth, max_depth, valid_cnt);
10195
10196 /* Input queue to the Transmit Buffer Descriptor state machine */
10197 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10198 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10199 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10200 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10201 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10202 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10203 cmd, ctl, cur_depth, max_depth, valid_cnt);
10204
10205 /* Input queue to the Transmit Processor */
10206 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10207 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10208 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10209 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10210 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10211 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10212 cmd, ctl, cur_depth, max_depth, valid_cnt);
10213
10214 /* Input queue to the Transmit DMA state machine */
10215 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10216 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10217 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10218 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10219 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10220 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10221 cmd, ctl, cur_depth, max_depth, valid_cnt);
10222
10223 /* Input queue to the Transmit Patch-Up Processor */
10224 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10225 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10226 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10227 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10228 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10229 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10230 cmd, ctl, cur_depth, max_depth, valid_cnt);
10231
10232 /* Input queue to the Transmit Assembler state machine */
10233 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10234 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10235 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10236 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10237 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10238 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10239 cmd, ctl, cur_depth, max_depth, valid_cnt);
10240
10241 /* Input queue to the Completion Processor */
10242 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10243 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10244 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10245 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10246 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10247 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10248 cmd, ctl, cur_depth, max_depth, valid_cnt);
10249
10250 /* Input queue to the Completion Processor */
10251 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10252 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10253 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10254 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10255 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10256 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10257 cmd, ctl, cur_depth, max_depth, valid_cnt);
10258
10259 /* Input queue to the Completion Processor */
10260 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10261 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10262 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10263 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10264 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10265 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10266 cmd, ctl, cur_depth, max_depth, valid_cnt);
10267
10268 /* Setup the generic statistic counters for the FTQ valid count. */
10269 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
10270 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
10271 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10272
10273 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10274 val = val |
10275 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10276 24);
10277 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10278
10279 /* Input queue to the Management Control Processor */
10280 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10281 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10282 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10283 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10284 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10285 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10286 cmd, ctl, cur_depth, max_depth, valid_cnt);
10287
10288 /* Input queue to the Command Processor */
10289 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10290 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10291 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10292 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10293 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10294 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10295 cmd, ctl, cur_depth, max_depth, valid_cnt);
10296
10297 /* Input queue to the Completion Scheduler state machine */
10298 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10299 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10300 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10301 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10302 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10303 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10304 cmd, ctl, cur_depth, max_depth, valid_cnt);
10305
10306 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10307 /* Input queue to the RV2P Command Scheduler */
10308 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10309 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10310 cur_depth = (ctl & 0xFFC00000) >> 22;
10311 max_depth = (ctl & 0x003FF000) >> 12;
10312 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10313 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10314 cmd, ctl, cur_depth, max_depth, valid_cnt);
10315 }
10316
10317 BCE_PRINTF(
10318 "----------------------------"
10319 "----------------"
10320 "----------------------------\n");
10321 }
10322
10323 /****************************************************************************/
10324 /* Prints out the TX chain. */
10325 /* */
10326 /* Returns: */
10327 /* Nothing. */
10328 /****************************************************************************/
10329 static __attribute__ ((noinline)) void
bce_dump_tx_chain(struct bce_softc * sc,u16 tx_prod,int count)10330 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10331 {
10332 struct tx_bd *txbd;
10333
10334 /* First some info about the tx_bd chain structure. */
10335 BCE_PRINTF(
10336 "----------------------------"
10337 " tx_bd chain "
10338 "----------------------------\n");
10339
10340 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n",
10341 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10342 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10343 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10344 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10345
10346 BCE_PRINTF(
10347 "----------------------------"
10348 " tx_bd data "
10349 "----------------------------\n");
10350
10351 /* Now print out a decoded list of TX buffer descriptors. */
10352 for (int i = 0; i < count; i++) {
10353 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10354 bce_dump_txbd(sc, tx_prod, txbd);
10355 tx_prod++;
10356 }
10357
10358 BCE_PRINTF(
10359 "----------------------------"
10360 "----------------"
10361 "----------------------------\n");
10362 }
10363
10364 /****************************************************************************/
10365 /* Prints out the RX chain. */
10366 /* */
10367 /* Returns: */
10368 /* Nothing. */
10369 /****************************************************************************/
10370 static __attribute__ ((noinline)) void
bce_dump_rx_bd_chain(struct bce_softc * sc,u16 rx_prod,int count)10371 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10372 {
10373 struct rx_bd *rxbd;
10374
10375 /* First some info about the rx_bd chain structure. */
10376 BCE_PRINTF(
10377 "----------------------------"
10378 " rx_bd chain "
10379 "----------------------------\n");
10380
10381 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n",
10382 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10383
10384 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10385 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10386
10387 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10388
10389 BCE_PRINTF(
10390 "----------------------------"
10391 " rx_bd data "
10392 "----------------------------\n");
10393
10394 /* Now print out the rx_bd's themselves. */
10395 for (int i = 0; i < count; i++) {
10396 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10397 bce_dump_rxbd(sc, rx_prod, rxbd);
10398 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10399 }
10400
10401 BCE_PRINTF(
10402 "----------------------------"
10403 "----------------"
10404 "----------------------------\n");
10405 }
10406
10407 /****************************************************************************/
10408 /* Prints out the page chain. */
10409 /* */
10410 /* Returns: */
10411 /* Nothing. */
10412 /****************************************************************************/
10413 static __attribute__ ((noinline)) void
bce_dump_pg_chain(struct bce_softc * sc,u16 pg_prod,int count)10414 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10415 {
10416 struct rx_bd *pgbd;
10417
10418 /* First some info about the page chain structure. */
10419 BCE_PRINTF(
10420 "----------------------------"
10421 " page chain "
10422 "----------------------------\n");
10423
10424 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n",
10425 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10426
10427 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10428 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10429
10430 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10431
10432 BCE_PRINTF(
10433 "----------------------------"
10434 " page data "
10435 "----------------------------\n");
10436
10437 /* Now print out the rx_bd's themselves. */
10438 for (int i = 0; i < count; i++) {
10439 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10440 bce_dump_pgbd(sc, pg_prod, pgbd);
10441 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10442 }
10443
10444 BCE_PRINTF(
10445 "----------------------------"
10446 "----------------"
10447 "----------------------------\n");
10448 }
10449
10450 #define BCE_PRINT_RX_CONS(arg) \
10451 if (sblk->status_rx_quick_consumer_index##arg) \
10452 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \
10453 sblk->status_rx_quick_consumer_index##arg, (u16) \
10454 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \
10455 arg);
10456
10457 #define BCE_PRINT_TX_CONS(arg) \
10458 if (sblk->status_tx_quick_consumer_index##arg) \
10459 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \
10460 sblk->status_tx_quick_consumer_index##arg, (u16) \
10461 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \
10462 arg);
10463
10464 /****************************************************************************/
10465 /* Prints out the status block from host memory. */
10466 /* */
10467 /* Returns: */
10468 /* Nothing. */
10469 /****************************************************************************/
10470 static __attribute__ ((noinline)) void
bce_dump_status_block(struct bce_softc * sc)10471 bce_dump_status_block(struct bce_softc *sc)
10472 {
10473 struct status_block *sblk;
10474
10475 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10476
10477 sblk = sc->status_block;
10478
10479 BCE_PRINTF(
10480 "----------------------------"
10481 " Status Block "
10482 "----------------------------\n");
10483
10484 /* Theses indices are used for normal L2 drivers. */
10485 BCE_PRINTF(" 0x%08X - attn_bits\n",
10486 sblk->status_attn_bits);
10487
10488 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
10489 sblk->status_attn_bits_ack);
10490
10491 BCE_PRINT_RX_CONS(0);
10492 BCE_PRINT_TX_CONS(0)
10493
10494 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
10495
10496 /* Theses indices are not used for normal L2 drivers. */
10497 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3);
10498 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6);
10499 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9);
10500 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12);
10501 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15);
10502
10503 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3);
10504
10505 if (sblk->status_completion_producer_index ||
10506 sblk->status_cmd_consumer_index)
10507 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n",
10508 sblk->status_completion_producer_index,
10509 sblk->status_cmd_consumer_index);
10510
10511 BCE_PRINTF(
10512 "----------------------------"
10513 "----------------"
10514 "----------------------------\n");
10515 }
10516
10517 #define BCE_PRINT_64BIT_STAT(arg) \
10518 if (sblk->arg##_lo || sblk->arg##_hi) \
10519 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \
10520 sblk->arg##_lo, #arg);
10521
10522 #define BCE_PRINT_32BIT_STAT(arg) \
10523 if (sblk->arg) \
10524 BCE_PRINTF(" 0x%08X : %s\n", \
10525 sblk->arg, #arg);
10526
10527 /****************************************************************************/
10528 /* Prints out the statistics block from host memory. */
10529 /* */
10530 /* Returns: */
10531 /* Nothing. */
10532 /****************************************************************************/
10533 static __attribute__ ((noinline)) void
bce_dump_stats_block(struct bce_softc * sc)10534 bce_dump_stats_block(struct bce_softc *sc)
10535 {
10536 struct statistics_block *sblk;
10537
10538 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10539
10540 sblk = sc->stats_block;
10541
10542 BCE_PRINTF(
10543 "---------------"
10544 " Stats Block (All Stats Not Shown Are 0) "
10545 "---------------\n");
10546
10547 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10548 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10549 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10550 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10551 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10552 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10553 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10554 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10555 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10556 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10557 BCE_PRINT_32BIT_STAT(
10558 stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10559 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10560 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10561 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10562 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10563 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10564 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10565 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10566 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10567 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10568 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10569 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10570 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10571 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10572 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10573 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10574 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10575 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10576 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10577 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10578 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10579 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10580 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10581 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10582 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10583 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10584 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10585 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10586 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10587 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10588 BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10589 BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10590 BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10591 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10592 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10593 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10594 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10595 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10596 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10597 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10598 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10599 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10600 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10601 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10602
10603 BCE_PRINTF(
10604 "----------------------------"
10605 "----------------"
10606 "----------------------------\n");
10607 }
10608
10609 /****************************************************************************/
10610 /* Prints out a summary of the driver state. */
10611 /* */
10612 /* Returns: */
10613 /* Nothing. */
10614 /****************************************************************************/
10615 static __attribute__ ((noinline)) void
bce_dump_driver_state(struct bce_softc * sc)10616 bce_dump_driver_state(struct bce_softc *sc)
10617 {
10618 u32 val_hi, val_lo;
10619
10620 BCE_PRINTF(
10621 "-----------------------------"
10622 " Driver State "
10623 "-----------------------------\n");
10624
10625 val_hi = BCE_ADDR_HI(sc);
10626 val_lo = BCE_ADDR_LO(sc);
10627 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10628 "address\n", val_hi, val_lo);
10629
10630 val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10631 val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10632 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10633 "address\n", val_hi, val_lo);
10634
10635 val_hi = BCE_ADDR_HI(sc->status_block);
10636 val_lo = BCE_ADDR_LO(sc->status_block);
10637 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10638 "virtual address\n", val_hi, val_lo);
10639
10640 val_hi = BCE_ADDR_HI(sc->stats_block);
10641 val_lo = BCE_ADDR_LO(sc->stats_block);
10642 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10643 "virtual address\n", val_hi, val_lo);
10644
10645 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10646 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10647 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10648 "virtual address\n", val_hi, val_lo);
10649
10650 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10651 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10652 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10653 "virtual address\n", val_hi, val_lo);
10654
10655 if (bce_hdr_split == TRUE) {
10656 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10657 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10658 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10659 "virtual address\n", val_hi, val_lo);
10660 }
10661
10662 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10663 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10664 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10665 "virtual address\n", val_hi, val_lo);
10666
10667 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10668 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10669 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10670 "virtual address\n", val_hi, val_lo);
10671
10672 if (bce_hdr_split == TRUE) {
10673 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10674 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10675 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10676 "virtual address\n", val_hi, val_lo);
10677 }
10678
10679 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10680 "h/w intrs\n",
10681 (long long unsigned int) sc->interrupts_generated);
10682
10683 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10684 "rx interrupts handled\n",
10685 (long long unsigned int) sc->interrupts_rx);
10686
10687 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10688 "tx interrupts handled\n",
10689 (long long unsigned int) sc->interrupts_tx);
10690
10691 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10692 "phy interrupts handled\n",
10693 (long long unsigned int) sc->phy_interrupts);
10694
10695 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) "
10696 "status block index\n", sc->last_status_idx);
10697
10698 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10699 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10700
10701 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10702 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10703
10704 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer "
10705 "byte seq index\n", sc->tx_prod_bseq);
10706
10707 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10708 "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10709
10710 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used "
10711 "tx_bd's\n", sc->used_tx_bd);
10712
10713 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10714 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10715
10716 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10717 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10718
10719 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10720 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10721
10722 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer "
10723 "byte seq index\n", sc->rx_prod_bseq);
10724
10725 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/"
10726 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10727
10728 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10729 "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10730
10731 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free "
10732 "rx_bd's\n", sc->free_rx_bd);
10733
10734 if (bce_hdr_split == TRUE) {
10735 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer "
10736 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10737
10738 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10739 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10740
10741 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page "
10742 "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10743 }
10744
10745 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page "
10746 "rx_bd's\n", sc->free_pg_bd);
10747
10748 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/"
10749 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10750
10751 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) "
10752 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10753
10754 BCE_PRINTF(" 0x%08X - (sc->bce_flags) "
10755 "bce mac flags\n", sc->bce_flags);
10756
10757 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) "
10758 "bce phy flags\n", sc->bce_phy_flags);
10759
10760 BCE_PRINTF(
10761 "----------------------------"
10762 "----------------"
10763 "----------------------------\n");
10764 }
10765
10766 /****************************************************************************/
10767 /* Prints out the hardware state through a summary of important register, */
10768 /* followed by a complete register dump. */
10769 /* */
10770 /* Returns: */
10771 /* Nothing. */
10772 /****************************************************************************/
10773 static __attribute__ ((noinline)) void
bce_dump_hw_state(struct bce_softc * sc)10774 bce_dump_hw_state(struct bce_softc *sc)
10775 {
10776 u32 val;
10777
10778 BCE_PRINTF(
10779 "----------------------------"
10780 " Hardware State "
10781 "----------------------------\n");
10782
10783 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10784
10785 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10786 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10787 val, BCE_MISC_ENABLE_STATUS_BITS);
10788
10789 val = REG_RD(sc, BCE_DMA_STATUS);
10790 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10791 val, BCE_DMA_STATUS);
10792
10793 val = REG_RD(sc, BCE_CTX_STATUS);
10794 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10795 val, BCE_CTX_STATUS);
10796
10797 val = REG_RD(sc, BCE_EMAC_STATUS);
10798 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10799 val, BCE_EMAC_STATUS);
10800
10801 val = REG_RD(sc, BCE_RPM_STATUS);
10802 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10803 val, BCE_RPM_STATUS);
10804
10805 /* ToDo: Create a #define for this constant. */
10806 val = REG_RD(sc, 0x2004);
10807 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
10808 val, 0x2004);
10809
10810 val = REG_RD(sc, BCE_RV2P_STATUS);
10811 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
10812 val, BCE_RV2P_STATUS);
10813
10814 /* ToDo: Create a #define for this constant. */
10815 val = REG_RD(sc, 0x2c04);
10816 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
10817 val, 0x2c04);
10818
10819 val = REG_RD(sc, BCE_TBDR_STATUS);
10820 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
10821 val, BCE_TBDR_STATUS);
10822
10823 val = REG_RD(sc, BCE_TDMA_STATUS);
10824 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
10825 val, BCE_TDMA_STATUS);
10826
10827 val = REG_RD(sc, BCE_HC_STATUS);
10828 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
10829 val, BCE_HC_STATUS);
10830
10831 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
10832 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10833 val, BCE_TXP_CPU_STATE);
10834
10835 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
10836 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10837 val, BCE_TPAT_CPU_STATE);
10838
10839 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
10840 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10841 val, BCE_RXP_CPU_STATE);
10842
10843 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
10844 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10845 val, BCE_COM_CPU_STATE);
10846
10847 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
10848 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
10849 val, BCE_MCP_CPU_STATE);
10850
10851 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
10852 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10853 val, BCE_CP_CPU_STATE);
10854
10855 BCE_PRINTF(
10856 "----------------------------"
10857 "----------------"
10858 "----------------------------\n");
10859
10860 BCE_PRINTF(
10861 "----------------------------"
10862 " Register Dump "
10863 "----------------------------\n");
10864
10865 for (int i = 0x400; i < 0x8000; i += 0x10) {
10866 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10867 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10868 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10869 }
10870
10871 BCE_PRINTF(
10872 "----------------------------"
10873 "----------------"
10874 "----------------------------\n");
10875 }
10876
10877 /****************************************************************************/
10878 /* Prints out the contentst of shared memory which is used for host driver */
10879 /* to bootcode firmware communication. */
10880 /* */
10881 /* Returns: */
10882 /* Nothing. */
10883 /****************************************************************************/
10884 static __attribute__ ((noinline)) void
bce_dump_shmem_state(struct bce_softc * sc)10885 bce_dump_shmem_state(struct bce_softc *sc)
10886 {
10887 BCE_PRINTF(
10888 "----------------------------"
10889 " Hardware State "
10890 "----------------------------\n");
10891
10892 BCE_PRINTF("0x%08X - Shared memory base address\n",
10893 sc->bce_shmem_base);
10894 BCE_PRINTF("%s - bootcode version\n",
10895 sc->bce_bc_ver);
10896
10897 BCE_PRINTF(
10898 "----------------------------"
10899 " Shared Mem "
10900 "----------------------------\n");
10901
10902 for (int i = 0x0; i < 0x200; i += 0x10) {
10903 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10904 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
10905 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
10906 }
10907
10908 BCE_PRINTF(
10909 "----------------------------"
10910 "----------------"
10911 "----------------------------\n");
10912 }
10913
10914 /****************************************************************************/
10915 /* Prints out the mailbox queue registers. */
10916 /* */
10917 /* Returns: */
10918 /* Nothing. */
10919 /****************************************************************************/
10920 static __attribute__ ((noinline)) void
bce_dump_mq_regs(struct bce_softc * sc)10921 bce_dump_mq_regs(struct bce_softc *sc)
10922 {
10923 BCE_PRINTF(
10924 "----------------------------"
10925 " MQ Regs "
10926 "----------------------------\n");
10927
10928 BCE_PRINTF(
10929 "----------------------------"
10930 "----------------"
10931 "----------------------------\n");
10932
10933 for (int i = 0x3c00; i < 0x4000; i += 0x10) {
10934 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10935 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10936 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10937 }
10938
10939 BCE_PRINTF(
10940 "----------------------------"
10941 "----------------"
10942 "----------------------------\n");
10943 }
10944
10945 /****************************************************************************/
10946 /* Prints out the bootcode state. */
10947 /* */
10948 /* Returns: */
10949 /* Nothing. */
10950 /****************************************************************************/
10951 static __attribute__ ((noinline)) void
bce_dump_bc_state(struct bce_softc * sc)10952 bce_dump_bc_state(struct bce_softc *sc)
10953 {
10954 u32 val;
10955
10956 BCE_PRINTF(
10957 "----------------------------"
10958 " Bootcode State "
10959 "----------------------------\n");
10960
10961 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10962
10963 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
10964 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
10965 val, BCE_BC_RESET_TYPE);
10966
10967 val = bce_shmem_rd(sc, BCE_BC_STATE);
10968 BCE_PRINTF("0x%08X - (0x%06X) state\n",
10969 val, BCE_BC_STATE);
10970
10971 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
10972 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
10973 val, BCE_BC_STATE_CONDITION);
10974
10975 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
10976 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
10977 val, BCE_BC_STATE_DEBUG_CMD);
10978
10979 BCE_PRINTF(
10980 "----------------------------"
10981 "----------------"
10982 "----------------------------\n");
10983 }
10984
10985 /****************************************************************************/
10986 /* Prints out the TXP processor state. */
10987 /* */
10988 /* Returns: */
10989 /* Nothing. */
10990 /****************************************************************************/
10991 static __attribute__ ((noinline)) void
bce_dump_txp_state(struct bce_softc * sc,int regs)10992 bce_dump_txp_state(struct bce_softc *sc, int regs)
10993 {
10994 u32 val;
10995 u32 fw_version[3];
10996
10997 BCE_PRINTF(
10998 "----------------------------"
10999 " TXP State "
11000 "----------------------------\n");
11001
11002 for (int i = 0; i < 3; i++)
11003 fw_version[i] = htonl(REG_RD_IND(sc,
11004 (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11005 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11006
11007 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11008 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11009 val, BCE_TXP_CPU_MODE);
11010
11011 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11012 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11013 val, BCE_TXP_CPU_STATE);
11014
11015 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11016 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11017 val, BCE_TXP_CPU_EVENT_MASK);
11018
11019 if (regs) {
11020 BCE_PRINTF(
11021 "----------------------------"
11022 " Register Dump "
11023 "----------------------------\n");
11024
11025 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11026 /* Skip the big blank spaces */
11027 if (i < 0x454000 && i > 0x5ffff)
11028 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11029 "0x%08X 0x%08X\n", i,
11030 REG_RD_IND(sc, i),
11031 REG_RD_IND(sc, i + 0x4),
11032 REG_RD_IND(sc, i + 0x8),
11033 REG_RD_IND(sc, i + 0xC));
11034 }
11035 }
11036
11037 BCE_PRINTF(
11038 "----------------------------"
11039 "----------------"
11040 "----------------------------\n");
11041 }
11042
11043 /****************************************************************************/
11044 /* Prints out the RXP processor state. */
11045 /* */
11046 /* Returns: */
11047 /* Nothing. */
11048 /****************************************************************************/
11049 static __attribute__ ((noinline)) void
bce_dump_rxp_state(struct bce_softc * sc,int regs)11050 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11051 {
11052 u32 val;
11053 u32 fw_version[3];
11054
11055 BCE_PRINTF(
11056 "----------------------------"
11057 " RXP State "
11058 "----------------------------\n");
11059
11060 for (int i = 0; i < 3; i++)
11061 fw_version[i] = htonl(REG_RD_IND(sc,
11062 (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11063
11064 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11065
11066 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11067 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11068 val, BCE_RXP_CPU_MODE);
11069
11070 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11071 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11072 val, BCE_RXP_CPU_STATE);
11073
11074 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11075 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11076 val, BCE_RXP_CPU_EVENT_MASK);
11077
11078 if (regs) {
11079 BCE_PRINTF(
11080 "----------------------------"
11081 " Register Dump "
11082 "----------------------------\n");
11083
11084 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11085 /* Skip the big blank sapces */
11086 if (i < 0xc5400 && i > 0xdffff)
11087 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11088 "0x%08X 0x%08X\n", i,
11089 REG_RD_IND(sc, i),
11090 REG_RD_IND(sc, i + 0x4),
11091 REG_RD_IND(sc, i + 0x8),
11092 REG_RD_IND(sc, i + 0xC));
11093 }
11094 }
11095
11096 BCE_PRINTF(
11097 "----------------------------"
11098 "----------------"
11099 "----------------------------\n");
11100 }
11101
11102 /****************************************************************************/
11103 /* Prints out the TPAT processor state. */
11104 /* */
11105 /* Returns: */
11106 /* Nothing. */
11107 /****************************************************************************/
11108 static __attribute__ ((noinline)) void
bce_dump_tpat_state(struct bce_softc * sc,int regs)11109 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11110 {
11111 u32 val;
11112 u32 fw_version[3];
11113
11114 BCE_PRINTF(
11115 "----------------------------"
11116 " TPAT State "
11117 "----------------------------\n");
11118
11119 for (int i = 0; i < 3; i++)
11120 fw_version[i] = htonl(REG_RD_IND(sc,
11121 (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11122
11123 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11124
11125 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11126 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11127 val, BCE_TPAT_CPU_MODE);
11128
11129 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11130 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11131 val, BCE_TPAT_CPU_STATE);
11132
11133 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11134 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11135 val, BCE_TPAT_CPU_EVENT_MASK);
11136
11137 if (regs) {
11138 BCE_PRINTF(
11139 "----------------------------"
11140 " Register Dump "
11141 "----------------------------\n");
11142
11143 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11144 /* Skip the big blank spaces */
11145 if (i < 0x854000 && i > 0x9ffff)
11146 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11147 "0x%08X 0x%08X\n", i,
11148 REG_RD_IND(sc, i),
11149 REG_RD_IND(sc, i + 0x4),
11150 REG_RD_IND(sc, i + 0x8),
11151 REG_RD_IND(sc, i + 0xC));
11152 }
11153 }
11154
11155 BCE_PRINTF(
11156 "----------------------------"
11157 "----------------"
11158 "----------------------------\n");
11159 }
11160
11161 /****************************************************************************/
11162 /* Prints out the Command Procesor (CP) state. */
11163 /* */
11164 /* Returns: */
11165 /* Nothing. */
11166 /****************************************************************************/
11167 static __attribute__ ((noinline)) void
bce_dump_cp_state(struct bce_softc * sc,int regs)11168 bce_dump_cp_state(struct bce_softc *sc, int regs)
11169 {
11170 u32 val;
11171 u32 fw_version[3];
11172
11173 BCE_PRINTF(
11174 "----------------------------"
11175 " CP State "
11176 "----------------------------\n");
11177
11178 for (int i = 0; i < 3; i++)
11179 fw_version[i] = htonl(REG_RD_IND(sc,
11180 (BCE_CP_SCRATCH + 0x10 + i * 4)));
11181
11182 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11183
11184 val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11185 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11186 val, BCE_CP_CPU_MODE);
11187
11188 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11189 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11190 val, BCE_CP_CPU_STATE);
11191
11192 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11193 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11194 BCE_CP_CPU_EVENT_MASK);
11195
11196 if (regs) {
11197 BCE_PRINTF(
11198 "----------------------------"
11199 " Register Dump "
11200 "----------------------------\n");
11201
11202 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11203 /* Skip the big blank spaces */
11204 if (i < 0x185400 && i > 0x19ffff)
11205 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11206 "0x%08X 0x%08X\n", i,
11207 REG_RD_IND(sc, i),
11208 REG_RD_IND(sc, i + 0x4),
11209 REG_RD_IND(sc, i + 0x8),
11210 REG_RD_IND(sc, i + 0xC));
11211 }
11212 }
11213
11214 BCE_PRINTF(
11215 "----------------------------"
11216 "----------------"
11217 "----------------------------\n");
11218 }
11219
11220 /****************************************************************************/
11221 /* Prints out the Completion Procesor (COM) state. */
11222 /* */
11223 /* Returns: */
11224 /* Nothing. */
11225 /****************************************************************************/
11226 static __attribute__ ((noinline)) void
bce_dump_com_state(struct bce_softc * sc,int regs)11227 bce_dump_com_state(struct bce_softc *sc, int regs)
11228 {
11229 u32 val;
11230 u32 fw_version[4];
11231
11232 BCE_PRINTF(
11233 "----------------------------"
11234 " COM State "
11235 "----------------------------\n");
11236
11237 for (int i = 0; i < 3; i++)
11238 fw_version[i] = htonl(REG_RD_IND(sc,
11239 (BCE_COM_SCRATCH + 0x10 + i * 4)));
11240
11241 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11242
11243 val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11244 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11245 val, BCE_COM_CPU_MODE);
11246
11247 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11248 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11249 val, BCE_COM_CPU_STATE);
11250
11251 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11252 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11253 BCE_COM_CPU_EVENT_MASK);
11254
11255 if (regs) {
11256 BCE_PRINTF(
11257 "----------------------------"
11258 " Register Dump "
11259 "----------------------------\n");
11260
11261 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11262 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11263 "0x%08X 0x%08X\n", i,
11264 REG_RD_IND(sc, i),
11265 REG_RD_IND(sc, i + 0x4),
11266 REG_RD_IND(sc, i + 0x8),
11267 REG_RD_IND(sc, i + 0xC));
11268 }
11269 }
11270
11271 BCE_PRINTF(
11272 "----------------------------"
11273 "----------------"
11274 "----------------------------\n");
11275 }
11276
11277 /****************************************************************************/
11278 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */
11279 /* */
11280 /* Returns: */
11281 /* Nothing. */
11282 /****************************************************************************/
11283 static __attribute__ ((noinline)) void
bce_dump_rv2p_state(struct bce_softc * sc)11284 bce_dump_rv2p_state(struct bce_softc *sc)
11285 {
11286 u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11287
11288 BCE_PRINTF(
11289 "----------------------------"
11290 " RV2P State "
11291 "----------------------------\n");
11292
11293 /* Stall the RV2P processors. */
11294 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11295 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11296 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11297
11298 /* Read the firmware version. */
11299 val = 0x00000001;
11300 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11301 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11302 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11303 BCE_RV2P_INSTR_HIGH_HIGH;
11304 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11305 fw_ver_high, fw_ver_low);
11306
11307 val = 0x00000001;
11308 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11309 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11310 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11311 BCE_RV2P_INSTR_HIGH_HIGH;
11312 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11313 fw_ver_high, fw_ver_low);
11314
11315 /* Resume the RV2P processors. */
11316 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11317 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11318 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11319
11320 /* Fetch the program counter value. */
11321 val = 0x68007800;
11322 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11323 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11324 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11325 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11326 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11327 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11328
11329 /* Fetch the program counter value again to see if it is advancing. */
11330 val = 0x68007800;
11331 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11332 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11333 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11334 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11335 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11336 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11337
11338 BCE_PRINTF(
11339 "----------------------------"
11340 "----------------"
11341 "----------------------------\n");
11342 }
11343
11344 /****************************************************************************/
11345 /* Prints out the driver state and then enters the debugger. */
11346 /* */
11347 /* Returns: */
11348 /* Nothing. */
11349 /****************************************************************************/
11350 static __attribute__ ((noinline)) void
bce_breakpoint(struct bce_softc * sc)11351 bce_breakpoint(struct bce_softc *sc)
11352 {
11353
11354 /*
11355 * Unreachable code to silence compiler warnings
11356 * about unused functions.
11357 */
11358 if (0) {
11359 bce_freeze_controller(sc);
11360 bce_unfreeze_controller(sc);
11361 bce_dump_enet(sc, NULL);
11362 bce_dump_txbd(sc, 0, NULL);
11363 bce_dump_rxbd(sc, 0, NULL);
11364 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11365 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11366 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11367 bce_dump_l2fhdr(sc, 0, NULL);
11368 bce_dump_ctx(sc, RX_CID);
11369 bce_dump_ftqs(sc);
11370 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11371 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11372 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11373 bce_dump_status_block(sc);
11374 bce_dump_stats_block(sc);
11375 bce_dump_driver_state(sc);
11376 bce_dump_hw_state(sc);
11377 bce_dump_bc_state(sc);
11378 bce_dump_txp_state(sc, 0);
11379 bce_dump_rxp_state(sc, 0);
11380 bce_dump_tpat_state(sc, 0);
11381 bce_dump_cp_state(sc, 0);
11382 bce_dump_com_state(sc, 0);
11383 bce_dump_rv2p_state(sc);
11384 bce_dump_pgbd(sc, 0, NULL);
11385 }
11386
11387 bce_dump_status_block(sc);
11388 bce_dump_driver_state(sc);
11389
11390 /* Call the debugger. */
11391 breakpoint();
11392 }
11393 #endif
11394