1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2025 Chelsio Communications. 5 * Written by: Navdeep Parhar <np@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __T4_ADAPTER_H__ 31 #define __T4_ADAPTER_H__ 32 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/counter.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/seqc.h> 42 #include <sys/sx.h> 43 #include <sys/vmem.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/taskqueue.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <net/pfil.h> 57 #include <netinet/in.h> 58 #include <netinet/tcp_lro.h> 59 60 #include "offload.h" 61 #include "t4_ioctl.h" 62 #include "common/t4_msg.h" 63 #include "firmware/t4fw_interface.h" 64 65 #define KTR_CXGBE KTR_SPARE3 66 MALLOC_DECLARE(M_CXGBE); 67 #define CXGBE_UNIMPLEMENTED(s) \ 68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 69 70 /* 71 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 72 * LIST_HEAD when building iw_cxgbe. 73 */ 74 #define CXGBE_LIST_HEAD(name, type) \ 75 struct name { \ 76 struct type *lh_first; /* first element */ \ 77 } 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 SYSCTL_DECL(_hw_cxgbe); 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 1024, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_SGL_SEGS_VM = 38, 120 TX_SGL_SEGS_VM_TSO = 37, 121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 122 TX_SGL_SEGS_VXLAN_TSO = 37, 123 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 124 }; 125 126 enum { 127 /* adapter intr_type */ 128 INTR_INTX = (1 << 0), 129 INTR_MSI = (1 << 1), 130 INTR_MSIX = (1 << 2) 131 }; 132 133 enum { 134 XGMAC_MTU = (1 << 0), 135 XGMAC_PROMISC = (1 << 1), 136 XGMAC_ALLMULTI = (1 << 2), 137 XGMAC_VLANEX = (1 << 3), 138 XGMAC_UCADDR = (1 << 4), 139 XGMAC_MCADDRS = (1 << 5), 140 141 XGMAC_ALL = 0xffff 142 }; 143 144 enum { 145 /* flags understood by begin_synchronized_op */ 146 HOLD_LOCK = (1 << 0), 147 SLEEP_OK = (1 << 1), 148 INTR_OK = (1 << 2), 149 150 /* flags understood by end_synchronized_op */ 151 LOCK_HELD = HOLD_LOCK, 152 }; 153 154 enum { 155 /* adapter flags. synch_op or adapter_lock. */ 156 FULL_INIT_DONE = (1 << 0), 157 FW_OK = (1 << 1), 158 CHK_MBOX_ACCESS = (1 << 2), 159 MASTER_PF = (1 << 3), 160 BUF_PACKING_OK = (1 << 6), 161 IS_VF = (1 << 7), 162 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 163 CXGBE_BUSY = (1 << 9), 164 165 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 166 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 167 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 168 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 169 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 170 171 /* port flags */ 172 HAS_TRACEQ = (1 << 3), 173 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 174 175 /* VI flags */ 176 VI_DETACHING = (1 << 0), 177 VI_INIT_DONE = (1 << 1), 178 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 179 TX_USES_VM_WR = (1 << 3), 180 VI_SKIP_STATS = (1 << 4), 181 182 /* adapter debug_flags */ 183 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 184 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 185 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 186 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 187 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 188 }; 189 190 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING) 191 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0) 192 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0) 193 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 194 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 195 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 196 197 struct vi_info { 198 device_t dev; 199 struct port_info *pi; 200 struct adapter *adapter; 201 202 if_t ifp; 203 struct pfil_head *pfil; 204 205 unsigned long flags; 206 int if_flags; 207 208 uint16_t *rss, *nm_rss; 209 uint16_t viid; /* opaque VI identifier */ 210 uint16_t smt_idx; 211 uint16_t vin; 212 uint8_t vfvld; 213 int16_t xact_addr_filt;/* index of exact MAC address filter */ 214 uint16_t rss_size; /* size of VI's RSS table slice */ 215 uint16_t rss_base; /* start of VI's RSS table slice */ 216 int hashen; 217 218 int nintr; 219 int first_intr; 220 221 /* These need to be int as they are used in sysctl */ 222 int ntxq; /* # of tx queues */ 223 int first_txq; /* index of first tx queue */ 224 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 225 int nrxq; /* # of rx queues */ 226 int first_rxq; /* index of first rx queue */ 227 int nofldtxq; /* # of offload tx queues */ 228 int first_ofld_txq; /* index of first offload tx queue */ 229 int nofldrxq; /* # of offload rx queues */ 230 int first_ofld_rxq; /* index of first offload rx queue */ 231 int nnmtxq; 232 int first_nm_txq; 233 int nnmrxq; 234 int first_nm_rxq; 235 int tmr_idx; 236 int ofld_tmr_idx; 237 int pktc_idx; 238 int ofld_pktc_idx; 239 int qsize_rxq; 240 int qsize_txq; 241 242 struct timeval last_refreshed; 243 struct fw_vi_stats_vf stats; 244 struct mtx tick_mtx; 245 struct callout tick; 246 247 struct sysctl_ctx_list ctx; 248 struct sysctl_oid *rxq_oid; 249 struct sysctl_oid *txq_oid; 250 struct sysctl_oid *nm_rxq_oid; 251 struct sysctl_oid *nm_txq_oid; 252 struct sysctl_oid *ofld_rxq_oid; 253 struct sysctl_oid *ofld_txq_oid; 254 255 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 256 u_int txq_rr; 257 u_int rxq_rr; 258 }; 259 260 struct tx_ch_rl_params { 261 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 262 uint32_t maxrate; 263 }; 264 265 /* CLRL state */ 266 enum clrl_state { 267 CS_UNINITIALIZED = 0, 268 CS_PARAMS_SET, /* sw parameters have been set. */ 269 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 270 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 271 CS_HW_CONFIGURED /* configured in the hardware. */ 272 }; 273 274 /* CLRL flags */ 275 enum { 276 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 277 }; 278 279 struct tx_cl_rl_params { 280 enum clrl_state state; 281 int refcount; 282 uint8_t flags; 283 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 284 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 285 enum fw_sched_params_mode mode; /* aggr or per-flow */ 286 uint32_t maxrate; 287 uint16_t pktsize; 288 uint16_t burstsize; 289 }; 290 291 /* Tx scheduler parameters for a channel/port */ 292 struct tx_sched_params { 293 /* Channel Rate Limiter */ 294 struct tx_ch_rl_params ch_rl; 295 296 /* Class WRR */ 297 /* XXX */ 298 299 /* Class Rate Limiter (including the default pktsize and burstsize). */ 300 int pktsize; 301 int burstsize; 302 struct tx_cl_rl_params cl_rl[]; 303 }; 304 305 struct port_info { 306 device_t dev; 307 struct adapter *adapter; 308 309 struct vi_info *vi; 310 int nvi; 311 int up_vis; 312 int uld_vis; 313 bool vxlan_tcam_entry; 314 315 struct tx_sched_params *sched_params; 316 317 struct mtx pi_lock; 318 char lockname[16]; 319 unsigned long flags; 320 321 uint8_t hw_port; /* associated hardware port idx */ 322 int8_t mdio_addr; 323 uint8_t port_type; 324 uint8_t mod_type; 325 uint8_t port_id; 326 uint8_t tx_chan; /* tx TP c-channel */ 327 uint8_t rx_chan; /* rx TP c-channel */ 328 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 329 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 330 331 struct link_config link_cfg; 332 struct ifmedia media; 333 334 struct port_stats stats; 335 u_int tnl_cong_drops; 336 u_int tx_parse_error; 337 int fcs_reg; 338 uint64_t fcs_base; 339 340 struct sysctl_ctx_list ctx; 341 }; 342 343 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 344 345 struct cluster_metadata { 346 uma_zone_t zone; 347 caddr_t cl; 348 u_int refcount; 349 }; 350 351 struct fl_sdesc { 352 caddr_t cl; 353 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 354 int16_t moff; /* offset of metadata from cl */ 355 uint8_t zidx; 356 }; 357 358 struct tx_desc { 359 __be64 flit[8]; 360 }; 361 362 struct tx_sdesc { 363 struct mbuf *m; /* m_nextpkt linked chain of frames */ 364 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 365 }; 366 367 368 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 369 struct iq_desc { 370 struct rss_header rss; 371 uint8_t cpl[IQ_PAD]; 372 struct rsp_ctrl rsp; 373 }; 374 #undef IQ_PAD 375 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 376 377 enum { 378 /* iq type */ 379 IQ_OTHER = FW_IQ_IQTYPE_OTHER, 380 IQ_ETH = FW_IQ_IQTYPE_NIC, 381 IQ_OFLD = FW_IQ_IQTYPE_OFLD, 382 383 /* iq flags */ 384 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 385 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 386 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 387 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 388 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 389 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 390 391 /* iq state */ 392 IQS_DISABLED = 0, 393 IQS_BUSY = 1, 394 IQS_IDLE = 2, 395 396 /* netmap related flags */ 397 NM_OFF = 0, 398 NM_ON = 1, 399 NM_BUSY = 2, 400 }; 401 402 enum { 403 CPL_COOKIE_RESERVED = 0, 404 CPL_COOKIE_FILTER, 405 CPL_COOKIE_DDP0, 406 CPL_COOKIE_DDP1, 407 CPL_COOKIE_TOM, 408 CPL_COOKIE_HASHFILTER, 409 CPL_COOKIE_ETHOFLD, 410 CPL_COOKIE_KERN_TLS, 411 412 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 413 }; 414 415 /* 416 * Crypto replies use the low bit in the 64-bit cookie of CPL_FW6_PLD as a 417 * CPL cookie to identify the sender/receiver. 418 */ 419 enum { 420 CPL_FW6_COOKIE_CCR = 0, 421 CPL_FW6_COOKIE_KTLS, 422 423 NUM_CPL_FW6_COOKIES = 2 /* Low bits of cookie value. */ 424 }; 425 426 _Static_assert(powerof2(NUM_CPL_FW6_COOKIES), 427 "NUM_CPL_FW6_COOKIES must be a power of 2"); 428 429 #define CPL_FW6_COOKIE_MASK (NUM_CPL_FW6_COOKIES - 1) 430 431 #define CPL_FW6_PLD_COOKIE(cpl) (be64toh((cpl)->data[1]) & ~CPL_FW6_COOKIE_MASK) 432 433 struct sge_iq; 434 struct rss_header; 435 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 436 struct mbuf *); 437 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 438 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 439 440 /* 441 * Ingress Queue: T4 is producer, driver is consumer. 442 */ 443 struct sge_iq { 444 uint16_t flags; 445 uint8_t qtype; 446 volatile int state; 447 struct adapter *adapter; 448 struct iq_desc *desc; /* KVA of descriptor ring */ 449 int8_t intr_pktc_idx; /* packet count threshold index */ 450 uint8_t gen; /* generation bit */ 451 uint8_t intr_params; /* interrupt holdoff parameters */ 452 int8_t cong_drop; /* congestion drop settings for the queue */ 453 uint16_t qsize; /* size (# of entries) of the queue */ 454 uint16_t sidx; /* index of the entry with the status page */ 455 uint16_t cidx; /* consumer index */ 456 uint16_t cntxt_id; /* SGE context id for the iq */ 457 uint16_t abs_id; /* absolute SGE id for the iq */ 458 int16_t intr_idx; /* interrupt used by the queue */ 459 460 STAILQ_ENTRY(sge_iq) link; 461 462 bus_dma_tag_t desc_tag; 463 bus_dmamap_t desc_map; 464 bus_addr_t ba; /* bus address of descriptor ring */ 465 }; 466 467 enum { 468 /* eq type */ 469 EQ_CTRL = 1, 470 EQ_ETH = 2, 471 EQ_OFLD = 3, 472 473 /* eq flags */ 474 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 475 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 476 EQ_ENABLED = (1 << 3), /* open for business */ 477 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 478 }; 479 480 /* Listed in order of preference. Update t4_sysctls too if you change these */ 481 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 482 483 /* 484 * Egress Queue: driver is producer, T4 is consumer. 485 * 486 * Note: A free list is an egress queue (driver produces the buffers and T4 487 * consumes them) but it's special enough to have its own struct (see sge_fl). 488 */ 489 struct sge_eq { 490 unsigned int flags; /* MUST be first */ 491 unsigned int cntxt_id; /* SGE context id for the eq */ 492 unsigned int abs_id; /* absolute SGE id for the eq */ 493 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 494 uint8_t doorbells; 495 uint8_t port_id; /* port_id of the port associated with the eq */ 496 uint8_t tx_chan; /* tx channel used by the eq */ 497 uint8_t hw_port; /* hw port used by the eq */ 498 struct mtx eq_lock; 499 500 struct tx_desc *desc; /* KVA of descriptor ring */ 501 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 502 u_int udb_qid; /* relative qid within the doorbell page */ 503 uint16_t sidx; /* index of the entry with the status page */ 504 uint16_t cidx; /* consumer idx (desc idx) */ 505 uint16_t pidx; /* producer idx (desc idx) */ 506 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 507 uint16_t dbidx; /* pidx of the most recent doorbell */ 508 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 509 volatile u_int equiq; /* EQUIQ outstanding */ 510 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 511 512 bus_dma_tag_t desc_tag; 513 bus_dmamap_t desc_map; 514 bus_addr_t ba; /* bus address of descriptor ring */ 515 char lockname[16]; 516 }; 517 518 struct rx_buf_info { 519 uma_zone_t zone; /* zone that this cluster comes from */ 520 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 521 * hwsize[hwidx1] = size1. No spare. */ 522 uint16_t size2; /* hwsize[hwidx2] = size2. 523 * spare in cluster = size1 - size2. */ 524 int8_t hwidx1; /* SGE bufsize idx for size1 */ 525 int8_t hwidx2; /* SGE bufsize idx for size2 */ 526 uint8_t type; /* EXT_xxx type of the cluster */ 527 }; 528 529 enum { 530 NUM_MEMWIN = 3, 531 532 MEMWIN0_APERTURE = 2048, 533 MEMWIN0_BASE = 0x1b800, 534 535 MEMWIN1_APERTURE = 32768, 536 MEMWIN1_BASE = 0x28000, 537 538 MEMWIN2_APERTURE_T4 = 65536, 539 MEMWIN2_BASE_T4 = 0x30000, 540 541 MEMWIN2_APERTURE_T5 = 128 * 1024, 542 MEMWIN2_BASE_T5 = 0x60000, 543 }; 544 545 struct memwin { 546 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 547 uint32_t mw_base; /* constant after setup_memwin */ 548 uint32_t mw_aperture; /* ditto */ 549 uint32_t mw_curpos; /* protected by mw_lock */ 550 }; 551 552 enum { 553 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 554 FL_DOOMED = (1 << 1), /* about to be destroyed */ 555 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 556 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 557 }; 558 559 #define FL_RUNNING_LOW(fl) \ 560 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 561 #define FL_NOT_RUNNING_LOW(fl) \ 562 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 563 564 struct sge_fl { 565 struct mtx fl_lock; 566 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 567 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 568 uint16_t zidx; /* refill zone idx */ 569 uint16_t safe_zidx; 570 uint16_t lowat; /* # of buffers <= this means fl needs help */ 571 int flags; 572 uint16_t buf_boundary; 573 574 /* The 16b idx all deal with hw descriptors */ 575 uint16_t dbidx; /* hw pidx after last doorbell */ 576 uint16_t sidx; /* index of status page */ 577 volatile uint16_t hw_cidx; 578 579 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 580 uint32_t cidx; /* consumer index */ 581 uint32_t pidx; /* producer index */ 582 583 uint32_t dbval; 584 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 585 volatile uint32_t *udb; 586 587 uint64_t cl_allocated; /* # of clusters allocated */ 588 uint64_t cl_recycled; /* # of clusters recycled */ 589 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 590 591 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 592 struct mbuf *m0; 593 struct mbuf **pnext; 594 u_int remaining; 595 596 uint16_t qsize; /* # of hw descriptors (status page included) */ 597 uint16_t cntxt_id; /* SGE context id for the freelist */ 598 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 599 bus_dma_tag_t desc_tag; 600 bus_dmamap_t desc_map; 601 char lockname[16]; 602 bus_addr_t ba; /* bus address of descriptor ring */ 603 }; 604 605 struct mp_ring; 606 607 struct txpkts { 608 uint8_t wr_type; /* type 0 or type 1 */ 609 uint8_t npkt; /* # of packets in this work request */ 610 uint8_t len16; /* # of 16B pieces used by this work request */ 611 uint8_t score; 612 uint8_t max_npkt; /* maximum number of packets allowed */ 613 uint16_t plen; /* total payload (sum of all packets) */ 614 615 /* straight from fw_eth_tx_pkts_vm_wr. */ 616 __u8 ethmacdst[6]; 617 __u8 ethmacsrc[6]; 618 __be16 ethtype; 619 __be16 vlantci; 620 621 struct mbuf *mb[15]; 622 }; 623 624 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 625 struct sge_txq { 626 struct sge_eq eq; /* MUST be first */ 627 628 if_t ifp; /* the interface this txq belongs to */ 629 struct mp_ring *r; /* tx software ring */ 630 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 631 struct sglist *gl; 632 __be32 cpl_ctrl0; /* for convenience */ 633 int tc_idx; /* traffic class */ 634 uint64_t last_tx; /* cycle count when eth_tx was last called */ 635 struct txpkts txp; 636 637 struct task tx_reclaim_task; 638 /* stats for common events first */ 639 640 uint64_t txcsum; /* # of times hardware assisted with checksum */ 641 uint64_t tso_wrs; /* # of TSO work requests */ 642 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 643 uint64_t imm_wrs; /* # of work requests with immediate data */ 644 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 645 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 646 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 647 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 648 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 649 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 650 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 651 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 652 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 653 uint64_t vxlan_txcsum; 654 655 uint64_t kern_tls_records; 656 uint64_t kern_tls_short; 657 uint64_t kern_tls_partial; 658 uint64_t kern_tls_full; 659 uint64_t kern_tls_octets; 660 uint64_t kern_tls_waste; 661 uint64_t kern_tls_header; 662 uint64_t kern_tls_fin_short; 663 uint64_t kern_tls_cbc; 664 uint64_t kern_tls_gcm; 665 union { 666 struct { 667 /* T6 only. */ 668 uint64_t kern_tls_options; 669 uint64_t kern_tls_fin; 670 }; 671 struct { 672 /* T7 only. */ 673 uint64_t kern_tls_ghash_received; 674 uint64_t kern_tls_ghash_requested; 675 uint64_t kern_tls_lso; 676 uint64_t kern_tls_partial_ghash; 677 uint64_t kern_tls_splitmode; 678 uint64_t kern_tls_trailer; 679 }; 680 }; 681 682 /* stats for not-that-common events */ 683 684 /* Optional scratch space for constructing work requests. */ 685 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 686 } __aligned(CACHE_LINE_SIZE); 687 688 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 689 struct sge_rxq { 690 struct sge_iq iq; /* MUST be first */ 691 struct sge_fl fl; /* MUST follow iq */ 692 693 if_t ifp; /* the interface this rxq belongs to */ 694 struct lro_ctrl lro; /* LRO state */ 695 696 /* stats for common events first */ 697 698 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 699 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 700 uint64_t vxlan_rxcsum; 701 702 /* stats for not-that-common events */ 703 704 } __aligned(CACHE_LINE_SIZE); 705 706 static inline struct sge_rxq * 707 iq_to_rxq(struct sge_iq *iq) 708 { 709 710 return (__containerof(iq, struct sge_rxq, iq)); 711 } 712 713 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 714 struct sge_ofld_rxq { 715 struct sge_iq iq; /* MUST be first */ 716 struct sge_fl fl; /* MUST follow iq */ 717 counter_u64_t rx_iscsi_ddp_setup_ok; 718 counter_u64_t rx_iscsi_ddp_setup_error; 719 uint64_t rx_iscsi_ddp_pdus; 720 uint64_t rx_iscsi_ddp_octets; 721 uint64_t rx_iscsi_fl_pdus; 722 uint64_t rx_iscsi_fl_octets; 723 uint64_t rx_iscsi_padding_errors; 724 uint64_t rx_iscsi_header_digest_errors; 725 uint64_t rx_iscsi_data_digest_errors; 726 uint64_t rx_aio_ddp_jobs; 727 uint64_t rx_aio_ddp_octets; 728 u_long rx_toe_tls_records; 729 u_long rx_toe_tls_octets; 730 u_long rx_toe_ddp_octets; 731 counter_u64_t ddp_buffer_alloc; 732 counter_u64_t ddp_buffer_reuse; 733 counter_u64_t ddp_buffer_free; 734 } __aligned(CACHE_LINE_SIZE); 735 736 static inline struct sge_ofld_rxq * 737 iq_to_ofld_rxq(struct sge_iq *iq) 738 { 739 740 return (__containerof(iq, struct sge_ofld_rxq, iq)); 741 } 742 743 struct wrqe { 744 STAILQ_ENTRY(wrqe) link; 745 struct sge_wrq *wrq; 746 int wr_len; 747 char wr[] __aligned(16); 748 }; 749 750 struct wrq_cookie { 751 TAILQ_ENTRY(wrq_cookie) link; 752 int ndesc; 753 int pidx; 754 }; 755 756 /* 757 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 758 * are of this type. 759 */ 760 struct sge_wrq { 761 struct sge_eq eq; /* MUST be first */ 762 763 struct adapter *adapter; 764 struct task wrq_tx_task; 765 766 /* Tx desc reserved but WR not "committed" yet. */ 767 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 768 769 /* List of WRs ready to go out as soon as descriptors are available. */ 770 STAILQ_HEAD(, wrqe) wr_list; 771 u_int nwr_pending; 772 u_int ndesc_needed; 773 774 /* stats for common events first */ 775 776 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 777 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 778 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 779 780 /* stats for not-that-common events */ 781 782 /* 783 * Scratch space for work requests that wrap around after reaching the 784 * status page, and some information about the last WR that used it. 785 */ 786 uint16_t ss_pidx; 787 uint16_t ss_len; 788 uint8_t ss[SGE_MAX_WR_LEN]; 789 790 } __aligned(CACHE_LINE_SIZE); 791 792 /* ofld_txq: SGE egress queue + miscellaneous items */ 793 struct sge_ofld_txq { 794 struct sge_wrq wrq; 795 counter_u64_t tx_iscsi_pdus; 796 counter_u64_t tx_iscsi_octets; 797 counter_u64_t tx_iscsi_iso_wrs; 798 counter_u64_t tx_aio_jobs; 799 counter_u64_t tx_aio_octets; 800 counter_u64_t tx_toe_tls_records; 801 counter_u64_t tx_toe_tls_octets; 802 } __aligned(CACHE_LINE_SIZE); 803 804 static inline int 805 ofld_txq_group(int val, int mask) 806 { 807 const uint32_t ngroup = 1 << bitcount32(mask); 808 const int mshift = ffs(mask) - 1; 809 const uint32_t gmask = ngroup - 1; 810 811 return (val >> mshift & gmask); 812 } 813 814 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 815 struct sge_nm_rxq { 816 /* Items used by the driver rx ithread are in this cacheline. */ 817 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 818 u_int nid; /* netmap ring # for this queue */ 819 struct vi_info *vi; 820 821 struct iq_desc *iq_desc; 822 uint16_t iq_abs_id; 823 uint16_t iq_cntxt_id; 824 uint16_t iq_cidx; 825 uint16_t iq_sidx; 826 uint8_t iq_gen; 827 uint32_t fl_sidx; 828 829 /* Items used by netmap rxsync are in this cacheline. */ 830 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 831 uint16_t fl_cntxt_id; 832 uint32_t fl_pidx; 833 uint32_t fl_sidx2; /* copy of fl_sidx */ 834 uint32_t fl_db_val; 835 u_int fl_db_saved; 836 u_int fl_db_threshold; /* in descriptors */ 837 u_int fl_hwidx:4; 838 839 /* 840 * fl_cidx is used by both the ithread and rxsync, the rest are not used 841 * in the rx fast path. 842 */ 843 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 844 845 bus_dma_tag_t iq_desc_tag; 846 bus_dmamap_t iq_desc_map; 847 bus_addr_t iq_ba; 848 int intr_idx; 849 850 bus_dma_tag_t fl_desc_tag; 851 bus_dmamap_t fl_desc_map; 852 bus_addr_t fl_ba; 853 }; 854 855 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 856 struct sge_nm_txq { 857 struct tx_desc *desc; 858 uint16_t cidx; 859 uint16_t pidx; 860 uint16_t sidx; 861 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 862 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 863 uint16_t dbidx; /* pidx of the most recent doorbell */ 864 uint8_t doorbells; 865 volatile uint32_t *udb; 866 u_int udb_qid; 867 u_int cntxt_id; 868 __be32 cpl_ctrl0; /* for convenience */ 869 __be32 op_pkd; /* ditto */ 870 u_int nid; /* netmap ring # for this queue */ 871 872 /* infrequently used items after this */ 873 874 bus_dma_tag_t desc_tag; 875 bus_dmamap_t desc_map; 876 bus_addr_t ba; 877 int iqidx; 878 } __aligned(CACHE_LINE_SIZE); 879 880 struct sge { 881 int nctrlq; /* total # of control queues */ 882 int nrxq; /* total # of Ethernet rx queues */ 883 int ntxq; /* total # of Ethernet tx queues */ 884 int nofldrxq; /* total # of TOE rx queues */ 885 int nofldtxq; /* total # of TOE tx queues */ 886 int nnmrxq; /* total # of netmap rx queues */ 887 int nnmtxq; /* total # of netmap tx queues */ 888 int niq; /* total # of ingress queues */ 889 int neq; /* total # of egress queues */ 890 891 struct sge_iq fwq; /* Firmware event queue */ 892 struct sge_wrq *ctrlq; /* Control queues */ 893 struct sge_txq *txq; /* NIC tx queues */ 894 struct sge_rxq *rxq; /* NIC rx queues */ 895 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 896 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 897 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 898 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 899 900 uint16_t iq_start; /* first cntxt_id */ 901 uint16_t iq_base; /* first abs_id */ 902 int eq_start; /* first cntxt_id */ 903 int eq_base; /* first abs_id */ 904 int iqmap_sz; 905 int eqmap_sz; 906 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 907 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 908 909 int8_t safe_zidx; 910 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 911 }; 912 913 struct devnames { 914 const char *nexus_name; 915 const char *ifnet_name; 916 const char *vi_ifnet_name; 917 const char *pf03_drv_name; 918 const char *vf_nexus_name; 919 const char *vf_ifnet_name; 920 }; 921 922 struct clip_entry; 923 924 #define CNT_CAL_INFO 3 925 struct clock_sync { 926 uint64_t hw_cur; 927 uint64_t hw_prev; 928 sbintime_t sbt_cur; 929 sbintime_t sbt_prev; 930 seqc_t gen; 931 }; 932 933 struct adapter { 934 SLIST_ENTRY(adapter) link; 935 device_t dev; 936 struct cdev *cdev; 937 const struct devnames *names; 938 939 /* PCIe register resources */ 940 int regs_rid; 941 struct resource *regs_res; 942 int msix_rid; 943 struct resource *msix_res; 944 bus_space_handle_t bh; 945 bus_space_tag_t bt; 946 bus_size_t mmio_len; 947 int udbs_rid; 948 struct resource *udbs_res; 949 volatile uint8_t *udbs_base; 950 951 unsigned int pf; 952 unsigned int mbox; 953 unsigned int vpd_busy; 954 unsigned int vpd_flag; 955 956 /* Interrupt information */ 957 int intr_type; 958 int intr_count; 959 struct irq { 960 struct resource *res; 961 int rid; 962 void *tag; 963 struct sge_rxq *rxq; 964 struct sge_nm_rxq *nm_rxq; 965 } __aligned(CACHE_LINE_SIZE) *irq; 966 int sge_gts_reg; 967 int sge_kdoorbell_reg; 968 969 bus_dma_tag_t dmat; /* Parent DMA tag */ 970 971 struct sge sge; 972 int lro_timeout; 973 int sc_do_rxcopy; 974 975 int vxlan_port; 976 u_int vxlan_refcount; 977 int rawf_base; 978 int nrawf; 979 u_int vlan_id; 980 981 struct taskqueue *tq[MAX_NPORTS]; /* General purpose taskqueues */ 982 struct port_info *port[MAX_NPORTS]; 983 uint8_t chan_map[MAX_NCHAN]; /* tx_chan -> port_id */ 984 uint8_t port_map[MAX_NPORTS]; /* hw_port -> port_id */ 985 986 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 987 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 988 u_long clip_mask; 989 int clip_gen; 990 struct timeout_task clip_task; 991 992 void *tom_softc; /* (struct tom_data *) */ 993 struct tom_tunables tt; 994 struct t4_offload_policy *policy; 995 struct rwlock policy_lock; 996 997 void *iwarp_softc; /* (struct c4iw_dev *) */ 998 struct iw_tunables iwt; 999 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 1000 struct l2t_data *l2t; /* L2 table */ 1001 struct smt_data *smt; /* Source MAC Table */ 1002 struct tid_info tids; 1003 vmem_t *key_map; 1004 struct tls_tunables tlst; 1005 1006 vmem_t *pbl_arena; 1007 vmem_t *stag_arena; 1008 1009 uint8_t doorbells; 1010 int offload_map; /* port_id's with IFCAP_TOE enabled */ 1011 int bt_map; /* hw_port's that are BASE-T */ 1012 int active_ulds; /* ULDs activated on this adapter */ 1013 int flags; 1014 int debug_flags; 1015 int error_flags; /* Used by error handler and live reset. */ 1016 1017 char ifp_lockname[16]; 1018 struct mtx ifp_lock; 1019 if_t ifp; /* tracer ifp */ 1020 struct ifmedia media; 1021 int traceq; /* iq used by all tracers, -1 if none */ 1022 int tracer_valid; /* bitmap of valid tracers */ 1023 int tracer_enabled; /* bitmap of enabled tracers */ 1024 1025 char fw_version[16]; 1026 char tp_version[16]; 1027 char er_version[16]; 1028 char bs_version[16]; 1029 char cfg_file[32]; 1030 u_int cfcsum; 1031 struct adapter_params params; 1032 const struct chip_params *chip_params; 1033 struct t4_virt_res vres; 1034 1035 uint16_t nbmcaps; 1036 uint16_t linkcaps; 1037 uint16_t switchcaps; 1038 uint16_t nvmecaps; 1039 uint16_t niccaps; 1040 uint16_t toecaps; 1041 uint16_t rdmacaps; 1042 uint16_t cryptocaps; 1043 uint16_t iscsicaps; 1044 uint16_t fcoecaps; 1045 1046 struct sysctl_ctx_list ctx; 1047 struct sysctl_oid *ctrlq_oid; 1048 struct sysctl_oid *fwq_oid; 1049 1050 struct mtx sc_lock; 1051 char lockname[16]; 1052 1053 /* Starving free lists */ 1054 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 1055 TAILQ_HEAD(, sge_fl) sfl; 1056 struct callout sfl_callout; 1057 struct callout cal_callout; 1058 struct clock_sync cal_info[CNT_CAL_INFO]; 1059 int cal_current; 1060 int cal_count; 1061 uint32_t cal_gen; 1062 1063 /* 1064 * Driver code that can run when the adapter is suspended must use this 1065 * lock or a synchronized_op and check for HW_OFF_LIMITS before 1066 * accessing hardware. 1067 * 1068 * XXX: could be changed to rwlock. wlock in suspend/resume and for 1069 * indirect register access, rlock everywhere else. 1070 */ 1071 struct mtx reg_lock; 1072 1073 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 1074 1075 struct mtx tc_lock; 1076 struct task tc_task; 1077 1078 struct task fatal_error_task; 1079 struct task reset_task; 1080 const void *reset_thread; 1081 int num_resets; 1082 int incarnation; 1083 1084 const char *last_op; 1085 const void *last_op_thr; 1086 int last_op_flags; 1087 1088 int swintr; 1089 int sensor_resets; 1090 1091 struct callout ktls_tick; 1092 }; 1093 1094 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1095 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1096 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1097 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1098 1099 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1100 KASSERT(IS_BUSY(sc) && \ 1101 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1102 ("%s: operation not synchronized.", __func__)) 1103 1104 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1105 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1106 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1107 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1108 1109 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1110 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1111 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1112 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1113 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1114 1115 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1116 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1117 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1118 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1119 1120 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1121 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1122 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1123 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1124 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1125 1126 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1127 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1128 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1129 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1130 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1131 1132 #define for_each_txq(vi, iter, q) \ 1133 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1134 iter < vi->ntxq; ++iter, ++q) 1135 #define for_each_rxq(vi, iter, q) \ 1136 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1137 iter < vi->nrxq; ++iter, ++q) 1138 #define for_each_ofld_txq(vi, iter, q) \ 1139 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1140 iter < vi->nofldtxq; ++iter, ++q) 1141 #define for_each_ofld_rxq(vi, iter, q) \ 1142 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1143 iter < vi->nofldrxq; ++iter, ++q) 1144 #define for_each_nm_txq(vi, iter, q) \ 1145 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1146 iter < vi->nnmtxq; ++iter, ++q) 1147 #define for_each_nm_rxq(vi, iter, q) \ 1148 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1149 iter < vi->nnmrxq; ++iter, ++q) 1150 #define for_each_vi(_pi, _iter, _vi) \ 1151 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1152 ++(_iter), ++(_vi)) 1153 1154 #define IDXINCR(idx, incr, wrap) do { \ 1155 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1156 } while (0) 1157 #define IDXDIFF(head, tail, wrap) \ 1158 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1159 1160 /* One for errors, one for firmware events */ 1161 #define T4_EXTRA_INTR 2 1162 1163 /* One for firmware events */ 1164 #define T4VF_EXTRA_INTR 1 1165 1166 static inline int 1167 forwarding_intr_to_fwq(struct adapter *sc) 1168 { 1169 1170 return (sc->intr_count == 1); 1171 } 1172 1173 /* Works reliably inside a synch_op or with reg_lock held. */ 1174 static inline bool 1175 hw_off_limits(struct adapter *sc) 1176 { 1177 const int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1178 1179 return (__predict_false(off_limits != 0)); 1180 } 1181 1182 /* Works reliably inside a synch_op or with reg_lock held. */ 1183 static inline bool 1184 hw_all_ok(struct adapter *sc) 1185 { 1186 const int not_ok = atomic_load_int(&sc->error_flags) & 1187 (ADAP_STOPPED | HW_OFF_LIMITS); 1188 1189 return (__predict_true(not_ok == 0)); 1190 } 1191 1192 static inline int 1193 mbuf_nsegs(struct mbuf *m) 1194 { 1195 M_ASSERTPKTHDR(m); 1196 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 1197 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1198 1199 return (m->m_pkthdr.inner_l5hlen); 1200 } 1201 1202 static inline void 1203 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1204 { 1205 M_ASSERTPKTHDR(m); 1206 m->m_pkthdr.inner_l5hlen = nsegs; 1207 } 1208 1209 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 1210 #define MC_NOMAP 0x01 1211 #define MC_RAW_WR 0x02 1212 #define MC_TLS 0x04 1213 1214 static inline int 1215 mbuf_cflags(struct mbuf *m) 1216 { 1217 M_ASSERTPKTHDR(m); 1218 return (m->m_pkthdr.PH_loc.eight[4]); 1219 } 1220 1221 static inline void 1222 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 1223 { 1224 M_ASSERTPKTHDR(m); 1225 m->m_pkthdr.PH_loc.eight[4] = flags; 1226 } 1227 1228 static inline int 1229 mbuf_len16(struct mbuf *m) 1230 { 1231 int n; 1232 1233 M_ASSERTPKTHDR(m); 1234 n = m->m_pkthdr.PH_loc.eight[0]; 1235 if (!(mbuf_cflags(m) & MC_TLS)) 1236 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1237 1238 return (n); 1239 } 1240 1241 static inline void 1242 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1243 { 1244 M_ASSERTPKTHDR(m); 1245 if (!(mbuf_cflags(m) & MC_TLS)) 1246 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 1247 m->m_pkthdr.PH_loc.eight[0] = len16; 1248 } 1249 1250 static inline uint32_t 1251 t4_read_reg(struct adapter *sc, uint32_t reg) 1252 { 1253 if (hw_off_limits(sc)) 1254 MPASS(curthread == sc->reset_thread); 1255 return bus_space_read_4(sc->bt, sc->bh, reg); 1256 } 1257 1258 static inline void 1259 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1260 { 1261 if (hw_off_limits(sc)) 1262 MPASS(curthread == sc->reset_thread); 1263 bus_space_write_4(sc->bt, sc->bh, reg, val); 1264 } 1265 1266 static inline uint64_t 1267 t4_read_reg64(struct adapter *sc, uint32_t reg) 1268 { 1269 if (hw_off_limits(sc)) 1270 MPASS(curthread == sc->reset_thread); 1271 #ifdef __LP64__ 1272 return bus_space_read_8(sc->bt, sc->bh, reg); 1273 #else 1274 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1275 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1276 1277 #endif 1278 } 1279 1280 static inline void 1281 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1282 { 1283 if (hw_off_limits(sc)) 1284 MPASS(curthread == sc->reset_thread); 1285 #ifdef __LP64__ 1286 bus_space_write_8(sc->bt, sc->bh, reg, val); 1287 #else 1288 bus_space_write_4(sc->bt, sc->bh, reg, val); 1289 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1290 #endif 1291 } 1292 1293 static inline void 1294 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1295 { 1296 if (hw_off_limits(sc)) 1297 MPASS(curthread == sc->reset_thread); 1298 *val = pci_read_config(sc->dev, reg, 1); 1299 } 1300 1301 static inline void 1302 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1303 { 1304 if (hw_off_limits(sc)) 1305 MPASS(curthread == sc->reset_thread); 1306 pci_write_config(sc->dev, reg, val, 1); 1307 } 1308 1309 static inline void 1310 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1311 { 1312 1313 if (hw_off_limits(sc)) 1314 MPASS(curthread == sc->reset_thread); 1315 *val = pci_read_config(sc->dev, reg, 2); 1316 } 1317 1318 static inline void 1319 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1320 { 1321 if (hw_off_limits(sc)) 1322 MPASS(curthread == sc->reset_thread); 1323 pci_write_config(sc->dev, reg, val, 2); 1324 } 1325 1326 static inline void 1327 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1328 { 1329 if (hw_off_limits(sc)) 1330 MPASS(curthread == sc->reset_thread); 1331 *val = pci_read_config(sc->dev, reg, 4); 1332 } 1333 1334 static inline void 1335 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1336 { 1337 if (hw_off_limits(sc)) 1338 MPASS(curthread == sc->reset_thread); 1339 pci_write_config(sc->dev, reg, val, 4); 1340 } 1341 1342 static inline struct port_info * 1343 adap2pinfo(struct adapter *sc, int idx) 1344 { 1345 1346 return (sc->port[idx]); 1347 } 1348 1349 static inline void 1350 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1351 { 1352 1353 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1354 } 1355 1356 static inline int 1357 tx_resume_threshold(struct sge_eq *eq) 1358 { 1359 1360 /* not quite the same as qsize / 4, but this will do. */ 1361 return (eq->sidx / 4); 1362 } 1363 1364 static inline int 1365 t4_use_ldst(struct adapter *sc) 1366 { 1367 1368 #ifdef notyet 1369 return (sc->flags & FW_OK || !sc->use_bd); 1370 #else 1371 return (0); 1372 #endif 1373 } 1374 1375 static inline void 1376 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1377 const char *msg, const __be64 *const p, const bool err) 1378 { 1379 1380 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1381 return; 1382 if (p != NULL) { 1383 log(err ? LOG_ERR : LOG_DEBUG, 1384 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1385 "%016llx %016llx %016llx %016llx\n", 1386 device_get_nameunit(sc->dev), mbox, msg, 1387 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1388 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1389 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1390 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1391 } else { 1392 log(err ? LOG_ERR : LOG_DEBUG, 1393 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1394 "%016llx %016llx %016llx %016llx\n", 1395 device_get_nameunit(sc->dev), mbox, msg, 1396 (long long)t4_read_reg64(sc, reg), 1397 (long long)t4_read_reg64(sc, reg + 8), 1398 (long long)t4_read_reg64(sc, reg + 16), 1399 (long long)t4_read_reg64(sc, reg + 24), 1400 (long long)t4_read_reg64(sc, reg + 32), 1401 (long long)t4_read_reg64(sc, reg + 40), 1402 (long long)t4_read_reg64(sc, reg + 48), 1403 (long long)t4_read_reg64(sc, reg + 56)); 1404 } 1405 } 1406 1407 /* t4_main.c */ 1408 extern int t4_ntxq; 1409 extern int t4_nrxq; 1410 extern int t4_intr_types; 1411 extern int t4_tmr_idx; 1412 extern int t4_pktc_idx; 1413 extern unsigned int t4_qsize_rxq; 1414 extern unsigned int t4_qsize_txq; 1415 extern int t4_ddp_rcvbuf_len; 1416 extern unsigned int t4_ddp_rcvbuf_cache; 1417 extern device_method_t cxgbe_methods[]; 1418 1419 int t4_os_find_pci_capability(struct adapter *, int); 1420 void t4_os_portmod_changed(struct port_info *); 1421 void t4_os_link_changed(struct port_info *); 1422 void t4_iterate(void (*)(struct adapter *, void *), void *); 1423 void t4_init_devnames(struct adapter *); 1424 void t4_add_adapter(struct adapter *); 1425 int t4_detach_common(device_t); 1426 int t4_map_bars_0_and_4(struct adapter *); 1427 int t4_map_bar_2(struct adapter *); 1428 int t4_adj_doorbells(struct adapter *); 1429 int t4_setup_intr_handlers(struct adapter *); 1430 void t4_sysctls(struct adapter *); 1431 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1432 void end_synchronized_op(struct adapter *, int); 1433 void begin_vi_detach(struct adapter *, struct vi_info *); 1434 void end_vi_detach(struct adapter *, struct vi_info *); 1435 int update_mac_settings(if_t, int); 1436 int adapter_init(struct adapter *); 1437 int vi_init(struct vi_info *); 1438 void vi_sysctls(struct vi_info *); 1439 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1440 int alloc_atid(struct adapter *, void *); 1441 void *lookup_atid(struct adapter *, int); 1442 void free_atid(struct adapter *, int); 1443 void release_tid(struct adapter *, int, struct sge_wrq *); 1444 int cxgbe_media_change(if_t); 1445 void cxgbe_media_status(if_t, struct ifmediareq *); 1446 void t4_os_cim_err(struct adapter *); 1447 int suspend_adapter(struct adapter *); 1448 int resume_adapter(struct adapter *); 1449 int toe_capability(struct vi_info *, bool); 1450 1451 #ifdef KERN_TLS 1452 /* t6_kern_tls.c */ 1453 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1454 struct m_snd_tag **); 1455 void t6_ktls_modload(void); 1456 void t6_ktls_modunload(void); 1457 int t6_ktls_try(if_t, struct socket *, struct ktls_session *); 1458 int t6_ktls_parse_pkt(struct mbuf *); 1459 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1460 1461 /* t7_kern_tls.c */ 1462 int t7_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1463 struct m_snd_tag **); 1464 void t7_ktls_modload(void); 1465 void t7_ktls_modunload(void); 1466 int t7_ktls_parse_pkt(struct mbuf *); 1467 int t7_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1468 #endif 1469 1470 /* t4_keyctx.c */ 1471 struct auth_hash; 1472 union authctx; 1473 #ifdef KERN_TLS 1474 struct ktls_session; 1475 struct tls_key_req; 1476 struct tls_keyctx; 1477 #endif 1478 1479 void t4_aes_getdeckey(void *, const void *, unsigned int); 1480 void t4_copy_partial_hash(int, union authctx *, void *); 1481 void t4_init_gmac_hash(const char *, int, char *); 1482 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1483 char *); 1484 #ifdef KERN_TLS 1485 u_int t4_tls_key_info_size(const struct ktls_session *); 1486 int t4_tls_proto_ver(const struct ktls_session *); 1487 int t4_tls_cipher_mode(const struct ktls_session *); 1488 int t4_tls_auth_mode(const struct ktls_session *); 1489 int t4_tls_hmac_ctrl(const struct ktls_session *); 1490 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1491 int t4_alloc_tls_keyid(struct adapter *); 1492 void t4_free_tls_keyid(struct adapter *, int); 1493 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1494 struct tls_key_req *); 1495 #endif 1496 1497 #ifdef DEV_NETMAP 1498 /* t4_netmap.c */ 1499 struct sge_nm_rxq; 1500 void cxgbe_nm_attach(struct vi_info *); 1501 void cxgbe_nm_detach(struct vi_info *); 1502 void service_nm_rxq(struct sge_nm_rxq *); 1503 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1504 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1505 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1506 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1507 #endif 1508 1509 /* t4_sge.c */ 1510 void t4_sge_modload(void); 1511 void t4_sge_modunload(void); 1512 uint64_t t4_sge_extfree_refs(void); 1513 void t4_tweak_chip_settings(struct adapter *); 1514 int t4_verify_chip_settings(struct adapter *); 1515 void t4_init_rx_buf_info(struct adapter *); 1516 int t4_create_dma_tag(struct adapter *); 1517 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1518 struct sysctl_oid_list *); 1519 int t4_destroy_dma_tag(struct adapter *); 1520 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1521 bus_addr_t *, void **); 1522 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1523 void *); 1524 void free_fl_buffers(struct adapter *, struct sge_fl *); 1525 int t4_setup_adapter_queues(struct adapter *); 1526 int t4_teardown_adapter_queues(struct adapter *); 1527 int t4_setup_vi_queues(struct vi_info *); 1528 int t4_teardown_vi_queues(struct vi_info *); 1529 void t4_intr_all(void *); 1530 void t4_intr(void *); 1531 #ifdef DEV_NETMAP 1532 void t4_nm_intr(void *); 1533 void t4_vi_intr(void *); 1534 #endif 1535 void t4_intr_err(void *); 1536 void t4_intr_evt(void *); 1537 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1538 void t4_update_fl_bufsize(if_t); 1539 struct mbuf *alloc_wr_mbuf(int, int); 1540 int parse_pkt(struct mbuf **, bool); 1541 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1542 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1543 int t4_sge_set_conm_context(struct adapter *, int, int, int); 1544 void t4_register_an_handler(an_handler_t); 1545 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1546 void t4_register_cpl_handler(int, cpl_handler_t); 1547 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1548 #ifdef RATELIMIT 1549 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1550 #endif 1551 1552 /* t4_tracer.c */ 1553 struct t4_tracer; 1554 void t4_tracer_modload(void); 1555 void t4_tracer_modunload(void); 1556 void t4_tracer_port_detach(struct adapter *); 1557 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1558 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1559 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1560 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1561 1562 /* t4_sched.c */ 1563 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1564 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1565 int t4_init_tx_sched(struct adapter *); 1566 int t4_free_tx_sched(struct adapter *); 1567 void t4_update_tx_sched(struct adapter *); 1568 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1569 void t4_release_cl_rl(struct adapter *, int, int); 1570 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1571 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1572 #ifdef RATELIMIT 1573 void t4_init_etid_table(struct adapter *); 1574 void t4_free_etid_table(struct adapter *); 1575 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1576 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1577 struct m_snd_tag **); 1578 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1579 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *); 1580 #endif 1581 1582 /* t4_filter.c */ 1583 int get_filter_mode(struct adapter *, uint32_t *); 1584 int set_filter_mode(struct adapter *, uint32_t); 1585 int set_filter_mask(struct adapter *, uint32_t); 1586 int get_filter(struct adapter *, struct t4_filter *); 1587 int set_filter(struct adapter *, struct t4_filter *); 1588 int del_filter(struct adapter *, struct t4_filter *); 1589 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1590 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1591 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1592 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1593 void free_hftid_hash(struct tid_info *); 1594 1595 /* t4_tpt.c */ 1596 #define T4_STAG_UNSET 0xffffffff 1597 #define T4_WRITE_MEM_DMA_LEN \ 1598 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_sgl), 16) 1599 #define T4_ULPTX_MIN_IO 32 1600 #define T4_MAX_INLINE_SIZE 96 1601 #define T4_WRITE_MEM_INLINE_LEN(len) \ 1602 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_idata) + \ 1603 roundup((len), T4_ULPTX_MIN_IO), 16) 1604 1605 uint32_t t4_pblpool_alloc(struct adapter *, int); 1606 void t4_pblpool_free(struct adapter *, uint32_t, int); 1607 uint32_t t4_stag_alloc(struct adapter *, int); 1608 void t4_stag_free(struct adapter *, uint32_t, int); 1609 void t4_init_tpt(struct adapter *); 1610 void t4_free_tpt(struct adapter *); 1611 void t4_write_mem_dma_wr(struct adapter *, void *, int, int, uint32_t, 1612 uint32_t, vm_paddr_t, uint64_t); 1613 void t4_write_mem_inline_wr(struct adapter *, void *, int, int, uint32_t, 1614 uint32_t, void *, uint64_t); 1615 1616 static inline struct wrqe * 1617 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1618 { 1619 int len = offsetof(struct wrqe, wr) + wr_len; 1620 struct wrqe *wr; 1621 1622 wr = malloc(len, M_CXGBE, M_NOWAIT); 1623 if (__predict_false(wr == NULL)) 1624 return (NULL); 1625 wr->wr_len = wr_len; 1626 wr->wrq = wrq; 1627 return (wr); 1628 } 1629 1630 static inline void * 1631 wrtod(struct wrqe *wr) 1632 { 1633 return (&wr->wr[0]); 1634 } 1635 1636 static inline void 1637 free_wrqe(struct wrqe *wr) 1638 { 1639 free(wr, M_CXGBE); 1640 } 1641 1642 static inline void 1643 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1644 { 1645 struct sge_wrq *wrq = wr->wrq; 1646 1647 TXQ_LOCK(wrq); 1648 if (__predict_true(wrq->eq.flags & EQ_HW_ALLOCATED)) 1649 t4_wrq_tx_locked(sc, wrq, wr); 1650 else 1651 free(wr, M_CXGBE); 1652 TXQ_UNLOCK(wrq); 1653 } 1654 1655 static inline int 1656 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1657 int len) 1658 { 1659 1660 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1661 } 1662 1663 static inline int 1664 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1665 const uint32_t *val, int len) 1666 { 1667 1668 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1669 } 1670 1671 /* Number of len16 -> number of descriptors */ 1672 static inline int 1673 tx_len16_to_desc(int len16) 1674 { 1675 1676 return (howmany(len16, EQ_ESIZE / 16)); 1677 } 1678 #endif 1679