1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17 #if defined(__FreeBSD__)
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/etherdevice.h>
21 #include <linux/rcupdate.h>
22 #include <linux/lockdep.h>
23 #include <linux/seq_file.h>
24 #include <linux/leds.h>
25 #endif
26
27 #include "util.h"
28
29 #define RTW_MAX_MAC_ID_NUM 32
30 #define RTW_MAX_SEC_CAM_NUM 32
31 #define MAX_PG_CAM_BACKUP_NUM 8
32
33 #define RTW_SCAN_MAX_SSIDS 4
34
35 #define RTW_MAX_PATTERN_NUM 12
36 #define RTW_MAX_PATTERN_MASK_SIZE 16
37 #define RTW_MAX_PATTERN_SIZE 128
38
39 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
40
41 #define RFREG_MASK 0xfffff
42 #define INV_RF_DATA 0xffffffff
43 #define TX_PAGE_SIZE_SHIFT 7
44 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
45
46 #define RTW_CHANNEL_WIDTH_MAX 3
47 #define RTW_RF_PATH_MAX 4
48 #define HW_FEATURE_LEN 13
49
50 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
51
52 extern bool rtw_bf_support;
53 extern bool rtw_disable_lps_deep_mode;
54 extern unsigned int rtw_debug_mask;
55 extern bool rtw_edcca_enabled;
56 extern const struct ieee80211_ops rtw_ops;
57
58 #define RTW_MAX_CHANNEL_NUM_2G 14
59 #define RTW_MAX_CHANNEL_NUM_5G 49
60
61 struct rtw_dev;
62 struct rtw_debugfs;
63
64 enum rtw_hci_type {
65 RTW_HCI_TYPE_PCIE,
66 RTW_HCI_TYPE_USB,
67 RTW_HCI_TYPE_SDIO,
68
69 RTW_HCI_TYPE_UNDEFINE,
70 };
71
72 struct rtw_hci {
73 const struct rtw_hci_ops *ops;
74 enum rtw_hci_type type;
75
76 u32 rpwm_addr;
77 u32 cpwm_addr;
78
79 u8 bulkout_num;
80 };
81
82 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
83 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
84 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
85 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
86
87 #define IS_CH_5G_BAND_MID(channel) \
88 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
89
90 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
91 #define IS_CH_5G_BAND(channel) \
92 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
93 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
94
95 enum rtw_supported_band {
96 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
97 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
98 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
99 };
100
101 /* now, support up to 80M bw */
102 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
103
104 enum rtw_bandwidth {
105 RTW_CHANNEL_WIDTH_20 = 0,
106 RTW_CHANNEL_WIDTH_40 = 1,
107 RTW_CHANNEL_WIDTH_80 = 2,
108 RTW_CHANNEL_WIDTH_160 = 3,
109 RTW_CHANNEL_WIDTH_80_80 = 4,
110 RTW_CHANNEL_WIDTH_5 = 5,
111 RTW_CHANNEL_WIDTH_10 = 6,
112 };
113
114 enum rtw_sc_offset {
115 RTW_SC_DONT_CARE = 0,
116 RTW_SC_20_UPPER = 1,
117 RTW_SC_20_LOWER = 2,
118 RTW_SC_20_UPMOST = 3,
119 RTW_SC_20_LOWEST = 4,
120 RTW_SC_40_UPPER = 9,
121 RTW_SC_40_LOWER = 10,
122 };
123
124 enum rtw_net_type {
125 RTW_NET_NO_LINK = 0,
126 RTW_NET_AD_HOC = 1,
127 RTW_NET_MGD_LINKED = 2,
128 RTW_NET_AP_MODE = 3,
129 };
130
131 enum rtw_rf_type {
132 RF_1T1R = 0,
133 RF_1T2R = 1,
134 RF_2T2R = 2,
135 RF_2T3R = 3,
136 RF_2T4R = 4,
137 RF_3T3R = 5,
138 RF_3T4R = 6,
139 RF_4T4R = 7,
140 RF_TYPE_MAX,
141 };
142
143 enum rtw_rf_path {
144 RF_PATH_A = 0,
145 RF_PATH_B = 1,
146 RF_PATH_C = 2,
147 RF_PATH_D = 3,
148 };
149
150 enum rtw_bb_path {
151 BB_PATH_A = BIT(0),
152 BB_PATH_B = BIT(1),
153 BB_PATH_C = BIT(2),
154 BB_PATH_D = BIT(3),
155
156 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
157 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
158 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
159 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
160 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
161 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
162
163 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
164 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
165 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
166 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
167
168 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
169 };
170
171 enum rtw_rate_section {
172 RTW_RATE_SECTION_CCK = 0,
173 RTW_RATE_SECTION_OFDM,
174 RTW_RATE_SECTION_HT_1S,
175 RTW_RATE_SECTION_HT_2S,
176 RTW_RATE_SECTION_VHT_1S,
177 RTW_RATE_SECTION_VHT_2S,
178 __RTW_RATE_SECTION_2SS_MAX = RTW_RATE_SECTION_VHT_2S,
179 RTW_RATE_SECTION_HT_3S,
180 RTW_RATE_SECTION_HT_4S,
181 RTW_RATE_SECTION_VHT_3S,
182 RTW_RATE_SECTION_VHT_4S,
183
184 /* keep last */
185 RTW_RATE_SECTION_NUM,
186 };
187
188 enum rtw_wireless_set {
189 WIRELESS_CCK = 0x00000001,
190 WIRELESS_OFDM = 0x00000002,
191 WIRELESS_HT = 0x00000004,
192 WIRELESS_VHT = 0x00000008,
193 };
194
195 #define HT_STBC_EN BIT(0)
196 #define VHT_STBC_EN BIT(1)
197 #define HT_LDPC_EN BIT(0)
198 #define VHT_LDPC_EN BIT(1)
199
200 enum rtw_chip_type {
201 RTW_CHIP_TYPE_8822B,
202 RTW_CHIP_TYPE_8822C,
203 RTW_CHIP_TYPE_8723D,
204 RTW_CHIP_TYPE_8821C,
205 RTW_CHIP_TYPE_8703B,
206 RTW_CHIP_TYPE_8821A,
207 RTW_CHIP_TYPE_8812A,
208 RTW_CHIP_TYPE_8814A,
209 };
210
211 enum rtw_tx_queue_type {
212 /* the order of AC queues matters */
213 RTW_TX_QUEUE_BK = 0x0,
214 RTW_TX_QUEUE_BE = 0x1,
215 RTW_TX_QUEUE_VI = 0x2,
216 RTW_TX_QUEUE_VO = 0x3,
217
218 RTW_TX_QUEUE_BCN = 0x4,
219 RTW_TX_QUEUE_MGMT = 0x5,
220 RTW_TX_QUEUE_HI0 = 0x6,
221 RTW_TX_QUEUE_H2C = 0x7,
222 /* keep it last */
223 RTK_MAX_TX_QUEUE_NUM
224 };
225
226 enum rtw_rx_queue_type {
227 RTW_RX_QUEUE_MPDU = 0x0,
228 RTW_RX_QUEUE_C2H = 0x1,
229 /* keep it last */
230 RTK_MAX_RX_QUEUE_NUM
231 };
232
233 enum rtw_fw_type {
234 RTW_NORMAL_FW = 0x0,
235 RTW_WOWLAN_FW = 0x1,
236 };
237
238 enum rtw_rate_index {
239 RTW_RATEID_BGN_40M_2SS = 0,
240 RTW_RATEID_BGN_40M_1SS = 1,
241 RTW_RATEID_BGN_20M_2SS = 2,
242 RTW_RATEID_BGN_20M_1SS = 3,
243 RTW_RATEID_GN_N2SS = 4,
244 RTW_RATEID_GN_N1SS = 5,
245 RTW_RATEID_BG = 6,
246 RTW_RATEID_G = 7,
247 RTW_RATEID_B_20M = 8,
248 RTW_RATEID_ARFR0_AC_2SS = 9,
249 RTW_RATEID_ARFR1_AC_1SS = 10,
250 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
251 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
252 RTW_RATEID_ARFR4_AC_3SS = 13,
253 RTW_RATEID_ARFR5_N_3SS = 14,
254 RTW_RATEID_ARFR7_N_4SS = 15,
255 RTW_RATEID_ARFR6_AC_4SS = 16
256 };
257
258 enum rtw_trx_desc_rate {
259 DESC_RATE1M = 0x00,
260 DESC_RATE2M = 0x01,
261 DESC_RATE5_5M = 0x02,
262 DESC_RATE11M = 0x03,
263
264 DESC_RATE6M = 0x04,
265 DESC_RATE9M = 0x05,
266 DESC_RATE12M = 0x06,
267 DESC_RATE18M = 0x07,
268 DESC_RATE24M = 0x08,
269 DESC_RATE36M = 0x09,
270 DESC_RATE48M = 0x0a,
271 DESC_RATE54M = 0x0b,
272
273 DESC_RATEMCS0 = 0x0c,
274 DESC_RATEMCS1 = 0x0d,
275 DESC_RATEMCS2 = 0x0e,
276 DESC_RATEMCS3 = 0x0f,
277 DESC_RATEMCS4 = 0x10,
278 DESC_RATEMCS5 = 0x11,
279 DESC_RATEMCS6 = 0x12,
280 DESC_RATEMCS7 = 0x13,
281 DESC_RATEMCS8 = 0x14,
282 DESC_RATEMCS9 = 0x15,
283 DESC_RATEMCS10 = 0x16,
284 DESC_RATEMCS11 = 0x17,
285 DESC_RATEMCS12 = 0x18,
286 DESC_RATEMCS13 = 0x19,
287 DESC_RATEMCS14 = 0x1a,
288 DESC_RATEMCS15 = 0x1b,
289 DESC_RATEMCS16 = 0x1c,
290 DESC_RATEMCS17 = 0x1d,
291 DESC_RATEMCS18 = 0x1e,
292 DESC_RATEMCS19 = 0x1f,
293 DESC_RATEMCS20 = 0x20,
294 DESC_RATEMCS21 = 0x21,
295 DESC_RATEMCS22 = 0x22,
296 DESC_RATEMCS23 = 0x23,
297 DESC_RATEMCS24 = 0x24,
298 DESC_RATEMCS25 = 0x25,
299 DESC_RATEMCS26 = 0x26,
300 DESC_RATEMCS27 = 0x27,
301 DESC_RATEMCS28 = 0x28,
302 DESC_RATEMCS29 = 0x29,
303 DESC_RATEMCS30 = 0x2a,
304 DESC_RATEMCS31 = 0x2b,
305
306 DESC_RATEVHT1SS_MCS0 = 0x2c,
307 DESC_RATEVHT1SS_MCS1 = 0x2d,
308 DESC_RATEVHT1SS_MCS2 = 0x2e,
309 DESC_RATEVHT1SS_MCS3 = 0x2f,
310 DESC_RATEVHT1SS_MCS4 = 0x30,
311 DESC_RATEVHT1SS_MCS5 = 0x31,
312 DESC_RATEVHT1SS_MCS6 = 0x32,
313 DESC_RATEVHT1SS_MCS7 = 0x33,
314 DESC_RATEVHT1SS_MCS8 = 0x34,
315 DESC_RATEVHT1SS_MCS9 = 0x35,
316
317 DESC_RATEVHT2SS_MCS0 = 0x36,
318 DESC_RATEVHT2SS_MCS1 = 0x37,
319 DESC_RATEVHT2SS_MCS2 = 0x38,
320 DESC_RATEVHT2SS_MCS3 = 0x39,
321 DESC_RATEVHT2SS_MCS4 = 0x3a,
322 DESC_RATEVHT2SS_MCS5 = 0x3b,
323 DESC_RATEVHT2SS_MCS6 = 0x3c,
324 DESC_RATEVHT2SS_MCS7 = 0x3d,
325 DESC_RATEVHT2SS_MCS8 = 0x3e,
326 DESC_RATEVHT2SS_MCS9 = 0x3f,
327
328 DESC_RATEVHT3SS_MCS0 = 0x40,
329 DESC_RATEVHT3SS_MCS1 = 0x41,
330 DESC_RATEVHT3SS_MCS2 = 0x42,
331 DESC_RATEVHT3SS_MCS3 = 0x43,
332 DESC_RATEVHT3SS_MCS4 = 0x44,
333 DESC_RATEVHT3SS_MCS5 = 0x45,
334 DESC_RATEVHT3SS_MCS6 = 0x46,
335 DESC_RATEVHT3SS_MCS7 = 0x47,
336 DESC_RATEVHT3SS_MCS8 = 0x48,
337 DESC_RATEVHT3SS_MCS9 = 0x49,
338
339 DESC_RATEVHT4SS_MCS0 = 0x4a,
340 DESC_RATEVHT4SS_MCS1 = 0x4b,
341 DESC_RATEVHT4SS_MCS2 = 0x4c,
342 DESC_RATEVHT4SS_MCS3 = 0x4d,
343 DESC_RATEVHT4SS_MCS4 = 0x4e,
344 DESC_RATEVHT4SS_MCS5 = 0x4f,
345 DESC_RATEVHT4SS_MCS6 = 0x50,
346 DESC_RATEVHT4SS_MCS7 = 0x51,
347 DESC_RATEVHT4SS_MCS8 = 0x52,
348 DESC_RATEVHT4SS_MCS9 = 0x53,
349
350 DESC_RATE_MAX,
351 };
352
353 enum rtw_regulatory_domains {
354 RTW_REGD_FCC = 0,
355 RTW_REGD_MKK = 1,
356 RTW_REGD_ETSI = 2,
357 RTW_REGD_IC = 3,
358 RTW_REGD_KCC = 4,
359 RTW_REGD_ACMA = 5,
360 RTW_REGD_CHILE = 6,
361 RTW_REGD_UKRAINE = 7,
362 RTW_REGD_MEXICO = 8,
363 RTW_REGD_CN = 9,
364 RTW_REGD_QATAR = 10,
365 RTW_REGD_UK = 11,
366
367 RTW_REGD_WW,
368 RTW_REGD_MAX
369 };
370
371 enum rtw_txq_flags {
372 RTW_TXQ_AMPDU,
373 RTW_TXQ_BLOCK_BA,
374 };
375
376 enum rtw_flags {
377 RTW_FLAG_RUNNING,
378 RTW_FLAG_FW_RUNNING,
379 RTW_FLAG_SCANNING,
380 RTW_FLAG_POWERON,
381 RTW_FLAG_LEISURE_PS,
382 RTW_FLAG_LEISURE_PS_DEEP,
383 RTW_FLAG_DIG_DISABLE,
384 RTW_FLAG_BUSY_TRAFFIC,
385 RTW_FLAG_WOWLAN,
386 RTW_FLAG_RESTARTING,
387 RTW_FLAG_RESTART_TRIGGERING,
388 RTW_FLAG_FORCE_LOWEST_RATE,
389
390 NUM_OF_RTW_FLAGS,
391 };
392
393 enum rtw_evm {
394 RTW_EVM_OFDM = 0,
395 RTW_EVM_1SS,
396 RTW_EVM_2SS_A,
397 RTW_EVM_2SS_B,
398 RTW_EVM_3SS_A,
399 RTW_EVM_3SS_B,
400 RTW_EVM_3SS_C,
401 /* keep it last */
402 RTW_EVM_NUM
403 };
404
405 enum rtw_snr {
406 RTW_SNR_OFDM_A = 0,
407 RTW_SNR_OFDM_B,
408 RTW_SNR_OFDM_C,
409 RTW_SNR_OFDM_D,
410 RTW_SNR_1SS_A,
411 RTW_SNR_1SS_B,
412 RTW_SNR_1SS_C,
413 RTW_SNR_1SS_D,
414 RTW_SNR_2SS_A,
415 RTW_SNR_2SS_B,
416 RTW_SNR_2SS_C,
417 RTW_SNR_2SS_D,
418 RTW_SNR_3SS_A,
419 RTW_SNR_3SS_B,
420 RTW_SNR_3SS_C,
421 RTW_SNR_3SS_D,
422 /* keep it last */
423 RTW_SNR_NUM
424 };
425
426 enum rtw_port {
427 RTW_PORT_0 = 0,
428 RTW_PORT_1 = 1,
429 RTW_PORT_2 = 2,
430 RTW_PORT_3 = 3,
431 RTW_PORT_4 = 4,
432 RTW_PORT_NUM
433 };
434
435 enum rtw_wow_flags {
436 RTW_WOW_FLAG_EN_MAGIC_PKT,
437 RTW_WOW_FLAG_EN_REKEY_PKT,
438 RTW_WOW_FLAG_EN_DISCONNECT,
439
440 /* keep it last */
441 RTW_WOW_FLAG_MAX,
442 };
443
444 /* the power index is represented by differences, which cck-1s & ht40-1s are
445 * the base values, so for 1s's differences, there are only ht20 & ofdm
446 */
447 struct rtw_2g_1s_pwr_idx_diff {
448 #ifdef __LITTLE_ENDIAN
449 s8 ofdm:4;
450 s8 bw20:4;
451 #else
452 s8 bw20:4;
453 s8 ofdm:4;
454 #endif
455 } __packed;
456
457 struct rtw_2g_ns_pwr_idx_diff {
458 #ifdef __LITTLE_ENDIAN
459 s8 bw20:4;
460 s8 bw40:4;
461 s8 cck:4;
462 s8 ofdm:4;
463 #else
464 s8 ofdm:4;
465 s8 cck:4;
466 s8 bw40:4;
467 s8 bw20:4;
468 #endif
469 } __packed;
470
471 struct rtw_2g_txpwr_idx {
472 u8 cck_base[6];
473 u8 bw40_base[5];
474 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
475 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
476 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
477 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
478 };
479
480 struct rtw_5g_ht_1s_pwr_idx_diff {
481 #ifdef __LITTLE_ENDIAN
482 s8 ofdm:4;
483 s8 bw20:4;
484 #else
485 s8 bw20:4;
486 s8 ofdm:4;
487 #endif
488 } __packed;
489
490 struct rtw_5g_ht_ns_pwr_idx_diff {
491 #ifdef __LITTLE_ENDIAN
492 s8 bw20:4;
493 s8 bw40:4;
494 #else
495 s8 bw40:4;
496 s8 bw20:4;
497 #endif
498 } __packed;
499
500 struct rtw_5g_ofdm_ns_pwr_idx_diff {
501 #ifdef __LITTLE_ENDIAN
502 s8 ofdm_3s:4;
503 s8 ofdm_2s:4;
504 s8 ofdm_4s:4;
505 s8 res:4;
506 #else
507 s8 res:4;
508 s8 ofdm_4s:4;
509 s8 ofdm_2s:4;
510 s8 ofdm_3s:4;
511 #endif
512 } __packed;
513
514 struct rtw_5g_vht_ns_pwr_idx_diff {
515 #ifdef __LITTLE_ENDIAN
516 s8 bw160:4;
517 s8 bw80:4;
518 #else
519 s8 bw80:4;
520 s8 bw160:4;
521 #endif
522 } __packed;
523
524 struct rtw_5g_txpwr_idx {
525 u8 bw40_base[14];
526 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
527 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
528 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
529 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
530 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
531 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
532 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
533 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
534 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
535 } __packed;
536
537 struct rtw_txpwr_idx {
538 struct rtw_2g_txpwr_idx pwr_idx_2g;
539 struct rtw_5g_txpwr_idx pwr_idx_5g;
540 } __packed;
541
542 struct rtw_channel_params {
543 u8 center_chan;
544 u8 primary_chan;
545 u8 bandwidth;
546 };
547
548 struct rtw_hw_reg {
549 u32 addr;
550 u32 mask;
551 };
552
553 struct rtw_hw_reg_desc {
554 u32 addr;
555 u32 mask;
556 const char *desc;
557 };
558
559 struct rtw_ltecoex_addr {
560 u32 ctrl;
561 u32 wdata;
562 u32 rdata;
563 };
564
565 struct rtw_reg_domain {
566 u32 addr;
567 u32 mask;
568 #define RTW_REG_DOMAIN_MAC32 0
569 #define RTW_REG_DOMAIN_MAC16 1
570 #define RTW_REG_DOMAIN_MAC8 2
571 #define RTW_REG_DOMAIN_RF_A 3
572 #define RTW_REG_DOMAIN_RF_B 4
573 #define RTW_REG_DOMAIN_NL 0xFF
574 u8 domain;
575 };
576
577 struct rtw_rf_sipi_addr {
578 u32 hssi_1;
579 u32 hssi_2;
580 u32 lssi_read;
581 u32 lssi_read_pi;
582 };
583
584 struct rtw_hw_reg_offset {
585 struct rtw_hw_reg hw_reg;
586 u8 offset;
587 };
588
589 struct rtw_backup_info {
590 u8 len;
591 u32 reg;
592 u32 val;
593 };
594
595 enum rtw_vif_port_set {
596 PORT_SET_MAC_ADDR = BIT(0),
597 PORT_SET_BSSID = BIT(1),
598 PORT_SET_NET_TYPE = BIT(2),
599 PORT_SET_AID = BIT(3),
600 PORT_SET_BCN_CTRL = BIT(4),
601 };
602
603 struct rtw_vif_port {
604 struct rtw_hw_reg mac_addr;
605 struct rtw_hw_reg bssid;
606 struct rtw_hw_reg net_type;
607 struct rtw_hw_reg aid;
608 struct rtw_hw_reg bcn_ctrl;
609 };
610
611 struct rtw_tx_pkt_info {
612 u32 tx_pkt_size;
613 u8 offset;
614 u8 pkt_offset;
615 u8 tim_offset;
616 u8 mac_id;
617 u8 rate_id;
618 u8 rate;
619 u8 qsel;
620 u8 bw;
621 u8 sec_type;
622 u8 sn;
623 bool ampdu_en;
624 u8 ampdu_factor;
625 u8 ampdu_density;
626 u16 seq;
627 bool stbc;
628 bool ldpc;
629 bool dis_rate_fallback;
630 bool bmc;
631 bool use_rate;
632 bool ls;
633 bool fs;
634 bool short_gi;
635 bool report;
636 bool rts;
637 bool dis_qselseq;
638 bool en_hwseq;
639 u8 hw_ssn_sel;
640 bool nav_use_hdr;
641 bool bt_null;
642 };
643
644 struct rtw_rx_pkt_stat {
645 bool phy_status;
646 bool icv_err;
647 bool crc_err;
648 bool decrypted;
649 bool is_c2h;
650 bool channel_invalid;
651
652 s32 signal_power;
653 u16 pkt_len;
654 u8 bw;
655 u8 drv_info_sz;
656 u8 shift;
657 u8 rate;
658 u8 mac_id;
659 u8 cam_id;
660 u8 ppdu_cnt;
661 u32 tsf_low;
662 s8 rx_power[RTW_RF_PATH_MAX];
663 u8 rssi;
664 u8 rxsc;
665 s8 rx_snr[RTW_RF_PATH_MAX];
666 u8 rx_evm[RTW_RF_PATH_MAX];
667 s8 cfo_tail[RTW_RF_PATH_MAX];
668 u16 freq;
669 u8 band;
670
671 struct rtw_sta_info *si;
672 struct ieee80211_vif *vif;
673 struct ieee80211_hdr *hdr;
674 };
675
676 DECLARE_EWMA(tp, 10, 2);
677
678 struct rtw_traffic_stats {
679 /* units in bytes */
680 u64 tx_unicast;
681 u64 rx_unicast;
682
683 /* count for packets */
684 u64 tx_cnt;
685 u64 rx_cnt;
686
687 /* units in Mbps */
688 u32 tx_throughput;
689 u32 rx_throughput;
690 struct ewma_tp tx_ewma_tp;
691 struct ewma_tp rx_ewma_tp;
692 };
693
694 enum rtw_lps_mode {
695 RTW_MODE_ACTIVE = 0,
696 RTW_MODE_LPS = 1,
697 RTW_MODE_WMM_PS = 2,
698 };
699
700 enum rtw_lps_deep_mode {
701 LPS_DEEP_MODE_NONE = 0,
702 LPS_DEEP_MODE_LCLK = 1,
703 LPS_DEEP_MODE_PG = 2,
704 };
705
706 enum rtw_pwr_state {
707 RTW_RF_OFF = 0x0,
708 RTW_RF_ON = 0x4,
709 RTW_ALL_ON = 0xc,
710 };
711
712 struct rtw_lps_conf {
713 enum rtw_lps_mode mode;
714 enum rtw_lps_deep_mode deep_mode;
715 enum rtw_lps_deep_mode wow_deep_mode;
716 enum rtw_pwr_state state;
717 u8 awake_interval;
718 u8 rlbm;
719 u8 smart_ps;
720 u8 port_id;
721 bool sec_cam_backup;
722 bool pattern_cam_backup;
723 };
724
725 enum rtw_hw_key_type {
726 RTW_CAM_NONE = 0,
727 RTW_CAM_WEP40 = 1,
728 RTW_CAM_TKIP = 2,
729 RTW_CAM_AES = 4,
730 RTW_CAM_WEP104 = 5,
731 };
732
733 struct rtw_cam_entry {
734 bool valid;
735 bool group;
736 u8 addr[ETH_ALEN];
737 u8 hw_key_type;
738 struct ieee80211_key_conf *key;
739 };
740
741 struct rtw_sec_desc {
742 /* search strategy */
743 bool default_key_search;
744
745 u32 total_cam_num;
746 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
747 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
748 };
749
750 struct rtw_tx_report {
751 /* protect the tx report queue */
752 spinlock_t q_lock;
753 struct sk_buff_head queue;
754 atomic_t sn;
755 struct timer_list purge_timer;
756 };
757
758 struct rtw_ra_report {
759 struct rate_info txrate;
760 u32 bit_rate;
761 u8 desc_rate;
762 };
763
764 struct rtw_txq {
765 struct list_head list;
766 unsigned long flags;
767 };
768
769 DECLARE_EWMA(rssi, 10, 16);
770
771 struct rtw_sta_info {
772 struct rtw_dev *rtwdev;
773 struct ieee80211_sta *sta;
774 struct ieee80211_vif *vif;
775
776 struct ewma_rssi avg_rssi;
777 u8 rssi_level;
778
779 u8 mac_id;
780 u8 rate_id;
781 enum rtw_bandwidth bw_mode;
782 u8 stbc_en:2;
783 u8 ldpc_en:2;
784 bool sgi_enable;
785 bool vht_enable;
786 u8 init_ra_lv;
787 u64 ra_mask;
788
789 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
790
791 struct rtw_ra_report ra_report;
792
793 bool use_cfg_mask;
794 struct cfg80211_bitrate_mask *mask;
795
796 struct work_struct rc_work;
797 };
798
799 enum rtw_bfee_role {
800 RTW_BFEE_NONE,
801 RTW_BFEE_SU,
802 RTW_BFEE_MU
803 };
804
805 struct rtw_bfee {
806 enum rtw_bfee_role role;
807
808 u16 p_aid;
809 u8 g_id;
810 u8 mac_addr[ETH_ALEN];
811 u8 sound_dim;
812
813 /* SU-MIMO */
814 u8 su_reg_index;
815
816 /* MU-MIMO */
817 u16 aid;
818 };
819
820 struct rtw_bf_info {
821 u8 bfer_mu_cnt;
822 u8 bfer_su_cnt;
823 DECLARE_BITMAP(bfer_su_reg_maping, 2);
824 u8 cur_csi_rpt_rate;
825 };
826
827 struct rtw_vif {
828 enum rtw_net_type net_type;
829 u16 aid;
830 u8 mac_id;
831 u8 mac_addr[ETH_ALEN];
832 u8 bssid[ETH_ALEN];
833 u8 port;
834 u8 bcn_ctrl;
835 struct list_head rsvd_page_list;
836 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
837 const struct rtw_vif_port *conf;
838 struct cfg80211_scan_request *scan_req;
839 struct ieee80211_scan_ies *scan_ies;
840
841 struct rtw_traffic_stats stats;
842
843 struct rtw_bfee bfee;
844 };
845
846 struct rtw_regulatory {
847 char alpha2[2] __nonstring;
848 u8 txpwr_regd_2g;
849 u8 txpwr_regd_5g;
850 };
851
852 enum rtw_regd_state {
853 RTW_REGD_STATE_WORLDWIDE,
854 RTW_REGD_STATE_PROGRAMMED,
855 RTW_REGD_STATE_SETTING,
856
857 RTW_REGD_STATE_NR,
858 };
859
860 struct rtw_regd {
861 enum rtw_regd_state state;
862 const struct rtw_regulatory *regulatory;
863 enum nl80211_dfs_regions dfs_region;
864 };
865
866 struct rtw_chip_ops {
867 int (*power_on)(struct rtw_dev *rtwdev);
868 void (*power_off)(struct rtw_dev *rtwdev);
869 int (*mac_init)(struct rtw_dev *rtwdev);
870 int (*mac_postinit)(struct rtw_dev *rtwdev);
871 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
872 void (*shutdown)(struct rtw_dev *rtwdev);
873 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
874 void (*phy_set_param)(struct rtw_dev *rtwdev);
875 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
876 u8 bandwidth, u8 primary_chan_idx);
877 void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status,
878 struct rtw_rx_pkt_stat *pkt_stat);
879 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
880 u32 addr, u32 mask);
881 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
882 u32 addr, u32 mask, u32 data);
883 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
884 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
885 u32 size);
886 int (*set_antenna)(struct rtw_dev *rtwdev, int radio_idx,
887 u32 antenna_tx,
888 u32 antenna_rx);
889 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
890 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
891 void (*set_ampdu_factor)(struct rtw_dev *rtwdev, u8 factor);
892 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
893 void (*phy_calibration)(struct rtw_dev *rtwdev);
894 void (*dpk_track)(struct rtw_dev *rtwdev);
895 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
896 void (*pwr_track)(struct rtw_dev *rtwdev);
897 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
898 struct rtw_bfee *bfee, bool enable);
899 void (*set_gid_table)(struct rtw_dev *rtwdev,
900 struct ieee80211_vif *vif,
901 struct ieee80211_bss_conf *conf);
902 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
903 u8 fixrate_en, u8 *new_rate);
904 void (*adaptivity_init)(struct rtw_dev *rtwdev);
905 void (*adaptivity)(struct rtw_dev *rtwdev);
906 void (*cfo_init)(struct rtw_dev *rtwdev);
907 void (*cfo_track)(struct rtw_dev *rtwdev);
908 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
909 enum rtw_bb_path tx_path_1ss,
910 enum rtw_bb_path tx_path_cck,
911 bool is_tx2_path);
912 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
913 u8 rx_path, bool is_tx2_path);
914 void (*led_set)(struct led_classdev *led, enum led_brightness brightness);
915 /* for USB/SDIO only */
916 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
917 struct rtw_tx_pkt_info *pkt_info,
918 u8 *txdesc);
919
920 /* for coex */
921 void (*coex_set_init)(struct rtw_dev *rtwdev);
922 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
923 u8 ctrl_type, u8 pos_type);
924 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
925 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
926 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
927 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
928 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
929 };
930
931 #define RTW_PWR_POLLING_CNT 20000
932
933 #define RTW_PWR_CMD_READ 0x00
934 #define RTW_PWR_CMD_WRITE 0x01
935 #define RTW_PWR_CMD_POLLING 0x02
936 #define RTW_PWR_CMD_DELAY 0x03
937 #define RTW_PWR_CMD_END 0x04
938
939 /* define the base address of each block */
940 #define RTW_PWR_ADDR_MAC 0x00
941 #define RTW_PWR_ADDR_USB 0x01
942 #define RTW_PWR_ADDR_PCIE 0x02
943 #define RTW_PWR_ADDR_SDIO 0x03
944
945 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
946 #define RTW_PWR_INTF_USB_MSK BIT(1)
947 #define RTW_PWR_INTF_PCI_MSK BIT(2)
948 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
949
950 #define RTW_PWR_CUT_TEST_MSK BIT(0)
951 #define RTW_PWR_CUT_A_MSK BIT(1)
952 #define RTW_PWR_CUT_B_MSK BIT(2)
953 #define RTW_PWR_CUT_C_MSK BIT(3)
954 #define RTW_PWR_CUT_D_MSK BIT(4)
955 #define RTW_PWR_CUT_E_MSK BIT(5)
956 #define RTW_PWR_CUT_F_MSK BIT(6)
957 #define RTW_PWR_CUT_G_MSK BIT(7)
958 #define RTW_PWR_CUT_ALL_MSK 0xFF
959
960 enum rtw_pwr_seq_cmd_delay_unit {
961 RTW_PWR_DELAY_US,
962 RTW_PWR_DELAY_MS,
963 };
964
965 struct rtw_pwr_seq_cmd {
966 u16 offset;
967 u8 cut_mask;
968 u8 intf_mask;
969 u8 base:4;
970 u8 cmd:4;
971 u8 mask;
972 u8 value;
973 };
974
975 enum rtw_chip_ver {
976 RTW_CHIP_VER_CUT_A = 0x00,
977 RTW_CHIP_VER_CUT_B = 0x01,
978 RTW_CHIP_VER_CUT_C = 0x02,
979 RTW_CHIP_VER_CUT_D = 0x03,
980 RTW_CHIP_VER_CUT_E = 0x04,
981 RTW_CHIP_VER_CUT_F = 0x05,
982 RTW_CHIP_VER_CUT_G = 0x06,
983 };
984
985 #define RTW_INTF_PHY_PLATFORM_ALL 0
986
987 enum rtw_intf_phy_cut {
988 RTW_INTF_PHY_CUT_A = BIT(0),
989 RTW_INTF_PHY_CUT_B = BIT(1),
990 RTW_INTF_PHY_CUT_C = BIT(2),
991 RTW_INTF_PHY_CUT_D = BIT(3),
992 RTW_INTF_PHY_CUT_E = BIT(4),
993 RTW_INTF_PHY_CUT_F = BIT(5),
994 RTW_INTF_PHY_CUT_G = BIT(6),
995 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
996 };
997
998 enum rtw_ip_sel {
999 RTW_IP_SEL_PHY = 0,
1000 RTW_IP_SEL_MAC = 1,
1001 RTW_IP_SEL_DBI = 2,
1002
1003 RTW_IP_SEL_UNDEF = 0xFFFF
1004 };
1005
1006 enum rtw_pq_map_id {
1007 RTW_PQ_MAP_VO = 0x0,
1008 RTW_PQ_MAP_VI = 0x1,
1009 RTW_PQ_MAP_BE = 0x2,
1010 RTW_PQ_MAP_BK = 0x3,
1011 RTW_PQ_MAP_MG = 0x4,
1012 RTW_PQ_MAP_HI = 0x5,
1013 RTW_PQ_MAP_NUM = 0x6,
1014
1015 RTW_PQ_MAP_UNDEF,
1016 };
1017
1018 enum rtw_dma_mapping {
1019 RTW_DMA_MAPPING_EXTRA = 0,
1020 RTW_DMA_MAPPING_LOW = 1,
1021 RTW_DMA_MAPPING_NORMAL = 2,
1022 RTW_DMA_MAPPING_HIGH = 3,
1023
1024 RTW_DMA_MAPPING_MAX,
1025 RTW_DMA_MAPPING_UNDEF,
1026 };
1027
1028 struct rtw_rqpn {
1029 enum rtw_dma_mapping dma_map_vo;
1030 enum rtw_dma_mapping dma_map_vi;
1031 enum rtw_dma_mapping dma_map_be;
1032 enum rtw_dma_mapping dma_map_bk;
1033 enum rtw_dma_mapping dma_map_mg;
1034 enum rtw_dma_mapping dma_map_hi;
1035 };
1036
1037 struct rtw_prioq_addr {
1038 u32 rsvd;
1039 u32 avail;
1040 };
1041
1042 struct rtw_prioq_addrs {
1043 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1044 bool wsize;
1045 };
1046
1047 struct rtw_page_table {
1048 u16 hq_num;
1049 u16 nq_num;
1050 u16 lq_num;
1051 u16 exq_num;
1052 u16 gapq_num;
1053 };
1054
1055 struct rtw_intf_phy_para {
1056 u16 offset;
1057 u16 value;
1058 u16 ip_sel;
1059 u16 cut_mask;
1060 u16 platform;
1061 };
1062
1063 struct rtw_wow_pattern {
1064 u16 crc;
1065 u8 type;
1066 u8 valid;
1067 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1068 };
1069
1070 struct rtw_pno_request {
1071 bool inited;
1072 u32 match_set_cnt;
1073 struct cfg80211_match_set *match_sets;
1074 u8 channel_cnt;
1075 struct ieee80211_channel *channels;
1076 struct cfg80211_sched_scan_plan scan_plan;
1077 };
1078
1079 struct rtw_wow_param {
1080 struct ieee80211_vif *wow_vif;
1081 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1082 u8 txpause;
1083 u8 pattern_cnt;
1084 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1085
1086 bool ips_enabled;
1087 struct rtw_pno_request pno_req;
1088 };
1089
1090 struct rtw_intf_phy_para_table {
1091 const struct rtw_intf_phy_para *usb2_para;
1092 const struct rtw_intf_phy_para *usb3_para;
1093 const struct rtw_intf_phy_para *gen1_para;
1094 const struct rtw_intf_phy_para *gen2_para;
1095 u8 n_usb2_para;
1096 u8 n_usb3_para;
1097 u8 n_gen1_para;
1098 u8 n_gen2_para;
1099 };
1100
1101 struct rtw_table {
1102 const void *data;
1103 const u32 size;
1104 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1105 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1106 u32 addr, u32 data);
1107 enum rtw_rf_path rf_path;
1108 };
1109
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1110 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1111 const struct rtw_table *tbl)
1112 {
1113 (*tbl->parse)(rtwdev, tbl);
1114 }
1115
1116 enum rtw_rfe_fem {
1117 RTW_RFE_IFEM,
1118 RTW_RFE_EFEM,
1119 RTW_RFE_IFEM2G_EFEM5G,
1120 RTW_RFE_NUM,
1121 };
1122
1123 struct rtw_rfe_def {
1124 const struct rtw_table *phy_pg_tbl;
1125 const struct rtw_table *txpwr_lmt_tbl;
1126 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1127 const struct rtw_table *agc_btg_tbl;
1128 };
1129
1130 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt, track) { \
1131 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1132 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1133 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \
1134 }
1135
1136 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, track, btg) { \
1137 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1138 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1139 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \
1140 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1141 }
1142
1143 #define RTW_PWR_TRK_5G_1 0
1144 #define RTW_PWR_TRK_5G_2 1
1145 #define RTW_PWR_TRK_5G_3 2
1146 #define RTW_PWR_TRK_5G_NUM 3
1147
1148 #define RTW_PWR_TRK_TBL_SZ 30
1149
1150 /* This table stores the values of TX power that will be adjusted by power
1151 * tracking.
1152 *
1153 * For 5G bands, there are 3 different settings.
1154 * For 2G there are cck rate and ofdm rate with different settings.
1155 */
1156 struct rtw_pwr_track_tbl {
1157 const u8 *pwrtrk_5gd_n[RTW_PWR_TRK_5G_NUM];
1158 const u8 *pwrtrk_5gd_p[RTW_PWR_TRK_5G_NUM];
1159 const u8 *pwrtrk_5gc_n[RTW_PWR_TRK_5G_NUM];
1160 const u8 *pwrtrk_5gc_p[RTW_PWR_TRK_5G_NUM];
1161 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1162 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1163 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1164 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1165 const u8 *pwrtrk_2gd_n;
1166 const u8 *pwrtrk_2gd_p;
1167 const u8 *pwrtrk_2gc_n;
1168 const u8 *pwrtrk_2gc_p;
1169 const u8 *pwrtrk_2gb_n;
1170 const u8 *pwrtrk_2gb_p;
1171 const u8 *pwrtrk_2ga_n;
1172 const u8 *pwrtrk_2ga_p;
1173 const u8 *pwrtrk_2g_cckd_n;
1174 const u8 *pwrtrk_2g_cckd_p;
1175 const u8 *pwrtrk_2g_cckc_n;
1176 const u8 *pwrtrk_2g_cckc_p;
1177 const u8 *pwrtrk_2g_cckb_n;
1178 const u8 *pwrtrk_2g_cckb_p;
1179 const u8 *pwrtrk_2g_ccka_n;
1180 const u8 *pwrtrk_2g_ccka_p;
1181 const s8 *pwrtrk_xtal_n;
1182 const s8 *pwrtrk_xtal_p;
1183 };
1184
1185 enum rtw_wlan_cpu {
1186 RTW_WCPU_3081,
1187 RTW_WCPU_8051,
1188 };
1189
1190 enum rtw_fw_fifo_sel {
1191 RTW_FW_FIFO_SEL_TX,
1192 RTW_FW_FIFO_SEL_RX,
1193 RTW_FW_FIFO_SEL_RSVD_PAGE,
1194 RTW_FW_FIFO_SEL_REPORT,
1195 RTW_FW_FIFO_SEL_LLT,
1196 RTW_FW_FIFO_SEL_RXBUF_FW,
1197
1198 RTW_FW_FIFO_MAX,
1199 };
1200
1201 enum rtw_fwcd_item {
1202 RTW_FWCD_TLV,
1203 RTW_FWCD_REG,
1204 RTW_FWCD_ROM,
1205 RTW_FWCD_IMEM,
1206 RTW_FWCD_DMEM,
1207 RTW_FWCD_EMEM,
1208 };
1209
1210 /* hardware configuration for each IC */
1211 struct rtw_chip_info {
1212 const struct rtw_chip_ops *ops;
1213 u8 id;
1214
1215 const char *fw_name;
1216 enum rtw_wlan_cpu wlan_cpu;
1217 u8 tx_pkt_desc_sz;
1218 u8 tx_buf_desc_sz;
1219 u8 rx_pkt_desc_sz;
1220 u8 rx_buf_desc_sz;
1221 u32 phy_efuse_size;
1222 u32 log_efuse_size;
1223 u32 ptct_efuse_size;
1224 u32 txff_size;
1225 u32 rxff_size;
1226 u32 fw_rxff_size;
1227 u16 rsvd_drv_pg_num;
1228 u8 band;
1229 u16 page_size;
1230 u8 csi_buf_pg_num;
1231 u8 dig_max;
1232 u8 dig_min;
1233 u8 txgi_factor;
1234 bool is_pwr_by_rate_dec;
1235 bool rx_ldpc;
1236 bool tx_stbc;
1237 u8 max_power_index;
1238 u8 ampdu_density;
1239
1240 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1241 const struct rtw_fwcd_segs *fwcd_segs;
1242
1243 bool amsdu_in_ampdu;
1244 u8 usb_tx_agg_desc_num;
1245 bool hw_feature_report;
1246 u8 c2h_ra_report_size;
1247 bool old_datarate_fb_limit;
1248
1249 u8 default_1ss_tx_path;
1250
1251 bool path_div_supported;
1252 bool ht_supported;
1253 bool vht_supported;
1254 u8 lps_deep_mode_supported;
1255
1256 /* init values */
1257 u8 sys_func_en;
1258 const struct rtw_pwr_seq_cmd * const *pwr_on_seq;
1259 const struct rtw_pwr_seq_cmd * const *pwr_off_seq;
1260 const struct rtw_rqpn *rqpn_table;
1261 const struct rtw_prioq_addrs *prioq_addrs;
1262 const struct rtw_page_table *page_table;
1263 const struct rtw_intf_phy_para_table *intf_table;
1264
1265 const struct rtw_hw_reg *dig;
1266 const struct rtw_hw_reg *dig_cck;
1267 u32 rf_base_addr[RTW_RF_PATH_MAX];
1268 u32 rf_sipi_addr[RTW_RF_PATH_MAX];
1269 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1270 u8 fix_rf_phy_num;
1271 const struct rtw_ltecoex_addr *ltecoex_addr;
1272
1273 const struct rtw_table *mac_tbl;
1274 const struct rtw_table *agc_tbl;
1275 const struct rtw_table *bb_tbl;
1276 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1277 const struct rtw_table *rfk_init_tbl;
1278
1279 const struct rtw_rfe_def *rfe_defs;
1280 u32 rfe_defs_size;
1281
1282 bool en_dis_dpd;
1283 u16 dpd_ratemask;
1284 u8 iqk_threshold;
1285 u8 lck_threshold;
1286
1287 u8 bfer_su_max_num;
1288 u8 bfer_mu_max_num;
1289
1290 const struct rtw_hw_reg_offset *edcca_th;
1291 s8 l2h_th_ini_cs;
1292 s8 l2h_th_ini_ad;
1293
1294 const char *wow_fw_name;
1295 const struct wiphy_wowlan_support *wowlan_stub;
1296 const u8 max_sched_scan_ssids;
1297 const u16 max_scan_ie_len;
1298
1299 /* coex paras */
1300 u32 coex_para_ver;
1301 u8 bt_desired_ver;
1302 bool scbd_support;
1303 bool new_scbd10_def; /* true: fix 2M(8822c) */
1304 bool ble_hid_profile_support;
1305 bool wl_mimo_ps_support;
1306 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1307 u8 bt_rssi_type;
1308 u8 ant_isolation;
1309 u8 rssi_tolerance;
1310 u8 table_sant_num;
1311 u8 table_nsant_num;
1312 u8 tdma_sant_num;
1313 u8 tdma_nsant_num;
1314 u8 bt_afh_span_bw20;
1315 u8 bt_afh_span_bw40;
1316 u8 afh_5g_num;
1317 u8 wl_rf_para_num;
1318 u8 coex_info_hw_regs_num;
1319 const u8 *bt_rssi_step;
1320 const u8 *wl_rssi_step;
1321 const struct coex_table_para *table_nsant;
1322 const struct coex_table_para *table_sant;
1323 const struct coex_tdma_para *tdma_sant;
1324 const struct coex_tdma_para *tdma_nsant;
1325 const struct coex_rf_para *wl_rf_para_tx;
1326 const struct coex_rf_para *wl_rf_para_rx;
1327 const struct coex_5g_afh_map *afh_5g;
1328 const struct rtw_hw_reg *btg_reg;
1329 const struct rtw_reg_domain *coex_info_hw_regs;
1330 u32 wl_fw_desired_ver;
1331 };
1332
1333 enum rtw_coex_bt_state_cnt {
1334 COEX_CNT_BT_RETRY,
1335 COEX_CNT_BT_REINIT,
1336 COEX_CNT_BT_REENABLE,
1337 COEX_CNT_BT_POPEVENT,
1338 COEX_CNT_BT_SETUPLINK,
1339 COEX_CNT_BT_IGNWLANACT,
1340 COEX_CNT_BT_INQ,
1341 COEX_CNT_BT_PAGE,
1342 COEX_CNT_BT_ROLESWITCH,
1343 COEX_CNT_BT_AFHUPDATE,
1344 COEX_CNT_BT_INFOUPDATE,
1345 COEX_CNT_BT_IQK,
1346 COEX_CNT_BT_IQKFAIL,
1347
1348 COEX_CNT_BT_MAX
1349 };
1350
1351 enum rtw_coex_wl_state_cnt {
1352 COEX_CNT_WL_SCANAP,
1353 COEX_CNT_WL_CONNPKT,
1354 COEX_CNT_WL_COEXRUN,
1355 COEX_CNT_WL_NOISY0,
1356 COEX_CNT_WL_NOISY1,
1357 COEX_CNT_WL_NOISY2,
1358 COEX_CNT_WL_5MS_NOEXTEND,
1359 COEX_CNT_WL_FW_NOTIFY,
1360
1361 COEX_CNT_WL_MAX
1362 };
1363
1364 struct rtw_coex_rfe {
1365 bool ant_switch_exist;
1366 bool ant_switch_diversity;
1367 bool ant_switch_with_bt;
1368 u8 rfe_module_type;
1369 u8 ant_switch_polarity;
1370
1371 /* true if WLG at BTG, else at WLAG */
1372 bool wlg_at_btg;
1373 };
1374
1375 #define COEX_WL_TDMA_PARA_LENGTH 5
1376
1377 struct rtw_coex_dm {
1378 bool cur_ps_tdma_on;
1379 bool cur_wl_rx_low_gain_en;
1380 bool ignore_wl_act;
1381
1382 u8 reason;
1383 u8 bt_rssi_state[4];
1384 u8 wl_rssi_state[4];
1385 u8 wl_ch_info[3];
1386 u8 cur_ps_tdma;
1387 u8 cur_table;
1388 u8 ps_tdma_para[5];
1389 u8 cur_bt_pwr_lvl;
1390 u8 cur_bt_lna_lvl;
1391 u8 cur_wl_pwr_lvl;
1392 u8 bt_status;
1393 u32 cur_ant_pos_type;
1394 u32 cur_switch_status;
1395 u32 setting_tdma;
1396 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1397 };
1398
1399 #define COEX_BTINFO_SRC_WL_FW 0x0
1400 #define COEX_BTINFO_SRC_BT_RSP 0x1
1401 #define COEX_BTINFO_SRC_BT_ACT 0x2
1402 #define COEX_BTINFO_SRC_BT_IQK 0x3
1403 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1404 #define COEX_BTINFO_SRC_H2C60 0x5
1405 #define COEX_BTINFO_SRC_MAX 0x6
1406
1407 #define COEX_INFO_FTP BIT(7)
1408 #define COEX_INFO_A2DP BIT(6)
1409 #define COEX_INFO_HID BIT(5)
1410 #define COEX_INFO_SCO_BUSY BIT(4)
1411 #define COEX_INFO_ACL_BUSY BIT(3)
1412 #define COEX_INFO_INQ_PAGE BIT(2)
1413 #define COEX_INFO_SCO_ESCO BIT(1)
1414 #define COEX_INFO_CONNECTION BIT(0)
1415 #define COEX_BTINFO_LENGTH_MAX 10
1416 #define COEX_BTINFO_LENGTH 7
1417
1418 #define COEX_BT_HIDINFO_LIST 0x0
1419 #define COEX_BT_HIDINFO_A 0x1
1420 #define COEX_BT_HIDINFO_NAME 3
1421
1422 #define COEX_BT_HIDINFO_LENGTH 6
1423 #define COEX_BT_HIDINFO_HANDLE_NUM 4
1424 #define COEX_BT_HIDINFO_C2H_HANDLE 0
1425 #define COEX_BT_HIDINFO_C2H_VENDOR 1
1426 #define COEX_BT_BLE_HANDLE_THRS 0x10
1427 #define COEX_BT_HIDINFO_NOTCON 0xff
1428
1429 struct rtw_coex_hid {
1430 u8 hid_handle;
1431 u8 hid_vendor;
1432 u8 hid_name[COEX_BT_HIDINFO_NAME];
1433 bool hid_info_completed;
1434 bool is_game_hid;
1435 };
1436
1437 struct rtw_coex_hid_handle_list {
1438 u8 cmd_id;
1439 u8 len;
1440 u8 subid;
1441 u8 handle_cnt;
1442 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1443 } __packed;
1444
1445 struct rtw_coex_hid_info_a {
1446 u8 cmd_id;
1447 u8 len;
1448 u8 subid;
1449 u8 handle;
1450 u8 vendor;
1451 u8 name[COEX_BT_HIDINFO_NAME];
1452 } __packed;
1453
1454 struct rtw_coex_stat {
1455 bool bt_disabled;
1456 bool bt_disabled_pre;
1457 bool bt_link_exist;
1458 bool bt_whck_test;
1459 bool bt_inq_page;
1460 bool bt_inq_remain;
1461 bool bt_inq;
1462 bool bt_page;
1463 bool bt_ble_voice;
1464 bool bt_ble_exist;
1465 bool bt_hfp_exist;
1466 bool bt_a2dp_exist;
1467 bool bt_hid_exist;
1468 bool bt_pan_exist; /* PAN or OPP */
1469 bool bt_opp_exist; /* OPP only */
1470 bool bt_acl_busy;
1471 bool bt_fix_2M;
1472 bool bt_setup_link;
1473 bool bt_multi_link;
1474 bool bt_multi_link_pre;
1475 bool bt_multi_link_remain;
1476 bool bt_a2dp_sink;
1477 bool bt_a2dp_active;
1478 bool bt_reenable;
1479 bool bt_ble_scan_en;
1480 bool bt_init_scan;
1481 bool bt_slave;
1482 bool bt_418_hid_exist;
1483 bool bt_ble_hid_exist;
1484 bool bt_game_hid_exist;
1485 bool bt_hid_handle_cnt;
1486 bool bt_mailbox_reply;
1487
1488 bool wl_under_lps;
1489 bool wl_under_ips;
1490 bool wl_hi_pri_task1;
1491 bool wl_hi_pri_task2;
1492 bool wl_force_lps_ctrl;
1493 bool wl_gl_busy;
1494 bool wl_linkscan_proc;
1495 bool wl_ps_state_fail;
1496 bool wl_tx_limit_en;
1497 bool wl_ampdu_limit_en;
1498 bool wl_connected;
1499 bool wl_slot_extend;
1500 bool wl_cck_lock;
1501 bool wl_cck_lock_pre;
1502 bool wl_cck_lock_ever;
1503 bool wl_connecting;
1504 bool wl_slot_toggle;
1505 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1506 bool wl_mimo_ps;
1507
1508 u32 bt_supported_version;
1509 u32 bt_supported_feature;
1510 u32 hi_pri_tx;
1511 u32 hi_pri_rx;
1512 u32 lo_pri_tx;
1513 u32 lo_pri_rx;
1514 u32 patch_ver;
1515 u16 bt_reg_vendor_ae;
1516 u16 bt_reg_vendor_ac;
1517 s8 bt_rssi;
1518 u8 kt_ver;
1519 u8 gnt_workaround_state;
1520 u8 tdma_timer_base;
1521 u8 bt_profile_num;
1522 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1523 u8 bt_info_lb2;
1524 u8 bt_info_lb3;
1525 u8 bt_info_hb0;
1526 u8 bt_info_hb1;
1527 u8 bt_info_hb2;
1528 u8 bt_info_hb3;
1529 u8 bt_ble_scan_type;
1530 u8 bt_hid_pair_num;
1531 u8 bt_hid_slot;
1532 u8 bt_a2dp_bitpool;
1533 u8 bt_iqk_state;
1534 u8 bt_disable_cnt;
1535
1536 u16 wl_beacon_interval;
1537 u8 wl_noisy_level;
1538 u8 wl_fw_dbg_info[10];
1539 u8 wl_fw_dbg_info_pre[10];
1540 u8 wl_rx_rate;
1541 u8 wl_tx_rate;
1542 u8 wl_rts_rx_rate;
1543 u8 wl_coex_mode;
1544 u8 wl_iot_peer;
1545 u8 ampdu_max_time;
1546 u8 wl_tput_dir;
1547
1548 u8 wl_toggle_para[6];
1549 u8 wl_toggle_interval;
1550
1551 u16 score_board;
1552 u16 retry_limit;
1553
1554 /* counters to record bt states */
1555 u32 cnt_bt[COEX_CNT_BT_MAX];
1556
1557 /* counters to record wifi states */
1558 u32 cnt_wl[COEX_CNT_WL_MAX];
1559
1560 /* counters to record bt c2h data */
1561 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1562
1563 u32 darfrc;
1564 u32 darfrch;
1565
1566 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1567 struct rtw_coex_hid_handle_list hid_handle_list;
1568 };
1569
1570 struct rtw_coex {
1571 struct sk_buff_head queue;
1572 wait_queue_head_t wait;
1573
1574 bool under_5g;
1575 bool stop_dm;
1576 bool freeze;
1577 bool freerun;
1578 bool wl_rf_off;
1579 bool manual_control;
1580
1581 struct rtw_coex_stat stat;
1582 struct rtw_coex_dm dm;
1583 struct rtw_coex_rfe rfe;
1584
1585 struct delayed_work bt_relink_work;
1586 struct delayed_work bt_reenable_work;
1587 struct delayed_work defreeze_work;
1588 struct delayed_work wl_remain_work;
1589 struct delayed_work bt_remain_work;
1590 struct delayed_work wl_connecting_work;
1591 struct delayed_work bt_multi_link_remain_work;
1592 struct delayed_work wl_ccklock_work;
1593
1594 };
1595
1596 #define DPK_RF_REG_NUM 7
1597 #define DPK_RF_PATH_NUM 2
1598 #define DPK_BB_REG_NUM 18
1599 #define DPK_CHANNEL_WIDTH_80 1
1600
1601 DECLARE_EWMA(thermal, 10, 4);
1602
1603 struct rtw_dpk_info {
1604 bool is_dpk_pwr_on;
1605 bool is_reload;
1606
1607 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1608
1609 u8 thermal_dpk[DPK_RF_PATH_NUM];
1610 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1611
1612 u32 gnt_control;
1613 u32 gnt_value;
1614
1615 u8 result[RTW_RF_PATH_MAX];
1616 u8 dpk_txagc[RTW_RF_PATH_MAX];
1617 u32 coef[RTW_RF_PATH_MAX][20];
1618 u16 dpk_gs[RTW_RF_PATH_MAX];
1619 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1620 u8 pre_pwsf[RTW_RF_PATH_MAX];
1621
1622 u8 dpk_band;
1623 u8 dpk_ch;
1624 u8 dpk_bw;
1625 };
1626
1627 struct rtw_phy_cck_pd_reg {
1628 u32 reg_pd;
1629 u32 mask_pd;
1630 u32 reg_cs;
1631 u32 mask_cs;
1632 };
1633
1634 #define DACK_MSBK_BACKUP_NUM 0xf
1635 #define DACK_DCK_BACKUP_NUM 0x2
1636
1637 struct rtw_swing_table {
1638 const u8 *p[RTW_RF_PATH_MAX];
1639 const u8 *n[RTW_RF_PATH_MAX];
1640 };
1641
1642 struct rtw_pkt_count {
1643 u16 num_bcn_pkt;
1644 u16 num_qry_pkt[DESC_RATE_MAX];
1645 };
1646
1647 DECLARE_EWMA(evm, 10, 4);
1648 DECLARE_EWMA(snr, 10, 4);
1649
1650 struct rtw_iqk_info {
1651 bool done;
1652 struct {
1653 u32 s1_x;
1654 u32 s1_y;
1655 u32 s0_x;
1656 u32 s0_y;
1657 } result;
1658 };
1659
1660 enum rtw_rf_band {
1661 RF_BAND_2G_CCK,
1662 RF_BAND_2G_OFDM,
1663 RF_BAND_5G_L,
1664 RF_BAND_5G_M,
1665 RF_BAND_5G_H,
1666 RF_BAND_MAX
1667 };
1668
1669 #define RF_GAIN_NUM 11
1670 #define RF_HW_OFFSET_NUM 10
1671
1672 struct rtw_gapk_info {
1673 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1674 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1675 bool txgapk_bp_done;
1676 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1677 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1678 u8 read_txgain;
1679 u8 channel;
1680 };
1681
1682 #define EDCCA_TH_L2H_IDX 0
1683 #define EDCCA_TH_H2L_IDX 1
1684 #define EDCCA_TH_L2H_LB 48
1685 #define EDCCA_ADC_BACKOFF 12
1686 #define EDCCA_IGI_BASE 50
1687 #define EDCCA_IGI_L2H_DIFF 8
1688 #define EDCCA_L2H_H2L_DIFF 7
1689 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1690
1691 enum rtw_edcca_mode {
1692 RTW_EDCCA_NORMAL = 0,
1693 RTW_EDCCA_ADAPTIVITY = 1,
1694 };
1695
1696 struct rtw_cfo_track {
1697 bool is_adjust;
1698 u8 crystal_cap;
1699 s32 cfo_tail[RTW_RF_PATH_MAX];
1700 s32 cfo_cnt[RTW_RF_PATH_MAX];
1701 u32 packet_count;
1702 u32 packet_count_pre;
1703 };
1704
1705 #define RRSR_INIT_2G 0x15f
1706 #define RRSR_INIT_5G 0x150
1707
1708 enum rtw_dm_cap {
1709 RTW_DM_CAP_NA,
1710 RTW_DM_CAP_TXGAPK,
1711 RTW_DM_CAP_NUM
1712 };
1713
1714 struct rtw_dm_info {
1715 u32 cck_fa_cnt;
1716 u32 ofdm_fa_cnt;
1717 u32 total_fa_cnt;
1718 u32 cck_cca_cnt;
1719 u32 ofdm_cca_cnt;
1720 u32 total_cca_cnt;
1721
1722 u32 cck_ok_cnt;
1723 u32 cck_err_cnt;
1724 u32 ofdm_ok_cnt;
1725 u32 ofdm_err_cnt;
1726 u32 ht_ok_cnt;
1727 u32 ht_err_cnt;
1728 u32 vht_ok_cnt;
1729 u32 vht_err_cnt;
1730
1731 u8 min_rssi;
1732 u8 pre_min_rssi;
1733 u16 fa_history[4];
1734 u8 igi_history[4];
1735 u8 igi_bitmap;
1736 bool damping;
1737 u8 damping_cnt;
1738 u8 damping_rssi;
1739
1740 u8 cck_gi_u_bnd;
1741 u8 cck_gi_l_bnd;
1742
1743 u8 fix_rate;
1744 u8 tx_rate;
1745 u32 rrsr_val_init;
1746 u32 rrsr_mask_min;
1747 u8 thermal_avg[RTW_RF_PATH_MAX];
1748 u8 thermal_meter_k;
1749 u8 thermal_meter_lck;
1750 s8 delta_power_index[RTW_RF_PATH_MAX];
1751 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1752 u8 default_ofdm_index;
1753 u8 default_cck_index;
1754 bool pwr_trk_triggered;
1755 bool pwr_trk_init_trigger;
1756 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1757 s8 txagc_remnant_cck;
1758 s8 txagc_remnant_ofdm[RTW_RF_PATH_MAX];
1759 u8 rx_cck_agc_report_type;
1760
1761 /* backup dack results for each path and I/Q */
1762 u32 dack_adck[RTW_RF_PATH_MAX];
1763 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1764 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1765
1766 struct rtw_dpk_info dpk_info;
1767 struct rtw_cfo_track cfo_track;
1768
1769 /* [bandwidth 0:20M/1:40M][number of path] */
1770 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1771 u32 cck_fa_avg;
1772 u8 cck_pd_default;
1773
1774 /* save the last rx phy status for debug */
1775 s8 rx_snr[RTW_RF_PATH_MAX];
1776 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1777 s16 cfo_tail[RTW_RF_PATH_MAX];
1778 u8 rssi[RTW_RF_PATH_MAX];
1779 u8 curr_rx_rate;
1780 struct rtw_pkt_count cur_pkt_count;
1781 struct rtw_pkt_count last_pkt_count;
1782 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1783 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1784
1785 u32 dm_flags; /* enum rtw_dm_cap */
1786 struct rtw_iqk_info iqk;
1787 struct rtw_gapk_info gapk;
1788 bool is_bt_iqk_timeout;
1789
1790 s8 l2h_th_ini;
1791 enum rtw_edcca_mode edcca_mode;
1792 u8 scan_density;
1793 };
1794
1795 struct rtw_efuse {
1796 u32 size;
1797 u32 physical_size;
1798 u32 logical_size;
1799 u32 protect_size;
1800
1801 u8 addr[ETH_ALEN];
1802 u8 channel_plan;
1803 u8 country_code[2];
1804 u8 rf_board_option;
1805 u8 rfe_option;
1806 u8 power_track_type;
1807 u8 thermal_meter[RTW_RF_PATH_MAX];
1808 u8 thermal_meter_k;
1809 u8 crystal_cap;
1810 u8 ant_div_cfg;
1811 u8 ant_div_type;
1812 u8 regd;
1813 u8 afe;
1814
1815 u8 lna_type_2g;
1816 u8 lna_type_5g;
1817 u8 glna_type;
1818 u8 alna_type;
1819 bool ext_lna_2g;
1820 bool ext_lna_5g;
1821 u8 pa_type_2g;
1822 u8 pa_type_5g;
1823 u8 gpa_type;
1824 u8 apa_type;
1825 bool ext_pa_2g;
1826 bool ext_pa_5g;
1827 u8 tx_bb_swing_setting_2g;
1828 u8 tx_bb_swing_setting_5g;
1829
1830 bool btcoex;
1831 /* bt share antenna with wifi */
1832 bool share_ant;
1833 u8 bt_setting;
1834
1835 u8 usb_mode_switch;
1836
1837 struct {
1838 u8 hci;
1839 u8 bw;
1840 u8 ptcl;
1841 u8 nss;
1842 u8 ant_num;
1843 } hw_cap;
1844
1845 struct rtw_txpwr_idx txpwr_idx_table[4];
1846 };
1847
1848 struct rtw_phy_cond {
1849 #ifdef __LITTLE_ENDIAN
1850 u32 rfe:8;
1851 u32 intf:4;
1852 u32 pkg:4;
1853 u32 plat:4;
1854 u32 intf_rsvd:4;
1855 u32 cut:4;
1856 u32 branch:2;
1857 u32 neg:1;
1858 u32 pos:1;
1859 #else
1860 u32 pos:1;
1861 u32 neg:1;
1862 u32 branch:2;
1863 u32 cut:4;
1864 u32 intf_rsvd:4;
1865 u32 plat:4;
1866 u32 pkg:4;
1867 u32 intf:4;
1868 u32 rfe:8;
1869 #endif
1870 /* for intf:4 */
1871 #define INTF_PCIE BIT(0)
1872 #define INTF_USB BIT(1)
1873 #define INTF_SDIO BIT(2)
1874 /* for branch:2 */
1875 #define BRANCH_IF 0
1876 #define BRANCH_ELIF 1
1877 #define BRANCH_ELSE 2
1878 #define BRANCH_ENDIF 3
1879 };
1880
1881 struct rtw_phy_cond2 {
1882 #ifdef __LITTLE_ENDIAN
1883 u8 type_glna;
1884 u8 type_gpa;
1885 u8 type_alna;
1886 u8 type_apa;
1887 #else
1888 u8 type_apa;
1889 u8 type_alna;
1890 u8 type_gpa;
1891 u8 type_glna;
1892 #endif
1893 };
1894
1895 struct rtw_fifo_conf {
1896 /* tx fifo information */
1897 u16 rsvd_boundary;
1898 u16 rsvd_pg_num;
1899 u16 rsvd_drv_pg_num;
1900 u16 txff_pg_num;
1901 u16 acq_pg_num;
1902 u16 rsvd_drv_addr;
1903 u16 rsvd_h2c_info_addr;
1904 u16 rsvd_h2c_sta_info_addr;
1905 u16 rsvd_h2cq_addr;
1906 u16 rsvd_cpu_instr_addr;
1907 u16 rsvd_fw_txbuf_addr;
1908 u16 rsvd_csibuf_addr;
1909 const struct rtw_rqpn *rqpn;
1910 };
1911
1912 struct rtw_fwcd_desc {
1913 u32 size;
1914 u8 *next;
1915 u8 *data;
1916 };
1917
1918 struct rtw_fwcd_segs {
1919 const u32 *segs;
1920 u8 num;
1921 };
1922
1923 #define FW_CD_TYPE 0xffff
1924 #define FW_CD_LEN 4
1925 #define FW_CD_VAL 0xaabbccdd
1926 struct rtw_fw_state {
1927 const struct firmware *firmware;
1928 struct rtw_dev *rtwdev;
1929 struct completion completion;
1930 struct rtw_fwcd_desc fwcd_desc;
1931 u16 version;
1932 u8 sub_version;
1933 u8 sub_index;
1934 u16 h2c_version;
1935 u32 feature;
1936 u32 feature_ext;
1937 enum rtw_fw_type type;
1938 };
1939
1940 enum rtw_sar_sources {
1941 RTW_SAR_SOURCE_NONE,
1942 RTW_SAR_SOURCE_COMMON,
1943 };
1944
1945 enum rtw_sar_bands {
1946 RTW_SAR_BAND_0,
1947 RTW_SAR_BAND_1,
1948 /* RTW_SAR_BAND_2, not used now */
1949 RTW_SAR_BAND_3,
1950 RTW_SAR_BAND_4,
1951
1952 RTW_SAR_BAND_NR,
1953 };
1954
1955 /* the union is reserved for other kinds of SAR sources
1956 * which might not re-use same format with array common.
1957 */
1958 union rtw_sar_cfg {
1959 s8 common[RTW_SAR_BAND_NR];
1960 };
1961
1962 struct rtw_sar {
1963 enum rtw_sar_sources src;
1964 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_NUM];
1965 };
1966
1967 struct rtw_hal {
1968 u32 rcr;
1969
1970 u32 chip_version;
1971 u8 cut_version;
1972 u8 mp_chip;
1973 u8 oem_id;
1974 u8 pkg_type;
1975 struct rtw_phy_cond phy_cond;
1976 struct rtw_phy_cond2 phy_cond2;
1977 bool rfe_btg;
1978
1979 u8 ps_mode;
1980 u8 current_channel;
1981 u8 current_primary_channel_index;
1982 u8 current_band_width;
1983 u8 current_band_type;
1984 u8 primary_channel;
1985
1986 /* center channel for different available bandwidth,
1987 * val of (bw > current_band_width) is invalid
1988 */
1989 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1990
1991 u8 sec_ch_offset;
1992 u8 rf_type;
1993 u8 rf_path_num;
1994 u8 rf_phy_num;
1995 u32 antenna_tx;
1996 u32 antenna_rx;
1997 u8 bfee_sts_cap;
1998 bool txrx_1ss;
1999 bool cck_high_power;
2000
2001 /* protect tx power section */
2002 struct mutex tx_power_mutex;
2003 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
2004 [DESC_RATE_MAX];
2005 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
2006 [DESC_RATE_MAX];
2007 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
2008 [RTW_RATE_SECTION_NUM];
2009 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
2010 [RTW_RATE_SECTION_NUM];
2011 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
2012 [RTW_CHANNEL_WIDTH_MAX]
2013 [RTW_RATE_SECTION_NUM]
2014 [RTW_MAX_CHANNEL_NUM_2G];
2015 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
2016 [RTW_CHANNEL_WIDTH_MAX]
2017 [RTW_RATE_SECTION_NUM]
2018 [RTW_MAX_CHANNEL_NUM_5G];
2019 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
2020 [DESC_RATE_MAX];
2021
2022 enum rtw_sar_bands sar_band;
2023 struct rtw_sar sar;
2024
2025 /* for 8821c set channel */
2026 u32 ch_param[3];
2027 };
2028
2029 struct rtw_path_div {
2030 enum rtw_bb_path current_tx_path;
2031 u32 path_a_sum;
2032 u32 path_b_sum;
2033 u16 path_a_cnt;
2034 u16 path_b_cnt;
2035 };
2036
2037 struct rtw_chan_info {
2038 int pri_ch_idx;
2039 int action_id;
2040 int bw;
2041 u8 extra_info;
2042 u8 channel;
2043 u16 timeout;
2044 };
2045
2046 struct rtw_chan_list {
2047 u32 buf_size;
2048 u32 ch_num;
2049 u32 size;
2050 u16 addr;
2051 };
2052
2053 struct rtw_hw_scan_info {
2054 struct ieee80211_vif *scanning_vif;
2055 u8 probe_pg_size;
2056 u8 op_pri_ch_idx;
2057 u8 op_pri_ch;
2058 u8 op_chan;
2059 u8 op_bw;
2060 };
2061
2062 struct rtw_dev {
2063 struct ieee80211_hw *hw;
2064 struct device *dev;
2065
2066 struct rtw_hci hci;
2067
2068 struct rtw_hw_scan_info scan_info;
2069 const struct rtw_chip_info *chip;
2070 struct rtw_hal hal;
2071 struct rtw_fifo_conf fifo;
2072 struct rtw_fw_state fw;
2073 struct rtw_efuse efuse;
2074 struct rtw_sec_desc sec;
2075 struct rtw_traffic_stats stats;
2076 struct rtw_regd regd;
2077 struct rtw_bf_info bf_info;
2078
2079 struct rtw_dm_info dm_info;
2080 struct rtw_coex coex;
2081
2082 /* ensures exclusive access from mac80211 callbacks */
2083 struct mutex mutex;
2084
2085 /* watch dog every 2 sec */
2086 struct delayed_work watch_dog_work;
2087 u32 watch_dog_cnt;
2088
2089 struct list_head rsvd_page_list;
2090
2091 /* c2h cmd queue & handler work */
2092 struct sk_buff_head c2h_queue;
2093 struct work_struct c2h_work;
2094 struct work_struct ips_work;
2095 struct work_struct fw_recovery_work;
2096 struct work_struct update_beacon_work;
2097
2098 /* used to protect txqs list */
2099 spinlock_t txq_lock;
2100 struct list_head txqs;
2101 struct workqueue_struct *tx_wq;
2102 struct work_struct tx_work;
2103 struct work_struct ba_work;
2104
2105 struct rtw_tx_report tx_report;
2106
2107 struct {
2108 /* indicate the mail box to use with fw */
2109 u8 last_box_num;
2110 u32 seq;
2111 } h2c;
2112
2113 /* lps power state & handler work */
2114 struct rtw_lps_conf lps_conf;
2115 bool ps_enabled;
2116 bool beacon_loss;
2117 struct completion lps_leave_check;
2118
2119 struct rtw_debugfs *debugfs;
2120
2121 u8 sta_cnt;
2122 u32 rts_threshold;
2123
2124 DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
2125 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2126 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2127
2128 u8 mp_mode;
2129 struct rtw_path_div dm_path_div;
2130
2131 struct rtw_fw_state wow_fw;
2132 struct rtw_wow_param wow;
2133
2134 bool need_rfk;
2135 struct completion fw_scan_density;
2136 bool ap_active;
2137
2138 bool led_registered;
2139 char led_name[32];
2140 struct led_classdev led_cdev;
2141
2142 /* hci related data, must be last */
2143 u8 priv[] __aligned(sizeof(void *));
2144 };
2145
2146 #include "hci.h"
2147
rtw_is_assoc(struct rtw_dev * rtwdev)2148 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2149 {
2150 return !!rtwdev->sta_cnt;
2151 }
2152
rtwtxq_to_txq(struct rtw_txq * rtwtxq)2153 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2154 {
2155 void *p = rtwtxq;
2156
2157 return container_of(p, struct ieee80211_txq, drv_priv);
2158 }
2159
rtwvif_to_vif(struct rtw_vif * rtwvif)2160 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2161 {
2162 void *p = rtwvif;
2163
2164 return container_of(p, struct ieee80211_vif, drv_priv);
2165 }
2166
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)2167 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2168 {
2169 if (rtwdev->chip->ops->efuse_grant)
2170 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2171 }
2172
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)2173 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2174 {
2175 if (rtwdev->chip->ops->efuse_grant)
2176 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2177 }
2178
rtw_chip_wcpu_8051(struct rtw_dev * rtwdev)2179 static inline bool rtw_chip_wcpu_8051(struct rtw_dev *rtwdev)
2180 {
2181 return rtwdev->chip->wlan_cpu == RTW_WCPU_8051;
2182 }
2183
rtw_chip_wcpu_3081(struct rtw_dev * rtwdev)2184 static inline bool rtw_chip_wcpu_3081(struct rtw_dev *rtwdev)
2185 {
2186 return rtwdev->chip->wlan_cpu == RTW_WCPU_3081;
2187 }
2188
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2189 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2190 {
2191 return rtwdev->chip->rx_ldpc;
2192 }
2193
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2194 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2195 {
2196 return rtwdev->chip->tx_stbc;
2197 }
2198
rtw_acquire_macid(struct rtw_dev * rtwdev)2199 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
2200 {
2201 unsigned long mac_id;
2202
2203 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
2204 if (mac_id < RTW_MAX_MAC_ID_NUM)
2205 set_bit(mac_id, rtwdev->mac_id_map);
2206
2207 return mac_id;
2208 }
2209
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2210 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2211 {
2212 clear_bit(mac_id, rtwdev->mac_id_map);
2213 }
2214
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2215 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2216 {
2217 if (rtwdev->chip->ops->dump_fw_crash)
2218 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2219
2220 return 0;
2221 }
2222
2223 static inline
rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)2224 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2225 {
2226 switch (hw_band) {
2227 default:
2228 case RTW_BAND_2G:
2229 return NL80211_BAND_2GHZ;
2230 case RTW_BAND_5G:
2231 return NL80211_BAND_5GHZ;
2232 case RTW_BAND_60G:
2233 return NL80211_BAND_60GHZ;
2234 }
2235 }
2236
2237 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2238 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2239 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2240 struct rtw_channel_params *ch_param);
2241 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2242 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2243 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2244 void rtw_restore_reg(struct rtw_dev *rtwdev,
2245 struct rtw_backup_info *bckp, u32 num);
2246 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2247 void rtw_set_channel(struct rtw_dev *rtwdev);
2248 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2249 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2250 u32 config);
2251 void rtw_tx_report_purge_timer(struct timer_list *t);
2252 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2253 bool reset_ra_mask);
2254 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2255 const u8 *mac_addr, bool hw_scan);
2256 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2257 bool hw_scan);
2258 int rtw_core_start(struct rtw_dev *rtwdev);
2259 void rtw_power_off(struct rtw_dev *rtwdev);
2260 void rtw_core_stop(struct rtw_dev *rtwdev);
2261 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2262 int rtw_core_init(struct rtw_dev *rtwdev);
2263 void rtw_core_deinit(struct rtw_dev *rtwdev);
2264 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2265 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2266 u16 rtw_desc_to_bitrate(u8 desc_rate);
2267 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2268 struct ieee80211_bss_conf *conf);
2269 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2270 struct ieee80211_vif *vif);
2271 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2272 bool fw_exist);
2273 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2274 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev);
2275 int rtw_power_on(struct rtw_dev *rtwdev);
2276 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2277 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2278 u32 fwcd_item);
2279 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2280 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2281 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2282 u8 primary_channel, enum rtw_supported_band band,
2283 enum rtw_bandwidth bandwidth);
2284 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2285 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
2286 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
2287 void rtw_set_ampdu_factor(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2288 struct ieee80211_bss_conf *bss_conf);
2289
2290 #if defined(__linux__)
2291 #define rtw88_static_assert(_x) static_assert(_x)
2292 #elif defined(__FreeBSD__)
2293 #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size")
2294 #endif
2295
2296 #endif
2297