xref: /linux/drivers/clk/mediatek/clk-mt7622-eth.c (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Chen Zhong <chen.zhong@mediatek.com>
5  *	   Sean Wang <sean.wang@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/platform_device.h>
11 
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
14 
15 #include <dt-bindings/clock/mt7622-clk.h>
16 
17 #define GATE_ETH(_id, _name, _parent, _shift)			\
18 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
19 
20 static const struct mtk_gate_regs eth_cg_regs = {
21 	.set_ofs = 0x30,
22 	.clr_ofs = 0x30,
23 	.sta_ofs = 0x30,
24 };
25 
26 static const struct mtk_gate eth_clks[] = {
27 	GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
28 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
29 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
30 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
31 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
32 };
33 
34 static const struct mtk_gate_regs sgmii_cg_regs = {
35 	.set_ofs = 0xE4,
36 	.clr_ofs = 0xE4,
37 	.sta_ofs = 0xE4,
38 };
39 
40 #define GATE_SGMII(_id, _name, _parent, _shift)			\
41 	GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
42 
43 static const struct mtk_gate sgmii_clks[] = {
44 	GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
45 		   "ssusb_tx250m", 2),
46 	GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
47 		   "ssusb_eq_rx250m", 3),
48 	GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
49 		   "ssusb_cdr_ref", 4),
50 	GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
51 		   "ssusb_cdr_fb", 5),
52 };
53 
54 static u16 rst_ofs[] = { 0x34, };
55 
56 static const struct mtk_clk_rst_desc clk_rst_desc = {
57 	.version = MTK_RST_SIMPLE,
58 	.rst_bank_ofs = rst_ofs,
59 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
60 };
61 
62 static const struct mtk_clk_desc eth_desc = {
63 	.clks = eth_clks,
64 	.num_clks = ARRAY_SIZE(eth_clks),
65 	.rst_desc = &clk_rst_desc,
66 };
67 
68 static const struct mtk_clk_desc sgmii_desc = {
69 	.clks = sgmii_clks,
70 	.num_clks = ARRAY_SIZE(sgmii_clks),
71 };
72 
73 static const struct of_device_id of_match_clk_mt7622_eth[] = {
74 	{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
75 	{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
76 	{ /* sentinel */ }
77 };
78 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth);
79 
80 static struct platform_driver clk_mt7622_eth_drv = {
81 	.probe = mtk_clk_simple_probe,
82 	.remove = mtk_clk_simple_remove,
83 	.driver = {
84 		.name = "clk-mt7622-eth",
85 		.of_match_table = of_match_clk_mt7622_eth,
86 	},
87 };
88 module_platform_driver(clk_mt7622_eth_drv);
89 
90 MODULE_DESCRIPTION("MediaTek MT7622 Ethernet clocks driver");
91 MODULE_LICENSE("GPL");
92