1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/bus.h>
39 #include <sys/sysctl.h>
40
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44
45 #include <dev/ic/ns16550.h>
46
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49
50 #include <dev/puc/puc_bus.h>
51 #include <dev/puc/puc_cfg.h>
52 #include <dev/puc/puc_bfe.h>
53
54 static puc_config_f puc_config_advantech;
55 static puc_config_f puc_config_amc;
56 static puc_config_f puc_config_diva;
57 static puc_config_f puc_config_exar;
58 static puc_config_f puc_config_exar_pcie;
59 static puc_config_f puc_config_icbook;
60 static puc_config_f puc_config_moxa;
61 static puc_config_f puc_config_oxford_pci954;
62 static puc_config_f puc_config_oxford_pcie;
63 static puc_config_f puc_config_quatech;
64 static puc_config_f puc_config_syba;
65 static puc_config_f puc_config_siig;
66 static puc_config_f puc_config_sunix;
67 static puc_config_f puc_config_timedia;
68 static puc_config_f puc_config_titan;
69
70 const struct puc_cfg puc_pci_devices[] = {
71 { 0x0009, 0x7168, 0xffff, 0,
72 "Sunix SUN1889",
73 DEFAULT_RCLK * 8,
74 PUC_PORT_2S, 0x10, 0, 8,
75 },
76
77 { 0x103c, 0x1048, 0x103c, 0x1049,
78 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
79 DEFAULT_RCLK,
80 PUC_PORT_3S, 0x10, 0, -1,
81 .config_function = puc_config_diva
82 },
83
84 { 0x103c, 0x1048, 0x103c, 0x104a,
85 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
86 DEFAULT_RCLK,
87 PUC_PORT_2S, 0x10, 0, -1,
88 .config_function = puc_config_diva
89 },
90
91 { 0x103c, 0x1048, 0x103c, 0x104b,
92 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
93 DEFAULT_RCLK,
94 PUC_PORT_4S, 0x10, 0, -1,
95 .config_function = puc_config_diva
96 },
97
98 { 0x103c, 0x1048, 0x103c, 0x1223,
99 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
100 DEFAULT_RCLK,
101 PUC_PORT_3S, 0x10, 0, -1,
102 .config_function = puc_config_diva
103 },
104
105 { 0x103c, 0x1048, 0x103c, 0x1226,
106 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
107 DEFAULT_RCLK,
108 PUC_PORT_3S, 0x10, 0, -1,
109 .config_function = puc_config_diva
110 },
111
112 { 0x103c, 0x1048, 0x103c, 0x1282,
113 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
114 DEFAULT_RCLK,
115 PUC_PORT_3S, 0x10, 0, -1,
116 .config_function = puc_config_diva
117 },
118
119 { 0x10b5, 0x1076, 0x10b5, 0x1076,
120 "VScom PCI-800",
121 DEFAULT_RCLK * 8,
122 PUC_PORT_8S, 0x18, 0, 8,
123 },
124
125 { 0x10b5, 0x1077, 0x10b5, 0x1077,
126 "VScom PCI-400",
127 DEFAULT_RCLK * 8,
128 PUC_PORT_4S, 0x18, 0, 8,
129 },
130
131 { 0x10b5, 0x1103, 0x10b5, 0x1103,
132 "VScom PCI-200",
133 DEFAULT_RCLK * 8,
134 PUC_PORT_2S, 0x18, 4, 0,
135 },
136
137 /*
138 * Boca Research Turbo Serial 658 (8 serial port) card.
139 * Appears to be the same as Chase Research PLC PCI-FAST8
140 * and Perle PCI-FAST8 Multi-Port serial cards.
141 */
142 { 0x10b5, 0x9050, 0x12e0, 0x0021,
143 "Boca Research Turbo Serial 658",
144 DEFAULT_RCLK * 4,
145 PUC_PORT_8S, 0x18, 0, 8,
146 },
147
148 { 0x10b5, 0x9050, 0x12e0, 0x0031,
149 "Boca Research Turbo Serial 654",
150 DEFAULT_RCLK * 4,
151 PUC_PORT_4S, 0x18, 0, 8,
152 },
153
154 /*
155 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
156 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
157 * into the subsystem fields, and claims that it's a
158 * network/misc (0x02/0x80) device.
159 */
160 { 0x10b5, 0x9050, 0xd84d, 0x6808,
161 "Dolphin Peripherals 4035",
162 DEFAULT_RCLK,
163 PUC_PORT_2S, 0x18, 4, 0,
164 },
165
166 /*
167 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
168 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
169 * into the subsystem fields, and claims that it's a
170 * network/misc (0x02/0x80) device.
171 */
172 { 0x10b5, 0x9050, 0xd84d, 0x6810,
173 "Dolphin Peripherals 4014",
174 0,
175 PUC_PORT_2P, 0x20, 4, 0,
176 },
177
178 { 0x10e8, 0x818e, 0xffff, 0,
179 "Applied Micro Circuits 8 Port UART",
180 DEFAULT_RCLK,
181 PUC_PORT_8S, 0x14, -1, -1,
182 .config_function = puc_config_amc
183 },
184
185 /*
186 * The following members of the Digi International Neo series are
187 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
188 * Accordingly, the PCIe versions of these cards incorporate a PLX
189 * PCIe-PCI-bridge.
190 */
191
192 { 0x114f, 0x00b0, 0xffff, 0,
193 "Digi Neo PCI 4 Port",
194 DEFAULT_RCLK * 8,
195 PUC_PORT_4S, 0x10, 0, -1,
196 .config_function = puc_config_exar
197 },
198
199 { 0x114f, 0x00b1, 0xffff, 0,
200 "Digi Neo PCI 8 Port",
201 DEFAULT_RCLK * 8,
202 PUC_PORT_8S, 0x10, 0, -1,
203 .config_function = puc_config_exar
204 },
205
206 { 0x114f, 0x00f0, 0xffff, 0,
207 "Digi Neo PCIe 8 Port",
208 DEFAULT_RCLK * 8,
209 PUC_PORT_8S, 0x10, 0, -1,
210 .config_function = puc_config_exar
211 },
212
213 { 0x114f, 0x00f1, 0xffff, 0,
214 "Digi Neo PCIe 4 Port",
215 DEFAULT_RCLK * 8,
216 PUC_PORT_4S, 0x10, 0, -1,
217 .config_function = puc_config_exar
218 },
219
220 { 0x114f, 0x00f2, 0xffff, 0,
221 "Digi Neo PCIe 4 Port RJ45",
222 DEFAULT_RCLK * 8,
223 PUC_PORT_4S, 0x10, 0, -1,
224 .config_function = puc_config_exar
225 },
226
227 { 0x114f, 0x00f3, 0xffff, 0,
228 "Digi Neo PCIe 8 Port RJ45",
229 DEFAULT_RCLK * 8,
230 PUC_PORT_8S, 0x10, 0, -1,
231 .config_function = puc_config_exar
232 },
233
234 { 0x11fe, 0x8010, 0xffff, 0,
235 "Comtrol RocketPort 550/8 RJ11 part A",
236 DEFAULT_RCLK * 4,
237 PUC_PORT_4S, 0x10, 0, 8,
238 },
239
240 { 0x11fe, 0x8011, 0xffff, 0,
241 "Comtrol RocketPort 550/8 RJ11 part B",
242 DEFAULT_RCLK * 4,
243 PUC_PORT_4S, 0x10, 0, 8,
244 },
245
246 { 0x11fe, 0x8012, 0xffff, 0,
247 "Comtrol RocketPort 550/8 Octa part A",
248 DEFAULT_RCLK * 4,
249 PUC_PORT_4S, 0x10, 0, 8,
250 },
251
252 { 0x11fe, 0x8013, 0xffff, 0,
253 "Comtrol RocketPort 550/8 Octa part B",
254 DEFAULT_RCLK * 4,
255 PUC_PORT_4S, 0x10, 0, 8,
256 },
257
258 { 0x11fe, 0x8014, 0xffff, 0,
259 "Comtrol RocketPort 550/4 RJ45",
260 DEFAULT_RCLK * 4,
261 PUC_PORT_4S, 0x10, 0, 8,
262 },
263
264 { 0x11fe, 0x8015, 0xffff, 0,
265 "Comtrol RocketPort 550/Quad",
266 DEFAULT_RCLK * 4,
267 PUC_PORT_4S, 0x10, 0, 8,
268 },
269
270 { 0x11fe, 0x8016, 0xffff, 0,
271 "Comtrol RocketPort 550/16 part A",
272 DEFAULT_RCLK * 4,
273 PUC_PORT_4S, 0x10, 0, 8,
274 },
275
276 { 0x11fe, 0x8017, 0xffff, 0,
277 "Comtrol RocketPort 550/16 part B",
278 DEFAULT_RCLK * 4,
279 PUC_PORT_12S, 0x10, 0, 8,
280 },
281
282 { 0x11fe, 0x8018, 0xffff, 0,
283 "Comtrol RocketPort 550/8 part A",
284 DEFAULT_RCLK * 4,
285 PUC_PORT_4S, 0x10, 0, 8,
286 },
287
288 { 0x11fe, 0x8019, 0xffff, 0,
289 "Comtrol RocketPort 550/8 part B",
290 DEFAULT_RCLK * 4,
291 PUC_PORT_4S, 0x10, 0, 8,
292 },
293
294 /*
295 * IBM SurePOS 300 Series (481033H) serial ports
296 * Details can be found on the IBM RSS websites
297 */
298
299 { 0x1014, 0x0297, 0xffff, 0,
300 "IBM SurePOS 300 Series (481033H) serial ports",
301 DEFAULT_RCLK,
302 PUC_PORT_4S, 0x10, 4, 0
303 },
304
305 /*
306 * SIIG Boards.
307 *
308 * SIIG provides documentation for their boards at:
309 * <URL:http://www.siig.com/downloads.asp>
310 */
311
312 { 0x131f, 0x1010, 0xffff, 0,
313 "SIIG Cyber I/O PCI 16C550 (10x family)",
314 DEFAULT_RCLK,
315 PUC_PORT_1S1P, 0x18, 4, 0,
316 },
317
318 { 0x131f, 0x1011, 0xffff, 0,
319 "SIIG Cyber I/O PCI 16C650 (10x family)",
320 DEFAULT_RCLK,
321 PUC_PORT_1S1P, 0x18, 4, 0,
322 },
323
324 { 0x131f, 0x1012, 0xffff, 0,
325 "SIIG Cyber I/O PCI 16C850 (10x family)",
326 DEFAULT_RCLK,
327 PUC_PORT_1S1P, 0x18, 4, 0,
328 },
329
330 { 0x131f, 0x1021, 0xffff, 0,
331 "SIIG Cyber Parallel Dual PCI (10x family)",
332 0,
333 PUC_PORT_2P, 0x18, 8, 0,
334 },
335
336 { 0x131f, 0x1030, 0xffff, 0,
337 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
338 DEFAULT_RCLK,
339 PUC_PORT_2S, 0x18, 4, 0,
340 },
341
342 { 0x131f, 0x1031, 0xffff, 0,
343 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
344 DEFAULT_RCLK,
345 PUC_PORT_2S, 0x18, 4, 0,
346 },
347
348 { 0x131f, 0x1032, 0xffff, 0,
349 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
350 DEFAULT_RCLK,
351 PUC_PORT_2S, 0x18, 4, 0,
352 },
353
354 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
355 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
356 DEFAULT_RCLK,
357 PUC_PORT_2S1P, 0x18, 4, 0,
358 },
359
360 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
361 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
362 DEFAULT_RCLK,
363 PUC_PORT_2S1P, 0x18, 4, 0,
364 },
365
366 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
367 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
368 DEFAULT_RCLK,
369 PUC_PORT_2S1P, 0x18, 4, 0,
370 },
371
372 { 0x131f, 0x1050, 0xffff, 0,
373 "SIIG Cyber 4S PCI 16C550 (10x family)",
374 DEFAULT_RCLK,
375 PUC_PORT_4S, 0x18, 4, 0,
376 },
377
378 { 0x131f, 0x1051, 0xffff, 0,
379 "SIIG Cyber 4S PCI 16C650 (10x family)",
380 DEFAULT_RCLK,
381 PUC_PORT_4S, 0x18, 4, 0,
382 },
383
384 { 0x131f, 0x1052, 0xffff, 0,
385 "SIIG Cyber 4S PCI 16C850 (10x family)",
386 DEFAULT_RCLK,
387 PUC_PORT_4S, 0x18, 4, 0,
388 },
389
390 { 0x131f, 0x2010, 0xffff, 0,
391 "SIIG Cyber I/O PCI 16C550 (20x family)",
392 DEFAULT_RCLK,
393 PUC_PORT_1S1P, 0x10, 4, 0,
394 },
395
396 { 0x131f, 0x2011, 0xffff, 0,
397 "SIIG Cyber I/O PCI 16C650 (20x family)",
398 DEFAULT_RCLK,
399 PUC_PORT_1S1P, 0x10, 4, 0,
400 },
401
402 { 0x131f, 0x2012, 0xffff, 0,
403 "SIIG Cyber I/O PCI 16C850 (20x family)",
404 DEFAULT_RCLK,
405 PUC_PORT_1S1P, 0x10, 4, 0,
406 },
407
408 { 0x131f, 0x2021, 0xffff, 0,
409 "SIIG Cyber Parallel Dual PCI (20x family)",
410 0,
411 PUC_PORT_2P, 0x10, 8, 0,
412 },
413
414 { 0x131f, 0x2030, 0xffff, 0,
415 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
416 DEFAULT_RCLK,
417 PUC_PORT_2S, 0x10, 4, 0,
418 },
419
420 { 0x131f, 0x2031, 0xffff, 0,
421 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
422 DEFAULT_RCLK,
423 PUC_PORT_2S, 0x10, 4, 0,
424 },
425
426 { 0x131f, 0x2032, 0xffff, 0,
427 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
428 DEFAULT_RCLK,
429 PUC_PORT_2S, 0x10, 4, 0,
430 },
431
432 { 0x131f, 0x2040, 0xffff, 0,
433 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
434 DEFAULT_RCLK,
435 PUC_PORT_1S2P, 0x10, -1, 0,
436 .config_function = puc_config_siig
437 },
438
439 { 0x131f, 0x2041, 0xffff, 0,
440 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
441 DEFAULT_RCLK,
442 PUC_PORT_1S2P, 0x10, -1, 0,
443 .config_function = puc_config_siig
444 },
445
446 { 0x131f, 0x2042, 0xffff, 0,
447 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
448 DEFAULT_RCLK,
449 PUC_PORT_1S2P, 0x10, -1, 0,
450 .config_function = puc_config_siig
451 },
452
453 { 0x131f, 0x2050, 0xffff, 0,
454 "SIIG Cyber 4S PCI 16C550 (20x family)",
455 DEFAULT_RCLK,
456 PUC_PORT_4S, 0x10, 4, 0,
457 },
458
459 { 0x131f, 0x2051, 0xffff, 0,
460 "SIIG Cyber 4S PCI 16C650 (20x family)",
461 DEFAULT_RCLK,
462 PUC_PORT_4S, 0x10, 4, 0,
463 },
464
465 { 0x131f, 0x2052, 0xffff, 0,
466 "SIIG Cyber 4S PCI 16C850 (20x family)",
467 DEFAULT_RCLK,
468 PUC_PORT_4S, 0x10, 4, 0,
469 },
470
471 { 0x131f, 0x2060, 0xffff, 0,
472 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
473 DEFAULT_RCLK,
474 PUC_PORT_2S1P, 0x10, 4, 0,
475 },
476
477 { 0x131f, 0x2061, 0xffff, 0,
478 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
479 DEFAULT_RCLK,
480 PUC_PORT_2S1P, 0x10, 4, 0,
481 },
482
483 { 0x131f, 0x2062, 0xffff, 0,
484 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
485 DEFAULT_RCLK,
486 PUC_PORT_2S1P, 0x10, 4, 0,
487 },
488
489 { 0x131f, 0x2081, 0xffff, 0,
490 "SIIG PS8000 8S PCI 16C650 (20x family)",
491 DEFAULT_RCLK,
492 PUC_PORT_8S, 0x10, -1, -1,
493 .config_function = puc_config_siig
494 },
495
496 { 0x135c, 0x0010, 0xffff, 0,
497 "Quatech QSC-100",
498 -3, /* max 8x clock rate */
499 PUC_PORT_4S, 0x14, 0, 8,
500 .config_function = puc_config_quatech
501 },
502
503 { 0x135c, 0x0020, 0xffff, 0,
504 "Quatech DSC-100",
505 -1, /* max 2x clock rate */
506 PUC_PORT_2S, 0x14, 0, 8,
507 .config_function = puc_config_quatech
508 },
509
510 { 0x135c, 0x0030, 0xffff, 0,
511 "Quatech DSC-200/300",
512 -1, /* max 2x clock rate */
513 PUC_PORT_2S, 0x14, 0, 8,
514 .config_function = puc_config_quatech
515 },
516
517 { 0x135c, 0x0040, 0xffff, 0,
518 "Quatech QSC-200/300",
519 -3, /* max 8x clock rate */
520 PUC_PORT_4S, 0x14, 0, 8,
521 .config_function = puc_config_quatech
522 },
523
524 { 0x135c, 0x0050, 0xffff, 0,
525 "Quatech ESC-100D",
526 -3, /* max 8x clock rate */
527 PUC_PORT_8S, 0x14, 0, 8,
528 .config_function = puc_config_quatech
529 },
530
531 { 0x135c, 0x0060, 0xffff, 0,
532 "Quatech ESC-100M",
533 -3, /* max 8x clock rate */
534 PUC_PORT_8S, 0x14, 0, 8,
535 .config_function = puc_config_quatech
536 },
537
538 { 0x135c, 0x0170, 0xffff, 0,
539 "Quatech QSCLP-100",
540 -1, /* max 2x clock rate */
541 PUC_PORT_4S, 0x18, 0, 8,
542 .config_function = puc_config_quatech
543 },
544
545 { 0x135c, 0x0180, 0xffff, 0,
546 "Quatech DSCLP-100",
547 -1, /* max 3x clock rate */
548 PUC_PORT_2S, 0x18, 0, 8,
549 .config_function = puc_config_quatech
550 },
551
552 { 0x135c, 0x01b0, 0xffff, 0,
553 "Quatech DSCLP-200/300",
554 -1, /* max 2x clock rate */
555 PUC_PORT_2S, 0x18, 0, 8,
556 .config_function = puc_config_quatech
557 },
558
559 { 0x135c, 0x01e0, 0xffff, 0,
560 "Quatech ESCLP-100",
561 -3, /* max 8x clock rate */
562 PUC_PORT_8S, 0x10, 0, 8,
563 .config_function = puc_config_quatech
564 },
565
566 { 0x1393, 0x1024, 0xffff, 0,
567 "Moxa Technologies, Smartio CP-102E/PCIe",
568 DEFAULT_RCLK * 8,
569 PUC_PORT_2S, 0x14, 0, -1,
570 .config_function = puc_config_moxa
571 },
572
573 { 0x1393, 0x1025, 0xffff, 0,
574 "Moxa Technologies, Smartio CP-102EL/PCIe",
575 DEFAULT_RCLK * 8,
576 PUC_PORT_2S, 0x14, 0, -1,
577 .config_function = puc_config_moxa
578 },
579
580 { 0x1393, 0x1040, 0xffff, 0,
581 "Moxa Technologies, Smartio C104H/PCI",
582 DEFAULT_RCLK * 8,
583 PUC_PORT_4S, 0x18, 0, 8,
584 },
585
586 { 0x1393, 0x1041, 0xffff, 0,
587 "Moxa Technologies, Smartio CP-104UL/PCI",
588 DEFAULT_RCLK * 8,
589 PUC_PORT_4S, 0x18, 0, 8,
590 },
591
592 { 0x1393, 0x1042, 0xffff, 0,
593 "Moxa Technologies, Smartio CP-104JU/PCI",
594 DEFAULT_RCLK * 8,
595 PUC_PORT_4S, 0x18, 0, 8,
596 },
597
598 { 0x1393, 0x1043, 0xffff, 0,
599 "Moxa Technologies, Smartio CP-104EL/PCIe",
600 DEFAULT_RCLK * 8,
601 PUC_PORT_4S, 0x18, 0, 8,
602 },
603
604 { 0x1393, 0x1045, 0xffff, 0,
605 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
606 DEFAULT_RCLK * 8,
607 PUC_PORT_4S, 0x14, 0, -1,
608 .config_function = puc_config_moxa
609 },
610
611 { 0x1393, 0x1120, 0xffff, 0,
612 "Moxa Technologies, CP-112UL",
613 DEFAULT_RCLK * 8,
614 PUC_PORT_2S, 0x18, 0, 8,
615 },
616
617 { 0x1393, 0x1141, 0xffff, 0,
618 "Moxa Technologies, Industio CP-114",
619 DEFAULT_RCLK * 8,
620 PUC_PORT_4S, 0x18, 0, 8,
621 },
622
623 { 0x1393, 0x1144, 0xffff, 0,
624 "Moxa Technologies, Smartio CP-114EL/PCIe",
625 DEFAULT_RCLK * 8,
626 PUC_PORT_4S, 0x14, 0, -1,
627 .config_function = puc_config_moxa
628 },
629
630 { 0x1393, 0x1182, 0xffff, 0,
631 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
632 DEFAULT_RCLK * 8,
633 PUC_PORT_8S, 0x14, 0, -1,
634 .config_function = puc_config_moxa
635 },
636
637 { 0x1393, 0x1680, 0xffff, 0,
638 "Moxa Technologies, C168H/PCI",
639 DEFAULT_RCLK * 8,
640 PUC_PORT_8S, 0x18, 0, 8,
641 },
642
643 { 0x1393, 0x1681, 0xffff, 0,
644 "Moxa Technologies, C168U/PCI",
645 DEFAULT_RCLK * 8,
646 PUC_PORT_8S, 0x18, 0, 8,
647 },
648
649 { 0x1393, 0x1682, 0xffff, 0,
650 "Moxa Technologies, CP-168EL/PCIe",
651 DEFAULT_RCLK * 8,
652 PUC_PORT_8S, 0x18, 0, 8,
653 },
654
655 { 0x1393, 0x1683, 0xffff, 0,
656 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
657 DEFAULT_RCLK * 8,
658 PUC_PORT_8S, 0x14, 0, -1,
659 .config_function = puc_config_moxa
660 },
661
662 { 0x13a8, 0x0152, 0xffff, 0,
663 "Exar XR17C/D152",
664 DEFAULT_RCLK * 8,
665 PUC_PORT_2S, 0x10, 0, -1,
666 .config_function = puc_config_exar
667 },
668
669 { 0x13a8, 0x0154, 0xffff, 0,
670 "Exar XR17C154",
671 DEFAULT_RCLK * 8,
672 PUC_PORT_4S, 0x10, 0, -1,
673 .config_function = puc_config_exar
674 },
675
676 { 0x13a8, 0x0158, 0xffff, 0,
677 "Exar XR17C158",
678 DEFAULT_RCLK * 8,
679 PUC_PORT_8S, 0x10, 0, -1,
680 .config_function = puc_config_exar
681 },
682
683 { 0x13a8, 0x0258, 0xffff, 0,
684 "Exar XR17V258IV",
685 DEFAULT_RCLK * 8,
686 PUC_PORT_8S, 0x10, 0, -1,
687 .config_function = puc_config_exar
688 },
689
690 { 0x13a8, 0x0352, 0xffff, 0,
691 "Exar XR17V352",
692 125000000,
693 PUC_PORT_2S, 0x10, 0, -1,
694 .config_function = puc_config_exar_pcie
695 },
696
697 { 0x13a8, 0x0354, 0xffff, 0,
698 "Exar XR17V354",
699 125000000,
700 PUC_PORT_4S, 0x10, 0, -1,
701 .config_function = puc_config_exar_pcie
702 },
703
704 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
705 { 0x13a8, 0x0358, 0xffff, 0,
706 "Exar XR17V358",
707 125000000,
708 PUC_PORT_8S, 0x10, 0, -1,
709 .config_function = puc_config_exar_pcie
710 },
711
712 /*
713 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
714 * Semiconductor OXuPCI954. Note these boards have a hardware bug in
715 * that they drive the RS-422/485 transmitters after power-on until a
716 * driver initializes the UARTs.
717 */
718 { 0x13fe, 0x1600, 0x1602, 0x0002,
719 "Advantech PCI-1602 Rev. A",
720 DEFAULT_RCLK * 8,
721 PUC_PORT_2S, 0x10, 0, 8,
722 .config_function = puc_config_advantech
723 },
724
725 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
726 { 0x13fe, 0xa102, 0x13fe, 0xa102,
727 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
728 DEFAULT_RCLK * 8,
729 PUC_PORT_2S, 0x10, 4, 0,
730 .config_function = puc_config_advantech
731 },
732
733 { 0x1407, 0x0100, 0xffff, 0,
734 "Lava Computers Dual Serial",
735 DEFAULT_RCLK,
736 PUC_PORT_2S, 0x10, 4, 0,
737 },
738
739 { 0x1407, 0x0101, 0xffff, 0,
740 "Lava Computers Quatro A",
741 DEFAULT_RCLK,
742 PUC_PORT_2S, 0x10, 4, 0,
743 },
744
745 { 0x1407, 0x0102, 0xffff, 0,
746 "Lava Computers Quatro B",
747 DEFAULT_RCLK,
748 PUC_PORT_2S, 0x10, 4, 0,
749 },
750
751 { 0x1407, 0x0120, 0xffff, 0,
752 "Lava Computers Quattro-PCI A",
753 DEFAULT_RCLK,
754 PUC_PORT_2S, 0x10, 4, 0,
755 },
756
757 { 0x1407, 0x0121, 0xffff, 0,
758 "Lava Computers Quattro-PCI B",
759 DEFAULT_RCLK,
760 PUC_PORT_2S, 0x10, 4, 0,
761 },
762
763 { 0x1407, 0x0180, 0xffff, 0,
764 "Lava Computers Octo A",
765 DEFAULT_RCLK,
766 PUC_PORT_4S, 0x10, 4, 0,
767 },
768
769 { 0x1407, 0x0181, 0xffff, 0,
770 "Lava Computers Octo B",
771 DEFAULT_RCLK,
772 PUC_PORT_4S, 0x10, 4, 0,
773 },
774
775 { 0x1409, 0x7268, 0xffff, 0,
776 "Sunix SUN1888",
777 0,
778 PUC_PORT_2P, 0x10, 0, 8,
779 },
780
781 { 0x1409, 0x7168, 0xffff, 0,
782 NULL,
783 DEFAULT_RCLK * 8,
784 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
785 .config_function = puc_config_timedia
786 },
787
788 /*
789 * Boards with an Oxford Semiconductor chip.
790 *
791 * Oxford Semiconductor provides documentation for their chip at:
792 * <URL:http://www.plxtech.com/products/uart/>
793 *
794 * As sold by Kouwell <URL:http://www.kouwell.com/>.
795 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
796 */
797 {
798 0x1415, 0x9501, 0x10fc, 0xc070,
799 "I-O DATA RSA-PCI2/R",
800 DEFAULT_RCLK * 8,
801 PUC_PORT_2S, 0x10, 0, 8,
802 },
803
804 { 0x1415, 0x9501, 0x131f, 0x2050,
805 "SIIG Cyber 4 PCI 16550",
806 DEFAULT_RCLK * 10,
807 PUC_PORT_4S, 0x10, 0, 8,
808 },
809
810 { 0x1415, 0x9501, 0x131f, 0x2051,
811 "SIIG Cyber 4S PCI 16C650 (20x family)",
812 DEFAULT_RCLK * 10,
813 PUC_PORT_4S, 0x10, 0, 8,
814 },
815
816 { 0x1415, 0x9501, 0x131f, 0x2052,
817 "SIIG Quartet Serial 850",
818 DEFAULT_RCLK * 10,
819 PUC_PORT_4S, 0x10, 0, 8,
820 },
821
822 { 0x1415, 0x9501, 0x14db, 0x2150,
823 "Kuroutoshikou SERIAL4P-LPPCI2",
824 DEFAULT_RCLK * 10,
825 PUC_PORT_4S, 0x10, 0, 8,
826 },
827
828 { 0x1415, 0x9501, 0xffff, 0,
829 "Oxford Semiconductor OX16PCI954 UARTs",
830 0,
831 PUC_PORT_4S, 0x10, 0, 8,
832 .config_function = puc_config_oxford_pci954
833 },
834
835 { 0x1415, 0x950a, 0x131f, 0x2030,
836 "SIIG Cyber 2S PCIe",
837 DEFAULT_RCLK * 10,
838 PUC_PORT_2S, 0x10, 0, 8,
839 },
840
841 { 0x1415, 0x950a, 0x131f, 0x2032,
842 "SIIG Cyber Serial Dual PCI 16C850",
843 DEFAULT_RCLK * 10,
844 PUC_PORT_4S, 0x10, 0, 8,
845 },
846
847 { 0x1415, 0x950a, 0x131f, 0x2061,
848 "SIIG Cyber 2SP1 PCIe",
849 DEFAULT_RCLK * 10,
850 PUC_PORT_2S, 0x10, 0, 8,
851 },
852
853 { 0x1415, 0x950a, 0xffff, 0,
854 "Oxford Semiconductor OX16PCI954 UARTs",
855 DEFAULT_RCLK,
856 PUC_PORT_4S, 0x10, 0, 8,
857 },
858
859 { 0x1415, 0x9511, 0xffff, 0,
860 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
861 DEFAULT_RCLK,
862 PUC_PORT_4S, 0x10, 0, 8,
863 },
864
865 { 0x1415, 0x9521, 0xffff, 0,
866 "Oxford Semiconductor OX16PCI952 UARTs",
867 DEFAULT_RCLK,
868 PUC_PORT_2S, 0x10, 4, 0,
869 },
870
871 { 0x1415, 0x9538, 0xffff, 0,
872 "Oxford Semiconductor OX16PCI958 UARTs",
873 DEFAULT_RCLK,
874 PUC_PORT_8S, 0x18, 0, 8,
875 },
876
877 /*
878 * Perle boards use Oxford Semiconductor chips, but they store the
879 * Oxford Semiconductor device ID as a subvendor device ID and use
880 * their own device IDs.
881 */
882
883 { 0x155f, 0x0331, 0xffff, 0,
884 "Perle Ultraport4 Express",
885 DEFAULT_RCLK * 8,
886 PUC_PORT_4S, 0x10, 0, 8,
887 },
888
889 { 0x155f, 0xB012, 0xffff, 0,
890 "Perle Speed2 LE",
891 DEFAULT_RCLK * 8,
892 PUC_PORT_2S, 0x10, 0, 8,
893 },
894
895 { 0x155f, 0xB022, 0xffff, 0,
896 "Perle Speed2 LE",
897 DEFAULT_RCLK * 8,
898 PUC_PORT_2S, 0x10, 0, 8,
899 },
900
901 { 0x155f, 0xB004, 0xffff, 0,
902 "Perle Speed4 LE",
903 DEFAULT_RCLK * 8,
904 PUC_PORT_4S, 0x10, 0, 8,
905 },
906
907 { 0x155f, 0xB008, 0xffff, 0,
908 "Perle Speed8 LE",
909 DEFAULT_RCLK * 8,
910 PUC_PORT_8S, 0x10, 0, 8,
911 },
912
913 /*
914 * Oxford Semiconductor PCI Express Expresso family
915 *
916 * Found in many 'native' PCI Express serial boards such as:
917 *
918 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
919 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
920 *
921 * Lindy 51189 (4 port)
922 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
923 *
924 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
925 * <URL:http://www.startech.com>
926 */
927
928 { 0x1415, 0xc11b, 0xffff, 0,
929 "Oxford Semiconductor OXPCIe952 1S1P",
930 DEFAULT_RCLK * 0x22,
931 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
932 .config_function = puc_config_oxford_pcie
933 },
934
935 { 0x1415, 0xc138, 0xffff, 0,
936 "Oxford Semiconductor OXPCIe952 UARTs",
937 DEFAULT_RCLK * 0x22,
938 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
939 .config_function = puc_config_oxford_pcie
940 },
941
942 { 0x1415, 0xc158, 0xffff, 0,
943 "Oxford Semiconductor OXPCIe952 UARTs",
944 DEFAULT_RCLK * 0x22,
945 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
946 .config_function = puc_config_oxford_pcie
947 },
948
949 { 0x1415, 0xc15d, 0xffff, 0,
950 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
951 DEFAULT_RCLK * 0x22,
952 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
953 .config_function = puc_config_oxford_pcie
954 },
955
956 { 0x1415, 0xc208, 0xffff, 0,
957 "Oxford Semiconductor OXPCIe954 UARTs",
958 DEFAULT_RCLK * 0x22,
959 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
960 .config_function = puc_config_oxford_pcie
961 },
962
963 { 0x1415, 0xc20d, 0xffff, 0,
964 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
965 DEFAULT_RCLK * 0x22,
966 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
967 .config_function = puc_config_oxford_pcie
968 },
969
970 { 0x1415, 0xc308, 0xffff, 0,
971 "Oxford Semiconductor OXPCIe958 UARTs",
972 DEFAULT_RCLK * 0x22,
973 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
974 .config_function = puc_config_oxford_pcie
975 },
976
977 { 0x1415, 0xc30d, 0xffff, 0,
978 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
979 DEFAULT_RCLK * 0x22,
980 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
981 .config_function = puc_config_oxford_pcie
982 },
983
984 { 0x14d2, 0x8010, 0xffff, 0,
985 "VScom PCI-100L",
986 DEFAULT_RCLK * 8,
987 PUC_PORT_1S, 0x14, 0, 0,
988 },
989
990 { 0x14d2, 0x8020, 0xffff, 0,
991 "VScom PCI-200L",
992 DEFAULT_RCLK * 8,
993 PUC_PORT_2S, 0x14, 4, 0,
994 },
995
996 { 0x14d2, 0x8028, 0xffff, 0,
997 "VScom 200Li",
998 DEFAULT_RCLK,
999 PUC_PORT_2S, 0x20, 0, 8,
1000 },
1001
1002 /*
1003 * VScom (Titan?) PCI-800L. More modern variant of the
1004 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1005 * two of them obviously implemented as macro cells in
1006 * the ASIC. This causes the weird port access pattern
1007 * below, where two of the IO port ranges each access
1008 * one of the ASIC UARTs, and a block of IO addresses
1009 * access the external UARTs.
1010 */
1011 { 0x14d2, 0x8080, 0xffff, 0,
1012 "Titan VScom PCI-800L",
1013 DEFAULT_RCLK * 8,
1014 PUC_PORT_8S, 0x14, -1, -1,
1015 .config_function = puc_config_titan
1016 },
1017
1018 /*
1019 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1020 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1021 * device ID 3 and PCI device 1 device ID 4.
1022 */
1023 { 0x14d2, 0xa003, 0xffff, 0,
1024 "Titan PCI-800H",
1025 DEFAULT_RCLK * 8,
1026 PUC_PORT_4S, 0x10, 0, 8,
1027 },
1028
1029 { 0x14d2, 0xa004, 0xffff, 0,
1030 "Titan PCI-800H",
1031 DEFAULT_RCLK * 8,
1032 PUC_PORT_4S, 0x10, 0, 8,
1033 },
1034
1035 { 0x14d2, 0xa005, 0xffff, 0,
1036 "Titan PCI-200H",
1037 DEFAULT_RCLK * 8,
1038 PUC_PORT_2S, 0x10, 0, 8,
1039 },
1040
1041 { 0x14d2, 0xe020, 0xffff, 0,
1042 "Titan VScom PCI-200HV2",
1043 DEFAULT_RCLK * 8,
1044 PUC_PORT_2S, 0x10, 4, 0,
1045 },
1046
1047 { 0x14d2, 0xa007, 0xffff, 0,
1048 "Titan VScom PCIex-800H",
1049 DEFAULT_RCLK * 8,
1050 PUC_PORT_4S, 0x10, 0, 8,
1051 },
1052
1053 { 0x14d2, 0xa008, 0xffff, 0,
1054 "Titan VScom PCIex-800H",
1055 DEFAULT_RCLK * 8,
1056 PUC_PORT_4S, 0x10, 0, 8,
1057 },
1058
1059 { 0x14db, 0x2130, 0xffff, 0,
1060 "Avlab Technology, PCI IO 2S",
1061 DEFAULT_RCLK,
1062 PUC_PORT_2S, 0x10, 4, 0,
1063 },
1064
1065 { 0x14db, 0x2150, 0xffff, 0,
1066 "Avlab Low Profile PCI 4 Serial",
1067 DEFAULT_RCLK,
1068 PUC_PORT_4S, 0x10, 4, 0,
1069 },
1070
1071 { 0x14db, 0x2152, 0xffff, 0,
1072 "Avlab Low Profile PCI 4 Serial",
1073 DEFAULT_RCLK,
1074 PUC_PORT_4S, 0x10, 4, 0,
1075 },
1076
1077 { 0x1592, 0x0781, 0xffff, 0,
1078 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1079 DEFAULT_RCLK,
1080 PUC_PORT_4S1P, 0x10, 0, -1,
1081 .config_function = puc_config_syba
1082 },
1083
1084 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1085 "Sunix SER5xxxx 2-port serial",
1086 DEFAULT_RCLK * 8,
1087 PUC_PORT_2S, 0x10, 0, 8,
1088 },
1089
1090 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1091 "Sunix SER5xxxx 4-port serial",
1092 DEFAULT_RCLK * 8,
1093 PUC_PORT_4S, 0x10, 0, 8,
1094 },
1095
1096 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1097 "Sunix SER5xxxx 8-port serial",
1098 DEFAULT_RCLK * 8,
1099 PUC_PORT_8S, -1, -1, -1,
1100 .config_function = puc_config_sunix
1101 },
1102
1103 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1104 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1105 DEFAULT_RCLK * 8,
1106 PUC_PORT_1S1P, -1, -1, -1,
1107 .config_function = puc_config_sunix
1108 },
1109
1110 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1111 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1112 DEFAULT_RCLK * 8,
1113 PUC_PORT_2S1P, -1, -1, -1,
1114 .config_function = puc_config_sunix
1115 },
1116
1117 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1118 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1119 DEFAULT_RCLK * 8,
1120 PUC_PORT_4S1P, -1, -1, -1,
1121 .config_function = puc_config_sunix
1122 },
1123
1124 { 0x5372, 0x6872, 0xffff, 0,
1125 "Feasso PCI FPP-02 2S1P",
1126 DEFAULT_RCLK,
1127 PUC_PORT_2S1P, 0x10, 4, 0,
1128 },
1129
1130 { 0x5372, 0x6873, 0xffff, 0,
1131 "Sun 1040 PCI Quad Serial",
1132 DEFAULT_RCLK,
1133 PUC_PORT_4S, 0x10, 4, 0,
1134 },
1135
1136 { 0x6666, 0x0001, 0xffff, 0,
1137 "Decision Computer Inc, PCCOM 4-port serial",
1138 DEFAULT_RCLK,
1139 PUC_PORT_4S, 0x1c, 0, 8,
1140 },
1141
1142 { 0x6666, 0x0002, 0xffff, 0,
1143 "Decision Computer Inc, PCCOM 8-port serial",
1144 DEFAULT_RCLK,
1145 PUC_PORT_8S, 0x1c, 0, 8,
1146 },
1147
1148 { 0x6666, 0x0004, 0xffff, 0,
1149 "PCCOM dual port RS232/422/485",
1150 DEFAULT_RCLK,
1151 PUC_PORT_2S, 0x1c, 0, 8,
1152 },
1153
1154 { 0x9710, 0x9815, 0xffff, 0,
1155 "NetMos NM9815 Dual 1284 Printer port",
1156 0,
1157 PUC_PORT_2P, 0x10, 8, 0,
1158 },
1159
1160 /*
1161 * This is more specific than the generic NM9835 entry, and is placed
1162 * here to _prevent_ puc(4) from claiming this single port card.
1163 *
1164 * uart(4) will claim this device.
1165 */
1166 { 0x9710, 0x9835, 0x1000, 1,
1167 "NetMos NM9835 based 1-port serial",
1168 DEFAULT_RCLK,
1169 PUC_PORT_1S, 0x10, 4, 0,
1170 },
1171
1172 { 0x9710, 0x9835, 0x1000, 2,
1173 "NetMos NM9835 based 2-port serial",
1174 DEFAULT_RCLK,
1175 PUC_PORT_2S, 0x10, 4, 0,
1176 },
1177
1178 { 0x9710, 0x9835, 0xffff, 0,
1179 "NetMos NM9835 Dual UART and 1284 Printer port",
1180 DEFAULT_RCLK,
1181 PUC_PORT_2S1P, 0x10, 4, 0,
1182 },
1183
1184 { 0x9710, 0x9845, 0x1000, 0x0006,
1185 "NetMos NM9845 6 Port UART",
1186 DEFAULT_RCLK,
1187 PUC_PORT_6S, 0x10, 4, 0,
1188 },
1189
1190 { 0x9710, 0x9845, 0xffff, 0,
1191 "NetMos NM9845 Quad UART and 1284 Printer port",
1192 DEFAULT_RCLK,
1193 PUC_PORT_4S1P, 0x10, 4, 0,
1194 },
1195
1196 { 0x9710, 0x9865, 0xa000, 0x3002,
1197 "NetMos NM9865 Dual UART",
1198 DEFAULT_RCLK,
1199 PUC_PORT_2S, 0x10, 4, 0,
1200 },
1201
1202 { 0x9710, 0x9865, 0xa000, 0x3003,
1203 "NetMos NM9865 Triple UART",
1204 DEFAULT_RCLK,
1205 PUC_PORT_3S, 0x10, 4, 0,
1206 },
1207
1208 { 0x9710, 0x9865, 0xa000, 0x3004,
1209 "NetMos NM9865 Quad UART",
1210 DEFAULT_RCLK,
1211 PUC_PORT_4S, 0x10, 4, 0,
1212 },
1213
1214 { 0x9710, 0x9865, 0xa000, 0x3011,
1215 "NetMos NM9865 Single UART and 1284 Printer port",
1216 DEFAULT_RCLK,
1217 PUC_PORT_1S1P, 0x10, 4, 0,
1218 },
1219
1220 { 0x9710, 0x9865, 0xa000, 0x3012,
1221 "NetMos NM9865 Dual UART and 1284 Printer port",
1222 DEFAULT_RCLK,
1223 PUC_PORT_2S1P, 0x10, 4, 0,
1224 },
1225
1226 { 0x9710, 0x9865, 0xa000, 0x3020,
1227 "NetMos NM9865 Dual 1284 Printer port",
1228 DEFAULT_RCLK,
1229 PUC_PORT_2P, 0x10, 4, 0,
1230 },
1231
1232 { 0xb00c, 0x021c, 0xffff, 0,
1233 "IC Book Labs Gunboat x4 Lite",
1234 DEFAULT_RCLK,
1235 PUC_PORT_4S, 0x10, 0, 8,
1236 .config_function = puc_config_icbook
1237 },
1238
1239 { 0xb00c, 0x031c, 0xffff, 0,
1240 "IC Book Labs Gunboat x4 Pro",
1241 DEFAULT_RCLK,
1242 PUC_PORT_4S, 0x10, 0, 8,
1243 .config_function = puc_config_icbook
1244 },
1245
1246 { 0xb00c, 0x041c, 0xffff, 0,
1247 "IC Book Labs Ironclad x8 Lite",
1248 DEFAULT_RCLK,
1249 PUC_PORT_8S, 0x10, 0, 8,
1250 .config_function = puc_config_icbook
1251 },
1252
1253 { 0xb00c, 0x051c, 0xffff, 0,
1254 "IC Book Labs Ironclad x8 Pro",
1255 DEFAULT_RCLK,
1256 PUC_PORT_8S, 0x10, 0, 8,
1257 .config_function = puc_config_icbook
1258 },
1259
1260 { 0xb00c, 0x081c, 0xffff, 0,
1261 "IC Book Labs Dreadnought x16 Pro",
1262 DEFAULT_RCLK * 8,
1263 PUC_PORT_16S, 0x10, 0, 8,
1264 .config_function = puc_config_icbook
1265 },
1266
1267 { 0xb00c, 0x091c, 0xffff, 0,
1268 "IC Book Labs Dreadnought x16 Lite",
1269 DEFAULT_RCLK,
1270 PUC_PORT_16S, 0x10, 0, 8,
1271 .config_function = puc_config_icbook
1272 },
1273
1274 { 0xb00c, 0x0a1c, 0xffff, 0,
1275 "IC Book Labs Gunboat x2 Low Profile",
1276 DEFAULT_RCLK,
1277 PUC_PORT_2S, 0x10, 0, 8,
1278 },
1279
1280 { 0xb00c, 0x0b1c, 0xffff, 0,
1281 "IC Book Labs Gunboat x4 Low Profile",
1282 DEFAULT_RCLK,
1283 PUC_PORT_4S, 0x10, 0, 8,
1284 .config_function = puc_config_icbook
1285 },
1286 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1287 };
1288
1289 static int
puc_config_advantech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res __unused)1290 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1291 intptr_t *res __unused)
1292 {
1293 const struct puc_cfg *cfg;
1294 struct resource *cres;
1295 struct puc_bar *bar;
1296 device_t cdev, dev;
1297 bus_size_t off;
1298 int base, crtype, fixed, high, i, oxpcie;
1299 uint8_t acr, func, mask;
1300
1301 if (cmd != PUC_CFG_SETUP)
1302 return (ENXIO);
1303
1304 base = fixed = oxpcie = 0;
1305 crtype = SYS_RES_IOPORT;
1306 acr = mask = 0x0;
1307 func = high = 1;
1308 off = 0x60;
1309
1310 cfg = sc->sc_cfg;
1311 switch (cfg->subvendor) {
1312 case 0x13fe:
1313 switch (cfg->device) {
1314 case 0xa102:
1315 high = 0;
1316 break;
1317 default:
1318 break;
1319 }
1320 default:
1321 break;
1322 }
1323 if (fixed == 1)
1324 goto setup;
1325
1326 dev = sc->sc_dev;
1327 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1328 pci_get_slot(dev), func);
1329 if (cdev == NULL) {
1330 device_printf(dev, "could not find config function\n");
1331 return (ENXIO);
1332 }
1333
1334 i = PCIR_BAR(0);
1335 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE);
1336 if (cres == NULL) {
1337 device_printf(dev, "could not allocate config resource\n");
1338 return (ENXIO);
1339 }
1340
1341 if (oxpcie == 0) {
1342 mask = bus_read_1(cres, off);
1343 if (pci_get_function(dev) == 1)
1344 base = 4;
1345 }
1346
1347 setup:
1348 for (i = 0; i < sc->sc_nports; ++i) {
1349 device_printf(dev, "port %d: ", i);
1350 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid);
1351 if (bar == NULL) {
1352 printf("could not get BAR\n");
1353 continue;
1354 }
1355
1356 if (fixed == 0) {
1357 if ((mask & (1 << (base + i))) == 0) {
1358 acr = 0;
1359 printf("RS-232\n");
1360 } else {
1361 acr = (high == 1 ? 0x18 : 0x10);
1362 printf("RS-422/RS-485, active-%s auto-DTR\n",
1363 high == 1 ? "high" : "low");
1364 }
1365 }
1366
1367 bus_write_1(bar->b_res, REG_SPR, REG_ACR);
1368 bus_write_1(bar->b_res, REG_ICR, acr);
1369 }
1370
1371 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres);
1372 return (0);
1373 }
1374
1375 static int
puc_config_amc(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1376 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port,
1377 intptr_t *res)
1378 {
1379
1380 switch (cmd) {
1381 case PUC_CFG_GET_OFS:
1382 *res = 8 * (port & 1);
1383 return (0);
1384 case PUC_CFG_GET_RID:
1385 *res = 0x14 + (port >> 1) * 4;
1386 return (0);
1387 default:
1388 break;
1389 }
1390 return (ENXIO);
1391 }
1392
1393 static int
puc_config_diva(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1394 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1395 intptr_t *res)
1396 {
1397 const struct puc_cfg *cfg = sc->sc_cfg;
1398
1399 if (cmd == PUC_CFG_GET_OFS) {
1400 if (cfg->subdevice == 0x1282) /* Everest SP */
1401 port <<= 1;
1402 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1403 port = (port == 3) ? 4 : port;
1404 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1405 return (0);
1406 }
1407 return (ENXIO);
1408 }
1409
1410 static int
puc_config_exar(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1411 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1412 int port, intptr_t *res)
1413 {
1414
1415 if (cmd == PUC_CFG_GET_OFS) {
1416 *res = port * 0x200;
1417 return (0);
1418 }
1419 return (ENXIO);
1420 }
1421
1422 static int
puc_config_exar_pcie(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1423 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1424 int port, intptr_t *res)
1425 {
1426
1427 if (cmd == PUC_CFG_GET_OFS) {
1428 *res = port * 0x400;
1429 return (0);
1430 }
1431 return (ENXIO);
1432 }
1433
1434 static int
puc_config_icbook(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1435 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1436 int port __unused, intptr_t *res)
1437 {
1438
1439 if (cmd == PUC_CFG_GET_ILR) {
1440 *res = PUC_ILR_DIGI;
1441 return (0);
1442 }
1443 return (ENXIO);
1444 }
1445
1446 static int
puc_config_moxa(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1447 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1448 intptr_t *res)
1449 {
1450 const struct puc_cfg *cfg = sc->sc_cfg;
1451
1452 if (cmd == PUC_CFG_GET_OFS) {
1453 if (port == 3 && (cfg->device == 0x1045 ||
1454 cfg->device == 0x1144))
1455 port = 7;
1456 *res = port * 0x200;
1457
1458 return 0;
1459 }
1460 return (ENXIO);
1461 }
1462
1463 static int
puc_config_quatech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1464 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1465 int port __unused, intptr_t *res)
1466 {
1467 const struct puc_cfg *cfg = sc->sc_cfg;
1468 struct puc_bar *bar;
1469 uint8_t v0, v1;
1470
1471 switch (cmd) {
1472 case PUC_CFG_SETUP:
1473 /*
1474 * Check if the scratchpad register is enabled or if the
1475 * interrupt status and options registers are active.
1476 */
1477 bar = puc_get_bar(sc, cfg->rid);
1478 if (bar == NULL)
1479 return (ENXIO);
1480 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);
1481 bus_write_1(bar->b_res, REG_SPR, 0);
1482 v0 = bus_read_1(bar->b_res, REG_SPR);
1483 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);
1484 v1 = bus_read_1(bar->b_res, REG_SPR);
1485 bus_write_1(bar->b_res, REG_LCR, 0);
1486 sc->sc_cfg_data = (v0 << 8) | v1;
1487 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1488 /*
1489 * The SPR register echoed the two values written
1490 * by us. This means that the SPAD jumper is set.
1491 */
1492 device_printf(sc->sc_dev, "warning: extra features "
1493 "not usable -- SPAD compatibility enabled\n");
1494 return (0);
1495 }
1496 if (v0 != 0) {
1497 /*
1498 * The first value doesn't match. This can only mean
1499 * that the SPAD jumper is not set and that a non-
1500 * standard fixed clock multiplier jumper is set.
1501 */
1502 if (bootverbose)
1503 device_printf(sc->sc_dev, "fixed clock rate "
1504 "multiplier of %d\n", 1 << v0);
1505 if (v0 < -cfg->clock)
1506 device_printf(sc->sc_dev, "warning: "
1507 "suboptimal fixed clock rate multiplier "
1508 "setting\n");
1509 return (0);
1510 }
1511 /*
1512 * The first value matched, but the second didn't. We know
1513 * that the SPAD jumper is not set. We also know that the
1514 * clock rate multiplier is software controlled *and* that
1515 * we just programmed it to the maximum allowed.
1516 */
1517 if (bootverbose)
1518 device_printf(sc->sc_dev, "clock rate multiplier of "
1519 "%d selected\n", 1 << -cfg->clock);
1520 return (0);
1521 case PUC_CFG_GET_CLOCK:
1522 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1523 v1 = sc->sc_cfg_data & 0xff;
1524 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1525 /*
1526 * XXX With the SPAD jumper applied, there's no
1527 * easy way of knowing if there's also a clock
1528 * rate multiplier jumper installed. Let's hope
1529 * not ...
1530 */
1531 *res = DEFAULT_RCLK;
1532 } else if (v0 == 0) {
1533 /*
1534 * No clock rate multiplier jumper installed,
1535 * so we programmed the board with the maximum
1536 * multiplier allowed as given to us in the
1537 * clock field of the config record (negated).
1538 */
1539 *res = DEFAULT_RCLK << -cfg->clock;
1540 } else
1541 *res = DEFAULT_RCLK << v0;
1542 return (0);
1543 case PUC_CFG_GET_ILR:
1544 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1545 v1 = sc->sc_cfg_data & 0xff;
1546 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ?
1547 PUC_ILR_NONE : PUC_ILR_QUATECH;
1548 return (0);
1549 default:
1550 break;
1551 }
1552 return (ENXIO);
1553 }
1554
1555 static int
puc_config_syba(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1556 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1557 intptr_t *res)
1558 {
1559 static int base[] = { 0x251, 0x3f0, 0 };
1560 const struct puc_cfg *cfg = sc->sc_cfg;
1561 struct puc_bar *bar;
1562 int efir, idx, ofs;
1563 uint8_t v;
1564
1565 switch (cmd) {
1566 case PUC_CFG_SETUP:
1567 bar = puc_get_bar(sc, cfg->rid);
1568 if (bar == NULL)
1569 return (ENXIO);
1570
1571 /* configure both W83877TFs */
1572 bus_write_1(bar->b_res, 0x250, 0x89);
1573 bus_write_1(bar->b_res, 0x3f0, 0x87);
1574 bus_write_1(bar->b_res, 0x3f0, 0x87);
1575 idx = 0;
1576 while (base[idx] != 0) {
1577 efir = base[idx];
1578 bus_write_1(bar->b_res, efir, 0x09);
1579 v = bus_read_1(bar->b_res, efir + 1);
1580 if ((v & 0x0f) != 0x0c)
1581 return (ENXIO);
1582 bus_write_1(bar->b_res, efir, 0x16);
1583 v = bus_read_1(bar->b_res, efir + 1);
1584 bus_write_1(bar->b_res, efir, 0x16);
1585 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1586 bus_write_1(bar->b_res, efir, 0x16);
1587 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1588 ofs = base[idx] & 0x300;
1589 bus_write_1(bar->b_res, efir, 0x23);
1590 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1591 bus_write_1(bar->b_res, efir, 0x24);
1592 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1593 bus_write_1(bar->b_res, efir, 0x25);
1594 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1595 bus_write_1(bar->b_res, efir, 0x17);
1596 bus_write_1(bar->b_res, efir + 1, 0x03);
1597 bus_write_1(bar->b_res, efir, 0x28);
1598 bus_write_1(bar->b_res, efir + 1, 0x43);
1599 idx++;
1600 }
1601 bus_write_1(bar->b_res, 0x250, 0xaa);
1602 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1603 return (0);
1604 case PUC_CFG_GET_OFS:
1605 switch (port) {
1606 case 0:
1607 *res = 0x2f8;
1608 return (0);
1609 case 1:
1610 *res = 0x2e8;
1611 return (0);
1612 case 2:
1613 *res = 0x3f8;
1614 return (0);
1615 case 3:
1616 *res = 0x3e8;
1617 return (0);
1618 case 4:
1619 *res = 0x278;
1620 return (0);
1621 }
1622 break;
1623 default:
1624 break;
1625 }
1626 return (ENXIO);
1627 }
1628
1629 static int
puc_config_siig(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1630 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1631 intptr_t *res)
1632 {
1633 const struct puc_cfg *cfg = sc->sc_cfg;
1634
1635 switch (cmd) {
1636 case PUC_CFG_GET_OFS:
1637 if (cfg->ports == PUC_PORT_8S) {
1638 *res = (port > 4) ? 8 * (port - 4) : 0;
1639 return (0);
1640 }
1641 break;
1642 case PUC_CFG_GET_RID:
1643 if (cfg->ports == PUC_PORT_8S) {
1644 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1645 return (0);
1646 }
1647 if (cfg->ports == PUC_PORT_2S1P) {
1648 switch (port) {
1649 case 0: *res = 0x10; return (0);
1650 case 1: *res = 0x14; return (0);
1651 case 2: *res = 0x1c; return (0);
1652 }
1653 }
1654 break;
1655 default:
1656 break;
1657 }
1658 return (ENXIO);
1659 }
1660
1661 static int
puc_config_timedia(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1662 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1663 intptr_t *res)
1664 {
1665 static const uint16_t dual[] = {
1666 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1667 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1668 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1669 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1670 0xD079, 0
1671 };
1672 static const uint16_t quad[] = {
1673 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1674 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1675 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1676 0xB157, 0
1677 };
1678 static const uint16_t octa[] = {
1679 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1680 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1681 };
1682 static const struct {
1683 int ports;
1684 const uint16_t *ids;
1685 } subdevs[] = {
1686 { 2, dual },
1687 { 4, quad },
1688 { 8, octa },
1689 { 0, NULL }
1690 };
1691 static char desc[64];
1692 int dev, id;
1693 uint16_t subdev;
1694
1695 switch (cmd) {
1696 case PUC_CFG_GET_CLOCK:
1697 if (port < 2)
1698 *res = DEFAULT_RCLK * 8;
1699 else
1700 *res = DEFAULT_RCLK;
1701 return (0);
1702 case PUC_CFG_GET_DESC:
1703 snprintf(desc, sizeof(desc),
1704 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1705 *res = (intptr_t)desc;
1706 return (0);
1707 case PUC_CFG_GET_NPORTS:
1708 subdev = pci_get_subdevice(sc->sc_dev);
1709 dev = 0;
1710 while (subdevs[dev].ports != 0) {
1711 id = 0;
1712 while (subdevs[dev].ids[id] != 0) {
1713 if (subdev == subdevs[dev].ids[id]) {
1714 sc->sc_cfg_data = subdevs[dev].ports;
1715 *res = sc->sc_cfg_data;
1716 return (0);
1717 }
1718 id++;
1719 }
1720 dev++;
1721 }
1722 return (ENXIO);
1723 case PUC_CFG_GET_OFS:
1724 *res = (port == 1 || port == 3) ? 8 : 0;
1725 return (0);
1726 case PUC_CFG_GET_RID:
1727 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1728 return (0);
1729 case PUC_CFG_GET_TYPE:
1730 *res = PUC_TYPE_SERIAL;
1731 return (0);
1732 default:
1733 break;
1734 }
1735 return (ENXIO);
1736 }
1737
1738 static int
puc_config_oxford_pci954(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1739 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1740 int port __unused, intptr_t *res)
1741 {
1742
1743 switch (cmd) {
1744 case PUC_CFG_GET_CLOCK:
1745 /*
1746 * OXu16PCI954 use a 14.7456 MHz clock by default while
1747 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1748 */
1749 if (pci_get_revid(sc->sc_dev) == 1)
1750 *res = DEFAULT_RCLK * 8;
1751 else
1752 *res = DEFAULT_RCLK;
1753 return (0);
1754 default:
1755 break;
1756 }
1757 return (ENXIO);
1758 }
1759
1760 static int
puc_config_oxford_pcie(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1761 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1762 intptr_t *res)
1763 {
1764 const struct puc_cfg *cfg = sc->sc_cfg;
1765 int idx;
1766 struct puc_bar *bar;
1767 uint8_t value;
1768
1769 switch (cmd) {
1770 case PUC_CFG_SETUP:
1771 device_printf(sc->sc_dev, "%d UARTs detected\n",
1772 sc->sc_nports);
1773
1774 /* Set UARTs to enhanced mode */
1775 bar = puc_get_bar(sc, cfg->rid);
1776 if (bar == NULL)
1777 return (ENXIO);
1778 for (idx = 0; idx < sc->sc_nports; idx++) {
1779 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1780 0x92);
1781 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1782 value | 0x10);
1783 }
1784 return (0);
1785 case PUC_CFG_GET_LEN:
1786 *res = 0x200;
1787 return (0);
1788 case PUC_CFG_GET_NPORTS:
1789 /*
1790 * Check if we are being called from puc_bfe_attach()
1791 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1792 * puc_get_bar(), so we return a value of 16. This has
1793 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC,
1794 * sc->sc_cfg_data will not contain the true number of
1795 * ports in PUC_CFG_GET_DESC, but we are not implementing
1796 * that call for this device family anyway.
1797 *
1798 * The check is for initialization of sc->sc_bar[idx],
1799 * which is only done in puc_bfe_attach().
1800 */
1801 idx = 0;
1802 do {
1803 if (sc->sc_bar[idx++].b_rid != -1) {
1804 sc->sc_cfg_data = 16;
1805 *res = sc->sc_cfg_data;
1806 return (0);
1807 }
1808 } while (idx < PUC_PCI_BARS);
1809
1810 bar = puc_get_bar(sc, cfg->rid);
1811 if (bar == NULL)
1812 return (ENXIO);
1813
1814 value = bus_read_1(bar->b_res, 0x04);
1815 if (value == 0)
1816 return (ENXIO);
1817
1818 sc->sc_cfg_data = value;
1819 *res = sc->sc_cfg_data;
1820 return (0);
1821 case PUC_CFG_GET_OFS:
1822 *res = 0x1000 + (port << 9);
1823 return (0);
1824 case PUC_CFG_GET_TYPE:
1825 *res = PUC_TYPE_SERIAL;
1826 return (0);
1827 default:
1828 break;
1829 }
1830 return (ENXIO);
1831 }
1832
1833 static int
puc_config_sunix(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1834 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1835 intptr_t *res)
1836 {
1837 int error;
1838
1839 switch (cmd) {
1840 case PUC_CFG_GET_OFS:
1841 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1842 if (error != 0)
1843 return (error);
1844 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1845 return (0);
1846 case PUC_CFG_GET_RID:
1847 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1848 if (error != 0)
1849 return (error);
1850 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1851 return (0);
1852 default:
1853 break;
1854 }
1855 return (ENXIO);
1856 }
1857
1858 static int
puc_config_titan(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1859 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1860 int port, intptr_t *res)
1861 {
1862
1863 switch (cmd) {
1864 case PUC_CFG_GET_OFS:
1865 *res = (port < 3) ? 0 : (port - 2) << 3;
1866 return (0);
1867 case PUC_CFG_GET_RID:
1868 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
1869 return (0);
1870 default:
1871 break;
1872 }
1873 return (ENXIO);
1874 }
1875