1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #include <sys/nxge/nxge_impl.h>
27 #include <sys/nxge/nxge_hio.h>
28
29 #include <inet/common.h>
30 #include <inet/mi.h>
31 #include <inet/nd.h>
32
33 extern uint64_t npi_debug_level;
34
35 #define NXGE_PARAM_MAC_RW \
36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \
37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP
38
39 #define NXGE_PARAM_MAC_DONT_SHOW \
40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW
41
42 #define NXGE_PARAM_RXDMA_RW \
43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \
44 NXGE_PARAM_READ_PROP
45
46 #define NXGE_PARAM_RXDMA_RWC \
47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \
48 NXGE_PARAM_READ_PROP
49
50 #define NXGE_PARAM_L2CLASS_CFG \
51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \
52 NXGE_PARAM_NDD_WR_OK
53
54 #define NXGE_PARAM_CLASS_RWS \
55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP
56
57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL
58
59 #define SET_RX_INTR_TIME_DISABLE 0
60 #define SET_RX_INTR_TIME_ENABLE 1
61 #define SET_RX_INTR_PKTS 2
62
63 #define BASE_ANY 0
64 #define BASE_BINARY 2
65 #define BASE_HEX 16
66 #define BASE_DECIMAL 10
67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL
68 #define ALL_FF_32 0xFFFFFFFFUL
69
70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */
71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192
72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000
73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000
74
75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \
76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum))
77
78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \
79 ((mblk_t *)pmp)->b_wptr += plen; \
80 rlen -= plen; \
81 }
82
83 int nxge_param_set_mac(p_nxge_t, queue_t *,
84 mblk_t *, char *, caddr_t);
85 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *,
86 mblk_t *, char *, caddr_t);
87 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *,
88 mblk_t *, char *, caddr_t);
89 static int nxge_param_set_ether_usr(p_nxge_t,
90 queue_t *, mblk_t *, char *, caddr_t);
91 static int nxge_param_set_ip_usr(p_nxge_t,
92 queue_t *, mblk_t *, char *, caddr_t);
93 static int nxge_param_set_vlan_rdcgrp(p_nxge_t,
94 queue_t *, mblk_t *, char *, caddr_t);
95 static int nxge_param_set_mac_rdcgrp(p_nxge_t,
96 queue_t *, mblk_t *, char *, caddr_t);
97 static int nxge_param_fflp_hash_init(p_nxge_t,
98 queue_t *, mblk_t *, char *, caddr_t);
99 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *,
100 mblk_t *, char *, caddr_t);
101 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *,
102 mblk_t *, char *, caddr_t);
103 static int nxge_param_tcam_enable(p_nxge_t, queue_t *,
104 mblk_t *, char *, caddr_t);
105 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
106 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
107 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q,
108 p_mblk_t, caddr_t);
109 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q,
110 p_mblk_t, caddr_t);
111 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *,
112 p_mblk_t, caddr_t);
113 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
114 p_mblk_t, caddr_t);
115 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
116 p_mblk_t, caddr_t);
117 static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
118 static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
119 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
120 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
121 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
122 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *,
123 char *, caddr_t);
124 static int nxge_param_set_npi_debug_flag(p_nxge_t,
125 queue_t *, mblk_t *, char *, caddr_t);
126 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
127 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
128 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
129 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
130 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
131 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
132 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
133 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
134 static void nxge_param_sync(p_nxge_t);
135
136 /*
137 * Global array of Neptune changable parameters.
138 * This array is initialized to correspond to the default
139 * Neptune 4 port configuration. This array would be copied
140 * into each port's parameter structure and modifed per
141 * fcode and nxge.conf configuration. Later, the parameters are
142 * exported to ndd to display and run-time configuration (at least
143 * some of them).
144 *
145 * Parameters with DONT_SHOW are not shown by ndd.
146 *
147 */
148
149 static nxge_param_t nxge_param_arr[] = {
150 /*
151 * min max value old hw-name conf-name
152 */
153 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
154 0, 999, 1000, 0, "instance", "instance"},
155
156 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
157 0, 999, 1000, 0, "main-instance", "main_instance"},
158
159 { nxge_param_get_generic, NULL, NXGE_PARAM_READ,
160 0, 3, 0, 0, "function-number", "function_number"},
161
162 /* Partition Id */
163 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
164 0, 8, 0, 0, "partition-id", "partition_id"},
165
166 /* Read Write Permission Mode */
167 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
168 0, 2, 0, 0, "read-write-mode", "read_write_mode"},
169
170 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ,
171 0, 32, 0, 0, "version", "fw_version"},
172
173 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ,
174 0, 32, 0, 0, "port-mode", "port_mode"},
175
176 /* hw cfg types */
177 /* control the DMA config of Neptune/NIU */
178 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
179 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT,
180 "niu-cfg-type", "niu_cfg_type"},
181
182 /* control the TXDMA config of the Port controlled by tx-quick-cfg */
183 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
184 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
185 "tx-qcfg-type", "tx_qcfg_type"},
186
187 /* control the RXDMA config of the Port controlled by rx-quick-cfg */
188 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
189 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
190 "rx-qcfg-type", "rx_qcfg_type"},
191
192 { nxge_param_get_mac, nxge_param_set_mac,
193 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
194 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"},
195
196 { nxge_param_get_mac, nxge_param_set_mac,
197 NXGE_PARAM_DONT_SHOW,
198 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"},
199
200 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
201 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"},
202
203 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
204 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"},
205
206 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
207 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"},
208
209 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
210 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"},
211
212 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
213 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"},
214
215 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
216 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"},
217
218 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
219 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"},
220
221 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
222 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"},
223
224 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
225 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"},
226
227 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
228 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"},
229
230 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
231 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"},
232
233 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
234 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"},
235
236 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
237 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"},
238
239 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
240 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"},
241
242 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
243 0, 255, 8, 8, "ipg0", "ipg0"},
244
245 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
246 0, 255, 8, 8, "ipg1", "ipg1"},
247
248 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
249 0, 255, 4, 4, "ipg2", "ipg2"},
250
251 /* Transmit DMA channels */
252 { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
253 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
254 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"},
255
256 { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
257 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
258 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"},
259
260 { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
261 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
262 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"},
263 { nxge_param_get_txdma_info, NULL,
264 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
265 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"},
266
267 /* Receive DMA channels */
268 { nxge_param_get_generic, NULL,
269 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
270 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"},
271
272 { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
273 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
274 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"},
275
276 { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
277 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
278 0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
279 "rx-drr-weight", "rx_drr_weight"},
280
281 { nxge_param_get_generic, NULL, NXGE_PARAM_READ |
282 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
283 0, 1, 1, 0, "rx-full-header", "rx_full_header"},
284
285 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ |
286 NXGE_PARAM_DONT_SHOW,
287 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"},
288
289 { nxge_param_get_rxdma_info, NULL,
290 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
291 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0,
292 "rx-rbr-size", "rx_rbr_size"},
293
294 { nxge_param_get_rxdma_info, NULL,
295 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
296 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0,
297 "rx-rcr-size", "rx_rcr_size"},
298
299 { nxge_param_get_generic, nxge_param_set_port_rdc,
300 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
301 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
302
303 { nxge_param_get_rx_intr_time, nxge_param_rx_intr_time,
304 NXGE_PARAM_RXDMA_RW,
305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
306 NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"},
307
308 { nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts,
309 NXGE_PARAM_RXDMA_RW,
310 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
311 NXGE_RDC_RCR_THRESHOLD, 0,
312 "rxdma-intr-pkts", "rxdma_intr_pkts"},
313
314 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
315 NXGE_PARAM_DONT_SHOW,
316 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"},
317
318 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
319 NXGE_PARAM_DONT_SHOW,
320 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"},
321
322 { nxge_param_get_generic, nxge_param_set_grp_rdc,
323 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
324 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"},
325
326 { nxge_param_get_generic, nxge_param_set_grp_rdc,
327 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
328 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"},
329
330 { nxge_param_get_generic, nxge_param_set_grp_rdc,
331 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
332 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"},
333
334 { nxge_param_get_generic, nxge_param_set_grp_rdc,
335 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
336 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"},
337
338 { nxge_param_get_generic, nxge_param_set_grp_rdc,
339 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
340 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"},
341
342 { nxge_param_get_generic, nxge_param_set_grp_rdc,
343 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
344 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"},
345
346 { nxge_param_get_generic, nxge_param_set_grp_rdc,
347 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
348 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
349
350 { nxge_param_get_generic, nxge_param_set_grp_rdc,
351 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
352 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"},
353
354 { nxge_param_get_rxdma_rdcgrp_info, NULL,
355 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW,
356 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"},
357
358 /* Logical device groups */
359 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
360 0, 63, 0, 0, "start-ldg", "start_ldg"},
361
362 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
363 0, 64, 0, 0, "max-ldg", "max_ldg" },
364
365 /* MAC table information */
366 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp,
367 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
368 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"},
369
370 /* VLAN table information */
371 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp,
372 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
373 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"},
374
375 { nxge_param_get_generic, NULL,
376 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ |
377 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW,
378 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"},
379
380 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
381 NXGE_PARAM_DONT_SHOW,
382 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"},
383
384 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
385 NXGE_PARAM_DONT_SHOW,
386 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"},
387
388 { nxge_param_get_generic, nxge_param_tcam_enable,
389 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
390 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"},
391
392 { nxge_param_get_generic, nxge_param_hash_lookup_enable,
393 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
394 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"},
395
396 { nxge_param_get_generic, nxge_param_llc_snap_enable,
397 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
398 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"},
399
400 { nxge_param_get_generic, nxge_param_fflp_hash_init,
401 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
402 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"},
403
404 { nxge_param_get_generic, nxge_param_fflp_hash_init,
405 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
406 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"},
407
408 { nxge_param_get_generic, nxge_param_set_ether_usr,
409 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
410 0, ALL_FF_32, 0x0, 0,
411 "class-cfg-ether-usr1", "class_cfg_ether_usr1"},
412
413 { nxge_param_get_generic, nxge_param_set_ether_usr,
414 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
415 0, ALL_FF_32, 0x0, 0,
416 "class-cfg-ether-usr2", "class_cfg_ether_usr2"},
417
418 { nxge_param_get_generic, nxge_param_set_ip_usr,
419 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
420 0, ALL_FF_32, 0x0, 0,
421 "class-cfg-ip-usr4", "class_cfg_ip_usr4"},
422
423 { nxge_param_get_generic, nxge_param_set_ip_usr,
424 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
425 0, ALL_FF_32, 0x0, 0,
426 "class-cfg-ip-usr5", "class_cfg_ip_usr5"},
427
428 { nxge_param_get_generic, nxge_param_set_ip_usr,
429 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
430 0, ALL_FF_32, 0x0, 0,
431 "class-cfg-ip-usr6", "class_cfg_ip_usr6"},
432
433 { nxge_param_get_generic, nxge_param_set_ip_usr,
434 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
435 0, ALL_FF_32, 0x0, 0,
436 "class-cfg-ip-usr7", "class_cfg_ip_usr7"},
437
438 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
439 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
440 0, ALL_FF_32, 0x0, 0,
441 "class-opt-ip-usr4", "class_opt_ip_usr4"},
442
443 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
444 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
445 0, ALL_FF_32, 0x0, 0,
446 "class-opt-ip-usr5", "class_opt_ip_usr5"},
447
448 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
449 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
450 0, ALL_FF_32, 0x0, 0,
451 "class-opt-ip-usr6", "class_opt_ip_usr6"},
452
453 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
454 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
455 0, ALL_FF_32, 0x0, 0,
456 "class-opt-ip-usr7", "class_opt_ip_usr7"},
457
458 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
459 NXGE_PARAM_CLASS_RWS,
460 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
461 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
462
463 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
464 NXGE_PARAM_CLASS_RWS,
465 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
466 "class-opt-ipv4-udp", "class_opt_ipv4_udp"},
467
468 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
469 NXGE_PARAM_CLASS_RWS,
470 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
471 "class-opt-ipv4-ah", "class_opt_ipv4_ah"},
472
473 { nxge_param_get_ip_opt, nxge_param_set_ip_opt,
474 NXGE_PARAM_CLASS_RWS,
475 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
476 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
477
478 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
479 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
480 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
481
482 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
483 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
484 "class-opt-ipv6-udp", "class_opt_ipv6_udp"},
485
486 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
487 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
488 "class-opt-ipv6-ah", "class_opt_ipv6_ah"},
489
490 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
491 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
492 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"},
493
494 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag,
495 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
496 0ULL, ALL_FF_64, 0ULL, 0ULL,
497 "nxge-debug-flag", "nxge_debug_flag"},
498
499 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag,
500 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
501 0ULL, ALL_FF_64, 0ULL, 0ULL,
502 "npi-debug-flag", "npi_debug_flag"},
503
504 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
505 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"},
506
507 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
508 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"},
509
510 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ |
511 NXGE_PARAM_DONT_SHOW,
512 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"},
513
514 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ |
515 NXGE_PARAM_DONT_SHOW,
516 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"},
517
518 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ |
519 NXGE_PARAM_DONT_SHOW,
520 0, 0x0fffffff, 0x0fffffff, 0,
521 "dump-fflp-regs", "dump_fflp_regs"},
522
523 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ |
524 NXGE_PARAM_DONT_SHOW,
525 0, 0x0fffffff, 0x0fffffff, 0,
526 "dump-vlan-table", "dump_vlan_table"},
527
528 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ |
529 NXGE_PARAM_DONT_SHOW,
530 0, 0x0fffffff, 0x0fffffff, 0,
531 "dump-rdc-table", "dump_rdc_table"},
532
533 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ |
534 NXGE_PARAM_DONT_SHOW,
535 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"},
536
537 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
538 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"},
539 };
540
541 extern void *nxge_list;
542
543 void
nxge_get_param_soft_properties(p_nxge_t nxgep)544 nxge_get_param_soft_properties(p_nxge_t nxgep)
545 {
546
547 p_nxge_param_t param_arr;
548 uint_t prop_len;
549 int i, j;
550 uint32_t param_count;
551 uint32_t *int_prop_val;
552
553 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
554
555 param_arr = nxgep->param_arr;
556 param_count = nxgep->param_count;
557 for (i = 0; i < param_count; i++) {
558 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0)
559 continue;
560 if ((param_arr[i].type & NXGE_PARAM_PROP_STR))
561 continue;
562 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
563 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
564 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
565 nxgep->dip, 0, param_arr[i].fcode_name,
566 (int **)&int_prop_val,
567 (uint_t *)&prop_len)
568 == DDI_PROP_SUCCESS) {
569 uint32_t *cfg_value;
570 uint64_t prop_count;
571
572 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE)
573 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE;
574 cfg_value = (uint32_t *)param_arr[i].value;
575 for (j = 0; j < prop_len; j++) {
576 cfg_value[j] = int_prop_val[j];
577 }
578 prop_count = prop_len;
579 param_arr[i].type |=
580 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT);
581 ddi_prop_free(int_prop_val);
582 }
583 continue;
584 }
585
586 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
587 param_arr[i].fcode_name,
588 (int **)&int_prop_val,
589 &prop_len) == DDI_PROP_SUCCESS) {
590 if ((*int_prop_val >= param_arr[i].minimum) &&
591 (*int_prop_val <= param_arr[i].maximum))
592 param_arr[i].value = *int_prop_val;
593 #ifdef NXGE_DEBUG_ERROR
594 else {
595 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
596 "nxge%d: 'prom' file parameter error\n",
597 nxgep->instance));
598 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
599 "Parameter keyword '%s'"
600 " is outside valid range\n",
601 param_arr[i].name));
602 }
603 #endif
604 ddi_prop_free(int_prop_val);
605 }
606
607 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
608 param_arr[i].name,
609 (int **)&int_prop_val,
610 &prop_len) == DDI_PROP_SUCCESS) {
611 if ((*int_prop_val >= param_arr[i].minimum) &&
612 (*int_prop_val <= param_arr[i].maximum))
613 param_arr[i].value = *int_prop_val;
614 #ifdef NXGE_DEBUG_ERROR
615 else {
616 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
617 "nxge%d: 'conf' file parameter error\n",
618 nxgep->instance));
619 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
620 "Parameter keyword '%s'"
621 "is outside valid range\n",
622 param_arr[i].name));
623 }
624 #endif
625 ddi_prop_free(int_prop_val);
626 }
627 }
628 }
629
630 static int
nxge_private_param_register(p_nxge_t nxgep,p_nxge_param_t param_arr)631 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
632 {
633 int status = B_TRUE;
634 int channel;
635 uint8_t grp;
636 char *prop_name;
637 char *end;
638 uint32_t name_chars;
639
640 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
641 "nxge_private_param_register %s", param_arr->name));
642
643 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV)
644 return (B_TRUE);
645
646 prop_name = param_arr->name;
647 if (param_arr->type & NXGE_PARAM_RXDMA) {
648 if (strncmp("rxdma_intr", prop_name, 10) == 0)
649 return (B_TRUE);
650 name_chars = strlen("default_grp");
651 if (strncmp("default_grp", prop_name, name_chars) == 0) {
652 prop_name += name_chars;
653 grp = mi_strtol(prop_name, &end, 10);
654 /* now check if this rdcgrp is in config */
655 return (nxge_check_rdcgrp_port_member(nxgep, grp));
656 }
657 name_chars = strlen(prop_name);
658 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) {
659 return (B_TRUE);
660 }
661 return (B_FALSE);
662 }
663
664 if (param_arr->type & NXGE_PARAM_TXDMA) {
665 name_chars = strlen("txdma");
666 if (strncmp("txdma", prop_name, name_chars) == 0) {
667 prop_name += name_chars;
668 channel = mi_strtol(prop_name, &end, 10);
669 /* now check if this rdc is in config */
670 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
671 " nxge_private_param_register: %d",
672 channel));
673 return (nxge_check_txdma_port_member(nxgep, channel));
674 }
675 return (B_FALSE);
676 }
677
678 status = B_FALSE;
679 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
680
681 return (status);
682 }
683
684 void
nxge_setup_param(p_nxge_t nxgep)685 nxge_setup_param(p_nxge_t nxgep)
686 {
687 p_nxge_param_t param_arr;
688 int i;
689 pfi_t set_pfi;
690
691 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
692
693 /*
694 * Make sure the param_instance is set to a valid device instance.
695 */
696 if (nxge_param_arr[param_instance].value == 1000)
697 nxge_param_arr[param_instance].value = nxgep->instance;
698
699 param_arr = nxgep->param_arr;
700 param_arr[param_instance].value = nxgep->instance;
701 param_arr[param_function_number].value = nxgep->function_num;
702
703 for (i = 0; i < nxgep->param_count; i++) {
704 if ((param_arr[i].type & NXGE_PARAM_PRIV) &&
705 (nxge_private_param_register(nxgep,
706 ¶m_arr[i]) == B_FALSE)) {
707 param_arr[i].setf = NULL;
708 param_arr[i].getf = NULL;
709 }
710
711 if (param_arr[i].type & NXGE_PARAM_CMPLX)
712 param_arr[i].setf = NULL;
713
714 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) {
715 param_arr[i].setf = NULL;
716 param_arr[i].getf = NULL;
717 }
718
719 set_pfi = (pfi_t)param_arr[i].setf;
720
721 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) {
722 set_pfi = NULL;
723 }
724
725 }
726 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
727 }
728
729 void
nxge_init_param(p_nxge_t nxgep)730 nxge_init_param(p_nxge_t nxgep)
731 {
732 p_nxge_param_t param_arr;
733 int i, alloc_size;
734 uint64_t alloc_count;
735 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
736 /*
737 * Make sure the param_instance is set to a valid device instance.
738 */
739 if (nxge_param_arr[param_instance].value == 1000)
740 nxge_param_arr[param_instance].value = nxgep->instance;
741
742 param_arr = nxgep->param_arr;
743 if (param_arr == NULL) {
744 param_arr = (p_nxge_param_t)
745 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP);
746 }
747
748 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
749 param_arr[i] = nxge_param_arr[i];
750 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
751 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
752 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE;
753 alloc_size = alloc_count * sizeof (uint64_t);
754 param_arr[i].value =
755 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
756 param_arr[i].old_value =
757 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
758 param_arr[i].type |=
759 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT);
760 }
761 }
762
763 nxgep->param_arr = param_arr;
764 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
765
766 nxge_param_sync(nxgep);
767
768 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
769 nxgep->param_count));
770 }
771
772 void
nxge_destroy_param(p_nxge_t nxgep)773 nxge_destroy_param(p_nxge_t nxgep)
774 {
775 int i;
776 uint64_t free_size, free_count;
777
778 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
779
780 if (nxgep->param_arr == NULL)
781 return;
782 /*
783 * Make sure the param_instance is set to a valid device instance.
784 */
785 if (nxge_param_arr[param_instance].value == nxgep->instance) {
786 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) {
787 if ((ddi_get_soft_state(nxge_list, i) != NULL) &&
788 (i != nxgep->instance))
789 break;
790 }
791 nxge_param_arr[param_instance].value = i;
792 }
793
794 for (i = 0; i < nxgep->param_count; i++)
795 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
796 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
797 free_count = ((nxgep->param_arr[i].type &
798 NXGE_PARAM_ARRAY_ALLOC_MASK) >>
799 NXGE_PARAM_ARRAY_ALLOC_SHIFT);
800 free_count = NXGE_PARAM_ARRAY_INIT_SIZE;
801 free_size = sizeof (uint64_t) * free_count;
802 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
803 KMEM_FREE((void *)nxgep->param_arr[i].old_value,
804 free_size);
805 }
806
807 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
808 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
809 }
810
811 /*
812 * Extracts the value from the 'nxge' parameter array and prints the
813 * parameter value. cp points to the required parameter.
814 */
815
816 /* ARGSUSED */
817 int
nxge_param_get_generic(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)818 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
819 {
820 p_nxge_param_t pa = (p_nxge_param_t)cp;
821
822 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
823 "==> nxge_param_get_generic name %s ", pa->name));
824
825 if (pa->value > 0xffffffff)
826 (void) mi_mpprintf(mp, "%x%x",
827 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff));
828 else
829 (void) mi_mpprintf(mp, "%x", (int)pa->value);
830
831 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
832 return (0);
833 }
834
835 /* ARGSUSED */
836 static int
nxge_param_get_mac(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)837 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
838 {
839 p_nxge_param_t pa = (p_nxge_param_t)cp;
840
841 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
842
843 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value);
844 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
845 return (0);
846 }
847
848 /* ARGSUSED */
849 static int
nxge_param_get_fw_ver(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)850 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
851 {
852 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
853
854 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n",
855 nxgep->instance, nxgep->vpd_info.ver);
856
857 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
858 return (0);
859 }
860
861 /* ARGSUSED */
862 static int
nxge_param_get_port_mode(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)863 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
864 {
865 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
866
867 switch (nxgep->mac.portmode) {
868 case PORT_1G_COPPER:
869 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n",
870 nxgep->instance,
871 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
872 break;
873 case PORT_1G_FIBER:
874 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n",
875 nxgep->instance,
876 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
877 break;
878 case PORT_10G_COPPER:
879 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper "
880 "%s\n", nxgep->instance,
881 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
882 break;
883 case PORT_10G_FIBER:
884 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n",
885 nxgep->instance,
886 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
887 break;
888 case PORT_10G_SERDES:
889 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes "
890 "%s\n", nxgep->instance,
891 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
892 break;
893 case PORT_1G_SERDES:
894 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n",
895 nxgep->instance,
896 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
897 break;
898 case PORT_1G_RGMII_FIBER:
899 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII "
900 "Fiber %s\n", nxgep->instance,
901 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
902 break;
903 case PORT_HSP_MODE:
904 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable "
905 "PHY, Currently NOT present\n", nxgep->instance);
906 break;
907 case PORT_10G_TN1010:
908 (void) mi_mpprintf(mp, "Port mode for nxge%d:"
909 " 10G Copper with TN1010 %s\n", nxgep->instance,
910 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
911 break;
912 case PORT_1G_TN1010:
913 (void) mi_mpprintf(mp, "Port mode for nxge%d:"
914 " 1G Copper with TN1010 %s\n", nxgep->instance,
915 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
916 break;
917 default:
918 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n",
919 nxgep->instance,
920 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
921 break;
922 }
923
924 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n",
925 nxgep->instance,
926 nxgep->soft_lso_enable ? "enable" : "disable");
927
928 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
929 return (0);
930 }
931
932 /* ARGSUSED */
933 static int
nxge_param_get_rx_intr_time(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)934 nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
935 {
936 p_nxge_param_t pa = (p_nxge_param_t)cp;
937
938 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time"));
939
940 pa->value = (uint32_t)nxgep->intr_timeout;
941 (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout);
942
943 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time"));
944 return (0);
945 }
946
947 /* ARGSUSED */
948 static int
nxge_param_get_rx_intr_pkts(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)949 nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
950 {
951 p_nxge_param_t pa = (p_nxge_param_t)cp;
952
953 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts"));
954
955 pa->value = (uint32_t)nxgep->intr_threshold;
956 (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold);
957
958 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts"));
959 return (0);
960 }
961
962 /* ARGSUSED */
963 int
nxge_param_get_txdma_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)964 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
965 {
966
967 uint_t print_len, buf_len;
968 p_mblk_t np;
969
970 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
971 int tdc;
972
973 nxge_grp_set_t *set;
974
975 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
976
977 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n",
978 nxgep->function_num);
979
980 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
981 (void) mi_mpprintf(mp, "%s\n", "out of buffer");
982 return (0);
983 }
984
985 buf_len = buff_alloc_size;
986 mp->b_cont = np;
987 print_len = 0;
988
989 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
990 "TDC\t HW TDC\t\n");
991 ((mblk_t *)np)->b_wptr += print_len;
992 buf_len -= print_len;
993
994 set = &nxgep->tx_set;
995 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
996 if ((1 << tdc) & set->owned.map) {
997 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
998 buf_len, "%d\n", tdc);
999 ((mblk_t *)np)->b_wptr += print_len;
1000 buf_len -= print_len;
1001 }
1002 }
1003
1004 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
1005 return (0);
1006 }
1007
1008 /* ARGSUSED */
1009 int
nxge_param_get_rxdma_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)1010 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
1011 {
1012 uint_t print_len, buf_len;
1013 p_mblk_t np;
1014 int rdc;
1015 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1016 p_nxge_hw_pt_cfg_t p_cfgp;
1017 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
1018 p_rx_rcr_rings_t rx_rcr_rings;
1019 p_rx_rcr_ring_t *rcr_rings;
1020 p_rx_rbr_rings_t rx_rbr_rings;
1021 p_rx_rbr_ring_t *rbr_rings;
1022 nxge_grp_set_t *set;
1023
1024 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
1025
1026 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n",
1027 nxgep->function_num);
1028
1029 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1030 /* The following may work even if we cannot get a large buf. */
1031 (void) mi_mpprintf(mp, "%s\n", "out of buffer");
1032 return (0);
1033 }
1034
1035 buf_len = buff_alloc_size;
1036 mp->b_cont = np;
1037 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1038 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1039
1040 rx_rcr_rings = nxgep->rx_rcr_rings;
1041 rcr_rings = rx_rcr_rings->rcr_rings;
1042 rx_rbr_rings = nxgep->rx_rbr_rings;
1043 rbr_rings = rx_rbr_rings->rbr_rings;
1044
1045 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1046 "Total RDCs\t %d\n", p_cfgp->max_rdcs);
1047
1048 ((mblk_t *)np)->b_wptr += print_len;
1049 buf_len -= print_len;
1050 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1051 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
1052 "chunks\t RCR ptr\n");
1053
1054 ((mblk_t *)np)->b_wptr += print_len;
1055 buf_len -= print_len;
1056
1057 set = &nxgep->rx_set;
1058 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1059 if ((1 << rdc) & set->owned.map) {
1060 print_len = snprintf((char *)
1061 ((mblk_t *)np)->b_wptr, buf_len,
1062 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n",
1063 rdc,
1064 p_dma_cfgp->rcr_timeout[rdc],
1065 p_dma_cfgp->rcr_threshold[rdc],
1066 (void *)rbr_rings[rdc],
1067 rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]);
1068 ((mblk_t *)np)->b_wptr += print_len;
1069 buf_len -= print_len;
1070 }
1071 }
1072
1073 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
1074 return (0);
1075 }
1076
1077 /* ARGSUSED */
1078 int
nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)1079 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1080 p_mblk_t mp, caddr_t cp)
1081 {
1082 uint_t print_len, buf_len;
1083 p_mblk_t np;
1084 int offset, rdc, i, rdc_grp;
1085 p_nxge_rdc_grp_t rdc_grp_p;
1086 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1087 p_nxge_hw_pt_cfg_t p_cfgp;
1088
1089 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
1090 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1091 "==> nxge_param_get_rxdma_rdcgrp_info"));
1092
1093 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1094 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1095
1096 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n",
1097 nxgep->function_num);
1098
1099 rdc_grp = p_cfgp->def_mac_rxdma_grpid;
1100 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1101 /* The following may work even if we cannot get a large buf. */
1102 (void) mi_mpprintf(mp, "%s\n", "out of buffer");
1103 return (0);
1104 }
1105
1106 buf_len = buff_alloc_size;
1107 mp->b_cont = np;
1108 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1109 "Total RDC Groups\t %d \n"
1110 "default RDC group\t %d\n",
1111 p_cfgp->max_rdc_grpids,
1112 p_cfgp->def_mac_rxdma_grpid);
1113
1114 ((mblk_t *)np)->b_wptr += print_len;
1115 buf_len -= print_len;
1116
1117 for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) {
1118 if (p_cfgp->grpids[i]) {
1119 rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
1120 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1121 buf_len,
1122 "\nRDC Group Info for Group [%d] %d\n"
1123 "RDC Count %d\tstart RDC %d\n"
1124 "RDC Group Population Information"
1125 " (offsets 0 - 15)\n",
1126 i, rdc_grp, rdc_grp_p->max_rdcs,
1127 rdc_grp_p->start_rdc);
1128
1129 ((mblk_t *)np)->b_wptr += print_len;
1130 buf_len -= print_len;
1131 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1132 buf_len, "\n");
1133 ((mblk_t *)np)->b_wptr += print_len;
1134 buf_len -= print_len;
1135
1136 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) {
1137 print_len = snprintf(
1138 (char *)((mblk_t *)np)->b_wptr,
1139 buf_len, "[%d]=%d ", rdc,
1140 rdc_grp_p->start_rdc + rdc);
1141 ((mblk_t *)np)->b_wptr += print_len;
1142 buf_len -= print_len;
1143 }
1144 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1145 buf_len, "\n");
1146 ((mblk_t *)np)->b_wptr += print_len;
1147 buf_len -= print_len;
1148
1149 for (offset = 0; offset < 16; offset++) {
1150 print_len = snprintf(
1151 (char *)((mblk_t *)np)->b_wptr,
1152 buf_len, " %c",
1153 rdc_grp_p->map & (1 << offset) ?
1154 '1' : '0');
1155 ((mblk_t *)np)->b_wptr += print_len;
1156 buf_len -= print_len;
1157 }
1158 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1159 buf_len, "\n");
1160 ((mblk_t *)np)->b_wptr += print_len;
1161 buf_len -= print_len;
1162 }
1163 }
1164 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1165 "<== nxge_param_get_rxdma_rdcgrp_info"));
1166 return (0);
1167 }
1168
1169 int
nxge_mk_mblk_tail_space(p_mblk_t mp,p_mblk_t * nmp,size_t size)1170 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size)
1171 {
1172 p_mblk_t tmp;
1173
1174 tmp = mp;
1175 while (tmp->b_cont)
1176 tmp = tmp->b_cont;
1177 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) {
1178 tmp->b_cont = allocb(1024, BPRI_HI);
1179 tmp = tmp->b_cont;
1180 if (!tmp)
1181 return (ENOMEM);
1182 }
1183
1184 *nmp = tmp;
1185 return (0);
1186 }
1187
1188
1189 /* ARGSUSED */
1190 int
nxge_param_set_generic(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1191 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1192 char *value, caddr_t cp)
1193 {
1194 char *end;
1195 uint32_t new_value;
1196 p_nxge_param_t pa = (p_nxge_param_t)cp;
1197
1198 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic"));
1199 new_value = (uint32_t)mi_strtol(value, &end, 10);
1200 if (end == value || new_value < pa->minimum ||
1201 new_value > pa->maximum) {
1202 return (EINVAL);
1203 }
1204 pa->value = new_value;
1205 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic"));
1206 return (0);
1207 }
1208
1209
1210 /* ARGSUSED */
1211 int
nxge_param_set_instance(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1212 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1213 char *value, caddr_t cp)
1214 {
1215 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance"));
1216 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance"));
1217 return (0);
1218 }
1219
1220
1221 /* ARGSUSED */
1222 int
nxge_param_set_mac(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1223 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1224 char *value, caddr_t cp)
1225 {
1226 char *end;
1227 uint32_t new_value;
1228 int status = 0;
1229 p_nxge_param_t pa = (p_nxge_param_t)cp;
1230
1231 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac"));
1232 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL);
1233 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) {
1234 return (EINVAL);
1235 }
1236
1237 if (pa->value != new_value) {
1238 pa->old_value = pa->value;
1239 pa->value = new_value;
1240 }
1241
1242 if (!nxge_param_link_update(nxgep)) {
1243 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1244 " false ret from nxge_param_link_update"));
1245 status = EINVAL;
1246 }
1247
1248 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac"));
1249 return (status);
1250 }
1251
1252 /* ARGSUSED */
1253 int
nxge_param_rx_intr_pkts(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1254 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1255 char *value, caddr_t cp)
1256 {
1257 char *end;
1258 uint32_t cfg_value;
1259 p_nxge_param_t pa = (p_nxge_param_t)cp;
1260
1261 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts"));
1262
1263 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
1264
1265 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) ||
1266 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) {
1267 return (EINVAL);
1268 }
1269
1270 if ((pa->value != cfg_value)) {
1271 pa->old_value = pa->value;
1272 pa->value = cfg_value;
1273 nxgep->intr_threshold = pa->value;
1274 }
1275
1276 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts"));
1277 return (0);
1278 }
1279
1280 /* ARGSUSED */
1281 int
nxge_param_rx_intr_time(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1282 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1283 char *value, caddr_t cp)
1284 {
1285 char *end;
1286 uint32_t cfg_value;
1287 p_nxge_param_t pa = (p_nxge_param_t)cp;
1288
1289 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time"));
1290
1291 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
1292
1293 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) ||
1294 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) {
1295 return (EINVAL);
1296 }
1297
1298 if ((pa->value != cfg_value)) {
1299 pa->old_value = pa->value;
1300 pa->value = cfg_value;
1301 nxgep->intr_timeout = pa->value;
1302 }
1303
1304 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time"));
1305 return (0);
1306 }
1307
1308 /* ARGSUSED */
1309 static int
nxge_param_set_mac_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1310 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1311 mblk_t *mp, char *value, caddr_t cp)
1312 {
1313 char *end;
1314 uint32_t status = 0, cfg_value;
1315 p_nxge_param_t pa = (p_nxge_param_t)cp;
1316 uint32_t cfg_it = B_FALSE;
1317 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1318 p_nxge_hw_pt_cfg_t p_cfgp;
1319 uint32_t *val_ptr, *old_val_ptr;
1320 nxge_param_map_t *mac_map;
1321 p_nxge_class_pt_cfg_t p_class_cfgp;
1322 nxge_mv_cfg_t *mac_host_info;
1323
1324 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp "));
1325
1326 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1327 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1328 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1329 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
1330 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1331
1332 /*
1333 * now do decoding
1334 */
1335 mac_map = (nxge_param_map_t *)&cfg_value;
1336 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x",
1337 cfg_value, mac_map->param_id, mac_map->map_to));
1338
1339 if ((mac_map->param_id < p_cfgp->max_macs) &&
1340 p_cfgp->grpids[mac_map->map_to]) {
1341 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1342 " nxge_param_set_mac_rdcgrp mapping"
1343 " id %d grp %d", mac_map->param_id, mac_map->map_to));
1344 val_ptr = (uint32_t *)pa->value;
1345 old_val_ptr = (uint32_t *)pa->old_value;
1346 if (val_ptr[mac_map->param_id] != cfg_value) {
1347 old_val_ptr[mac_map->param_id] =
1348 val_ptr[mac_map->param_id];
1349 val_ptr[mac_map->param_id] = cfg_value;
1350 mac_host_info[mac_map->param_id].mpr_npr =
1351 mac_map->pref;
1352 mac_host_info[mac_map->param_id].flag = 1;
1353 mac_host_info[mac_map->param_id].rdctbl =
1354 mac_map->map_to;
1355 cfg_it = B_TRUE;
1356 }
1357 } else {
1358 return (EINVAL);
1359 }
1360
1361 if (cfg_it == B_TRUE) {
1362 status = nxge_logical_mac_assign_rdc_table(nxgep,
1363 (uint8_t)mac_map->param_id);
1364 if (status != NXGE_OK)
1365 return (EINVAL);
1366 }
1367
1368 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp"));
1369 return (0);
1370 }
1371
1372 /* ARGSUSED */
1373 static int
nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1374 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1375 mblk_t *mp, char *value, caddr_t cp)
1376 {
1377 char *end;
1378 uint32_t status = 0, cfg_value;
1379 p_nxge_param_t pa = (p_nxge_param_t)cp;
1380 uint32_t cfg_it = B_FALSE;
1381 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1382 p_nxge_hw_pt_cfg_t p_cfgp;
1383 uint32_t *val_ptr, *old_val_ptr;
1384 nxge_param_map_t *vmap, *old_map;
1385 p_nxge_class_pt_cfg_t p_class_cfgp;
1386 uint64_t cfgd_vlans;
1387 int i, inc = 0, cfg_position;
1388 nxge_mv_cfg_t *vlan_tbl;
1389
1390 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1391
1392 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1393 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1394 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1395 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
1396
1397 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1398
1399 /* now do decoding */
1400 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >>
1401 NXGE_PARAM_ARRAY_CNT_SHIFT);
1402
1403 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) {
1404 /*
1405 * for now, we process only upto max
1406 * NXGE_PARAM_ARRAY_INIT_SIZE parameters
1407 * In the future, we may want to expand
1408 * the storage array and continue
1409 */
1410 return (EINVAL);
1411 }
1412
1413 vmap = (nxge_param_map_t *)&cfg_value;
1414 if ((vmap->param_id) &&
1415 (vmap->param_id < NXGE_MAX_VLANS) &&
1416 (vmap->map_to < p_cfgp->max_rdc_grpids)) {
1417 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1418 "nxge_param_set_vlan_rdcgrp mapping"
1419 " id %d grp %d",
1420 vmap->param_id, vmap->map_to));
1421 val_ptr = (uint32_t *)pa->value;
1422 old_val_ptr = (uint32_t *)pa->old_value;
1423
1424 /* search to see if this vlan id is already configured */
1425 for (i = 0; i < cfgd_vlans; i++) {
1426 old_map = (nxge_param_map_t *)&val_ptr[i];
1427 if ((old_map->param_id == 0) ||
1428 (vmap->param_id == old_map->param_id) ||
1429 (vlan_tbl[vmap->param_id].flag)) {
1430 cfg_position = i;
1431 break;
1432 }
1433 }
1434
1435 if (cfgd_vlans == 0) {
1436 cfg_position = 0;
1437 inc++;
1438 }
1439
1440 if (i == cfgd_vlans) {
1441 cfg_position = i;
1442 inc++;
1443 }
1444
1445 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
1446 "set_vlan_rdcgrp mapping"
1447 " i %d cfgd_vlans %llx position %d ",
1448 i, cfgd_vlans, cfg_position));
1449 if (val_ptr[cfg_position] != cfg_value) {
1450 old_val_ptr[cfg_position] = val_ptr[cfg_position];
1451 val_ptr[cfg_position] = cfg_value;
1452 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
1453 vlan_tbl[vmap->param_id].flag = 1;
1454 vlan_tbl[vmap->param_id].rdctbl =
1455 vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
1456 cfg_it = B_TRUE;
1457 if (inc) {
1458 cfgd_vlans++;
1459 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK;
1460 pa->type |= (cfgd_vlans <<
1461 NXGE_PARAM_ARRAY_CNT_SHIFT);
1462
1463 }
1464 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
1465 "after: param_set_vlan_rdcgrp "
1466 " cfg_vlans %llx position %d \n",
1467 cfgd_vlans, cfg_position));
1468 }
1469 } else {
1470 return (EINVAL);
1471 }
1472
1473 if (cfg_it == B_TRUE) {
1474 status = nxge_fflp_config_vlan_table(nxgep,
1475 (uint16_t)vmap->param_id);
1476 if (status != NXGE_OK)
1477 return (EINVAL);
1478 }
1479
1480 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp"));
1481 return (0);
1482 }
1483
1484 /* ARGSUSED */
1485 static int
nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)1486 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1487 mblk_t *mp, caddr_t cp)
1488 {
1489
1490 uint_t print_len, buf_len;
1491 p_mblk_t np;
1492 int i;
1493 uint32_t *val_ptr;
1494 nxge_param_map_t *vmap;
1495 p_nxge_param_t pa = (p_nxge_param_t)cp;
1496 p_nxge_class_pt_cfg_t p_class_cfgp;
1497 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1498 p_nxge_hw_pt_cfg_t p_cfgp;
1499 uint64_t cfgd_vlans = 0;
1500 nxge_mv_cfg_t *vlan_tbl;
1501 int buff_alloc_size =
1502 NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
1503
1504 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1505 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n",
1506 nxgep->function_num);
1507
1508 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1509 (void) mi_mpprintf(mp, "%s\n", "out of buffer");
1510 return (0);
1511 }
1512
1513 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1514 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1515
1516 buf_len = buff_alloc_size;
1517 mp->b_cont = np;
1518 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >>
1519 NXGE_PARAM_ARRAY_CNT_SHIFT;
1520
1521 i = (int)cfgd_vlans;
1522 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1523 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
1524 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1525 "Configured VLANs %d\n"
1526 "VLAN ID\t RDC GRP (Actual/Port)\t"
1527 " Prefernce\n", i);
1528 ((mblk_t *)np)->b_wptr += print_len;
1529 buf_len -= print_len;
1530 val_ptr = (uint32_t *)pa->value;
1531
1532 for (i = 0; i < cfgd_vlans; i++) {
1533 vmap = (nxge_param_map_t *)&val_ptr[i];
1534 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) {
1535 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1536 buf_len,
1537 " %d\t\t %d/%d\t\t %d\n",
1538 vmap->param_id,
1539 vlan_tbl[vmap->param_id].rdctbl,
1540 vlan_tbl[vmap->param_id].rdctbl -
1541 p_cfgp->def_mac_rxdma_grpid,
1542 vlan_tbl[vmap->param_id].mpr_npr);
1543 ((mblk_t *)np)->b_wptr += print_len;
1544 buf_len -= print_len;
1545 }
1546 }
1547
1548 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp"));
1549 return (0);
1550 }
1551
1552 /* ARGSUSED */
1553 static int
nxge_param_get_mac_rdcgrp(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)1554 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1555 mblk_t *mp, caddr_t cp)
1556 {
1557 uint_t print_len, buf_len;
1558 p_mblk_t np;
1559 int i;
1560 p_nxge_class_pt_cfg_t p_class_cfgp;
1561 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1562 p_nxge_hw_pt_cfg_t p_cfgp;
1563 nxge_mv_cfg_t *mac_host_info;
1564
1565 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
1566 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp "));
1567 (void) mi_mpprintf(mp,
1568 "MAC ADDR RDC Mapping Information for Port\t %d\n",
1569 nxgep->function_num);
1570
1571 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1572 (void) mi_mpprintf(mp, "%s\n", "out of buffer");
1573 return (0);
1574 }
1575
1576 buf_len = buff_alloc_size;
1577 mp->b_cont = np;
1578 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1579 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1580 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1581 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
1582 print_len = snprintf((char *)np->b_wptr, buf_len,
1583 "MAC ID\t RDC GRP (Actual/Port)\t"
1584 " Prefernce\n");
1585 ((mblk_t *)np)->b_wptr += print_len;
1586 buf_len -= print_len;
1587 for (i = 0; i < p_cfgp->max_macs; i++) {
1588 if (mac_host_info[i].flag) {
1589 print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1590 buf_len,
1591 " %d\t %d/%d\t\t %d\n",
1592 i, mac_host_info[i].rdctbl,
1593 mac_host_info[i].rdctbl -
1594 p_cfgp->def_mac_rxdma_grpid,
1595 mac_host_info[i].mpr_npr);
1596 ((mblk_t *)np)->b_wptr += print_len;
1597 buf_len -= print_len;
1598 }
1599 }
1600 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1601 "Done Info Dumping \n");
1602 ((mblk_t *)np)->b_wptr += print_len;
1603 buf_len -= print_len;
1604 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp"));
1605 return (0);
1606 }
1607
1608 /* ARGSUSED */
1609 static int
nxge_param_tcam_enable(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1610 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q,
1611 mblk_t *mp, char *value, caddr_t cp)
1612 {
1613 uint32_t status = 0, cfg_value;
1614 p_nxge_param_t pa = (p_nxge_param_t)cp;
1615 uint32_t cfg_it = B_FALSE;
1616 char *end;
1617
1618 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable"));
1619
1620 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
1621 if (pa->value != cfg_value) {
1622 pa->old_value = pa->value;
1623 pa->value = cfg_value;
1624 cfg_it = B_TRUE;
1625 }
1626
1627 if (cfg_it == B_TRUE) {
1628 if (pa->value)
1629 status = nxge_fflp_config_tcam_enable(nxgep);
1630 else
1631 status = nxge_fflp_config_tcam_disable(nxgep);
1632 if (status != NXGE_OK)
1633 return (EINVAL);
1634 }
1635
1636 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable"));
1637 return (0);
1638 }
1639
1640 /* ARGSUSED */
1641 static int
nxge_param_hash_lookup_enable(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1642 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q,
1643 mblk_t *mp, char *value, caddr_t cp)
1644 {
1645 uint32_t status = 0, cfg_value;
1646 p_nxge_param_t pa = (p_nxge_param_t)cp;
1647 uint32_t cfg_it = B_FALSE;
1648 char *end;
1649
1650 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable"));
1651
1652 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
1653 if (pa->value != cfg_value) {
1654 pa->old_value = pa->value;
1655 pa->value = cfg_value;
1656 cfg_it = B_TRUE;
1657 }
1658
1659 if (cfg_it == B_TRUE) {
1660 if (pa->value)
1661 status = nxge_fflp_config_hash_lookup_enable(nxgep);
1662 else
1663 status = nxge_fflp_config_hash_lookup_disable(nxgep);
1664 if (status != NXGE_OK)
1665 return (EINVAL);
1666 }
1667
1668 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable"));
1669 return (0);
1670 }
1671
1672 /* ARGSUSED */
1673 static int
nxge_param_llc_snap_enable(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1674 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q,
1675 mblk_t *mp, char *value, caddr_t cp)
1676 {
1677 char *end;
1678 uint32_t status = 0, cfg_value;
1679 p_nxge_param_t pa = (p_nxge_param_t)cp;
1680 uint32_t cfg_it = B_FALSE;
1681
1682 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable"));
1683
1684 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
1685 if (pa->value != cfg_value) {
1686 pa->old_value = pa->value;
1687 pa->value = cfg_value;
1688 cfg_it = B_TRUE;
1689 }
1690
1691 if (cfg_it == B_TRUE) {
1692 if (pa->value)
1693 status = nxge_fflp_config_tcam_enable(nxgep);
1694 else
1695 status = nxge_fflp_config_tcam_disable(nxgep);
1696 if (status != NXGE_OK)
1697 return (EINVAL);
1698 }
1699
1700 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable"));
1701 return (0);
1702 }
1703
1704 /* ARGSUSED */
1705 static int
nxge_param_set_ether_usr(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1706 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q,
1707 mblk_t *mp, char *value, caddr_t cp)
1708 {
1709 char *end;
1710 uint32_t status = 0, cfg_value;
1711 p_nxge_param_t pa = (p_nxge_param_t)cp;
1712 uint8_t cfg_it = B_FALSE;
1713
1714 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr"));
1715
1716 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1717 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1718 return (EINVAL);
1719 }
1720
1721 if (pa->value != cfg_value) {
1722 pa->old_value = pa->value;
1723 pa->value = cfg_value;
1724 cfg_it = B_TRUE;
1725 }
1726
1727 /* do the actual hw setup */
1728 if (cfg_it == B_TRUE) {
1729 (void) mi_strtol(pa->name, &end, BASE_DECIMAL);
1730 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr"));
1731 }
1732
1733 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr"));
1734 return (status);
1735 }
1736
1737 /* ARGSUSED */
1738 static int
nxge_param_set_ip_usr(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1739 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q,
1740 mblk_t *mp, char *value, caddr_t cp)
1741 {
1742 char *end;
1743 tcam_class_t class;
1744 uint32_t status, cfg_value;
1745 p_nxge_param_t pa = (p_nxge_param_t)cp;
1746 uint32_t cfg_it = B_FALSE;
1747
1748 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr"));
1749
1750 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1751 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1752 return (EINVAL);
1753 }
1754
1755 if (pa->value != cfg_value) {
1756 pa->old_value = pa->value;
1757 pa->value = cfg_value;
1758 cfg_it = B_TRUE;
1759 }
1760
1761 /* do the actual hw setup with cfg_value. */
1762 status = 0;
1763 if (cfg_it == B_TRUE) {
1764 class = mi_strtol(pa->name, &end, 10);
1765 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value);
1766 }
1767
1768 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr"));
1769 return (status);
1770 }
1771
1772 static int
nxge_class_name_2value(p_nxge_t nxgep,char * name)1773 nxge_class_name_2value(p_nxge_t nxgep, char *name)
1774 {
1775 int i;
1776 int class_instance = param_class_opt_ip_usr4;
1777 p_nxge_param_t param_arr;
1778
1779 param_arr = nxgep->param_arr;
1780 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) {
1781 if (strcmp(param_arr[class_instance].name, name) == 0)
1782 return (i);
1783 class_instance++;
1784 }
1785 return (-1);
1786 }
1787
1788 int
nxge_param_set_ip_opt(p_nxge_t nxgep,queue_t * q __unused,mblk_t * mp __unused,char * value,caddr_t cp)1789 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q __unused,
1790 mblk_t *mp __unused, char *value, caddr_t cp)
1791 {
1792 char *end;
1793 uint32_t status, cfg_value;
1794 p_nxge_param_t pa = (p_nxge_param_t)cp;
1795 tcam_class_t class;
1796 uint32_t cfg_it = B_FALSE;
1797
1798 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt"));
1799
1800 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1801 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1802 return (EINVAL);
1803 }
1804
1805 if (pa->value != cfg_value) {
1806 pa->old_value = pa->value;
1807 pa->value = cfg_value;
1808 cfg_it = B_TRUE;
1809 }
1810
1811 if (cfg_it == B_TRUE) {
1812 /* do the actual hw setup */
1813 class = nxge_class_name_2value(nxgep, pa->name);
1814 if (class == -1)
1815 return (EINVAL);
1816
1817 /* Filter out the allowed bits */
1818 pa->value &= (NXGE_CLASS_FLOW_USE_PORTNUM |
1819 NXGE_CLASS_FLOW_USE_L2DA | NXGE_CLASS_FLOW_USE_VLAN |
1820 NXGE_CLASS_FLOW_USE_PROTO | NXGE_CLASS_FLOW_USE_IPSRC |
1821 NXGE_CLASS_FLOW_USE_IPDST | NXGE_CLASS_FLOW_USE_SRC_PORT |
1822 NXGE_CLASS_FLOW_USE_DST_PORT);
1823
1824 status = nxge_fflp_ip_class_config(nxgep, class, pa->value);
1825 if (status != NXGE_OK)
1826 return (EINVAL);
1827 }
1828
1829 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt"));
1830 return (0);
1831 }
1832
1833 /* ARGSUSED */
1834 static int
nxge_param_get_ip_opt(p_nxge_t nxgep,queue_t * q,mblk_t * mp,caddr_t cp)1835 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q,
1836 mblk_t *mp, caddr_t cp)
1837 {
1838 uint32_t status, cfg_value;
1839 p_nxge_param_t pa = (p_nxge_param_t)cp;
1840 tcam_class_t class;
1841
1842 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt"));
1843
1844 /* do the actual hw setup */
1845 class = nxge_class_name_2value(nxgep, pa->name);
1846 if (class == -1)
1847 return (EINVAL);
1848
1849 cfg_value = 0;
1850 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
1851 if (status != NXGE_OK)
1852 return (EINVAL);
1853
1854 /* Filter out the allowed bits */
1855 cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA |
1856 NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO |
1857 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST |
1858 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT);
1859
1860 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1861 "nxge_param_get_ip_opt_get %x ", cfg_value));
1862
1863 pa->value = cfg_value;
1864 (void) mi_mpprintf(mp, "%x", cfg_value);
1865
1866 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
1867 return (0);
1868 }
1869
1870 /* ARGSUSED */
1871 static int
nxge_param_fflp_hash_init(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1872 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q,
1873 mblk_t *mp, char *value, caddr_t cp)
1874 {
1875 char *end;
1876 uint32_t status, cfg_value;
1877 p_nxge_param_t pa = (p_nxge_param_t)cp;
1878 tcam_class_t class;
1879 uint32_t cfg_it = B_FALSE;
1880
1881 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init"));
1882
1883 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1884 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1885 return (EINVAL);
1886 }
1887
1888 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1889 "nxge_param_fflp_hash_init value %x", cfg_value));
1890
1891 if (pa->value != cfg_value) {
1892 pa->old_value = pa->value;
1893 pa->value = cfg_value;
1894 cfg_it = B_TRUE;
1895 }
1896
1897 if (cfg_it == B_TRUE) {
1898 char *h_name;
1899
1900 /* do the actual hw setup */
1901 h_name = pa->name;
1902 h_name++;
1903 class = mi_strtol(h_name, &end, 10);
1904 switch (class) {
1905 case 1:
1906 status = nxge_fflp_set_hash1(nxgep,
1907 (uint32_t)pa->value);
1908 break;
1909 case 2:
1910 status = nxge_fflp_set_hash2(nxgep,
1911 (uint16_t)pa->value);
1912 break;
1913
1914 default:
1915 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1916 " nxge_param_fflp_hash_init"
1917 " %s Wrong hash var %d",
1918 pa->name, class));
1919 return (EINVAL);
1920 }
1921 if (status != NXGE_OK)
1922 return (EINVAL);
1923 }
1924
1925 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init"));
1926 return (0);
1927 }
1928
1929 /* ARGSUSED */
1930 static int
nxge_param_set_grp_rdc(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1931 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q,
1932 mblk_t *mp, char *value, caddr_t cp)
1933 {
1934 char *end;
1935 uint32_t status = 0, cfg_value;
1936 p_nxge_param_t pa = (p_nxge_param_t)cp;
1937 uint32_t cfg_it = B_FALSE;
1938 int rdc_grp;
1939 uint8_t real_rdc;
1940 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1941 p_nxge_hw_pt_cfg_t p_cfgp;
1942 p_nxge_rdc_grp_t rdc_grp_p;
1943
1944 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1945 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1946
1947 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc"));
1948
1949 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
1950 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1951 return (EINVAL);
1952 }
1953
1954 if (cfg_value >= p_cfgp->max_rdcs) {
1955 return (EINVAL);
1956 }
1957
1958 if (pa->value != cfg_value) {
1959 pa->old_value = pa->value;
1960 pa->value = cfg_value;
1961 cfg_it = B_TRUE;
1962 }
1963
1964 if (cfg_it == B_TRUE) {
1965 char *grp_name;
1966 grp_name = pa->name;
1967 grp_name += strlen("default-grp");
1968 rdc_grp = mi_strtol(grp_name, &end, 10);
1969 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
1970 real_rdc = rdc_grp_p->start_rdc + cfg_value;
1971 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp,
1972 cfg_value) == B_FALSE) {
1973 pa->value = pa->old_value;
1974 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1975 " nxge_param_set_grp_rdc"
1976 " %d read %d actual %d outof range",
1977 rdc_grp, cfg_value, real_rdc));
1978 return (EINVAL);
1979 }
1980 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp,
1981 real_rdc);
1982 if (status != NXGE_OK)
1983 return (EINVAL);
1984 }
1985
1986 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc"));
1987 return (0);
1988 }
1989
1990 /* ARGSUSED */
1991 static int
nxge_param_set_port_rdc(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)1992 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q,
1993 mblk_t *mp, char *value, caddr_t cp)
1994 {
1995 char *end;
1996 uint32_t status = B_TRUE, cfg_value;
1997 p_nxge_param_t pa = (p_nxge_param_t)cp;
1998 uint32_t cfg_it = B_FALSE;
1999
2000 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2001 p_nxge_hw_pt_cfg_t p_cfgp;
2002
2003 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc"));
2004 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2005 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2006
2007 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
2008 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
2009 return (EINVAL);
2010 }
2011
2012 if (pa->value != cfg_value) {
2013 if (cfg_value >= p_cfgp->max_rdcs)
2014 return (EINVAL);
2015 pa->old_value = pa->value;
2016 pa->value = cfg_value;
2017 cfg_it = B_TRUE;
2018 }
2019
2020 if (cfg_it == B_TRUE) {
2021 int rdc;
2022 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0)
2023 return (EINVAL);
2024 status = nxge_rxdma_cfg_port_default_rdc(nxgep,
2025 nxgep->function_num, rdc);
2026 if (status != NXGE_OK)
2027 return (EINVAL);
2028 }
2029
2030 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc"));
2031 return (0);
2032 }
2033
2034 /* ARGSUSED */
2035 static int
nxge_param_set_nxge_debug_flag(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)2036 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q,
2037 mblk_t *mp, char *value, caddr_t cp)
2038 {
2039 char *end;
2040 uint32_t status = 0;
2041 uint64_t cfg_value = 0;
2042 p_nxge_param_t pa = (p_nxge_param_t)cp;
2043 uint32_t cfg_it = B_FALSE;
2044
2045 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag"));
2046 cfg_value = mi_strtol(value, &end, BASE_HEX);
2047
2048 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
2049 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2050 " nxge_param_set_nxge_debug_flag"
2051 " outof range %llx", cfg_value));
2052 return (EINVAL);
2053 }
2054 if (pa->value != cfg_value) {
2055 pa->old_value = pa->value;
2056 pa->value = cfg_value;
2057 cfg_it = B_TRUE;
2058 }
2059
2060 if (cfg_it == B_TRUE) {
2061 nxgep->nxge_debug_level = pa->value;
2062 }
2063
2064 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag"));
2065 return (status);
2066 }
2067
2068 /* ARGSUSED */
2069 static int
nxge_param_get_debug_flag(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2070 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2071 {
2072 int status = 0;
2073 p_nxge_param_t pa = (p_nxge_param_t)cp;
2074
2075 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag"));
2076
2077 if (pa->value > 0xffffffff)
2078 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32),
2079 (int)(pa->value & 0xffffffff));
2080 else
2081 (void) mi_mpprintf(mp, "%x", (int)pa->value);
2082
2083 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag"));
2084 return (status);
2085 }
2086
2087 /* ARGSUSED */
2088 static int
nxge_param_set_npi_debug_flag(p_nxge_t nxgep,queue_t * q,mblk_t * mp,char * value,caddr_t cp)2089 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q,
2090 mblk_t *mp, char *value, caddr_t cp)
2091 {
2092 char *end;
2093 uint32_t status = 0;
2094 uint64_t cfg_value = 0;
2095 p_nxge_param_t pa;
2096 uint32_t cfg_it = B_FALSE;
2097
2098 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag"));
2099 cfg_value = mi_strtol(value, &end, BASE_HEX);
2100 pa = (p_nxge_param_t)cp;
2101 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
2102 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag"
2103 " outof range %llx", cfg_value));
2104 return (EINVAL);
2105 }
2106 if (pa->value != cfg_value) {
2107 pa->old_value = pa->value;
2108 pa->value = cfg_value;
2109 cfg_it = B_TRUE;
2110 }
2111
2112 if (cfg_it == B_TRUE) {
2113 npi_debug_level = pa->value;
2114 }
2115 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag"));
2116 return (status);
2117 }
2118
2119 /* ARGSUSED */
2120 static int
nxge_param_dump_rdc(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2121 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2122 {
2123 nxge_grp_set_t *set = &nxgep->rx_set;
2124 int rdc;
2125
2126 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc"));
2127
2128 if (!isLDOMguest(nxgep))
2129 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2130
2131 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) {
2132 if ((1 << rdc) & set->owned.map) {
2133 (void) nxge_dump_rxdma_channel(nxgep, rdc);
2134 }
2135 }
2136
2137 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc"));
2138 return (0);
2139 }
2140
2141 /* ARGSUSED */
2142 static int
nxge_param_dump_tdc(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2143 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2144 {
2145 nxge_grp_set_t *set = &nxgep->tx_set;
2146 int tdc;
2147
2148 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc"));
2149
2150 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
2151 if ((1 << tdc) & set->owned.map) {
2152 (void) nxge_txdma_regs_dump(nxgep, tdc);
2153 }
2154 }
2155
2156 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc"));
2157 return (0);
2158 }
2159
2160 /* ARGSUSED */
2161 static int
nxge_param_dump_fflp_regs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2162 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2163 {
2164 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs"));
2165
2166 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2167
2168 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs"));
2169 return (0);
2170 }
2171
2172 /* ARGSUSED */
2173 static int
nxge_param_dump_mac_regs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2174 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2175 {
2176 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs"));
2177
2178 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
2179 nxgep->function_num);
2180
2181 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs"));
2182 return (0);
2183 }
2184
2185 /* ARGSUSED */
2186 static int
nxge_param_dump_ipp_regs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2187 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2188 {
2189 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs"));
2190
2191 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
2192 nxgep->function_num);
2193 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs"));
2194 return (0);
2195 }
2196
2197 /* ARGSUSED */
2198 static int
nxge_param_dump_vlan_table(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2199 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2200 {
2201 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table"));
2202
2203 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep));
2204
2205 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table"));
2206 return (0);
2207 }
2208
2209 /* ARGSUSED */
2210 static int
nxge_param_dump_rdc_table(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2211 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2212 {
2213 uint8_t table;
2214
2215 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table"));
2216 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) {
2217 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep),
2218 table);
2219 }
2220
2221 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table"));
2222 return (0);
2223 }
2224
2225 typedef struct block_info {
2226 char *name;
2227 uint32_t offset;
2228 } block_info_t;
2229
2230 block_info_t reg_block[] = {
2231 {"PIO", PIO},
2232 {"FZC_PIO", FZC_PIO},
2233 {"FZC_XMAC", FZC_MAC},
2234 {"FZC_IPP", FZC_IPP},
2235 {"FFLP", FFLP},
2236 {"FZC_FFLP", FZC_FFLP},
2237 {"PIO_VADDR", PIO_VADDR},
2238 {"ZCP", ZCP},
2239 {"FZC_ZCP", FZC_ZCP},
2240 {"DMC", DMC},
2241 {"FZC_DMC", FZC_DMC},
2242 {"TXC", TXC},
2243 {"FZC_TXC", FZC_TXC},
2244 {"PIO_LDSV", PIO_LDSV},
2245 {"PIO_LDGIM", PIO_LDGIM},
2246 {"PIO_IMASK0", PIO_IMASK0},
2247 {"PIO_IMASK1", PIO_IMASK1},
2248 {"FZC_PROM", FZC_PROM},
2249 {"END", ALL_FF_32},
2250 };
2251
2252 /* ARGSUSED */
2253 static int
nxge_param_dump_ptrs(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t cp)2254 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2255 {
2256 uint_t print_len, buf_len;
2257 p_mblk_t np;
2258 int rdc, tdc, block;
2259 uint64_t base;
2260 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2261 p_nxge_hw_pt_cfg_t p_cfgp;
2262 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K;
2263 p_tx_ring_t *tx_rings;
2264 p_rx_rcr_rings_t rx_rcr_rings;
2265 p_rx_rcr_ring_t *rcr_rings;
2266 p_rx_rbr_rings_t rx_rbr_rings;
2267 p_rx_rbr_ring_t *rbr_rings;
2268
2269 NXGE_DEBUG_MSG((nxgep, IOC_CTL,
2270 "==> nxge_param_dump_ptrs"));
2271
2272 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n",
2273 nxgep->function_num);
2274
2275 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
2276 /* The following may work even if we cannot get a large buf. */
2277 (void) mi_mpprintf(mp, "%s\n", "out of buffer");
2278 return (0);
2279 }
2280
2281 buf_len = buff_alloc_size;
2282 mp->b_cont = np;
2283 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2284 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2285
2286 rx_rcr_rings = nxgep->rx_rcr_rings;
2287 rcr_rings = rx_rcr_rings->rcr_rings;
2288 rx_rbr_rings = nxgep->rx_rbr_rings;
2289 rbr_rings = rx_rbr_rings->rbr_rings;
2290 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2291 "nxgep (nxge_t) $%p\n"
2292 "dev_regs (dev_regs_t) $%p\n",
2293 (void *)nxgep, (void *)nxgep->dev_regs);
2294
2295 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2296
2297 /* do register pointers */
2298 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2299 "reg base (npi_reg_ptr_t) $%p\t "
2300 "pci reg (npi_reg_ptr_t) $%p\n",
2301 (void *)nxgep->dev_regs->nxge_regp,
2302 (void *)nxgep->dev_regs->nxge_pciregp);
2303
2304 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2305
2306 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2307 "\nBlock \t Offset \n");
2308
2309 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2310 block = 0;
2311 base = (uint64_t)nxgep->dev_regs->nxge_regp;
2312 while (reg_block[block].offset != ALL_FF_32) {
2313 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2314 "%9s\t 0x%llx\n",
2315 reg_block[block].name,
2316 (unsigned long long)(reg_block[block].offset + base));
2317 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2318 block++;
2319 }
2320
2321 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2322 "\nRDC\t rcrp (rx_rcr_ring_t)\t "
2323 "rbrp (rx_rbr_ring_t)\n");
2324
2325 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2326
2327 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) {
2328 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2329 " %d\t $%p\t\t $%p\n",
2330 rdc, (void *)rcr_rings[rdc],
2331 (void *)rbr_rings[rdc]);
2332 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2333 }
2334
2335 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2336 "\nTDC\t tdcp (tx_ring_t)\n");
2337
2338 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2339 tx_rings = nxgep->tx_rings->rings;
2340 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) {
2341 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2342 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]);
2343 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2344 }
2345
2346 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n");
2347
2348 ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2349 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs"));
2350 return (0);
2351 }
2352
2353
2354 /* ARGSUSED */
2355 int
nxge_nd_get_names(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t param)2356 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param)
2357 {
2358 ND *nd;
2359 NDE *nde;
2360 char *rwtag;
2361 boolean_t get_ok, set_ok;
2362 size_t param_len;
2363 int status = 0;
2364
2365 nd = (ND *)param;
2366 if (!nd)
2367 return (ENOENT);
2368
2369 for (nde = nd->nd_tbl; nde->nde_name; nde++) {
2370 get_ok = (nde->nde_get_pfi != nxge_get_default) &&
2371 (nde->nde_get_pfi != NULL);
2372 set_ok = (nde->nde_set_pfi != nxge_set_default) &&
2373 (nde->nde_set_pfi != NULL);
2374 if (get_ok) {
2375 if (set_ok)
2376 rwtag = "read and write";
2377 else
2378 rwtag = "read only";
2379 } else if (set_ok)
2380 rwtag = "write only";
2381 else {
2382 continue;
2383 }
2384 param_len = strlen(rwtag);
2385 param_len += strlen(nde->nde_name);
2386 param_len += 4;
2387
2388 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag);
2389 }
2390 return (status);
2391 }
2392
2393 /* ARGSUSED */
2394 int
nxge_get_default(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,caddr_t data)2395 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data)
2396 {
2397 return (EACCES);
2398 }
2399
2400 /* ARGSUSED */
2401 int
nxge_set_default(p_nxge_t nxgep,queue_t * q,p_mblk_t mp,char * value,caddr_t data)2402 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value,
2403 caddr_t data)
2404 {
2405 return (EACCES);
2406 }
2407
2408 boolean_t
nxge_param_link_update(p_nxge_t nxgep)2409 nxge_param_link_update(p_nxge_t nxgep)
2410 {
2411 p_nxge_param_t param_arr;
2412 nxge_param_index_t i;
2413 boolean_t update_xcvr;
2414 boolean_t update_dev;
2415 int instance;
2416 boolean_t status = B_TRUE;
2417
2418 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update"));
2419
2420 param_arr = nxgep->param_arr;
2421 instance = nxgep->instance;
2422 update_xcvr = B_FALSE;
2423 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) {
2424 update_xcvr |= param_arr[i].value;
2425 }
2426
2427 if (update_xcvr) {
2428 update_xcvr = B_FALSE;
2429 for (i = param_autoneg; i < param_enable_ipg0; i++) {
2430 update_xcvr |=
2431 (param_arr[i].value != param_arr[i].old_value);
2432 param_arr[i].old_value = param_arr[i].value;
2433 }
2434 if (update_xcvr) {
2435 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2436 "==> nxge_param_link_update: update xcvr"));
2437 RW_ENTER_WRITER(&nxgep->filter_lock);
2438 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
2439 (void) nxge_link_init(nxgep);
2440 (void) nxge_mac_init(nxgep);
2441 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
2442 RW_EXIT(&nxgep->filter_lock);
2443 }
2444 } else {
2445 cmn_err(CE_WARN, " Last setting will leave nxge%d with "
2446 " no link capabilities.", instance);
2447 cmn_err(CE_WARN, " Restoring previous setting.");
2448 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++)
2449 param_arr[i].value = param_arr[i].old_value;
2450 }
2451
2452 update_dev = B_FALSE;
2453
2454 if (update_dev) {
2455 RW_ENTER_WRITER(&nxgep->filter_lock);
2456 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2457 "==> nxge_param_link_update: update dev"));
2458 (void) nxge_rx_mac_disable(nxgep);
2459 (void) nxge_tx_mac_disable(nxgep);
2460 (void) nxge_tx_mac_enable(nxgep);
2461 (void) nxge_rx_mac_enable(nxgep);
2462 RW_EXIT(&nxgep->filter_lock);
2463 }
2464
2465 nxge_param_hw_update_exit:
2466 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2467 "<== nxge_param_link_update status = 0x%08x", status));
2468 return (status);
2469 }
2470
2471 /*
2472 * synchronize the adv* and en* parameters.
2473 *
2474 * See comments in <sys/dld.h> for details of the *_en_*
2475 * parameters. The usage of ndd for setting adv parameters will
2476 * synchronize all the en parameters with the nxge parameters,
2477 * implicitly disabling any settings made via dladm.
2478 */
2479 static void
nxge_param_sync(p_nxge_t nxgep)2480 nxge_param_sync(p_nxge_t nxgep)
2481 {
2482 p_nxge_param_t param_arr;
2483 param_arr = nxgep->param_arr;
2484
2485 nxgep->param_en_pause = param_arr[param_anar_pause].value;
2486 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value;
2487 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value;
2488 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value;
2489 }
2490
2491 /* ARGSUSED */
2492 int
nxge_dld_get_ip_opt(p_nxge_t nxgep,caddr_t cp)2493 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp)
2494 {
2495 uint32_t status, cfg_value;
2496 p_nxge_param_t pa = (p_nxge_param_t)cp;
2497 tcam_class_t class;
2498
2499 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt"));
2500
2501 /* do the actual hw setup */
2502 class = nxge_class_name_2value(nxgep, pa->name);
2503 if (class == -1)
2504 return (EINVAL);
2505
2506 cfg_value = 0;
2507 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
2508 if (status != NXGE_OK)
2509 return (EINVAL);
2510
2511 /* Filter out the allowed bits */
2512 cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA |
2513 NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO |
2514 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST |
2515 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT);
2516
2517 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2518 "nxge_param_get_ip_opt_get %x ", cfg_value));
2519
2520 pa->value = cfg_value;
2521
2522 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
2523 return (0);
2524 }
2525