1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/ib_user_verbs.h>
55 #include <rdma/ib_umem.h>
56 #include <rdma/ib_addr.h>
57 #include <linux/hashtable.h>
58
59 #include "bnxt_ulp.h"
60 #include "roce_hsi.h"
61 #include "qplib_res.h"
62 #include "qplib_sp.h"
63 #include "qplib_fp.h"
64 #include "qplib_rcfw.h"
65 #include "bnxt_re.h"
66 #include "ib_verbs.h"
67 #include <rdma/bnxt_re-abi.h>
68 #include "bnxt.h"
69 #include "hw_counters.h"
70 #include "debugfs.h"
71
72 static char version[] =
73 BNXT_RE_DESC "\n";
74
75 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
76 MODULE_DESCRIPTION(BNXT_RE_DESC);
77 MODULE_LICENSE("Dual BSD/GPL");
78
79 /* globals */
80 static DEFINE_MUTEX(bnxt_re_mutex);
81
82 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
83
84 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
85 u32 *offset);
86 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
87 u8 port_num, enum ib_event_type event);
bnxt_re_set_db_offset(struct bnxt_re_dev * rdev)88 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
89 {
90 struct bnxt_qplib_chip_ctx *cctx;
91 struct bnxt_en_dev *en_dev;
92 struct bnxt_qplib_res *res;
93 u32 l2db_len = 0;
94 u32 offset = 0;
95 u32 barlen;
96 int rc;
97
98 res = &rdev->qplib_res;
99 en_dev = rdev->en_dev;
100 cctx = rdev->chip_ctx;
101
102 /* Issue qcfg */
103 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
104 if (rc)
105 dev_info(rdev_to_dev(rdev),
106 "Couldn't get DB bar size, Low latency framework is disabled\n");
107 /* set register offsets for both UC and WC */
108 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
109 res->dpi_tbl.ucreg.offset = offset;
110 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
111 } else {
112 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
113 BNXT_QPLIB_DBR_PF_DB_OFFSET;
114 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
115 }
116
117 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
118 * is equal to the DB-Bar actual size. This indicates that L2
119 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
120 * in such cases and DB-push will be disabled.
121 */
122 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
123 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
124 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
125 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
126 }
127 }
128
bnxt_re_set_drv_mode(struct bnxt_re_dev * rdev)129 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev)
130 {
131 struct bnxt_qplib_chip_ctx *cctx;
132
133 cctx = rdev->chip_ctx;
134 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ?
135 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC;
136 if (bnxt_re_hwrm_qcaps(rdev))
137 dev_err(rdev_to_dev(rdev),
138 "Failed to query hwrm qcaps\n");
139 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) {
140 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;
141 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT;
142 }
143 }
144
bnxt_re_destroy_chip_ctx(struct bnxt_re_dev * rdev)145 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
146 {
147 struct bnxt_qplib_chip_ctx *chip_ctx;
148
149 if (!rdev->chip_ctx)
150 return;
151
152 kfree(rdev->dev_attr);
153 rdev->dev_attr = NULL;
154
155 chip_ctx = rdev->chip_ctx;
156 rdev->chip_ctx = NULL;
157 rdev->rcfw.res = NULL;
158 rdev->qplib_res.cctx = NULL;
159 rdev->qplib_res.pdev = NULL;
160 rdev->qplib_res.netdev = NULL;
161 kfree(chip_ctx);
162 }
163
bnxt_re_setup_chip_ctx(struct bnxt_re_dev * rdev)164 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
165 {
166 struct bnxt_qplib_chip_ctx *chip_ctx;
167 struct bnxt_en_dev *en_dev;
168 int rc = -ENOMEM;
169
170 en_dev = rdev->en_dev;
171
172 rdev->qplib_res.pdev = en_dev->pdev;
173 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
174 if (!chip_ctx)
175 return -ENOMEM;
176 chip_ctx->chip_num = en_dev->chip_num;
177 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
178
179 rdev->chip_ctx = chip_ctx;
180 /* rest members to follow eventually */
181
182 rdev->qplib_res.cctx = rdev->chip_ctx;
183 rdev->rcfw.res = &rdev->qplib_res;
184 rdev->dev_attr = kzalloc(sizeof(*rdev->dev_attr), GFP_KERNEL);
185 if (!rdev->dev_attr)
186 goto free_chip_ctx;
187 rdev->qplib_res.dattr = rdev->dev_attr;
188 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
189 rdev->qplib_res.en_dev = en_dev;
190
191 bnxt_re_set_drv_mode(rdev);
192
193 bnxt_re_set_db_offset(rdev);
194 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
195 if (rc)
196 goto free_dev_attr;
197
198 if (bnxt_qplib_determine_atomics(en_dev->pdev))
199 ibdev_info(&rdev->ibdev,
200 "platform doesn't support global atomics.");
201 return 0;
202 free_dev_attr:
203 kfree(rdev->dev_attr);
204 rdev->dev_attr = NULL;
205 free_chip_ctx:
206 kfree(rdev->chip_ctx);
207 rdev->chip_ctx = NULL;
208 return rc;
209 }
210
211 /* SR-IOV helper functions */
212
bnxt_re_get_sriov_func_type(struct bnxt_re_dev * rdev)213 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
214 {
215 if (BNXT_EN_VF(rdev->en_dev))
216 rdev->is_virtfn = 1;
217 }
218
219 /* Set the maximum number of each resource that the driver actually wants
220 * to allocate. This may be up to the maximum number the firmware has
221 * reserved for the function. The driver may choose to allocate fewer
222 * resources than the firmware maximum.
223 */
bnxt_re_limit_pf_res(struct bnxt_re_dev * rdev)224 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
225 {
226 struct bnxt_qplib_dev_attr *attr;
227 struct bnxt_qplib_ctx *ctx;
228 int i;
229
230 attr = rdev->dev_attr;
231 ctx = &rdev->qplib_ctx;
232
233 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
234 attr->max_qp);
235 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
236 /* Use max_mr from fw since max_mrw does not get set */
237 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
238 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
239 attr->max_srq);
240 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
241 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
242 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
243 rdev->qplib_ctx.tqm_ctx.qcount[i] =
244 rdev->dev_attr->tqm_alloc_reqs[i];
245 }
246
bnxt_re_limit_vf_res(struct bnxt_qplib_ctx * qplib_ctx,u32 num_vf)247 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
248 {
249 struct bnxt_qplib_vf_res *vf_res;
250 u32 mrws = 0;
251 u32 vf_pct;
252 u32 nvfs;
253
254 vf_res = &qplib_ctx->vf_res;
255 /*
256 * Reserve a set of resources for the PF. Divide the remaining
257 * resources among the VFs
258 */
259 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
260 nvfs = num_vf;
261 num_vf = 100 * num_vf;
262 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
263 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
264 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
265 /*
266 * The driver allows many more MRs than other resources. If the
267 * firmware does also, then reserve a fixed amount for the PF and
268 * divide the rest among VFs. VFs may use many MRs for NFS
269 * mounts, ISER, NVME applications, etc. If the firmware severely
270 * restricts the number of MRs, then let PF have half and divide
271 * the rest among VFs, as for the other resource types.
272 */
273 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
274 mrws = qplib_ctx->mrw_count * vf_pct;
275 nvfs = num_vf;
276 } else {
277 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
278 }
279 vf_res->max_mrw_per_vf = (mrws / nvfs);
280 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
281 }
282
bnxt_re_set_resource_limits(struct bnxt_re_dev * rdev)283 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
284 {
285 u32 num_vfs;
286
287 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
288 bnxt_re_limit_pf_res(rdev);
289
290 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
291 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
292 if (num_vfs)
293 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
294 }
295
bnxt_re_vf_res_config(struct bnxt_re_dev * rdev)296 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
297 {
298 /*
299 * Use the total VF count since the actual VF count may not be
300 * available at this point.
301 */
302 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
303 if (!rdev->num_vfs)
304 return;
305
306 bnxt_re_set_resource_limits(rdev);
307 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
308 &rdev->qplib_ctx);
309 }
310
311 struct bnxt_re_dcb_work {
312 struct work_struct work;
313 struct bnxt_re_dev *rdev;
314 struct hwrm_async_event_cmpl cmpl;
315 };
316
bnxt_re_is_qp1_qp(struct bnxt_re_qp * qp)317 static bool bnxt_re_is_qp1_qp(struct bnxt_re_qp *qp)
318 {
319 return qp->ib_qp.qp_type == IB_QPT_GSI;
320 }
321
bnxt_re_get_qp1_qp(struct bnxt_re_dev * rdev)322 static struct bnxt_re_qp *bnxt_re_get_qp1_qp(struct bnxt_re_dev *rdev)
323 {
324 struct bnxt_re_qp *qp;
325
326 mutex_lock(&rdev->qp_lock);
327 list_for_each_entry(qp, &rdev->qp_list, list) {
328 if (bnxt_re_is_qp1_qp(qp)) {
329 mutex_unlock(&rdev->qp_lock);
330 return qp;
331 }
332 }
333 mutex_unlock(&rdev->qp_lock);
334 return NULL;
335 }
336
bnxt_re_update_qp1_tos_dscp(struct bnxt_re_dev * rdev)337 static int bnxt_re_update_qp1_tos_dscp(struct bnxt_re_dev *rdev)
338 {
339 struct bnxt_re_qp *qp;
340
341 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
342 return 0;
343
344 qp = bnxt_re_get_qp1_qp(rdev);
345 if (!qp)
346 return 0;
347
348 qp->qplib_qp.modify_flags = CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP;
349 qp->qplib_qp.tos_dscp = rdev->cc_param.qp1_tos_dscp;
350
351 return bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
352 }
353
bnxt_re_init_dcb_wq(struct bnxt_re_dev * rdev)354 static void bnxt_re_init_dcb_wq(struct bnxt_re_dev *rdev)
355 {
356 rdev->dcb_wq = create_singlethread_workqueue("bnxt_re_dcb_wq");
357 }
358
bnxt_re_uninit_dcb_wq(struct bnxt_re_dev * rdev)359 static void bnxt_re_uninit_dcb_wq(struct bnxt_re_dev *rdev)
360 {
361 if (!rdev->dcb_wq)
362 return;
363 destroy_workqueue(rdev->dcb_wq);
364 }
365
bnxt_re_dcb_wq_task(struct work_struct * work)366 static void bnxt_re_dcb_wq_task(struct work_struct *work)
367 {
368 struct bnxt_re_dcb_work *dcb_work =
369 container_of(work, struct bnxt_re_dcb_work, work);
370 struct bnxt_re_dev *rdev = dcb_work->rdev;
371 struct bnxt_qplib_cc_param *cc_param;
372 int rc;
373
374 if (!rdev)
375 goto free_dcb;
376
377 cc_param = &rdev->cc_param;
378 rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, cc_param);
379 if (rc) {
380 ibdev_dbg(&rdev->ibdev, "Failed to query ccparam rc:%d", rc);
381 goto free_dcb;
382 }
383 if (cc_param->qp1_tos_dscp != cc_param->tos_dscp) {
384 cc_param->qp1_tos_dscp = cc_param->tos_dscp;
385 rc = bnxt_re_update_qp1_tos_dscp(rdev);
386 if (rc) {
387 ibdev_dbg(&rdev->ibdev, "%s: Failed to modify QP1 rc:%d",
388 __func__, rc);
389 goto free_dcb;
390 }
391 }
392
393 free_dcb:
394 kfree(dcb_work);
395 }
396
bnxt_re_async_notifier(void * handle,struct hwrm_async_event_cmpl * cmpl)397 static void bnxt_re_async_notifier(void *handle, struct hwrm_async_event_cmpl *cmpl)
398 {
399 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
400 struct bnxt_re_dcb_work *dcb_work;
401 struct bnxt_re_dev *rdev;
402 u32 data1, data2;
403 u16 event_id;
404
405 rdev = en_info->rdev;
406 if (!rdev)
407 return;
408
409 event_id = le16_to_cpu(cmpl->event_id);
410 data1 = le32_to_cpu(cmpl->event_data1);
411 data2 = le32_to_cpu(cmpl->event_data2);
412
413 ibdev_dbg(&rdev->ibdev, "Async event_id = %d data1 = %d data2 = %d",
414 event_id, data1, data2);
415
416 switch (event_id) {
417 case ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE:
418 dcb_work = kzalloc(sizeof(*dcb_work), GFP_ATOMIC);
419 if (!dcb_work)
420 break;
421
422 dcb_work->rdev = rdev;
423 memcpy(&dcb_work->cmpl, cmpl, sizeof(*cmpl));
424 INIT_WORK(&dcb_work->work, bnxt_re_dcb_wq_task);
425 queue_work(rdev->dcb_wq, &dcb_work->work);
426 break;
427 default:
428 break;
429 }
430 }
431
bnxt_re_stop_irq(void * handle,bool reset)432 static void bnxt_re_stop_irq(void *handle, bool reset)
433 {
434 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
435 struct bnxt_qplib_rcfw *rcfw;
436 struct bnxt_re_dev *rdev;
437 struct bnxt_qplib_nq *nq;
438 int indx;
439
440 rdev = en_info->rdev;
441 if (!rdev)
442 return;
443 rcfw = &rdev->rcfw;
444
445 if (reset) {
446 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
447 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
448 wake_up_all(&rdev->rcfw.cmdq.waitq);
449 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
450 IB_EVENT_DEVICE_FATAL);
451 }
452
453 for (indx = BNXT_RE_NQ_IDX; indx < rdev->nqr->num_msix; indx++) {
454 nq = &rdev->nqr->nq[indx - 1];
455 bnxt_qplib_nq_stop_irq(nq, false);
456 }
457
458 bnxt_qplib_rcfw_stop_irq(rcfw, false);
459 }
460
bnxt_re_start_irq(void * handle,struct bnxt_msix_entry * ent)461 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
462 {
463 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
464 struct bnxt_msix_entry *msix_ent;
465 struct bnxt_qplib_rcfw *rcfw;
466 struct bnxt_re_dev *rdev;
467 struct bnxt_qplib_nq *nq;
468 int indx, rc;
469
470 rdev = en_info->rdev;
471 if (!rdev)
472 return;
473 msix_ent = rdev->nqr->msix_entries;
474 rcfw = &rdev->rcfw;
475 if (!ent) {
476 /* Not setting the f/w timeout bit in rcfw.
477 * During the driver unload the first command
478 * to f/w will timeout and that will set the
479 * timeout bit.
480 */
481 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
482 return;
483 }
484
485 /* Vectors may change after restart, so update with new vectors
486 * in device sctructure.
487 */
488 for (indx = 0; indx < rdev->nqr->num_msix; indx++)
489 rdev->nqr->msix_entries[indx].vector = ent[indx].vector;
490
491 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
492 false);
493 if (rc) {
494 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
495 return;
496 }
497 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->nqr->num_msix; indx++) {
498 nq = &rdev->nqr->nq[indx - 1];
499 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
500 msix_ent[indx].vector, false);
501 if (rc) {
502 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
503 indx - 1);
504 return;
505 }
506 }
507 }
508
509 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
510 .ulp_async_notifier = bnxt_re_async_notifier,
511 .ulp_irq_stop = bnxt_re_stop_irq,
512 .ulp_irq_restart = bnxt_re_start_irq
513 };
514
515 /* RoCE -> Net driver */
516
bnxt_re_register_netdev(struct bnxt_re_dev * rdev)517 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
518 {
519 struct bnxt_en_dev *en_dev;
520
521 en_dev = rdev->en_dev;
522 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev);
523 }
524
bnxt_re_init_hwrm_hdr(struct input * hdr,u16 opcd)525 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
526 {
527 hdr->req_type = cpu_to_le16(opcd);
528 hdr->cmpl_ring = cpu_to_le16(-1);
529 hdr->target_id = cpu_to_le16(-1);
530 }
531
bnxt_re_fill_fw_msg(struct bnxt_fw_msg * fw_msg,void * msg,int msg_len,void * resp,int resp_max_len,int timeout)532 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
533 int msg_len, void *resp, int resp_max_len,
534 int timeout)
535 {
536 fw_msg->msg = msg;
537 fw_msg->msg_len = msg_len;
538 fw_msg->resp = resp;
539 fw_msg->resp_max_len = resp_max_len;
540 fw_msg->timeout = timeout;
541 }
542
543 /* Query device config using common hwrm */
bnxt_re_hwrm_qcfg(struct bnxt_re_dev * rdev,u32 * db_len,u32 * offset)544 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
545 u32 *offset)
546 {
547 struct bnxt_en_dev *en_dev = rdev->en_dev;
548 struct hwrm_func_qcfg_output resp = {0};
549 struct hwrm_func_qcfg_input req = {0};
550 struct bnxt_fw_msg fw_msg = {};
551 int rc;
552
553 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
554 req.fid = cpu_to_le16(0xffff);
555 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
556 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
557 rc = bnxt_send_msg(en_dev, &fw_msg);
558 if (!rc) {
559 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
560 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
561 }
562 return rc;
563 }
564
565 /* Query function capabilities using common hwrm */
bnxt_re_hwrm_qcaps(struct bnxt_re_dev * rdev)566 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
567 {
568 struct bnxt_en_dev *en_dev = rdev->en_dev;
569 struct hwrm_func_qcaps_output resp = {};
570 struct hwrm_func_qcaps_input req = {};
571 struct bnxt_qplib_chip_ctx *cctx;
572 struct bnxt_fw_msg fw_msg = {};
573 u32 flags_ext2;
574 int rc;
575
576 cctx = rdev->chip_ctx;
577 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
578 req.fid = cpu_to_le16(0xffff);
579 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
580 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
581
582 rc = bnxt_send_msg(en_dev, &fw_msg);
583 if (rc)
584 return rc;
585 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
586
587 flags_ext2 = le32_to_cpu(resp.flags_ext2);
588 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED ||
589 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED;
590 return 0;
591 }
592
bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev * rdev)593 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
594 {
595 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
596 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
597 struct hwrm_func_dbr_pacing_qcfg_input req = {};
598 struct bnxt_en_dev *en_dev = rdev->en_dev;
599 struct bnxt_qplib_chip_ctx *cctx;
600 struct bnxt_fw_msg fw_msg = {};
601 int rc;
602
603 cctx = rdev->chip_ctx;
604 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
605 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
606 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
607 rc = bnxt_send_msg(en_dev, &fw_msg);
608 if (rc)
609 return rc;
610
611 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
612 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
613 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
614 cctx->dbr_stat_db_fifo =
615 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
616 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
617
618 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth);
619 if (!pacing_data->fifo_max_depth)
620 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx);
621 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask);
622 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift;
623
624 return 0;
625 }
626
627 /* Update the pacing tunable parameters to the default values */
bnxt_re_set_default_pacing_data(struct bnxt_re_dev * rdev)628 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
629 {
630 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
631
632 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
633 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
634 pacing_data->alarm_th =
635 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
636 }
637
__get_fifo_occupancy(struct bnxt_re_dev * rdev)638 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev)
639 {
640 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
641 u32 read_val, fifo_occup;
642
643 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
644 fifo_occup = pacing_data->fifo_max_depth -
645 ((read_val & pacing_data->fifo_room_mask) >>
646 pacing_data->fifo_room_shift);
647 return fifo_occup;
648 }
649
is_dbr_fifo_full(struct bnxt_re_dev * rdev)650 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev)
651 {
652 u32 max_occup, fifo_occup;
653
654 fifo_occup = __get_fifo_occupancy(rdev);
655 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1;
656 if (fifo_occup == max_occup)
657 return true;
658
659 return false;
660 }
661
__wait_for_fifo_occupancy_below_th(struct bnxt_re_dev * rdev)662 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
663 {
664 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
665 u32 retry_fifo_check = 1000;
666 u32 fifo_occup;
667
668 /* loop shouldn't run infintely as the occupancy usually goes
669 * below pacing algo threshold as soon as pacing kicks in.
670 */
671 while (1) {
672 fifo_occup = __get_fifo_occupancy(rdev);
673 /* Fifo occupancy cannot be greater the MAX FIFO depth */
674 if (fifo_occup > pacing_data->fifo_max_depth)
675 break;
676
677 if (fifo_occup < pacing_data->pacing_th)
678 break;
679 if (!retry_fifo_check--) {
680 dev_info_once(rdev_to_dev(rdev),
681 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n",
682 __func__, fifo_occup, pacing_data->fifo_max_depth,
683 pacing_data->pacing_th);
684 break;
685 }
686
687 }
688 }
689
bnxt_re_db_fifo_check(struct work_struct * work)690 static void bnxt_re_db_fifo_check(struct work_struct *work)
691 {
692 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
693 dbq_fifo_check_work);
694 struct bnxt_qplib_db_pacing_data *pacing_data;
695 u32 pacing_save;
696
697 if (!mutex_trylock(&rdev->pacing.dbq_lock))
698 return;
699 pacing_data = rdev->qplib_res.pacing_data;
700 pacing_save = rdev->pacing.do_pacing_save;
701 __wait_for_fifo_occupancy_below_th(rdev);
702 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
703 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
704 /* Double the do_pacing value during the congestion */
705 pacing_save = pacing_save << 1;
706 } else {
707 /*
708 * when a new congestion is detected increase the do_pacing
709 * by 8 times. And also increase the pacing_th by 4 times. The
710 * reason to increase pacing_th is to give more space for the
711 * queue to oscillate down without getting empty, but also more
712 * room for the queue to increase without causing another alarm.
713 */
714 pacing_save = pacing_save << 3;
715 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
716 }
717
718 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
719 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
720
721 pacing_data->do_pacing = pacing_save;
722 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
723 pacing_data->alarm_th =
724 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
725 schedule_delayed_work(&rdev->dbq_pacing_work,
726 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
727 rdev->stats.pacing.alerts++;
728 mutex_unlock(&rdev->pacing.dbq_lock);
729 }
730
bnxt_re_pacing_timer_exp(struct work_struct * work)731 static void bnxt_re_pacing_timer_exp(struct work_struct *work)
732 {
733 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
734 dbq_pacing_work.work);
735 struct bnxt_qplib_db_pacing_data *pacing_data;
736 u32 fifo_occup;
737
738 if (!mutex_trylock(&rdev->pacing.dbq_lock))
739 return;
740
741 pacing_data = rdev->qplib_res.pacing_data;
742 fifo_occup = __get_fifo_occupancy(rdev);
743
744 if (fifo_occup > pacing_data->pacing_th)
745 goto restart_timer;
746
747 /*
748 * Instead of immediately going back to the default do_pacing
749 * reduce it by 1/8 times and restart the timer.
750 */
751 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
752 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
753 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
754 bnxt_re_set_default_pacing_data(rdev);
755 rdev->stats.pacing.complete++;
756 goto dbq_unlock;
757 }
758
759 restart_timer:
760 schedule_delayed_work(&rdev->dbq_pacing_work,
761 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
762 rdev->stats.pacing.resched++;
763 dbq_unlock:
764 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
765 mutex_unlock(&rdev->pacing.dbq_lock);
766 }
767
bnxt_re_pacing_alert(struct bnxt_re_dev * rdev)768 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
769 {
770 struct bnxt_qplib_db_pacing_data *pacing_data;
771
772 if (!rdev->pacing.dbr_pacing)
773 return;
774 mutex_lock(&rdev->pacing.dbq_lock);
775 pacing_data = rdev->qplib_res.pacing_data;
776
777 /*
778 * Increase the alarm_th to max so that other user lib instances do not
779 * keep alerting the driver.
780 */
781 pacing_data->alarm_th = pacing_data->fifo_max_depth;
782 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
783 cancel_work_sync(&rdev->dbq_fifo_check_work);
784 schedule_work(&rdev->dbq_fifo_check_work);
785 mutex_unlock(&rdev->pacing.dbq_lock);
786 }
787
bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev * rdev)788 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
789 {
790 /* Allocate a page for app use */
791 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
792 if (!rdev->pacing.dbr_page)
793 return -ENOMEM;
794
795 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
796 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
797
798 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) {
799 free_page((u64)rdev->pacing.dbr_page);
800 rdev->pacing.dbr_page = NULL;
801 return -EIO;
802 }
803
804 /* MAP HW window 2 for reading db fifo depth */
805 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
806 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
807 rdev->pacing.dbr_db_fifo_reg_off =
808 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
809 BNXT_RE_GRC_FIFO_REG_BASE;
810 rdev->pacing.dbr_bar_addr =
811 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
812
813 if (is_dbr_fifo_full(rdev)) {
814 free_page((u64)rdev->pacing.dbr_page);
815 rdev->pacing.dbr_page = NULL;
816 return -EIO;
817 }
818
819 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
820 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
821 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
822 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
823 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
824 bnxt_re_set_default_pacing_data(rdev);
825 /* Initialize worker for DBR Pacing */
826 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
827 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
828 return 0;
829 }
830
bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev * rdev)831 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
832 {
833 cancel_work_sync(&rdev->dbq_fifo_check_work);
834 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
835 if (rdev->pacing.dbr_page)
836 free_page((u64)rdev->pacing.dbr_page);
837
838 rdev->pacing.dbr_page = NULL;
839 rdev->pacing.dbr_pacing = false;
840 }
841
bnxt_re_net_ring_free(struct bnxt_re_dev * rdev,u16 fw_ring_id,int type)842 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
843 u16 fw_ring_id, int type)
844 {
845 struct bnxt_en_dev *en_dev;
846 struct hwrm_ring_free_input req = {};
847 struct hwrm_ring_free_output resp;
848 struct bnxt_fw_msg fw_msg = {};
849 int rc = -EINVAL;
850
851 if (!rdev)
852 return rc;
853
854 en_dev = rdev->en_dev;
855
856 if (!en_dev)
857 return rc;
858
859 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
860 return 0;
861
862 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
863 req.ring_type = type;
864 req.ring_id = cpu_to_le16(fw_ring_id);
865 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
866 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
867 rc = bnxt_send_msg(en_dev, &fw_msg);
868 if (rc)
869 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
870 req.ring_id, rc);
871 return rc;
872 }
873
bnxt_re_net_ring_alloc(struct bnxt_re_dev * rdev,struct bnxt_re_ring_attr * ring_attr,u16 * fw_ring_id)874 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
875 struct bnxt_re_ring_attr *ring_attr,
876 u16 *fw_ring_id)
877 {
878 struct bnxt_en_dev *en_dev = rdev->en_dev;
879 struct hwrm_ring_alloc_input req = {};
880 struct hwrm_ring_alloc_output resp;
881 struct bnxt_fw_msg fw_msg = {};
882 int rc = -EINVAL;
883
884 if (!en_dev)
885 return rc;
886
887 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
888 req.enables = 0;
889 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
890 if (ring_attr->pages > 1) {
891 /* Page size is in log2 units */
892 req.page_size = BNXT_PAGE_SHIFT;
893 req.page_tbl_depth = 1;
894 }
895 req.fbo = 0;
896 /* Association of ring index with doorbell index and MSIX number */
897 req.logical_id = cpu_to_le16(ring_attr->lrid);
898 req.length = cpu_to_le32(ring_attr->depth + 1);
899 req.ring_type = ring_attr->type;
900 req.int_mode = ring_attr->mode;
901 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
902 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
903 rc = bnxt_send_msg(en_dev, &fw_msg);
904 if (!rc)
905 *fw_ring_id = le16_to_cpu(resp.ring_id);
906
907 return rc;
908 }
909
bnxt_re_net_stats_ctx_free(struct bnxt_re_dev * rdev,u32 fw_stats_ctx_id)910 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
911 u32 fw_stats_ctx_id)
912 {
913 struct bnxt_en_dev *en_dev = rdev->en_dev;
914 struct hwrm_stat_ctx_free_input req = {};
915 struct hwrm_stat_ctx_free_output resp = {};
916 struct bnxt_fw_msg fw_msg = {};
917 int rc = -EINVAL;
918
919 if (!en_dev)
920 return rc;
921
922 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
923 return 0;
924
925 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
926 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
927 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
928 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
929 rc = bnxt_send_msg(en_dev, &fw_msg);
930 if (rc)
931 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
932 rc);
933
934 return rc;
935 }
936
bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev * rdev,dma_addr_t dma_map,u32 * fw_stats_ctx_id)937 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
938 dma_addr_t dma_map,
939 u32 *fw_stats_ctx_id)
940 {
941 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
942 struct hwrm_stat_ctx_alloc_output resp = {};
943 struct hwrm_stat_ctx_alloc_input req = {};
944 struct bnxt_en_dev *en_dev = rdev->en_dev;
945 struct bnxt_fw_msg fw_msg = {};
946 int rc = -EINVAL;
947
948 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
949
950 if (!en_dev)
951 return rc;
952
953 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
954 req.update_period_ms = cpu_to_le32(1000);
955 req.stats_dma_addr = cpu_to_le64(dma_map);
956 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
957 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
958 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
959 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
960 rc = bnxt_send_msg(en_dev, &fw_msg);
961 if (!rc)
962 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
963
964 return rc;
965 }
966
bnxt_re_disassociate_ucontext(struct ib_ucontext * ibcontext)967 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
968 {
969 }
970
971 /* Device */
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)972 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
973 char *buf)
974 {
975 struct bnxt_re_dev *rdev =
976 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
977
978 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
979 }
980 static DEVICE_ATTR_RO(hw_rev);
981
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)982 static ssize_t hca_type_show(struct device *device,
983 struct device_attribute *attr, char *buf)
984 {
985 struct bnxt_re_dev *rdev =
986 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
987
988 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
989 }
990 static DEVICE_ATTR_RO(hca_type);
991
992 static struct attribute *bnxt_re_attributes[] = {
993 &dev_attr_hw_rev.attr,
994 &dev_attr_hca_type.attr,
995 NULL
996 };
997
998 static const struct attribute_group bnxt_re_dev_attr_group = {
999 .attrs = bnxt_re_attributes,
1000 };
1001
bnxt_re_fill_res_mr_entry(struct sk_buff * msg,struct ib_mr * ib_mr)1002 static int bnxt_re_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr)
1003 {
1004 struct bnxt_qplib_hwq *mr_hwq;
1005 struct nlattr *table_attr;
1006 struct bnxt_re_mr *mr;
1007
1008 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1009 if (!table_attr)
1010 return -EMSGSIZE;
1011
1012 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
1013 mr_hwq = &mr->qplib_mr.hwq;
1014
1015 if (rdma_nl_put_driver_u32(msg, "page_size",
1016 mr_hwq->qe_ppg * mr_hwq->element_size))
1017 goto err;
1018 if (rdma_nl_put_driver_u32(msg, "max_elements", mr_hwq->max_elements))
1019 goto err;
1020 if (rdma_nl_put_driver_u32(msg, "element_size", mr_hwq->element_size))
1021 goto err;
1022 if (rdma_nl_put_driver_u64_hex(msg, "hwq", (unsigned long)mr_hwq))
1023 goto err;
1024 if (rdma_nl_put_driver_u64_hex(msg, "va", mr->qplib_mr.va))
1025 goto err;
1026
1027 nla_nest_end(msg, table_attr);
1028 return 0;
1029
1030 err:
1031 nla_nest_cancel(msg, table_attr);
1032 return -EMSGSIZE;
1033 }
1034
bnxt_re_fill_res_mr_entry_raw(struct sk_buff * msg,struct ib_mr * ib_mr)1035 static int bnxt_re_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr)
1036 {
1037 struct bnxt_re_dev *rdev;
1038 struct bnxt_re_mr *mr;
1039 int err, len;
1040 void *data;
1041
1042 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
1043 rdev = mr->rdev;
1044
1045 err = bnxt_re_read_context_allowed(rdev);
1046 if (err)
1047 return err;
1048
1049 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P7 :
1050 BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P5;
1051 data = kzalloc(len, GFP_KERNEL);
1052 if (!data)
1053 return -ENOMEM;
1054
1055 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_MRW,
1056 mr->qplib_mr.lkey, len, data);
1057 if (!err)
1058 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1059
1060 kfree(data);
1061 return err;
1062 }
1063
bnxt_re_fill_res_cq_entry(struct sk_buff * msg,struct ib_cq * ib_cq)1064 static int bnxt_re_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq)
1065 {
1066 struct bnxt_qplib_hwq *cq_hwq;
1067 struct nlattr *table_attr;
1068 struct bnxt_re_cq *cq;
1069
1070 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
1071 cq_hwq = &cq->qplib_cq.hwq;
1072
1073 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1074 if (!table_attr)
1075 return -EMSGSIZE;
1076
1077 if (rdma_nl_put_driver_u32(msg, "cq_depth", cq_hwq->depth))
1078 goto err;
1079 if (rdma_nl_put_driver_u32(msg, "max_elements", cq_hwq->max_elements))
1080 goto err;
1081 if (rdma_nl_put_driver_u32(msg, "element_size", cq_hwq->element_size))
1082 goto err;
1083 if (rdma_nl_put_driver_u32(msg, "max_wqe", cq->qplib_cq.max_wqe))
1084 goto err;
1085
1086 nla_nest_end(msg, table_attr);
1087 return 0;
1088
1089 err:
1090 nla_nest_cancel(msg, table_attr);
1091 return -EMSGSIZE;
1092 }
1093
bnxt_re_fill_res_cq_entry_raw(struct sk_buff * msg,struct ib_cq * ib_cq)1094 static int bnxt_re_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq)
1095 {
1096 struct bnxt_re_dev *rdev;
1097 struct bnxt_re_cq *cq;
1098 int err, len;
1099 void *data;
1100
1101 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
1102 rdev = cq->rdev;
1103
1104 err = bnxt_re_read_context_allowed(rdev);
1105 if (err)
1106 return err;
1107
1108 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P7 :
1109 BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P5;
1110 data = kzalloc(len, GFP_KERNEL);
1111 if (!data)
1112 return -ENOMEM;
1113
1114 err = bnxt_qplib_read_context(&rdev->rcfw,
1115 CMDQ_READ_CONTEXT_TYPE_CQ,
1116 cq->qplib_cq.id, len, data);
1117 if (!err)
1118 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1119
1120 kfree(data);
1121 return err;
1122 }
1123
bnxt_re_fill_res_qp_entry(struct sk_buff * msg,struct ib_qp * ib_qp)1124 static int bnxt_re_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp)
1125 {
1126 struct bnxt_qplib_qp *qplib_qp;
1127 struct nlattr *table_attr;
1128 struct bnxt_re_qp *qp;
1129
1130 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1131 if (!table_attr)
1132 return -EMSGSIZE;
1133
1134 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1135 qplib_qp = &qp->qplib_qp;
1136
1137 if (rdma_nl_put_driver_u32(msg, "sq_max_wqe", qplib_qp->sq.max_wqe))
1138 goto err;
1139 if (rdma_nl_put_driver_u32(msg, "sq_max_sge", qplib_qp->sq.max_sge))
1140 goto err;
1141 if (rdma_nl_put_driver_u32(msg, "sq_wqe_size", qplib_qp->sq.wqe_size))
1142 goto err;
1143 if (rdma_nl_put_driver_u32(msg, "sq_swq_start", qplib_qp->sq.swq_start))
1144 goto err;
1145 if (rdma_nl_put_driver_u32(msg, "sq_swq_last", qplib_qp->sq.swq_last))
1146 goto err;
1147 if (rdma_nl_put_driver_u32(msg, "rq_max_wqe", qplib_qp->rq.max_wqe))
1148 goto err;
1149 if (rdma_nl_put_driver_u32(msg, "rq_max_sge", qplib_qp->rq.max_sge))
1150 goto err;
1151 if (rdma_nl_put_driver_u32(msg, "rq_wqe_size", qplib_qp->rq.wqe_size))
1152 goto err;
1153 if (rdma_nl_put_driver_u32(msg, "rq_swq_start", qplib_qp->rq.swq_start))
1154 goto err;
1155 if (rdma_nl_put_driver_u32(msg, "rq_swq_last", qplib_qp->rq.swq_last))
1156 goto err;
1157 if (rdma_nl_put_driver_u32(msg, "timeout", qplib_qp->timeout))
1158 goto err;
1159
1160 nla_nest_end(msg, table_attr);
1161 return 0;
1162
1163 err:
1164 nla_nest_cancel(msg, table_attr);
1165 return -EMSGSIZE;
1166 }
1167
bnxt_re_fill_res_qp_entry_raw(struct sk_buff * msg,struct ib_qp * ibqp)1168 static int bnxt_re_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ibqp)
1169 {
1170 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibqp->device, ibdev);
1171 int err, len;
1172 void *data;
1173
1174 err = bnxt_re_read_context_allowed(rdev);
1175 if (err)
1176 return err;
1177
1178 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P7 :
1179 BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P5;
1180 data = kzalloc(len, GFP_KERNEL);
1181 if (!data)
1182 return -ENOMEM;
1183
1184 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_QPC,
1185 ibqp->qp_num, len, data);
1186 if (!err)
1187 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1188
1189 kfree(data);
1190 return err;
1191 }
1192
bnxt_re_fill_res_srq_entry(struct sk_buff * msg,struct ib_srq * ib_srq)1193 static int bnxt_re_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq)
1194 {
1195 struct nlattr *table_attr;
1196 struct bnxt_re_srq *srq;
1197
1198 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1199 if (!table_attr)
1200 return -EMSGSIZE;
1201
1202 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1203
1204 if (rdma_nl_put_driver_u32_hex(msg, "wqe_size", srq->qplib_srq.wqe_size))
1205 goto err;
1206 if (rdma_nl_put_driver_u32_hex(msg, "max_wqe", srq->qplib_srq.max_wqe))
1207 goto err;
1208 if (rdma_nl_put_driver_u32_hex(msg, "max_sge", srq->qplib_srq.max_sge))
1209 goto err;
1210
1211 nla_nest_end(msg, table_attr);
1212 return 0;
1213
1214 err:
1215 nla_nest_cancel(msg, table_attr);
1216 return -EMSGSIZE;
1217 }
1218
bnxt_re_fill_res_srq_entry_raw(struct sk_buff * msg,struct ib_srq * ib_srq)1219 static int bnxt_re_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq)
1220 {
1221 struct bnxt_re_dev *rdev;
1222 struct bnxt_re_srq *srq;
1223 int err, len;
1224 void *data;
1225
1226 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1227 rdev = srq->rdev;
1228
1229 err = bnxt_re_read_context_allowed(rdev);
1230 if (err)
1231 return err;
1232
1233 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P7 :
1234 BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P5;
1235
1236 data = kzalloc(len, GFP_KERNEL);
1237 if (!data)
1238 return -ENOMEM;
1239
1240 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_SRQ,
1241 srq->qplib_srq.id, len, data);
1242 if (!err)
1243 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1244
1245 kfree(data);
1246 return err;
1247 }
1248
1249 static const struct ib_device_ops bnxt_re_dev_ops = {
1250 .owner = THIS_MODULE,
1251 .driver_id = RDMA_DRIVER_BNXT_RE,
1252 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
1253
1254 .add_gid = bnxt_re_add_gid,
1255 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
1256 .alloc_mr = bnxt_re_alloc_mr,
1257 .alloc_pd = bnxt_re_alloc_pd,
1258 .alloc_ucontext = bnxt_re_alloc_ucontext,
1259 .create_ah = bnxt_re_create_ah,
1260 .create_cq = bnxt_re_create_cq,
1261 .create_qp = bnxt_re_create_qp,
1262 .create_srq = bnxt_re_create_srq,
1263 .create_user_ah = bnxt_re_create_ah,
1264 .dealloc_pd = bnxt_re_dealloc_pd,
1265 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
1266 .del_gid = bnxt_re_del_gid,
1267 .dereg_mr = bnxt_re_dereg_mr,
1268 .destroy_ah = bnxt_re_destroy_ah,
1269 .destroy_cq = bnxt_re_destroy_cq,
1270 .destroy_qp = bnxt_re_destroy_qp,
1271 .destroy_srq = bnxt_re_destroy_srq,
1272 .device_group = &bnxt_re_dev_attr_group,
1273 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
1274 .get_dev_fw_str = bnxt_re_query_fw_str,
1275 .get_dma_mr = bnxt_re_get_dma_mr,
1276 .get_hw_stats = bnxt_re_ib_get_hw_stats,
1277 .get_link_layer = bnxt_re_get_link_layer,
1278 .get_port_immutable = bnxt_re_get_port_immutable,
1279 .map_mr_sg = bnxt_re_map_mr_sg,
1280 .mmap = bnxt_re_mmap,
1281 .mmap_free = bnxt_re_mmap_free,
1282 .modify_qp = bnxt_re_modify_qp,
1283 .modify_srq = bnxt_re_modify_srq,
1284 .poll_cq = bnxt_re_poll_cq,
1285 .post_recv = bnxt_re_post_recv,
1286 .post_send = bnxt_re_post_send,
1287 .post_srq_recv = bnxt_re_post_srq_recv,
1288 .process_mad = bnxt_re_process_mad,
1289 .query_ah = bnxt_re_query_ah,
1290 .query_device = bnxt_re_query_device,
1291 .modify_device = bnxt_re_modify_device,
1292 .query_pkey = bnxt_re_query_pkey,
1293 .query_port = bnxt_re_query_port,
1294 .query_qp = bnxt_re_query_qp,
1295 .query_srq = bnxt_re_query_srq,
1296 .reg_user_mr = bnxt_re_reg_user_mr,
1297 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
1298 .req_notify_cq = bnxt_re_req_notify_cq,
1299 .resize_cq = bnxt_re_resize_cq,
1300 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
1301 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
1302 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
1303 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
1304 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
1305 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
1306 };
1307
1308 static const struct ib_device_ops restrack_ops = {
1309 .fill_res_cq_entry = bnxt_re_fill_res_cq_entry,
1310 .fill_res_cq_entry_raw = bnxt_re_fill_res_cq_entry_raw,
1311 .fill_res_qp_entry = bnxt_re_fill_res_qp_entry,
1312 .fill_res_qp_entry_raw = bnxt_re_fill_res_qp_entry_raw,
1313 .fill_res_mr_entry = bnxt_re_fill_res_mr_entry,
1314 .fill_res_mr_entry_raw = bnxt_re_fill_res_mr_entry_raw,
1315 .fill_res_srq_entry = bnxt_re_fill_res_srq_entry,
1316 .fill_res_srq_entry_raw = bnxt_re_fill_res_srq_entry_raw,
1317 };
1318
bnxt_re_register_ib(struct bnxt_re_dev * rdev)1319 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
1320 {
1321 struct ib_device *ibdev = &rdev->ibdev;
1322 int ret;
1323
1324 /* ib device init */
1325 ibdev->node_type = RDMA_NODE_IB_CA;
1326 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
1327 strlen(BNXT_RE_DESC) + 5);
1328 ibdev->phys_port_cnt = 1;
1329
1330 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
1331
1332 ibdev->num_comp_vectors = rdev->nqr->num_msix - 1;
1333 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
1334 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
1335
1336 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
1337 ibdev->driver_def = bnxt_re_uapi_defs;
1338
1339 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
1340 ib_set_device_ops(ibdev, &restrack_ops);
1341 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
1342 if (ret)
1343 return ret;
1344
1345 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
1346 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
1347 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
1348 }
1349
bnxt_re_dev_add(struct auxiliary_device * adev,struct bnxt_en_dev * en_dev)1350 static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev,
1351 struct bnxt_en_dev *en_dev)
1352 {
1353 struct bnxt_re_dev *rdev;
1354
1355 /* Allocate bnxt_re_dev instance here */
1356 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
1357 if (!rdev) {
1358 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
1359 ROCE_DRV_MODULE_NAME);
1360 return NULL;
1361 }
1362 /* Default values */
1363 rdev->netdev = en_dev->net;
1364 rdev->en_dev = en_dev;
1365 rdev->adev = adev;
1366 rdev->id = rdev->en_dev->pdev->devfn;
1367 INIT_LIST_HEAD(&rdev->qp_list);
1368 mutex_init(&rdev->qp_lock);
1369 mutex_init(&rdev->pacing.dbq_lock);
1370 atomic_set(&rdev->stats.res.qp_count, 0);
1371 atomic_set(&rdev->stats.res.cq_count, 0);
1372 atomic_set(&rdev->stats.res.srq_count, 0);
1373 atomic_set(&rdev->stats.res.mr_count, 0);
1374 atomic_set(&rdev->stats.res.mw_count, 0);
1375 atomic_set(&rdev->stats.res.ah_count, 0);
1376 atomic_set(&rdev->stats.res.pd_count, 0);
1377 rdev->cosq[0] = 0xFFFF;
1378 rdev->cosq[1] = 0xFFFF;
1379 rdev->cq_coalescing.buf_maxtime = BNXT_QPLIB_CQ_COAL_DEF_BUF_MAXTIME;
1380 if (bnxt_re_chip_gen_p7(en_dev->chip_num)) {
1381 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P7;
1382 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P7;
1383 } else {
1384 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P5;
1385 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P5;
1386 }
1387 rdev->cq_coalescing.en_ring_idle_mode = BNXT_QPLIB_CQ_COAL_DEF_EN_RING_IDLE_MODE;
1388
1389 return rdev;
1390 }
1391
bnxt_re_handle_unaffi_async_event(struct creq_func_event * unaffi_async)1392 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
1393 *unaffi_async)
1394 {
1395 switch (unaffi_async->event) {
1396 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
1397 break;
1398 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
1399 break;
1400 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
1401 break;
1402 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
1403 break;
1404 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
1405 break;
1406 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
1407 break;
1408 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
1409 break;
1410 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
1411 break;
1412 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
1413 break;
1414 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
1415 break;
1416 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
1417 break;
1418 default:
1419 return -EINVAL;
1420 }
1421 return 0;
1422 }
1423
bnxt_re_handle_qp_async_event(struct creq_qp_event * qp_event,struct bnxt_re_qp * qp)1424 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
1425 struct bnxt_re_qp *qp)
1426 {
1427 struct creq_qp_error_notification *err_event;
1428 struct bnxt_re_srq *srq = NULL;
1429 struct ib_event event = {};
1430 unsigned int flags;
1431
1432 if (qp->qplib_qp.srq)
1433 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq,
1434 qplib_srq);
1435
1436 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
1437 rdma_is_kernel_res(&qp->ib_qp.res)) {
1438 flags = bnxt_re_lock_cqs(qp);
1439 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1440 bnxt_re_unlock_cqs(qp, flags);
1441 }
1442
1443 event.device = &qp->rdev->ibdev;
1444 event.element.qp = &qp->ib_qp;
1445 event.event = IB_EVENT_QP_FATAL;
1446
1447 err_event = (struct creq_qp_error_notification *)qp_event;
1448
1449 switch (err_event->req_err_state_reason) {
1450 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR:
1451 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT:
1452 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT:
1453 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2:
1454 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3:
1455 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP:
1456 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND:
1457 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG:
1458 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE:
1459 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR:
1460 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR:
1461 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR:
1462 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR:
1463 event.event = IB_EVENT_QP_ACCESS_ERR;
1464 break;
1465 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1:
1466 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4:
1467 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH:
1468 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR:
1469 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR:
1470 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR:
1471 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR:
1472 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR:
1473 event.event = IB_EVENT_QP_REQ_ERR;
1474 break;
1475 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR:
1476 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR:
1477 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR:
1478 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR:
1479 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR:
1480 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR:
1481 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR:
1482 event.event = IB_EVENT_QP_FATAL;
1483 break;
1484
1485 default:
1486 break;
1487 }
1488
1489 switch (err_event->res_err_state_reason) {
1490 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX:
1491 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH:
1492 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT:
1493 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY:
1494 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR:
1495 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION:
1496 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR:
1497 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY:
1498 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR:
1499 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION:
1500 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR:
1501 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC:
1502 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND:
1503 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY:
1504 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR:
1505 event.event = IB_EVENT_QP_ACCESS_ERR;
1506 break;
1507 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE:
1508 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR:
1509 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE:
1510 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE:
1511 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR:
1512 event.event = IB_EVENT_QP_REQ_ERR;
1513 break;
1514 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW:
1515 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR:
1516 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR:
1517 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR:
1518 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR:
1519 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR:
1520 event.event = IB_EVENT_QP_FATAL;
1521 break;
1522 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR:
1523 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR:
1524 if (srq)
1525 event.event = IB_EVENT_SRQ_ERR;
1526 break;
1527 default:
1528 break;
1529 }
1530
1531 if (err_event->res_err_state_reason || err_event->req_err_state_reason) {
1532 ibdev_dbg(&qp->rdev->ibdev,
1533 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n",
1534 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user",
1535 qp->qplib_qp.id,
1536 err_event->sq_cons_idx,
1537 err_event->rq_cons_idx,
1538 err_event->req_slow_path_state,
1539 err_event->req_err_state_reason,
1540 err_event->res_slow_path_state,
1541 err_event->res_err_state_reason);
1542 } else {
1543 if (srq)
1544 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
1545 }
1546
1547 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) {
1548 (*srq->ib_srq.event_handler)(&event,
1549 srq->ib_srq.srq_context);
1550 } else if (event.device && qp->ib_qp.event_handler) {
1551 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
1552 }
1553
1554 return 0;
1555 }
1556
bnxt_re_handle_cq_async_error(void * event,struct bnxt_re_cq * cq)1557 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq)
1558 {
1559 struct creq_cq_error_notification *cqerr;
1560 struct ib_event ibevent = {};
1561
1562 cqerr = event;
1563 switch (cqerr->cq_err_reason) {
1564 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR:
1565 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR:
1566 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR:
1567 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR:
1568 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR:
1569 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR:
1570 ibevent.event = IB_EVENT_CQ_ERR;
1571 break;
1572 default:
1573 break;
1574 }
1575
1576 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) {
1577 ibevent.element.cq = &cq->ib_cq;
1578 ibevent.device = &cq->rdev->ibdev;
1579
1580 ibdev_dbg(&cq->rdev->ibdev,
1581 "%s err reason %d\n", __func__, cqerr->cq_err_reason);
1582 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context);
1583 }
1584
1585 return 0;
1586 }
1587
bnxt_re_handle_affi_async_event(struct creq_qp_event * affi_async,void * obj)1588 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1589 void *obj)
1590 {
1591 struct bnxt_qplib_qp *lib_qp;
1592 struct bnxt_qplib_cq *lib_cq;
1593 struct bnxt_re_qp *qp;
1594 struct bnxt_re_cq *cq;
1595 int rc = 0;
1596 u8 event;
1597
1598 if (!obj)
1599 return rc; /* QP was already dead, still return success */
1600
1601 event = affi_async->event;
1602 switch (event) {
1603 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
1604 lib_qp = obj;
1605 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp);
1606 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1607 break;
1608 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION:
1609 lib_cq = obj;
1610 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq);
1611 rc = bnxt_re_handle_cq_async_error(affi_async, cq);
1612 break;
1613 default:
1614 rc = -EINVAL;
1615 }
1616 return rc;
1617 }
1618
bnxt_re_aeq_handler(struct bnxt_qplib_rcfw * rcfw,void * aeqe,void * obj)1619 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1620 void *aeqe, void *obj)
1621 {
1622 struct creq_qp_event *affi_async;
1623 struct creq_func_event *unaffi_async;
1624 u8 type;
1625 int rc;
1626
1627 type = ((struct creq_base *)aeqe)->type;
1628 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1629 unaffi_async = aeqe;
1630 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1631 } else {
1632 affi_async = aeqe;
1633 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1634 }
1635
1636 return rc;
1637 }
1638
bnxt_re_srqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_srq * handle,u8 event)1639 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1640 struct bnxt_qplib_srq *handle, u8 event)
1641 {
1642 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1643 qplib_srq);
1644 struct ib_event ib_event;
1645
1646 ib_event.device = &srq->rdev->ibdev;
1647 ib_event.element.srq = &srq->ib_srq;
1648
1649 if (srq->ib_srq.event_handler) {
1650 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1651 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1652 (*srq->ib_srq.event_handler)(&ib_event,
1653 srq->ib_srq.srq_context);
1654 }
1655 return 0;
1656 }
1657
bnxt_re_cqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_cq * handle)1658 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1659 struct bnxt_qplib_cq *handle)
1660 {
1661 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1662 qplib_cq);
1663
1664 if (cq->ib_cq.comp_handler)
1665 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1666
1667 return 0;
1668 }
1669
bnxt_re_cleanup_res(struct bnxt_re_dev * rdev)1670 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1671 {
1672 int i;
1673
1674 for (i = 1; i < rdev->nqr->num_msix; i++)
1675 bnxt_qplib_disable_nq(&rdev->nqr->nq[i - 1]);
1676
1677 if (rdev->qplib_res.rcfw)
1678 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1679 }
1680
bnxt_re_init_res(struct bnxt_re_dev * rdev)1681 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1682 {
1683 int num_vec_enabled = 0;
1684 int rc = 0, i;
1685 u32 db_offt;
1686
1687 bnxt_qplib_init_res(&rdev->qplib_res);
1688
1689 mutex_init(&rdev->nqr->load_lock);
1690
1691 for (i = 1; i < rdev->nqr->num_msix ; i++) {
1692 db_offt = rdev->nqr->msix_entries[i].db_offset;
1693 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nqr->nq[i - 1],
1694 i - 1, rdev->nqr->msix_entries[i].vector,
1695 db_offt, &bnxt_re_cqn_handler,
1696 &bnxt_re_srqn_handler);
1697 if (rc) {
1698 ibdev_err(&rdev->ibdev,
1699 "Failed to enable NQ with rc = 0x%x", rc);
1700 goto fail;
1701 }
1702 num_vec_enabled++;
1703 }
1704 return 0;
1705 fail:
1706 for (i = num_vec_enabled; i >= 0; i--)
1707 bnxt_qplib_disable_nq(&rdev->nqr->nq[i]);
1708 return rc;
1709 }
1710
bnxt_re_free_nq_res(struct bnxt_re_dev * rdev)1711 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1712 {
1713 struct bnxt_qplib_nq *nq;
1714 u8 type;
1715 int i;
1716
1717 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1718 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1719 nq = &rdev->nqr->nq[i];
1720 bnxt_re_net_ring_free(rdev, nq->ring_id, type);
1721 bnxt_qplib_free_nq(nq);
1722 nq->res = NULL;
1723 }
1724 }
1725
bnxt_re_free_res(struct bnxt_re_dev * rdev)1726 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1727 {
1728 bnxt_re_free_nq_res(rdev);
1729
1730 if (rdev->qplib_res.dpi_tbl.max) {
1731 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1732 &rdev->dpi_privileged);
1733 }
1734 if (rdev->qplib_res.rcfw) {
1735 bnxt_qplib_free_res(&rdev->qplib_res);
1736 rdev->qplib_res.rcfw = NULL;
1737 }
1738 }
1739
bnxt_re_alloc_res(struct bnxt_re_dev * rdev)1740 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1741 {
1742 struct bnxt_re_ring_attr rattr = {};
1743 int num_vec_created = 0;
1744 int rc, i;
1745 u8 type;
1746
1747 /* Configure and allocate resources for qplib */
1748 rdev->qplib_res.rcfw = &rdev->rcfw;
1749 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
1750 if (rc)
1751 goto fail;
1752
1753 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->netdev);
1754 if (rc)
1755 goto fail;
1756
1757 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1758 &rdev->dpi_privileged,
1759 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1760 if (rc)
1761 goto dealloc_res;
1762
1763 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1764 struct bnxt_qplib_nq *nq;
1765
1766 nq = &rdev->nqr->nq[i];
1767 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1768 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, nq);
1769 if (rc) {
1770 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1771 i, rc);
1772 goto free_nq;
1773 }
1774 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1775 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1776 rattr.pages = nq->hwq.pbl[rdev->nqr->nq[i].hwq.level].pg_count;
1777 rattr.type = type;
1778 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1779 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1780 rattr.lrid = rdev->nqr->msix_entries[i + 1].ring_idx;
1781 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1782 if (rc) {
1783 ibdev_err(&rdev->ibdev,
1784 "Failed to allocate NQ fw id with rc = 0x%x",
1785 rc);
1786 bnxt_qplib_free_nq(nq);
1787 goto free_nq;
1788 }
1789 num_vec_created++;
1790 }
1791 return 0;
1792 free_nq:
1793 for (i = num_vec_created - 1; i >= 0; i--) {
1794 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1795 bnxt_re_net_ring_free(rdev, rdev->nqr->nq[i].ring_id, type);
1796 bnxt_qplib_free_nq(&rdev->nqr->nq[i]);
1797 }
1798 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1799 &rdev->dpi_privileged);
1800 dealloc_res:
1801 bnxt_qplib_free_res(&rdev->qplib_res);
1802
1803 fail:
1804 rdev->qplib_res.rcfw = NULL;
1805 return rc;
1806 }
1807
bnxt_re_dispatch_event(struct ib_device * ibdev,struct ib_qp * qp,u8 port_num,enum ib_event_type event)1808 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1809 u8 port_num, enum ib_event_type event)
1810 {
1811 struct ib_event ib_event;
1812
1813 ib_event.device = ibdev;
1814 if (qp) {
1815 ib_event.element.qp = qp;
1816 ib_event.event = event;
1817 if (qp->event_handler)
1818 qp->event_handler(&ib_event, qp->qp_context);
1819
1820 } else {
1821 ib_event.element.port_num = port_num;
1822 ib_event.event = event;
1823 ib_dispatch_event(&ib_event);
1824 }
1825 }
1826
bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)1827 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1828 struct bnxt_re_qp *qp)
1829 {
1830 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1831 (qp == rdev->gsi_ctx.gsi_sqp);
1832 }
1833
bnxt_re_dev_stop(struct bnxt_re_dev * rdev)1834 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1835 {
1836 struct bnxt_re_qp *qp;
1837
1838 mutex_lock(&rdev->qp_lock);
1839 list_for_each_entry(qp, &rdev->qp_list, list) {
1840 /* Modify the state of all QPs except QP1/Shadow QP */
1841 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1842 if (qp->qplib_qp.state !=
1843 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1844 qp->qplib_qp.state !=
1845 CMDQ_MODIFY_QP_NEW_STATE_ERR)
1846 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1847 1, IB_EVENT_QP_FATAL);
1848 }
1849 }
1850 mutex_unlock(&rdev->qp_lock);
1851 }
1852
bnxt_re_update_gid(struct bnxt_re_dev * rdev)1853 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1854 {
1855 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1856 struct bnxt_qplib_gid gid;
1857 u16 gid_idx, index;
1858 int rc = 0;
1859
1860 if (!ib_device_try_get(&rdev->ibdev))
1861 return 0;
1862
1863 for (index = 0; index < sgid_tbl->active; index++) {
1864 gid_idx = sgid_tbl->hw_id[index];
1865
1866 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1867 sizeof(bnxt_qplib_gid_zero)))
1868 continue;
1869 /* need to modify the VLAN enable setting of non VLAN GID only
1870 * as setting is done for VLAN GID while adding GID
1871 */
1872 if (sgid_tbl->vlan[index])
1873 continue;
1874
1875 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1876
1877 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1878 rdev->qplib_res.netdev->dev_addr);
1879 }
1880
1881 ib_device_put(&rdev->ibdev);
1882 return rc;
1883 }
1884
bnxt_re_get_priority_mask(struct bnxt_re_dev * rdev)1885 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1886 {
1887 u32 prio_map = 0, tmp_map = 0;
1888 struct net_device *netdev;
1889 struct dcb_app app = {};
1890
1891 netdev = rdev->netdev;
1892
1893 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1894 app.protocol = ETH_P_IBOE;
1895 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1896 prio_map = tmp_map;
1897
1898 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1899 app.protocol = ROCE_V2_UDP_DPORT;
1900 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1901 prio_map |= tmp_map;
1902
1903 return prio_map;
1904 }
1905
bnxt_re_setup_qos(struct bnxt_re_dev * rdev)1906 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1907 {
1908 u8 prio_map = 0;
1909
1910 /* Get priority for roce */
1911 prio_map = bnxt_re_get_priority_mask(rdev);
1912
1913 if (prio_map == rdev->cur_prio_map)
1914 return 0;
1915 rdev->cur_prio_map = prio_map;
1916 /* Actual priorities are not programmed as they are already
1917 * done by L2 driver; just enable or disable priority vlan tagging
1918 */
1919 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1920 (prio_map != 0 && !rdev->qplib_res.prio)) {
1921 rdev->qplib_res.prio = prio_map;
1922 bnxt_re_update_gid(rdev);
1923 }
1924
1925 return 0;
1926 }
1927
bnxt_re_net_unregister_async_event(struct bnxt_re_dev * rdev)1928 static void bnxt_re_net_unregister_async_event(struct bnxt_re_dev *rdev)
1929 {
1930 if (rdev->is_virtfn)
1931 return;
1932
1933 memset(&rdev->event_bitmap, 0, sizeof(rdev->event_bitmap));
1934 bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap,
1935 ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE);
1936 }
1937
bnxt_re_net_register_async_event(struct bnxt_re_dev * rdev)1938 static void bnxt_re_net_register_async_event(struct bnxt_re_dev *rdev)
1939 {
1940 if (rdev->is_virtfn)
1941 return;
1942
1943 rdev->event_bitmap |= (1 << ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE);
1944 bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap,
1945 ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE);
1946 }
1947
bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev * rdev)1948 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1949 {
1950 struct bnxt_en_dev *en_dev = rdev->en_dev;
1951 struct hwrm_ver_get_output resp = {};
1952 struct hwrm_ver_get_input req = {};
1953 struct bnxt_qplib_chip_ctx *cctx;
1954 struct bnxt_fw_msg fw_msg = {};
1955 int rc;
1956
1957 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1958 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1959 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1960 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1961 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1962 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1963 rc = bnxt_send_msg(en_dev, &fw_msg);
1964 if (rc) {
1965 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1966 rc);
1967 return;
1968 }
1969
1970 cctx = rdev->chip_ctx;
1971 cctx->hwrm_intf_ver =
1972 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1973 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1974 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1975 le16_to_cpu(resp.hwrm_intf_patch);
1976
1977 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
1978
1979 if (!cctx->hwrm_cmd_max_timeout)
1980 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
1981 }
1982
bnxt_re_ib_init(struct bnxt_re_dev * rdev)1983 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1984 {
1985 int rc;
1986 u32 event;
1987
1988 /* Register ib dev */
1989 rc = bnxt_re_register_ib(rdev);
1990 if (rc) {
1991 pr_err("Failed to register with IB: %#x\n", rc);
1992 return rc;
1993 }
1994 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1995 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1996
1997 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1998 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1999
2000 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
2001
2002 return rc;
2003 }
2004
bnxt_re_alloc_nqr_mem(struct bnxt_re_dev * rdev)2005 static int bnxt_re_alloc_nqr_mem(struct bnxt_re_dev *rdev)
2006 {
2007 rdev->nqr = kzalloc(sizeof(*rdev->nqr), GFP_KERNEL);
2008 if (!rdev->nqr)
2009 return -ENOMEM;
2010
2011 return 0;
2012 }
2013
bnxt_re_free_nqr_mem(struct bnxt_re_dev * rdev)2014 static void bnxt_re_free_nqr_mem(struct bnxt_re_dev *rdev)
2015 {
2016 kfree(rdev->nqr);
2017 rdev->nqr = NULL;
2018 }
2019
bnxt_re_dev_uninit(struct bnxt_re_dev * rdev,u8 op_type)2020 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type)
2021 {
2022 u8 type;
2023 int rc;
2024
2025 bnxt_re_debugfs_rem_pdev(rdev);
2026
2027 bnxt_re_net_unregister_async_event(rdev);
2028 bnxt_re_uninit_dcb_wq(rdev);
2029
2030 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
2031 cancel_delayed_work_sync(&rdev->worker);
2032
2033 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
2034 &rdev->flags))
2035 bnxt_re_cleanup_res(rdev);
2036 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
2037 bnxt_re_free_res(rdev);
2038
2039 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
2040 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
2041 if (rc)
2042 ibdev_warn(&rdev->ibdev,
2043 "Failed to deinitialize RCFW: %#x", rc);
2044 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
2045 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
2046 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
2047 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2048 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
2049 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
2050 }
2051
2052 rdev->nqr->num_msix = 0;
2053
2054 if (rdev->pacing.dbr_pacing)
2055 bnxt_re_deinitialize_dbr_pacing(rdev);
2056
2057 bnxt_re_free_nqr_mem(rdev);
2058 bnxt_re_destroy_chip_ctx(rdev);
2059 if (op_type == BNXT_RE_COMPLETE_REMOVE) {
2060 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
2061 bnxt_unregister_dev(rdev->en_dev);
2062 }
2063 }
2064
2065 /* worker thread for polling periodic events. Now used for QoS programming*/
bnxt_re_worker(struct work_struct * work)2066 static void bnxt_re_worker(struct work_struct *work)
2067 {
2068 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
2069 worker.work);
2070
2071 bnxt_re_setup_qos(rdev);
2072 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
2073 }
2074
bnxt_re_dev_init(struct bnxt_re_dev * rdev,u8 op_type)2075 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type)
2076 {
2077 struct bnxt_re_ring_attr rattr = {};
2078 struct bnxt_qplib_creq_ctx *creq;
2079 u32 db_offt;
2080 int vid;
2081 u8 type;
2082 int rc;
2083
2084 if (op_type == BNXT_RE_COMPLETE_INIT) {
2085 /* Registered a new RoCE device instance to netdev */
2086 rc = bnxt_re_register_netdev(rdev);
2087 if (rc) {
2088 ibdev_err(&rdev->ibdev,
2089 "Failed to register with netedev: %#x\n", rc);
2090 return -EINVAL;
2091 }
2092 }
2093 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2094
2095 if (rdev->en_dev->ulp_tbl->msix_requested < BNXT_RE_MIN_MSIX) {
2096 ibdev_err(&rdev->ibdev,
2097 "RoCE requires minimum 2 MSI-X vectors, but only %d reserved\n",
2098 rdev->en_dev->ulp_tbl->msix_requested);
2099 bnxt_unregister_dev(rdev->en_dev);
2100 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2101 return -EINVAL;
2102 }
2103 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
2104 rdev->en_dev->ulp_tbl->msix_requested);
2105
2106 rc = bnxt_re_setup_chip_ctx(rdev);
2107 if (rc) {
2108 bnxt_unregister_dev(rdev->en_dev);
2109 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2110 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
2111 return -EINVAL;
2112 }
2113
2114 rc = bnxt_re_alloc_nqr_mem(rdev);
2115 if (rc) {
2116 bnxt_re_destroy_chip_ctx(rdev);
2117 bnxt_unregister_dev(rdev->en_dev);
2118 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2119 return rc;
2120 }
2121 rdev->nqr->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
2122 memcpy(rdev->nqr->msix_entries, rdev->en_dev->msix_entries,
2123 sizeof(struct bnxt_msix_entry) * rdev->nqr->num_msix);
2124
2125 /* Check whether VF or PF */
2126 bnxt_re_get_sriov_func_type(rdev);
2127
2128 bnxt_re_query_hwrm_intf_version(rdev);
2129
2130 /* Establish RCFW Communication Channel to initialize the context
2131 * memory for the function and all child VFs
2132 */
2133 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
2134 &rdev->qplib_ctx);
2135 if (rc) {
2136 ibdev_err(&rdev->ibdev,
2137 "Failed to allocate RCFW Channel: %#x\n", rc);
2138 goto fail;
2139 }
2140
2141 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2142 creq = &rdev->rcfw.creq;
2143 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
2144 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
2145 rattr.type = type;
2146 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
2147 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
2148 rattr.lrid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
2149 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
2150 if (rc) {
2151 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
2152 goto free_rcfw;
2153 }
2154 db_offt = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
2155 vid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].vector;
2156 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
2157 vid, db_offt,
2158 &bnxt_re_aeq_handler);
2159 if (rc) {
2160 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
2161 rc);
2162 goto free_ring;
2163 }
2164
2165 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
2166 rc = bnxt_re_initialize_dbr_pacing(rdev);
2167 if (!rc) {
2168 rdev->pacing.dbr_pacing = true;
2169 } else {
2170 ibdev_err(&rdev->ibdev,
2171 "DBR pacing disabled with error : %d\n", rc);
2172 rdev->pacing.dbr_pacing = false;
2173 }
2174 }
2175 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
2176 if (rc)
2177 goto disable_rcfw;
2178
2179 bnxt_re_set_resource_limits(rdev);
2180
2181 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
2182 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));
2183 if (rc) {
2184 ibdev_err(&rdev->ibdev,
2185 "Failed to allocate QPLIB context: %#x\n", rc);
2186 goto disable_rcfw;
2187 }
2188 rc = bnxt_re_net_stats_ctx_alloc(rdev,
2189 rdev->qplib_ctx.stats.dma_map,
2190 &rdev->qplib_ctx.stats.fw_id);
2191 if (rc) {
2192 ibdev_err(&rdev->ibdev,
2193 "Failed to allocate stats context: %#x\n", rc);
2194 goto free_ctx;
2195 }
2196
2197 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
2198 rdev->is_virtfn);
2199 if (rc) {
2200 ibdev_err(&rdev->ibdev,
2201 "Failed to initialize RCFW: %#x\n", rc);
2202 goto free_sctx;
2203 }
2204 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
2205
2206 /* Resources based on the 'new' device caps */
2207 rc = bnxt_re_alloc_res(rdev);
2208 if (rc) {
2209 ibdev_err(&rdev->ibdev,
2210 "Failed to allocate resources: %#x\n", rc);
2211 goto fail;
2212 }
2213 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
2214 rc = bnxt_re_init_res(rdev);
2215 if (rc) {
2216 ibdev_err(&rdev->ibdev,
2217 "Failed to initialize resources: %#x\n", rc);
2218 goto fail;
2219 }
2220
2221 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
2222
2223 if (!rdev->is_virtfn) {
2224 /* Query f/w defaults of CC params */
2225 rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, &rdev->cc_param);
2226 if (rc)
2227 ibdev_warn(&rdev->ibdev, "Failed to query CC defaults\n");
2228
2229 rc = bnxt_re_setup_qos(rdev);
2230 if (rc)
2231 ibdev_info(&rdev->ibdev,
2232 "RoCE priority not yet configured\n");
2233
2234 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
2235 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
2236 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
2237
2238 if (!(rdev->qplib_res.en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT))
2239 bnxt_re_vf_res_config(rdev);
2240 }
2241 hash_init(rdev->cq_hash);
2242 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT)
2243 hash_init(rdev->srq_hash);
2244
2245 bnxt_re_debugfs_add_pdev(rdev);
2246
2247 bnxt_re_init_dcb_wq(rdev);
2248 bnxt_re_net_register_async_event(rdev);
2249
2250 return 0;
2251 free_sctx:
2252 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
2253 free_ctx:
2254 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
2255 disable_rcfw:
2256 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
2257 free_ring:
2258 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2259 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
2260 free_rcfw:
2261 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
2262 fail:
2263 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2264
2265 return rc;
2266 }
2267
bnxt_re_setup_cc(struct bnxt_re_dev * rdev,bool enable)2268 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
2269 {
2270 struct bnxt_qplib_cc_param cc_param = {};
2271
2272 /* Do not enable congestion control on VFs */
2273 if (rdev->is_virtfn)
2274 return;
2275
2276 /* Currently enabling only for GenP5 adapters */
2277 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
2278 return;
2279
2280 if (enable) {
2281 cc_param.enable = 1;
2282 cc_param.tos_ecn = 1;
2283 }
2284
2285 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
2286 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
2287
2288 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
2289 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
2290 }
2291
bnxt_re_update_en_info_rdev(struct bnxt_re_dev * rdev,struct bnxt_re_en_dev_info * en_info,struct auxiliary_device * adev)2292 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev,
2293 struct bnxt_re_en_dev_info *en_info,
2294 struct auxiliary_device *adev)
2295 {
2296 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure,
2297 * take the rtnl lock to avoid accessing invalid rdev pointer from
2298 * L2 ULP callbacks. This is applicable in all the places where rdev
2299 * pointer is updated in bnxt_re_en_dev_info.
2300 */
2301 rtnl_lock();
2302 en_info->rdev = rdev;
2303 rtnl_unlock();
2304 }
2305
bnxt_re_add_device(struct auxiliary_device * adev,u8 op_type)2306 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type)
2307 {
2308 struct bnxt_aux_priv *aux_priv =
2309 container_of(adev, struct bnxt_aux_priv, aux_dev);
2310 struct bnxt_re_en_dev_info *en_info;
2311 struct bnxt_en_dev *en_dev;
2312 struct bnxt_re_dev *rdev;
2313 int rc;
2314
2315 en_info = auxiliary_get_drvdata(adev);
2316 en_dev = en_info->en_dev;
2317
2318
2319 rdev = bnxt_re_dev_add(adev, en_dev);
2320 if (!rdev || !rdev_to_dev(rdev)) {
2321 rc = -ENOMEM;
2322 goto exit;
2323 }
2324
2325 bnxt_re_update_en_info_rdev(rdev, en_info, adev);
2326
2327 rc = bnxt_re_dev_init(rdev, op_type);
2328 if (rc)
2329 goto re_dev_dealloc;
2330
2331 rc = bnxt_re_ib_init(rdev);
2332 if (rc) {
2333 pr_err("Failed to register with IB: %s",
2334 aux_priv->aux_dev.name);
2335 goto re_dev_uninit;
2336 }
2337
2338 bnxt_re_setup_cc(rdev, true);
2339
2340 return 0;
2341
2342 re_dev_uninit:
2343 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2344 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2345 re_dev_dealloc:
2346 ib_dealloc_device(&rdev->ibdev);
2347 exit:
2348 return rc;
2349 }
2350
2351 #define BNXT_ADEV_NAME "bnxt_en"
2352
bnxt_re_remove_device(struct bnxt_re_dev * rdev,u8 op_type,struct auxiliary_device * aux_dev)2353 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type,
2354 struct auxiliary_device *aux_dev)
2355 {
2356 bnxt_re_setup_cc(rdev, false);
2357 ib_unregister_device(&rdev->ibdev);
2358 bnxt_re_dev_uninit(rdev, op_type);
2359 ib_dealloc_device(&rdev->ibdev);
2360 }
2361
bnxt_re_remove(struct auxiliary_device * adev)2362 static void bnxt_re_remove(struct auxiliary_device *adev)
2363 {
2364 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2365 struct bnxt_re_dev *rdev;
2366
2367 mutex_lock(&bnxt_re_mutex);
2368 rdev = en_info->rdev;
2369
2370 if (rdev)
2371 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev);
2372 kfree(en_info);
2373 mutex_unlock(&bnxt_re_mutex);
2374 }
2375
bnxt_re_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)2376 static int bnxt_re_probe(struct auxiliary_device *adev,
2377 const struct auxiliary_device_id *id)
2378 {
2379 struct bnxt_aux_priv *aux_priv =
2380 container_of(adev, struct bnxt_aux_priv, aux_dev);
2381 struct bnxt_re_en_dev_info *en_info;
2382 struct bnxt_en_dev *en_dev;
2383 int rc;
2384
2385 en_dev = aux_priv->edev;
2386
2387 mutex_lock(&bnxt_re_mutex);
2388 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL);
2389 if (!en_info) {
2390 mutex_unlock(&bnxt_re_mutex);
2391 return -ENOMEM;
2392 }
2393 en_info->en_dev = en_dev;
2394
2395 auxiliary_set_drvdata(adev, en_info);
2396
2397 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT);
2398 if (rc)
2399 kfree(en_info);
2400
2401 mutex_unlock(&bnxt_re_mutex);
2402
2403 return rc;
2404 }
2405
bnxt_re_suspend(struct auxiliary_device * adev,pm_message_t state)2406 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
2407 {
2408 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2409 struct bnxt_en_dev *en_dev;
2410 struct bnxt_re_dev *rdev;
2411
2412 rdev = en_info->rdev;
2413 en_dev = en_info->en_dev;
2414 mutex_lock(&bnxt_re_mutex);
2415
2416 ibdev_info(&rdev->ibdev, "Handle device suspend call");
2417 /* Check the current device state from bnxt_en_dev and move the
2418 * device to detached state if FW_FATAL_COND is set.
2419 * This prevents more commands to HW during clean-up,
2420 * in case the device is already in error.
2421 */
2422 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) {
2423 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
2424 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
2425 wake_up_all(&rdev->rcfw.cmdq.waitq);
2426 bnxt_re_dev_stop(rdev);
2427 }
2428
2429 if (rdev->pacing.dbr_pacing)
2430 bnxt_re_set_pacing_dev_state(rdev);
2431
2432 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx",
2433 __func__, en_dev->en_state);
2434 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev);
2435 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2436 mutex_unlock(&bnxt_re_mutex);
2437
2438 return 0;
2439 }
2440
bnxt_re_resume(struct auxiliary_device * adev)2441 static int bnxt_re_resume(struct auxiliary_device *adev)
2442 {
2443 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2444 struct bnxt_re_dev *rdev;
2445
2446 mutex_lock(&bnxt_re_mutex);
2447 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT);
2448 rdev = en_info->rdev;
2449 ibdev_info(&rdev->ibdev, "Device resume completed");
2450 mutex_unlock(&bnxt_re_mutex);
2451
2452 return 0;
2453 }
2454
bnxt_re_shutdown(struct auxiliary_device * adev)2455 static void bnxt_re_shutdown(struct auxiliary_device *adev)
2456 {
2457 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2458 struct bnxt_re_dev *rdev;
2459
2460 rdev = en_info->rdev;
2461 ib_unregister_device(&rdev->ibdev);
2462 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2463 }
2464
2465 static const struct auxiliary_device_id bnxt_re_id_table[] = {
2466 { .name = BNXT_ADEV_NAME ".rdma", },
2467 {},
2468 };
2469
2470 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
2471
2472 static struct auxiliary_driver bnxt_re_driver = {
2473 .name = "rdma",
2474 .probe = bnxt_re_probe,
2475 .remove = bnxt_re_remove,
2476 .shutdown = bnxt_re_shutdown,
2477 .suspend = bnxt_re_suspend,
2478 .resume = bnxt_re_resume,
2479 .id_table = bnxt_re_id_table,
2480 };
2481
bnxt_re_mod_init(void)2482 static int __init bnxt_re_mod_init(void)
2483 {
2484 int rc;
2485
2486 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
2487 bnxt_re_register_debugfs();
2488
2489 rc = auxiliary_driver_register(&bnxt_re_driver);
2490 if (rc) {
2491 pr_err("%s: Failed to register auxiliary driver\n",
2492 ROCE_DRV_MODULE_NAME);
2493 goto err_debug;
2494 }
2495 return 0;
2496 err_debug:
2497 bnxt_re_unregister_debugfs();
2498 return rc;
2499 }
2500
bnxt_re_mod_exit(void)2501 static void __exit bnxt_re_mod_exit(void)
2502 {
2503 auxiliary_driver_unregister(&bnxt_re_driver);
2504 bnxt_re_unregister_debugfs();
2505 }
2506
2507 module_init(bnxt_re_mod_init);
2508 module_exit(bnxt_re_mod_exit);
2509