1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/notifier.h>
49 #include <linux/refcount.h>
50 #include <linux/auxiliary_bus.h>
51 #include <linux/mutex.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <net/devlink.h>
58
59 #define MLX5_ADEV_NAME "mlx5_core"
60
61 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
62
63 enum {
64 MLX5_BOARD_ID_LEN = 64,
65 };
66
67 enum {
68 MLX5_CMD_WQ_MAX_NAME = 32,
69 };
70
71 enum {
72 CMD_OWNER_SW = 0x0,
73 CMD_OWNER_HW = 0x1,
74 CMD_STATUS_SUCCESS = 0,
75 };
76
77 enum mlx5_sqp_t {
78 MLX5_SQP_SMI = 0,
79 MLX5_SQP_GSI = 1,
80 MLX5_SQP_IEEE_1588 = 2,
81 MLX5_SQP_SNIFFER = 3,
82 MLX5_SQP_SYNC_UMR = 4,
83 };
84
85 enum {
86 MLX5_MAX_PORTS = 8,
87 };
88
89 enum {
90 MLX5_ATOMIC_MODE_OFFSET = 16,
91 MLX5_ATOMIC_MODE_IB_COMP = 1,
92 MLX5_ATOMIC_MODE_CX = 2,
93 MLX5_ATOMIC_MODE_8B = 3,
94 MLX5_ATOMIC_MODE_16B = 4,
95 MLX5_ATOMIC_MODE_32B = 5,
96 MLX5_ATOMIC_MODE_64B = 6,
97 MLX5_ATOMIC_MODE_128B = 7,
98 MLX5_ATOMIC_MODE_256B = 8,
99 };
100
101 enum {
102 MLX5_REG_SBPR = 0xb001,
103 MLX5_REG_SBCM = 0xb002,
104 MLX5_REG_QPTS = 0x4002,
105 MLX5_REG_QETCR = 0x4005,
106 MLX5_REG_QTCT = 0x400a,
107 MLX5_REG_QPDPM = 0x4013,
108 MLX5_REG_QCAM = 0x4019,
109 MLX5_REG_DCBX_PARAM = 0x4020,
110 MLX5_REG_DCBX_APP = 0x4021,
111 MLX5_REG_FPGA_CAP = 0x4022,
112 MLX5_REG_FPGA_CTRL = 0x4023,
113 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
114 MLX5_REG_CORE_DUMP = 0x402e,
115 MLX5_REG_PCAP = 0x5001,
116 MLX5_REG_PMTU = 0x5003,
117 MLX5_REG_PTYS = 0x5004,
118 MLX5_REG_PAOS = 0x5006,
119 MLX5_REG_PFCC = 0x5007,
120 MLX5_REG_PPCNT = 0x5008,
121 MLX5_REG_PPTB = 0x500b,
122 MLX5_REG_PBMC = 0x500c,
123 MLX5_REG_PMAOS = 0x5012,
124 MLX5_REG_PUDE = 0x5009,
125 MLX5_REG_PMPE = 0x5010,
126 MLX5_REG_PELC = 0x500e,
127 MLX5_REG_PVLC = 0x500f,
128 MLX5_REG_PCMR = 0x5041,
129 MLX5_REG_PDDR = 0x5031,
130 MLX5_REG_PMLP = 0x5002,
131 MLX5_REG_PPLM = 0x5023,
132 MLX5_REG_PCAM = 0x507f,
133 MLX5_REG_NODE_DESC = 0x6001,
134 MLX5_REG_HOST_ENDIANNESS = 0x7004,
135 MLX5_REG_MTCAP = 0x9009,
136 MLX5_REG_MTMP = 0x900A,
137 MLX5_REG_MCIA = 0x9014,
138 MLX5_REG_MFRL = 0x9028,
139 MLX5_REG_MLCR = 0x902b,
140 MLX5_REG_MRTC = 0x902d,
141 MLX5_REG_MTRC_CAP = 0x9040,
142 MLX5_REG_MTRC_CONF = 0x9041,
143 MLX5_REG_MTRC_STDB = 0x9042,
144 MLX5_REG_MTRC_CTRL = 0x9043,
145 MLX5_REG_MPEIN = 0x9050,
146 MLX5_REG_MPCNT = 0x9051,
147 MLX5_REG_MTPPS = 0x9053,
148 MLX5_REG_MTPPSE = 0x9054,
149 MLX5_REG_MTUTC = 0x9055,
150 MLX5_REG_MPEGC = 0x9056,
151 MLX5_REG_MPIR = 0x9059,
152 MLX5_REG_MCQS = 0x9060,
153 MLX5_REG_MCQI = 0x9061,
154 MLX5_REG_MCC = 0x9062,
155 MLX5_REG_MCDA = 0x9063,
156 MLX5_REG_MCAM = 0x907f,
157 MLX5_REG_MSECQ = 0x9155,
158 MLX5_REG_MSEES = 0x9156,
159 MLX5_REG_MIRC = 0x9162,
160 MLX5_REG_MTPTM = 0x9180,
161 MLX5_REG_MTCTR = 0x9181,
162 MLX5_REG_MRTCQ = 0x9182,
163 MLX5_REG_SBCAM = 0xB01F,
164 MLX5_REG_RESOURCE_DUMP = 0xC000,
165 MLX5_REG_NIC_CAP = 0xC00D,
166 MLX5_REG_DTOR = 0xC00E,
167 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
168 };
169
170 enum mlx5_qpts_trust_state {
171 MLX5_QPTS_TRUST_PCP = 1,
172 MLX5_QPTS_TRUST_DSCP = 2,
173 };
174
175 enum mlx5_dcbx_oper_mode {
176 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
177 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
178 };
179
180 enum {
181 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
182 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
183 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
184 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
185 };
186
187 enum mlx5_page_fault_resume_flags {
188 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
189 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
190 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
191 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
192 };
193
194 enum dbg_rsc_type {
195 MLX5_DBG_RSC_QP,
196 MLX5_DBG_RSC_EQ,
197 MLX5_DBG_RSC_CQ,
198 };
199
200 enum port_state_policy {
201 MLX5_POLICY_DOWN = 0,
202 MLX5_POLICY_UP = 1,
203 MLX5_POLICY_FOLLOW = 2,
204 MLX5_POLICY_INVALID = 0xffffffff
205 };
206
207 enum mlx5_coredev_type {
208 MLX5_COREDEV_PF,
209 MLX5_COREDEV_VF,
210 MLX5_COREDEV_SF,
211 };
212
213 struct mlx5_field_desc {
214 int i;
215 };
216
217 struct mlx5_rsc_debug {
218 struct mlx5_core_dev *dev;
219 void *object;
220 enum dbg_rsc_type type;
221 struct dentry *root;
222 struct mlx5_field_desc fields[];
223 };
224
225 enum mlx5_dev_event {
226 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
227 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
228 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
229 };
230
231 enum mlx5_port_status {
232 MLX5_PORT_UP = 1,
233 MLX5_PORT_DOWN = 2,
234 };
235
236 enum mlx5_cmdif_state {
237 MLX5_CMDIF_STATE_UNINITIALIZED,
238 MLX5_CMDIF_STATE_UP,
239 MLX5_CMDIF_STATE_DOWN,
240 };
241
242 struct mlx5_cmd_first {
243 __be32 data[4];
244 };
245
246 struct mlx5_cmd_msg {
247 struct list_head list;
248 struct cmd_msg_cache *parent;
249 u32 len;
250 struct mlx5_cmd_first first;
251 struct mlx5_cmd_mailbox *next;
252 };
253
254 struct mlx5_cmd_debug {
255 struct dentry *dbg_root;
256 void *in_msg;
257 void *out_msg;
258 u8 status;
259 u16 inlen;
260 u16 outlen;
261 };
262
263 struct cmd_msg_cache {
264 /* protect block chain allocations
265 */
266 spinlock_t lock;
267 struct list_head head;
268 unsigned int max_inbox_size;
269 unsigned int num_ent;
270 };
271
272 enum {
273 MLX5_NUM_COMMAND_CACHES = 5,
274 };
275
276 struct mlx5_cmd_stats {
277 u64 sum;
278 u64 n;
279 /* number of times command failed */
280 u64 failed;
281 /* number of times command failed on bad status returned by FW */
282 u64 failed_mbox_status;
283 /* last command failed returned errno */
284 u32 last_failed_errno;
285 /* last bad status returned by FW */
286 u8 last_failed_mbox_status;
287 /* last command failed syndrome returned by FW */
288 u32 last_failed_syndrome;
289 struct dentry *root;
290 /* protect command average calculations */
291 spinlock_t lock;
292 };
293
294 struct mlx5_cmd {
295 struct mlx5_nb nb;
296
297 /* members which needs to be queried or reinitialized each reload */
298 struct {
299 u16 cmdif_rev;
300 u8 log_sz;
301 u8 log_stride;
302 int max_reg_cmds;
303 unsigned long bitmask;
304 struct semaphore sem;
305 struct semaphore pages_sem;
306 struct semaphore throttle_sem;
307 struct semaphore unprivileged_sem;
308 struct xarray privileged_uids;
309 } vars;
310 enum mlx5_cmdif_state state;
311 void *cmd_alloc_buf;
312 dma_addr_t alloc_dma;
313 int alloc_size;
314 void *cmd_buf;
315 dma_addr_t dma;
316
317 /* protect command queue allocations
318 */
319 spinlock_t alloc_lock;
320
321 /* protect token allocations
322 */
323 spinlock_t token_lock;
324 u8 token;
325 char wq_name[MLX5_CMD_WQ_MAX_NAME];
326 struct workqueue_struct *wq;
327 int mode;
328 u16 allowed_opcode;
329 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
330 struct dma_pool *pool;
331 struct mlx5_cmd_debug dbg;
332 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
333 int checksum_disabled;
334 struct xarray stats;
335 };
336
337 struct mlx5_cmd_mailbox {
338 void *buf;
339 dma_addr_t dma;
340 struct mlx5_cmd_mailbox *next;
341 };
342
343 struct mlx5_buf_list {
344 void *buf;
345 dma_addr_t map;
346 };
347
348 struct mlx5_frag_buf {
349 struct mlx5_buf_list *frags;
350 int npages;
351 int size;
352 u8 page_shift;
353 };
354
355 struct mlx5_frag_buf_ctrl {
356 struct mlx5_buf_list *frags;
357 u32 sz_m1;
358 u16 frag_sz_m1;
359 u16 strides_offset;
360 u8 log_sz;
361 u8 log_stride;
362 u8 log_frag_strides;
363 };
364
365 struct mlx5_core_psv {
366 u32 psv_idx;
367 struct psv_layout {
368 u32 pd;
369 u16 syndrome;
370 u16 reserved;
371 u16 bg;
372 u16 app_tag;
373 u32 ref_tag;
374 } psv;
375 };
376
377 struct mlx5_core_sig_ctx {
378 struct mlx5_core_psv psv_memory;
379 struct mlx5_core_psv psv_wire;
380 struct ib_sig_err err_item;
381 bool sig_status_checked;
382 bool sig_err_exists;
383 u32 sigerr_count;
384 };
385
386 #define MLX5_24BIT_MASK ((1 << 24) - 1)
387
388 enum mlx5_res_type {
389 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
390 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
391 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
392 MLX5_RES_SRQ = 3,
393 MLX5_RES_XSRQ = 4,
394 MLX5_RES_XRQ = 5,
395 };
396
397 struct mlx5_core_rsc_common {
398 enum mlx5_res_type res;
399 refcount_t refcount;
400 struct completion free;
401 bool invalid;
402 };
403
404 struct mlx5_uars_page {
405 void __iomem *map;
406 bool wc;
407 u32 index;
408 struct list_head list;
409 unsigned int bfregs;
410 unsigned long *reg_bitmap; /* for non fast path bf regs */
411 unsigned long *fp_bitmap;
412 unsigned int reg_avail;
413 unsigned int fp_avail;
414 struct kref ref_count;
415 struct mlx5_core_dev *mdev;
416 };
417
418 struct mlx5_bfreg_head {
419 /* protect blue flame registers allocations */
420 struct mutex lock;
421 struct list_head list;
422 };
423
424 struct mlx5_bfreg_data {
425 struct mlx5_bfreg_head reg_head;
426 struct mlx5_bfreg_head wc_head;
427 };
428
429 struct mlx5_sq_bfreg {
430 void __iomem *map;
431 struct mlx5_uars_page *up;
432 bool wc;
433 u32 index;
434 unsigned int offset;
435 };
436
437 struct mlx5_core_health {
438 struct health_buffer __iomem *health;
439 __be32 __iomem *health_counter;
440 struct timer_list timer;
441 u32 prev;
442 int miss_counter;
443 u8 synd;
444 u32 fatal_error;
445 u32 crdump_size;
446 struct workqueue_struct *wq;
447 unsigned long flags;
448 struct work_struct fatal_report_work;
449 struct work_struct report_work;
450 struct devlink_health_reporter *fw_reporter;
451 struct devlink_health_reporter *fw_fatal_reporter;
452 struct devlink_health_reporter *vnic_reporter;
453 struct delayed_work update_fw_log_ts_work;
454 };
455
456 enum {
457 MLX5_PF_NOTIFY_DISABLE_VF,
458 MLX5_PF_NOTIFY_ENABLE_VF,
459 };
460
461 struct mlx5_vf_context {
462 int enabled;
463 u64 port_guid;
464 u64 node_guid;
465 /* Valid bits are used to validate administrative guid only.
466 * Enabled after ndo_set_vf_guid
467 */
468 u8 port_guid_valid:1;
469 u8 node_guid_valid:1;
470 enum port_state_policy policy;
471 struct blocking_notifier_head notifier;
472 };
473
474 struct mlx5_core_sriov {
475 struct mlx5_vf_context *vfs_ctx;
476 int num_vfs;
477 u16 max_vfs;
478 u16 max_ec_vfs;
479 };
480
481 struct mlx5_events;
482 struct mlx5_mpfs;
483 struct mlx5_eswitch;
484 struct mlx5_lag;
485 struct mlx5_devcom_dev;
486 struct mlx5_fw_reset;
487 struct mlx5_eq_table;
488 struct mlx5_irq_table;
489 struct mlx5_vhca_state_notifier;
490 struct mlx5_sf_dev_table;
491 struct mlx5_sf_hw_table;
492 struct mlx5_sf_table;
493 struct mlx5_crypto_dek_priv;
494
495 struct mlx5_rate_limit {
496 u32 rate;
497 u32 max_burst_sz;
498 u16 typical_pkt_sz;
499 };
500
501 struct mlx5_rl_entry {
502 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
503 u64 refcount;
504 u16 index;
505 u16 uid;
506 u8 dedicated : 1;
507 };
508
509 struct mlx5_rl_table {
510 /* protect rate limit table */
511 struct mutex rl_lock;
512 u16 max_size;
513 u32 max_rate;
514 u32 min_rate;
515 struct mlx5_rl_entry *rl_entry;
516 u64 refcount;
517 };
518
519 struct mlx5_core_roce {
520 struct mlx5_flow_table *ft;
521 struct mlx5_flow_group *fg;
522 struct mlx5_flow_handle *allow_rule;
523 };
524
525 enum {
526 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
527 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
528 /* Set during device detach to block any further devices
529 * creation/deletion on drivers rescan. Unset during device attach.
530 */
531 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
532 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
533 };
534
535 struct mlx5_adev {
536 struct auxiliary_device adev;
537 struct mlx5_core_dev *mdev;
538 int idx;
539 };
540
541 struct mlx5_debugfs_entries {
542 struct dentry *dbg_root;
543 struct dentry *qp_debugfs;
544 struct dentry *eq_debugfs;
545 struct dentry *cq_debugfs;
546 struct dentry *cmdif_debugfs;
547 struct dentry *pages_debugfs;
548 struct dentry *lag_debugfs;
549 };
550
551 enum mlx5_func_type {
552 MLX5_PF,
553 MLX5_VF,
554 MLX5_SF,
555 MLX5_HOST_PF,
556 MLX5_EC_VF,
557 MLX5_FUNC_TYPE_NUM,
558 };
559
560 struct mlx5_ft_pool;
561 struct mlx5_priv {
562 /* IRQ table valid only for real pci devices PF or VF */
563 struct mlx5_irq_table *irq_table;
564 struct mlx5_eq_table *eq_table;
565
566 /* pages stuff */
567 struct mlx5_nb pg_nb;
568 struct workqueue_struct *pg_wq;
569 struct xarray page_root_xa;
570 atomic_t reg_pages;
571 struct list_head free_list;
572 u32 fw_pages;
573 u32 page_counters[MLX5_FUNC_TYPE_NUM];
574 u32 fw_pages_alloc_failed;
575 u32 give_pages_dropped;
576 u32 reclaim_pages_discard;
577
578 struct mlx5_core_health health;
579 struct list_head traps;
580
581 struct mlx5_debugfs_entries dbg;
582
583 /* start: alloc staff */
584 /* protect buffer allocation according to numa node */
585 struct mutex alloc_mutex;
586 int numa_node;
587
588 struct mutex pgdir_mutex;
589 struct list_head pgdir_list;
590 /* end: alloc staff */
591
592 struct mlx5_adev **adev;
593 int adev_idx;
594 int sw_vhca_id;
595 struct mlx5_events *events;
596 struct mlx5_vhca_events *vhca_events;
597
598 struct mlx5_flow_steering *steering;
599 struct mlx5_mpfs *mpfs;
600 struct mlx5_eswitch *eswitch;
601 struct mlx5_core_sriov sriov;
602 struct mlx5_lag *lag;
603 u32 flags;
604 struct mlx5_devcom_dev *devc;
605 struct mlx5_devcom_comp_dev *hca_devcom_comp;
606 struct mlx5_fw_reset *fw_reset;
607 struct mlx5_core_roce roce;
608 struct mlx5_fc_stats *fc_stats;
609 struct mlx5_rl_table rl_table;
610 struct mlx5_ft_pool *ft_pool;
611
612 struct mlx5_bfreg_data bfregs;
613 struct mlx5_uars_page *uar;
614 #ifdef CONFIG_MLX5_SF
615 struct mlx5_vhca_state_notifier *vhca_state_notifier;
616 struct mlx5_sf_dev_table *sf_dev_table;
617 struct mlx5_core_dev *parent_mdev;
618 #endif
619 #ifdef CONFIG_MLX5_SF_MANAGER
620 struct mlx5_sf_hw_table *sf_hw_table;
621 struct mlx5_sf_table *sf_table;
622 #endif
623 struct blocking_notifier_head lag_nh;
624 };
625
626 enum mlx5_device_state {
627 MLX5_DEVICE_STATE_UP = 1,
628 MLX5_DEVICE_STATE_INTERNAL_ERROR,
629 };
630
631 enum mlx5_interface_state {
632 MLX5_INTERFACE_STATE_UP = BIT(0),
633 MLX5_BREAK_FW_WAIT = BIT(1),
634 };
635
636 enum mlx5_pci_status {
637 MLX5_PCI_STATUS_DISABLED,
638 MLX5_PCI_STATUS_ENABLED,
639 };
640
641 enum mlx5_pagefault_type_flags {
642 MLX5_PFAULT_REQUESTOR = 1 << 0,
643 MLX5_PFAULT_WRITE = 1 << 1,
644 MLX5_PFAULT_RDMA = 1 << 2,
645 };
646
647 struct mlx5_td {
648 /* protects tirs list changes while tirs refresh */
649 struct mutex list_lock;
650 struct list_head tirs_list;
651 u32 tdn;
652 };
653
654 struct mlx5e_resources {
655 struct mlx5e_hw_objs {
656 u32 pdn;
657 struct mlx5_td td;
658 u32 mkey;
659 struct mlx5_sq_bfreg bfreg;
660 #define MLX5_MAX_NUM_TC 8
661 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
662 bool tisn_valid;
663 } hw_objs;
664 struct net_device *uplink_netdev;
665 struct mutex uplink_netdev_lock;
666 struct mlx5_crypto_dek_priv *dek_priv;
667 };
668
669 enum mlx5_sw_icm_type {
670 MLX5_SW_ICM_TYPE_STEERING,
671 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
672 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
673 MLX5_SW_ICM_TYPE_SW_ENCAP,
674 };
675
676 #define MLX5_MAX_RESERVED_GIDS 8
677
678 struct mlx5_rsvd_gids {
679 unsigned int start;
680 unsigned int count;
681 struct ida ida;
682 };
683
684 struct mlx5_clock;
685 struct mlx5_clock_dev_state;
686 struct mlx5_dm;
687 struct mlx5_fw_tracer;
688 struct mlx5_vxlan;
689 struct mlx5_geneve;
690 struct mlx5_hv_vhca;
691
692 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
693 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
694
695 enum {
696 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
697 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
698 };
699
700 enum {
701 MKEY_CACHE_LAST_STD_ENTRY = 20,
702 MLX5_IMR_KSM_CACHE_ENTRY,
703 MAX_MKEY_CACHE_ENTRIES
704 };
705
706 struct mlx5_profile {
707 u64 mask;
708 u8 log_max_qp;
709 u8 num_cmd_caches;
710 struct {
711 int size;
712 int limit;
713 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
714 };
715
716 struct mlx5_hca_cap {
717 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
718 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
719 };
720
721 enum mlx5_wc_state {
722 MLX5_WC_STATE_UNINITIALIZED,
723 MLX5_WC_STATE_UNSUPPORTED,
724 MLX5_WC_STATE_SUPPORTED,
725 };
726
727 struct mlx5_core_dev {
728 struct device *device;
729 enum mlx5_coredev_type coredev_type;
730 struct pci_dev *pdev;
731 /* sync pci state */
732 struct mutex pci_status_mutex;
733 enum mlx5_pci_status pci_status;
734 u8 rev_id;
735 char board_id[MLX5_BOARD_ID_LEN];
736 struct mlx5_cmd cmd;
737 struct {
738 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
739 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
740 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
741 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
742 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
743 u8 embedded_cpu;
744 } caps;
745 struct mlx5_timeouts *timeouts;
746 u64 sys_image_guid;
747 phys_addr_t iseg_base;
748 struct mlx5_init_seg __iomem *iseg;
749 phys_addr_t bar_addr;
750 enum mlx5_device_state state;
751 /* sync interface state */
752 struct mutex intf_state_mutex;
753 struct lock_class_key lock_key;
754 unsigned long intf_state;
755 struct mlx5_priv priv;
756 struct mlx5_profile profile;
757 u32 issi;
758 struct mlx5e_resources mlx5e_res;
759 struct mlx5_dm *dm;
760 struct mlx5_vxlan *vxlan;
761 struct mlx5_geneve *geneve;
762 struct {
763 struct mlx5_rsvd_gids reserved_gids;
764 u32 roce_en;
765 } roce;
766 #ifdef CONFIG_MLX5_FPGA
767 struct mlx5_fpga_device *fpga;
768 #endif
769 struct mlx5_clock *clock;
770 struct mlx5_clock_dev_state *clock_state;
771 struct mlx5_ib_clock_info *clock_info;
772 struct mlx5_fw_tracer *tracer;
773 struct mlx5_rsc_dump *rsc_dump;
774 u32 vsc_addr;
775 struct mlx5_hv_vhca *hv_vhca;
776 struct mlx5_hwmon *hwmon;
777 u64 num_block_tc;
778 u64 num_block_ipsec;
779 #ifdef CONFIG_MLX5_MACSEC
780 struct mlx5_macsec_fs *macsec_fs;
781 /* MACsec notifier chain to sync MACsec core and IB database */
782 struct blocking_notifier_head macsec_nh;
783 #endif
784 u64 num_ipsec_offloads;
785 struct mlx5_sd *sd;
786 enum mlx5_wc_state wc_state;
787 /* sync write combining state */
788 struct mutex wc_state_lock;
789 };
790
791 struct mlx5_db {
792 __be32 *db;
793 union {
794 struct mlx5_db_pgdir *pgdir;
795 struct mlx5_ib_user_db_page *user_page;
796 } u;
797 dma_addr_t dma;
798 int index;
799 };
800
801 enum {
802 MLX5_COMP_EQ_SIZE = 1024,
803 };
804
805 enum {
806 MLX5_PTYS_IB = 1 << 0,
807 MLX5_PTYS_EN = 1 << 2,
808 };
809
810 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
811
812 enum {
813 MLX5_CMD_ENT_STATE_PENDING_COMP,
814 };
815
816 struct mlx5_cmd_work_ent {
817 unsigned long state;
818 struct mlx5_cmd_msg *in;
819 struct mlx5_cmd_msg *out;
820 void *uout;
821 int uout_size;
822 mlx5_cmd_cbk_t callback;
823 struct delayed_work cb_timeout_work;
824 void *context;
825 int idx;
826 struct completion handling;
827 struct completion slotted;
828 struct completion done;
829 struct mlx5_cmd *cmd;
830 struct work_struct work;
831 struct mlx5_cmd_layout *lay;
832 int ret;
833 int page_queue;
834 u8 status;
835 u8 token;
836 u64 ts1;
837 u64 ts2;
838 u16 op;
839 bool polling;
840 /* Track the max comp handlers */
841 refcount_t refcnt;
842 };
843
844 enum phy_port_state {
845 MLX5_AAA_111
846 };
847
848 struct mlx5_hca_vport_context {
849 u32 field_select;
850 bool sm_virt_aware;
851 bool has_smi;
852 bool has_raw;
853 enum port_state_policy policy;
854 enum phy_port_state phys_state;
855 enum ib_port_state vport_state;
856 u8 port_physical_state;
857 u64 sys_image_guid;
858 u64 port_guid;
859 u64 node_guid;
860 u32 cap_mask1;
861 u32 cap_mask1_perm;
862 u16 cap_mask2;
863 u16 cap_mask2_perm;
864 u16 lid;
865 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
866 u8 lmc;
867 u8 subnet_timeout;
868 u16 sm_lid;
869 u8 sm_sl;
870 u16 qkey_violation_counter;
871 u16 pkey_violation_counter;
872 bool grh_required;
873 u8 num_plane;
874 };
875
876 #define STRUCT_FIELD(header, field) \
877 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
878 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
879
880 extern struct dentry *mlx5_debugfs_root;
881
fw_rev_maj(struct mlx5_core_dev * dev)882 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
883 {
884 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
885 }
886
fw_rev_min(struct mlx5_core_dev * dev)887 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
888 {
889 return ioread32be(&dev->iseg->fw_rev) >> 16;
890 }
891
fw_rev_sub(struct mlx5_core_dev * dev)892 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
893 {
894 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
895 }
896
mlx5_base_mkey(const u32 key)897 static inline u32 mlx5_base_mkey(const u32 key)
898 {
899 return key & 0xffffff00u;
900 }
901
wq_get_byte_sz(u8 log_sz,u8 log_stride)902 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
903 {
904 return ((u32)1 << log_sz) << log_stride;
905 }
906
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)907 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
908 u8 log_stride, u8 log_sz,
909 u16 strides_offset,
910 struct mlx5_frag_buf_ctrl *fbc)
911 {
912 fbc->frags = frags;
913 fbc->log_stride = log_stride;
914 fbc->log_sz = log_sz;
915 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
916 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
917 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
918 fbc->strides_offset = strides_offset;
919 }
920
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)921 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
922 u8 log_stride, u8 log_sz,
923 struct mlx5_frag_buf_ctrl *fbc)
924 {
925 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
926 }
927
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)928 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
929 u32 ix)
930 {
931 unsigned int frag;
932
933 ix += fbc->strides_offset;
934 frag = ix >> fbc->log_frag_strides;
935
936 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
937 }
938
939 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)940 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
941 {
942 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
943
944 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
945 }
946
947 enum {
948 CMD_ALLOWED_OPCODE_ALL,
949 };
950
951 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
952 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
953 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
954
955 struct mlx5_async_ctx {
956 struct mlx5_core_dev *dev;
957 atomic_t num_inflight;
958 struct completion inflight_done;
959 };
960
961 struct mlx5_async_work;
962
963 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
964
965 struct mlx5_async_work {
966 struct mlx5_async_ctx *ctx;
967 mlx5_async_cbk_t user_callback;
968 u16 opcode; /* cmd opcode */
969 u16 op_mod; /* cmd op_mod */
970 u8 throttle_locked:1;
971 u8 unpriv_locked:1;
972 void *out; /* pointer to the cmd output buffer */
973 };
974
975 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
976 struct mlx5_async_ctx *ctx);
977 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
978 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
979 void *out, int out_size, mlx5_async_cbk_t callback,
980 struct mlx5_async_work *work);
981 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
982 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
983 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
984 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
985 int out_size);
986
987 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
988 ({ \
989 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
990 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
991 })
992
993 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
994 ({ \
995 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
996 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
997 })
998
999 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1000 void *out, int out_size);
1001 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1002 int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1003 void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1004
1005 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1006 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1007
1008 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1009
1010 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1011 int mlx5_health_init(struct mlx5_core_dev *dev);
1012 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1013 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1014 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1015 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1016 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1017 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1018 struct mlx5_frag_buf *buf, int node);
1019 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1020 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1021 int inlen);
1022 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1023 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1024 int outlen);
1025 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1026 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1027 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1028 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1029 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1030 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1031 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1032 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1033 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1034 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1035 void mlx5_register_debugfs(void);
1036 void mlx5_unregister_debugfs(void);
1037
1038 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1039 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1040 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1041 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1042 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1043
1044 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1045 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1046 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1047 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1048 void *data_out, int size_out, u16 reg_id, int arg,
1049 int write, bool verbose);
1050 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1051 int size_in, void *data_out, int size_out,
1052 u16 reg_num, int arg, int write);
1053
1054 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1055 int node);
1056
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1057 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1058 {
1059 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1060 }
1061
1062 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1063
1064 const char *mlx5_command_str(int command);
1065 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1066 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1067 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1068 int npsvs, u32 *sig_index);
1069 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1070 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1071 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1072
1073 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1074 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1075 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1076 struct mlx5_rate_limit *rl);
1077 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1078 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1079 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1080 bool dedicated_entry, u16 *index);
1081 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1082 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1083 struct mlx5_rate_limit *rl_1);
1084 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1085 bool map_wc, bool fast_path);
1086 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1087
1088 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1089 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1090 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1091 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1092 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1093 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1094
mlx5_mkey_to_idx(u32 mkey)1095 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1096 {
1097 return mkey >> 8;
1098 }
1099
mlx5_idx_to_mkey(u32 mkey_idx)1100 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1101 {
1102 return mkey_idx << 8;
1103 }
1104
mlx5_mkey_variant(u32 mkey)1105 static inline u8 mlx5_mkey_variant(u32 mkey)
1106 {
1107 return mkey & 0xff;
1108 }
1109
1110 /* Async-atomic event notifier used by mlx5 core to forward FW
1111 * evetns received from event queue to mlx5 consumers.
1112 * Optimise event queue dipatching.
1113 */
1114 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1115 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1116
1117 /* Async-atomic event notifier used for forwarding
1118 * evetns from the event queue into the to mlx5 events dispatcher,
1119 * eswitch, clock and others.
1120 */
1121 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1122 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1123
1124 /* Blocking event notifier used to forward SW events, used for slow path */
1125 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1126 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1127 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1128 void *data);
1129
1130 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1131
1132 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1133 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1134 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1135 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1136 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1137 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1138 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1139 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1140 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1141 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1142 struct net_device *slave);
1143 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1144 u64 *values,
1145 int num_counters,
1146 size_t *offsets);
1147 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1148
1149 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1150 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1151 peer; \
1152 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1153
1154 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1155 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1156 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1157 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1158 u64 length, u32 log_alignment, u16 uid,
1159 phys_addr_t *addr, u32 *obj_id);
1160 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1161 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1162
1163 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1164 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1165
1166 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1167 int vf_id,
1168 struct notifier_block *nb);
1169 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1170 int vf_id,
1171 struct notifier_block *nb);
1172 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1173 struct ib_device *device,
1174 struct rdma_netdev_alloc_params *params);
1175
1176 enum {
1177 MLX5_PCI_DEV_IS_VF = 1 << 0,
1178 };
1179
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1180 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1181 {
1182 return dev->coredev_type == MLX5_COREDEV_PF;
1183 }
1184
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1185 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1186 {
1187 return dev->coredev_type == MLX5_COREDEV_VF;
1188 }
1189
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1190 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1191 const struct mlx5_core_dev *dev2)
1192 {
1193 return dev1->coredev_type == dev2->coredev_type;
1194 }
1195
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1196 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1197 {
1198 return dev->caps.embedded_cpu;
1199 }
1200
1201 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1202 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1203 {
1204 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1205 }
1206
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1207 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1208 {
1209 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1210 }
1211
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1212 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1213 {
1214 return dev->priv.sriov.max_vfs;
1215 }
1216
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1217 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1218 {
1219 /* LACP owner conditions:
1220 * 1) Function is physical.
1221 * 2) LAG is supported by FW.
1222 * 3) LAG is managed by driver (currently the only option).
1223 */
1224 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1225 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1226 MLX5_CAP_GEN(dev, lag_master);
1227 }
1228
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1229 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1230 {
1231 return dev->priv.sriov.max_ec_vfs;
1232 }
1233
mlx5_get_gid_table_len(u16 param)1234 static inline int mlx5_get_gid_table_len(u16 param)
1235 {
1236 if (param > 4) {
1237 pr_warn("gid table length is zero\n");
1238 return 0;
1239 }
1240
1241 return 8 * (1 << param);
1242 }
1243
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1244 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1245 {
1246 return !!(dev->priv.rl_table.max_size);
1247 }
1248
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1249 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1250 {
1251 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1252 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1253 }
1254
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1255 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1256 {
1257 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1258 }
1259
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1260 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1261 {
1262 return mlx5_core_is_mp_slave(dev) ||
1263 mlx5_core_is_mp_master(dev);
1264 }
1265
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1266 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1267 {
1268 if (!mlx5_core_mp_enabled(dev))
1269 return 1;
1270
1271 return MLX5_CAP_GEN(dev, native_port_num);
1272 }
1273
mlx5_get_dev_index(struct mlx5_core_dev * dev)1274 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1275 {
1276 int idx = MLX5_CAP_GEN(dev, native_port_num);
1277
1278 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1279 return idx - 1;
1280 else
1281 return PCI_FUNC(dev->pdev->devfn);
1282 }
1283
1284 enum {
1285 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1286 };
1287
1288 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1289
mlx5_get_roce_state(struct mlx5_core_dev * dev)1290 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1291 {
1292 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1293 return MLX5_CAP_GEN(dev, roce);
1294
1295 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1296 * in order to support RoCE enable/disable feature
1297 */
1298 return mlx5_is_roce_on(dev);
1299 }
1300
1301 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1302 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1303 {
1304 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1305 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1306 return false;
1307
1308 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1309 return false;
1310
1311 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1312 return false;
1313
1314 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1315 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1316 return false;
1317
1318 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1319 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1320 return false;
1321
1322 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1323 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1324 return false;
1325
1326 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1327 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1328 return false;
1329
1330 return true;
1331 }
1332
1333 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1334
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1335 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1336 {
1337 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1338 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1339 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1340 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1341 return false;
1342
1343 return true;
1344 }
1345 #endif
1346
1347 enum {
1348 MLX5_OCTWORD = 16,
1349 };
1350
1351 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1352 #endif /* MLX5_DRIVER_H */
1353