1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31 #include "opt_uart.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
40
41 #ifdef FDT
42 #include <dev/fdt/fdt_common.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #endif
46
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
49 #ifdef FDT
50 #include <dev/uart/uart_cpu_fdt.h>
51 #endif
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/uart/uart_ppstypes.h>
55 #ifdef DEV_ACPI
56 #include <dev/uart/uart_cpu_acpi.h>
57 #include <contrib/dev/acpica/include/acpi.h>
58 #endif
59
60 #include <dev/ic/ns16550.h>
61
62 #include "uart_if.h"
63
64 #define DEFAULT_RCLK 1843200
65
66 /*
67 * Set the default baudrate tolerance to 3.0%.
68 *
69 * Some embedded boards have odd reference clocks (eg 25MHz)
70 * and we need to handle higher variances in the target baud rate.
71 */
72 #ifndef UART_DEV_TOLERANCE_PCT
73 #define UART_DEV_TOLERANCE_PCT 30
74 #endif /* UART_DEV_TOLERANCE_PCT */
75
76 static int broken_txfifo = 0;
77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
79
80 /*
81 * To use early printf on x86, add the following to your kernel config:
82 *
83 * options UART_NS8250_EARLY_PORT=0x3f8
84 * options EARLY_PRINTF=ns8250
85 */
86 #if CHECK_EARLY_PRINTF(ns8250)
87 #if !(defined(__amd64__) || defined(__i386__))
88 #error ns8250 early putc is x86 specific as it uses inb/outb
89 #endif
90 static void
uart_ns8250_early_putc(int c)91 uart_ns8250_early_putc(int c)
92 {
93 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR;
94 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA;
95 int limit = 10000; /* 10ms is plenty of time */
96
97 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0)
98 continue;
99 outb(tx, c);
100 }
101 early_putc_t *early_putc = uart_ns8250_early_putc;
102 #endif /* EARLY_PRINTF */
103
104 /*
105 * Clear pending interrupts. THRE is cleared by reading IIR. Data
106 * that may have been received gets lost here.
107 */
108 static void
ns8250_clrint(struct uart_bas * bas)109 ns8250_clrint(struct uart_bas *bas)
110 {
111 uint8_t iir, lsr;
112
113 iir = uart_getreg(bas, REG_IIR);
114 while ((iir & IIR_NOPEND) == 0) {
115 iir &= IIR_IMASK;
116 if (iir == IIR_RLS) {
117 lsr = uart_getreg(bas, REG_LSR);
118 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
119 (void)uart_getreg(bas, REG_DATA);
120 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
121 (void)uart_getreg(bas, REG_DATA);
122 else if (iir == IIR_MLSC)
123 (void)uart_getreg(bas, REG_MSR);
124 uart_barrier(bas);
125 iir = uart_getreg(bas, REG_IIR);
126 }
127 }
128
129 static uint32_t
ns8250_get_divisor(struct uart_bas * bas)130 ns8250_get_divisor(struct uart_bas *bas)
131 {
132 uint32_t divisor;
133 uint8_t lcr;
134
135 lcr = uart_getreg(bas, REG_LCR);
136 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
137 uart_barrier(bas);
138 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
139 uart_barrier(bas);
140 uart_setreg(bas, REG_LCR, lcr);
141 uart_barrier(bas);
142
143 return (divisor);
144 }
145
146 static int
ns8250_delay(struct uart_bas * bas)147 ns8250_delay(struct uart_bas *bas)
148 {
149 int divisor;
150
151 divisor = ns8250_get_divisor(bas);
152
153 /* 1/10th the time to transmit 1 character (estimate). */
154 if (divisor <= 134)
155 return (16000000 * divisor / bas->rclk);
156 return (16000 * divisor / (bas->rclk / 1000));
157 }
158
159 static int
ns8250_divisor(int rclk,int baudrate)160 ns8250_divisor(int rclk, int baudrate)
161 {
162 int actual_baud, divisor;
163 int error;
164
165 if (baudrate == 0)
166 return (0);
167
168 divisor = (rclk / (baudrate << 3) + 1) >> 1;
169 if (divisor == 0 || divisor >= 65536)
170 return (0);
171 actual_baud = rclk / (divisor << 4);
172
173 /* 10 times error in percent: */
174 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
175
176 /* enforce maximum error tolerance: */
177 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
178 return (0);
179
180 return (divisor);
181 }
182
183 static int
ns8250_drain(struct uart_bas * bas,int what)184 ns8250_drain(struct uart_bas *bas, int what)
185 {
186 int delay, limit;
187
188 delay = ns8250_delay(bas);
189
190 if (what & UART_DRAIN_TRANSMITTER) {
191 /*
192 * Pick an arbitrary high limit to avoid getting stuck in
193 * an infinite loop when the hardware is broken. Make the
194 * limit high enough to handle large FIFOs.
195 */
196 limit = 10*1024;
197 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
198 DELAY(delay);
199 if (limit == 0) {
200 /* printf("uart: ns8250: transmitter appears stuck... "); */
201 return (EIO);
202 }
203 }
204
205 if (what & UART_DRAIN_RECEIVER) {
206 /*
207 * Pick an arbitrary high limit to avoid getting stuck in
208 * an infinite loop when the hardware is broken. Make the
209 * limit high enough to handle large FIFOs and integrated
210 * UARTs. The HP rx2600 for example has 3 UARTs on the
211 * management board that tend to get a lot of data send
212 * to it when the UART is first activated. Assume that we
213 * have finished draining if LSR_RXRDY is not asserted both
214 * prior to and after a DELAY; but as long as LSR_RXRDY is
215 * asserted, read (and discard) characters as quickly as
216 * possible.
217 */
218 limit=10*4096;
219 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
220 do {
221 (void)uart_getreg(bas, REG_DATA);
222 uart_barrier(bas);
223 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit);
224 uart_barrier(bas);
225 DELAY(delay << 2);
226 }
227 if (limit == 0) {
228 /* printf("uart: ns8250: receiver appears broken... "); */
229 return (EIO);
230 }
231 }
232
233 return (0);
234 }
235
236 /*
237 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
238 * drained. WARNING: this function clobbers the FIFO setting!
239 */
240 static void
ns8250_flush(struct uart_bas * bas,int what)241 ns8250_flush(struct uart_bas *bas, int what)
242 {
243 uint8_t fcr;
244 uint8_t lsr;
245 int drain = 0;
246
247 fcr = FCR_ENABLE;
248 if (what & UART_FLUSH_TRANSMITTER)
249 fcr |= FCR_XMT_RST;
250 if (what & UART_FLUSH_RECEIVER)
251 fcr |= FCR_RCV_RST;
252 uart_setreg(bas, REG_FCR, fcr);
253 uart_barrier(bas);
254
255 /*
256 * Detect and work around emulated UARTs which don't implement the
257 * FCR register; on these systems we need to drain the FIFO since
258 * the flush we request doesn't happen. One such system is the
259 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code:
260 * https://github.com/rust-vmm/vm-superio/issues/83
261 */
262 lsr = uart_getreg(bas, REG_LSR);
263 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER))
264 drain |= UART_DRAIN_TRANSMITTER;
265 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER))
266 drain |= UART_DRAIN_RECEIVER;
267 if (drain != 0) {
268 printf("uart: ns8250: UART FCR is broken\n");
269 ns8250_drain(bas, drain);
270 }
271 }
272
273 static int
ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)274 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
275 int parity)
276 {
277 int divisor;
278 uint8_t lcr;
279
280 /* Don't change settings when running on Hyper-V */
281 if (vm_guest == VM_GUEST_HV)
282 return (0);
283
284 lcr = 0;
285 if (databits >= 8)
286 lcr |= LCR_8BITS;
287 else if (databits == 7)
288 lcr |= LCR_7BITS;
289 else if (databits == 6)
290 lcr |= LCR_6BITS;
291 else
292 lcr |= LCR_5BITS;
293 if (stopbits > 1)
294 lcr |= LCR_STOPB;
295 lcr |= parity << 3;
296
297 /* Set baudrate if we know a rclk and both are not 0. */
298 if (baudrate > 0 && bas->rclk > 0) {
299 divisor = ns8250_divisor(bas->rclk, baudrate);
300 if (divisor == 0)
301 return (EINVAL);
302 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
303 uart_barrier(bas);
304 uart_setreg(bas, REG_DLL, divisor & 0xff);
305 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
306 uart_barrier(bas);
307 }
308
309 /* Set LCR and clear DLAB. */
310 uart_setreg(bas, REG_LCR, lcr);
311 uart_barrier(bas);
312 return (0);
313 }
314
315 /*
316 * Low-level UART interface.
317 */
318 static int ns8250_probe(struct uart_bas *bas);
319 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
320 static void ns8250_term(struct uart_bas *bas);
321 static void ns8250_putc(struct uart_bas *bas, int);
322 static int ns8250_rxready(struct uart_bas *bas);
323 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
324
325 struct uart_ops uart_ns8250_ops = {
326 .probe = ns8250_probe,
327 .init = ns8250_init,
328 .term = ns8250_term,
329 .putc = ns8250_putc,
330 .rxready = ns8250_rxready,
331 .getc = ns8250_getc,
332 };
333
334 static int
ns8250_probe(struct uart_bas * bas)335 ns8250_probe(struct uart_bas *bas)
336 {
337 u_char val;
338
339 /* Check known 0 bits that don't depend on DLAB. */
340 val = uart_getreg(bas, REG_IIR);
341 if (val & 0x30)
342 return (ENXIO);
343 /*
344 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
345 * chip, but otherwise doesn't seem to have a function. In
346 * other words, uart(4) works regardless. Ignore that bit so
347 * the probe succeeds.
348 */
349 val = uart_getreg(bas, REG_MCR);
350 if (val & 0xa0)
351 return (ENXIO);
352
353 return (0);
354 }
355
356 static void
ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)357 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
358 int parity)
359 {
360 u_char ier;
361
362 /* Disable all interrupt sources. */
363 /*
364 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
365 * UARTs split the receive time-out interrupt bit out separately as
366 * 0x10. This gets handled by ier_mask and ier_rxbits below.
367 */
368 ier = uart_getreg(bas, REG_IER) & 0xe0;
369 uart_setreg(bas, REG_IER, ier);
370 uart_barrier(bas);
371
372 /*
373 * Loader tells us to infer the rclk when it sets xo to 0 in
374 * hw.uart.console. We know the baudrate was set by the firmware, so
375 * calculate rclk from baudrate and the divisor register. If 'div' is
376 * actually 0, the resulting 0 value will have us fall back to other
377 * rclk methods.
378 */
379 if (bas->rclk_guess && bas->rclk == 0 && baudrate != 0) {
380 uint32_t div;
381
382 div = ns8250_get_divisor(bas);
383 bas->rclk = baudrate * div * 16;
384 }
385
386 /*
387 * Pick a default because we just don't know. This likely needs future
388 * refinement, but that's hard outside of consoles to know what to use.
389 * But defer as long as possible if there's no defined baud rate.
390 */
391 if (bas->rclk == 0 && baudrate != 0)
392 bas->rclk = DEFAULT_RCLK;
393
394 ns8250_param(bas, baudrate, databits, stopbits, parity);
395
396 /* Disable the FIFO (if present). */
397 uart_setreg(bas, REG_FCR, 0);
398 uart_barrier(bas);
399
400 /* Set RTS & DTR. */
401 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
402 uart_barrier(bas);
403
404 ns8250_clrint(bas);
405 }
406
407 static void
ns8250_term(struct uart_bas * bas)408 ns8250_term(struct uart_bas *bas)
409 {
410
411 /* Clear RTS & DTR. */
412 uart_setreg(bas, REG_MCR, MCR_IE);
413 uart_barrier(bas);
414 }
415
416 static void
ns8250_putc(struct uart_bas * bas,int c)417 ns8250_putc(struct uart_bas *bas, int c)
418 {
419 int limit;
420
421 if (vm_guest != VM_GUEST_HV) {
422 limit = 250000;
423 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
424 DELAY(4);
425 }
426 uart_setreg(bas, REG_DATA, c);
427 uart_barrier(bas);
428 }
429
430 static int
ns8250_rxready(struct uart_bas * bas)431 ns8250_rxready(struct uart_bas *bas)
432 {
433
434 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
435 }
436
437 static int
ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)438 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
439 {
440 int c;
441
442 uart_lock(hwmtx);
443
444 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
445 uart_unlock(hwmtx);
446 DELAY(4);
447 uart_lock(hwmtx);
448 }
449
450 c = uart_getreg(bas, REG_DATA);
451
452 uart_unlock(hwmtx);
453
454 return (c);
455 }
456
457 static kobj_method_t ns8250_methods[] = {
458 KOBJMETHOD(uart_attach, ns8250_bus_attach),
459 KOBJMETHOD(uart_detach, ns8250_bus_detach),
460 KOBJMETHOD(uart_flush, ns8250_bus_flush),
461 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
462 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
463 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
464 KOBJMETHOD(uart_param, ns8250_bus_param),
465 KOBJMETHOD(uart_probe, ns8250_bus_probe),
466 KOBJMETHOD(uart_receive, ns8250_bus_receive),
467 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
468 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
469 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy),
470 KOBJMETHOD(uart_grab, ns8250_bus_grab),
471 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
472 KOBJMETHOD_END
473 };
474
475 struct uart_class uart_ns8250_class = {
476 "ns8250",
477 ns8250_methods,
478 sizeof(struct ns8250_softc),
479 .uc_ops = &uart_ns8250_ops,
480 .uc_range = 8,
481 .uc_rclk = DEFAULT_RCLK,
482 .uc_rshift = 0
483 };
484 UART_CLASS(uart_ns8250_class);
485
486 /*
487 * XXX -- refactor out ACPI and FDT ifdefs
488 */
489 #ifdef DEV_ACPI
490 static struct acpi_uart_compat_data acpi_compat_data[] = {
491 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
492 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
493 {"APMC0D08", &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE, 2, 4, 0, 0, "APM compatible UART"},
494 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
495 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
496 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
497 {"INTC1006", &uart_ns8250_class, 0, 2, 0, 25000000, 0, "Intel ARM64 UART"},
498 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"},
499 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
500 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
501 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
502 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
503 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
504 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
505 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
506 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
507 {NULL, NULL, 0, 0 , 0, 0, 0, NULL},
508 };
509 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
510 #endif
511
512 #ifdef FDT
513 static struct ofw_compat_data compat_data[] = {
514 {"ns16550", (uintptr_t)&uart_ns8250_class},
515 {"ns16550a", (uintptr_t)&uart_ns8250_class},
516 {NULL, (uintptr_t)NULL},
517 };
518 UART_FDT_CLASS_AND_DEVICE(compat_data);
519 #endif
520
521 /* Use token-pasting to form SER_ and MSR_ named constants. */
522 #define SER(sig) SER_##sig
523 #define SERD(sig) SER_D##sig
524 #define MSR(sig) MSR_##sig
525 #define MSRD(sig) MSR_D##sig
526
527 /*
528 * Detect signal changes using software delta detection. The previous state of
529 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
530 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
531 * new state of both the signal and the delta bits.
532 */
533 #define SIGCHGSW(var, msr, sig) \
534 if ((msr) & MSR(sig)) { \
535 if ((var & SER(sig)) == 0) \
536 var |= SERD(sig) | SER(sig); \
537 } else { \
538 if ((var & SER(sig)) != 0) \
539 var = SERD(sig) | (var & ~SER(sig)); \
540 }
541
542 /*
543 * Detect signal changes using the hardware msr delta bits. This is currently
544 * used only when PPS timing information is being captured using the "narrow
545 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
546 * by time the interrupt handler is invoked. The hardware will latch the fact
547 * that it changed in the delta bits.
548 */
549 #define SIGCHGHW(var, msr, sig) \
550 if ((msr) & MSRD(sig)) { \
551 if (((msr) & MSR(sig)) != 0) \
552 var |= SERD(sig) | SER(sig); \
553 else \
554 var = SERD(sig) | (var & ~SER(sig)); \
555 }
556
557 int
ns8250_bus_attach(struct uart_softc * sc)558 ns8250_bus_attach(struct uart_softc *sc)
559 {
560 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
561 struct uart_bas *bas;
562 unsigned int ivar;
563 #ifdef FDT
564 phandle_t node;
565 pcell_t cell;
566 #endif
567
568 #ifdef FDT
569 /* Check whether uart has a broken txfifo. */
570 node = ofw_bus_get_node(sc->sc_dev);
571 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
572 broken_txfifo = cell ? 1 : 0;
573 #endif
574
575 bas = &sc->sc_bas;
576
577 ns8250->busy_detect = bas->busy_detect;
578 ns8250->mcr = uart_getreg(bas, REG_MCR);
579 ns8250->fcr = FCR_ENABLE;
580 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
581 &ivar)) {
582 if (UART_FLAGS_FCR_RX_LOW(ivar))
583 ns8250->fcr |= FCR_RX_LOW;
584 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
585 ns8250->fcr |= FCR_RX_MEDL;
586 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
587 ns8250->fcr |= FCR_RX_HIGH;
588 else
589 ns8250->fcr |= FCR_RX_MEDH;
590 } else
591 ns8250->fcr |= FCR_RX_MEDH;
592
593 /* Get IER mask */
594 ivar = 0xf0;
595 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
596 &ivar);
597 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
598
599 /* Get IER RX interrupt bits */
600 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
601 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
602 &ivar);
603 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
604
605 uart_setreg(bas, REG_FCR, ns8250->fcr);
606 uart_barrier(bas);
607 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
608
609 if (ns8250->mcr & MCR_DTR)
610 sc->sc_hwsig |= SER_DTR;
611 if (ns8250->mcr & MCR_RTS)
612 sc->sc_hwsig |= SER_RTS;
613 ns8250_bus_getsig(sc);
614
615 ns8250_clrint(bas);
616 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
617 ns8250->ier |= ns8250->ier_rxbits;
618 uart_setreg(bas, REG_IER, ns8250->ier);
619 uart_barrier(bas);
620
621 /*
622 * Timing of the H/W access was changed with r253161 of uart_core.c
623 * It has been observed that an ITE IT8513E would signal a break
624 * condition with pretty much every character it received, unless
625 * it had enough time to settle between ns8250_bus_attach() and
626 * ns8250_bus_ipend() -- which it accidentally had before r253161.
627 * It's not understood why the UART chip behaves this way and it
628 * could very well be that the DELAY make the H/W work in the same
629 * accidental manner as before. More analysis is warranted, but
630 * at least now we fixed a known regression.
631 */
632 DELAY(200);
633 return (0);
634 }
635
636 int
ns8250_bus_detach(struct uart_softc * sc)637 ns8250_bus_detach(struct uart_softc *sc)
638 {
639 struct ns8250_softc *ns8250;
640 struct uart_bas *bas;
641 u_char ier;
642
643 ns8250 = (struct ns8250_softc *)sc;
644 bas = &sc->sc_bas;
645 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
646 uart_setreg(bas, REG_IER, ier);
647 uart_barrier(bas);
648 ns8250_clrint(bas);
649 return (0);
650 }
651
652 int
ns8250_bus_flush(struct uart_softc * sc,int what)653 ns8250_bus_flush(struct uart_softc *sc, int what)
654 {
655 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
656 struct uart_bas *bas;
657 int error;
658
659 bas = &sc->sc_bas;
660 uart_lock(sc->sc_hwmtx);
661 if (sc->sc_rxfifosz > 1) {
662 ns8250_flush(bas, what);
663 uart_setreg(bas, REG_FCR, ns8250->fcr);
664 uart_barrier(bas);
665 error = 0;
666 } else
667 error = ns8250_drain(bas, what);
668 uart_unlock(sc->sc_hwmtx);
669 return (error);
670 }
671
672 int
ns8250_bus_getsig(struct uart_softc * sc)673 ns8250_bus_getsig(struct uart_softc *sc)
674 {
675 uint32_t old, sig;
676 uint8_t msr;
677
678 /*
679 * The delta bits are reputed to be broken on some hardware, so use
680 * software delta detection by default. Use the hardware delta bits
681 * when capturing PPS pulses which are too narrow for software detection
682 * to see the edges. Hardware delta for RI doesn't work like the
683 * others, so always use software for it. Other threads may be changing
684 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
685 * update without other changes happening. Note that the SIGCHGxx()
686 * macros carefully preserve the delta bits when we have to loop several
687 * times and a signal transitions between iterations.
688 */
689 do {
690 old = sc->sc_hwsig;
691 sig = old;
692 uart_lock(sc->sc_hwmtx);
693 msr = uart_getreg(&sc->sc_bas, REG_MSR);
694 uart_unlock(sc->sc_hwmtx);
695 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
696 SIGCHGHW(sig, msr, DSR);
697 SIGCHGHW(sig, msr, CTS);
698 SIGCHGHW(sig, msr, DCD);
699 } else {
700 SIGCHGSW(sig, msr, DSR);
701 SIGCHGSW(sig, msr, CTS);
702 SIGCHGSW(sig, msr, DCD);
703 }
704 SIGCHGSW(sig, msr, RI);
705 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
706 return (sig);
707 }
708
709 int
ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)710 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
711 {
712 struct uart_bas *bas;
713 int baudrate, divisor, error;
714 uint8_t efr, lcr;
715
716 bas = &sc->sc_bas;
717 error = 0;
718 uart_lock(sc->sc_hwmtx);
719 switch (request) {
720 case UART_IOCTL_BREAK:
721 lcr = uart_getreg(bas, REG_LCR);
722 if (data)
723 lcr |= LCR_SBREAK;
724 else
725 lcr &= ~LCR_SBREAK;
726 uart_setreg(bas, REG_LCR, lcr);
727 uart_barrier(bas);
728 break;
729 case UART_IOCTL_IFLOW:
730 lcr = uart_getreg(bas, REG_LCR);
731 uart_barrier(bas);
732 uart_setreg(bas, REG_LCR, 0xbf);
733 uart_barrier(bas);
734 efr = uart_getreg(bas, REG_EFR);
735 if (data)
736 efr |= EFR_RTS;
737 else
738 efr &= ~EFR_RTS;
739 uart_setreg(bas, REG_EFR, efr);
740 uart_barrier(bas);
741 uart_setreg(bas, REG_LCR, lcr);
742 uart_barrier(bas);
743 break;
744 case UART_IOCTL_OFLOW:
745 lcr = uart_getreg(bas, REG_LCR);
746 uart_barrier(bas);
747 uart_setreg(bas, REG_LCR, 0xbf);
748 uart_barrier(bas);
749 efr = uart_getreg(bas, REG_EFR);
750 if (data)
751 efr |= EFR_CTS;
752 else
753 efr &= ~EFR_CTS;
754 uart_setreg(bas, REG_EFR, efr);
755 uart_barrier(bas);
756 uart_setreg(bas, REG_LCR, lcr);
757 uart_barrier(bas);
758 break;
759 case UART_IOCTL_BAUD:
760 divisor = ns8250_get_divisor(bas);
761 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
762 if (baudrate > 0)
763 *(int*)data = baudrate;
764 else
765 error = ENXIO;
766 break;
767 default:
768 error = EINVAL;
769 break;
770 }
771 uart_unlock(sc->sc_hwmtx);
772 return (error);
773 }
774
775 int
ns8250_bus_ipend(struct uart_softc * sc)776 ns8250_bus_ipend(struct uart_softc *sc)
777 {
778 struct uart_bas *bas;
779 struct ns8250_softc *ns8250;
780 int ipend;
781 uint8_t iir, lsr;
782
783 ns8250 = (struct ns8250_softc *)sc;
784 bas = &sc->sc_bas;
785 uart_lock(sc->sc_hwmtx);
786 iir = uart_getreg(bas, REG_IIR);
787
788 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
789 (void)uart_getreg(bas, DW_REG_USR);
790 uart_unlock(sc->sc_hwmtx);
791 return (0);
792 }
793 if (iir & IIR_NOPEND) {
794 uart_unlock(sc->sc_hwmtx);
795 return (0);
796 }
797 ipend = 0;
798 if (iir & IIR_RXRDY) {
799 lsr = uart_getreg(bas, REG_LSR);
800 if (lsr & LSR_OE)
801 ipend |= SER_INT_OVERRUN;
802 if (lsr & LSR_BI)
803 ipend |= SER_INT_BREAK;
804 if (lsr & LSR_RXRDY)
805 ipend |= SER_INT_RXREADY;
806 } else {
807 if (iir & IIR_TXRDY) {
808 ipend |= SER_INT_TXIDLE;
809 ns8250->ier &= ~IER_ETXRDY;
810 uart_setreg(bas, REG_IER, ns8250->ier);
811 uart_barrier(bas);
812 } else
813 ipend |= SER_INT_SIGCHG;
814 }
815 if (ipend == 0)
816 ns8250_clrint(bas);
817 uart_unlock(sc->sc_hwmtx);
818 return (ipend);
819 }
820
821 int
ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)822 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
823 int stopbits, int parity)
824 {
825 struct ns8250_softc *ns8250;
826 struct uart_bas *bas;
827 int error, limit;
828
829 ns8250 = (struct ns8250_softc*)sc;
830 bas = &sc->sc_bas;
831 uart_lock(sc->sc_hwmtx);
832 /*
833 * When using DW UART with BUSY detection it is necessary to wait
834 * until all serial transfers are finished before manipulating the
835 * line control. LCR will not be affected when UART is busy.
836 */
837 if (ns8250->busy_detect != 0) {
838 /*
839 * Pick an arbitrary high limit to avoid getting stuck in
840 * an infinite loop in case when the hardware is broken.
841 */
842 limit = 10 * 1024;
843 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
844 --limit)
845 DELAY(4);
846
847 if (limit <= 0) {
848 /* UART appears to be stuck */
849 uart_unlock(sc->sc_hwmtx);
850 return (EIO);
851 }
852 }
853
854 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
855 uart_unlock(sc->sc_hwmtx);
856 return (error);
857 }
858
859 int
ns8250_bus_probe(struct uart_softc * sc)860 ns8250_bus_probe(struct uart_softc *sc)
861 {
862 struct uart_bas *bas;
863 int count, delay, error, limit;
864 uint8_t lsr, mcr, ier;
865
866 bas = &sc->sc_bas;
867
868 error = ns8250_probe(bas);
869 if (error)
870 return (error);
871
872 mcr = MCR_IE;
873 if (sc->sc_sysdev == NULL) {
874 /* By using ns8250_init() we also set DTR and RTS. */
875 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
876 } else
877 mcr |= MCR_DTR | MCR_RTS;
878
879 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
880 if (error)
881 return (error);
882
883 /*
884 * Set loopback mode. This avoids having garbage on the wire and
885 * also allows us send and receive data. We set DTR and RTS to
886 * avoid the possibility that automatic flow-control prevents
887 * any data from being sent.
888 */
889 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
890 uart_barrier(bas);
891
892 /*
893 * Enable FIFOs. And check that the UART has them. If not, we're
894 * done. Since this is the first time we enable the FIFOs, we reset
895 * them.
896 */
897 uart_setreg(bas, REG_FCR, FCR_ENABLE);
898 uart_barrier(bas);
899 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
900 /*
901 * NS16450 or INS8250. We don't bother to differentiate
902 * between them. They're too old to be interesting.
903 */
904 uart_setreg(bas, REG_MCR, mcr);
905 uart_barrier(bas);
906 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
907 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
908 return (0);
909 }
910
911 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
912 uart_barrier(bas);
913
914 count = 0;
915 delay = ns8250_delay(bas);
916
917 /* We have FIFOs. Drain the transmitter and receiver. */
918 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
919 if (error) {
920 uart_setreg(bas, REG_MCR, mcr);
921 uart_setreg(bas, REG_FCR, 0);
922 uart_barrier(bas);
923 goto describe;
924 }
925
926 /*
927 * We should have a sufficiently clean "pipe" to determine the
928 * size of the FIFOs. We send as much characters as is reasonable
929 * and wait for the overflow bit in the LSR register to be
930 * asserted, counting the characters as we send them. Based on
931 * that count we know the FIFO size.
932 */
933 do {
934 uart_setreg(bas, REG_DATA, 0);
935 uart_barrier(bas);
936 count++;
937
938 limit = 30;
939 lsr = 0;
940 /*
941 * LSR bits are cleared upon read, so we must accumulate
942 * them to be able to test LSR_OE below.
943 */
944 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
945 --limit)
946 DELAY(delay);
947 if (limit == 0) {
948 /* See the comment in ns8250_init(). */
949 ier = uart_getreg(bas, REG_IER) & 0xe0;
950 uart_setreg(bas, REG_IER, ier);
951 uart_setreg(bas, REG_MCR, mcr);
952 uart_setreg(bas, REG_FCR, 0);
953 uart_barrier(bas);
954 count = 0;
955 goto describe;
956 }
957 } while ((lsr & LSR_OE) == 0 && count < 260);
958 count--;
959
960 uart_setreg(bas, REG_MCR, mcr);
961
962 /* Reset FIFOs. */
963 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
964
965 describe:
966 if (count >= 14 && count <= 16) {
967 sc->sc_rxfifosz = 16;
968 device_set_desc(sc->sc_dev, "16550 or compatible");
969 } else if (count >= 28 && count <= 32) {
970 sc->sc_rxfifosz = 32;
971 device_set_desc(sc->sc_dev, "16650 or compatible");
972 } else if (count >= 56 && count <= 64) {
973 sc->sc_rxfifosz = 64;
974 device_set_desc(sc->sc_dev, "16750 or compatible");
975 } else if (count >= 112 && count <= 128) {
976 sc->sc_rxfifosz = 128;
977 device_set_desc(sc->sc_dev, "16950 or compatible");
978 } else if (count >= 224 && count <= 256) {
979 sc->sc_rxfifosz = 256;
980 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
981 } else {
982 sc->sc_rxfifosz = 16;
983 device_set_desc(sc->sc_dev,
984 "Non-standard ns8250 class UART with FIFOs");
985 }
986
987 /*
988 * Force the Tx FIFO size to 16 bytes for now. We don't program the
989 * Tx trigger. Also, we assume that all data has been sent when the
990 * interrupt happens.
991 */
992 sc->sc_txfifosz = 16;
993
994 #if 0
995 /*
996 * XXX there are some issues related to hardware flow control and
997 * it's likely that uart(4) is the cause. This basically needs more
998 * investigation, but we avoid using for hardware flow control
999 * until then.
1000 */
1001 /* 16650s or higher have automatic flow control. */
1002 if (sc->sc_rxfifosz > 16) {
1003 sc->sc_hwiflow = 1;
1004 sc->sc_hwoflow = 1;
1005 }
1006 #endif
1007
1008 return (0);
1009 }
1010
1011 int
ns8250_bus_receive(struct uart_softc * sc)1012 ns8250_bus_receive(struct uart_softc *sc)
1013 {
1014 struct uart_bas *bas;
1015 int xc;
1016 uint8_t lsr;
1017
1018 bas = &sc->sc_bas;
1019 uart_lock(sc->sc_hwmtx);
1020 lsr = uart_getreg(bas, REG_LSR);
1021 while (lsr & LSR_RXRDY) {
1022 if (uart_rx_full(sc)) {
1023 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
1024 break;
1025 }
1026 xc = uart_getreg(bas, REG_DATA);
1027 if (lsr & LSR_FE)
1028 xc |= UART_STAT_FRAMERR;
1029 if (lsr & LSR_PE)
1030 xc |= UART_STAT_PARERR;
1031 uart_rx_put(sc, xc);
1032 lsr = uart_getreg(bas, REG_LSR);
1033 }
1034 /* Discard everything left in the Rx FIFO. */
1035 while (lsr & LSR_RXRDY) {
1036 (void)uart_getreg(bas, REG_DATA);
1037 uart_barrier(bas);
1038 lsr = uart_getreg(bas, REG_LSR);
1039 }
1040 uart_unlock(sc->sc_hwmtx);
1041 return (0);
1042 }
1043
1044 int
ns8250_bus_setsig(struct uart_softc * sc,int sig)1045 ns8250_bus_setsig(struct uart_softc *sc, int sig)
1046 {
1047 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1048 struct uart_bas *bas;
1049 uint32_t new, old;
1050
1051 bas = &sc->sc_bas;
1052 do {
1053 old = sc->sc_hwsig;
1054 new = old;
1055 if (sig & SER_DDTR) {
1056 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
1057 }
1058 if (sig & SER_DRTS) {
1059 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
1060 }
1061 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
1062 uart_lock(sc->sc_hwmtx);
1063 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
1064 if (new & SER_DTR)
1065 ns8250->mcr |= MCR_DTR;
1066 if (new & SER_RTS)
1067 ns8250->mcr |= MCR_RTS;
1068 uart_setreg(bas, REG_MCR, ns8250->mcr);
1069 uart_barrier(bas);
1070 uart_unlock(sc->sc_hwmtx);
1071 return (0);
1072 }
1073
1074 int
ns8250_bus_transmit(struct uart_softc * sc)1075 ns8250_bus_transmit(struct uart_softc *sc)
1076 {
1077 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1078 struct uart_bas *bas;
1079 int i;
1080
1081 bas = &sc->sc_bas;
1082 uart_lock(sc->sc_hwmtx);
1083 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1084 DELAY(4);
1085 for (i = 0; i < sc->sc_txdatasz; i++) {
1086 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1087 uart_barrier(bas);
1088 }
1089 if (!broken_txfifo)
1090 ns8250->ier |= IER_ETXRDY;
1091 uart_setreg(bas, REG_IER, ns8250->ier);
1092 uart_barrier(bas);
1093 if (broken_txfifo)
1094 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1095 else
1096 sc->sc_txbusy = 1;
1097 uart_unlock(sc->sc_hwmtx);
1098 if (broken_txfifo)
1099 uart_sched_softih(sc, SER_INT_TXIDLE);
1100 return (0);
1101 }
1102
1103 bool
ns8250_bus_txbusy(struct uart_softc * sc)1104 ns8250_bus_txbusy(struct uart_softc *sc)
1105 {
1106 struct uart_bas *bas = &sc->sc_bas;
1107
1108 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=
1109 (LSR_TEMT | LSR_THRE))
1110 return (true);
1111 return (false);
1112 }
1113
1114 void
ns8250_bus_grab(struct uart_softc * sc)1115 ns8250_bus_grab(struct uart_softc *sc)
1116 {
1117 struct uart_bas *bas = &sc->sc_bas;
1118 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1119 u_char ier;
1120
1121 /*
1122 * turn off all interrupts to enter polling mode. Leave the
1123 * saved mask alone. We'll restore whatever it was in ungrab.
1124 * All pending interrupt signals are reset when IER is set to 0.
1125 */
1126 uart_lock(sc->sc_hwmtx);
1127 ier = uart_getreg(bas, REG_IER);
1128 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1129 uart_barrier(bas);
1130 uart_unlock(sc->sc_hwmtx);
1131 }
1132
1133 void
ns8250_bus_ungrab(struct uart_softc * sc)1134 ns8250_bus_ungrab(struct uart_softc *sc)
1135 {
1136 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1137 struct uart_bas *bas = &sc->sc_bas;
1138
1139 /*
1140 * Restore previous interrupt mask
1141 */
1142 uart_lock(sc->sc_hwmtx);
1143 uart_setreg(bas, REG_IER, ns8250->ier);
1144 uart_barrier(bas);
1145 uart_unlock(sc->sc_hwmtx);
1146 }
1147