1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31 #include "opt_uart.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
40
41 #ifdef FDT
42 #include <dev/fdt/fdt_common.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #endif
46
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
49 #ifdef FDT
50 #include <dev/uart/uart_cpu_fdt.h>
51 #endif
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/uart/uart_ppstypes.h>
55 #ifdef DEV_ACPI
56 #include <dev/uart/uart_cpu_acpi.h>
57 #include <contrib/dev/acpica/include/acpi.h>
58 #endif
59
60 #include <dev/ic/ns16550.h>
61
62 #include "uart_if.h"
63
64 #define DEFAULT_RCLK 1843200
65
66 /*
67 * Set the default baudrate tolerance to 3.0%.
68 *
69 * Some embedded boards have odd reference clocks (eg 25MHz)
70 * and we need to handle higher variances in the target baud rate.
71 */
72 #ifndef UART_DEV_TOLERANCE_PCT
73 #define UART_DEV_TOLERANCE_PCT 30
74 #endif /* UART_DEV_TOLERANCE_PCT */
75
76 static int broken_txfifo = 0;
77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
79
80 static int uart_noise_threshold = 0;
81 SYSCTL_INT(_hw, OID_AUTO, uart_noise_threshold, CTLFLAG_RWTUN,
82 &uart_noise_threshold, 0,
83 "Number of UART RX interrupts where TX is not ready, before data is discarded");
84
85 /*
86 * To use early printf on x86, add the following to your kernel config:
87 *
88 * options UART_NS8250_EARLY_PORT=0x3f8
89 * options EARLY_PRINTF=ns8250
90 */
91 #if CHECK_EARLY_PRINTF(ns8250)
92 #if !(defined(__amd64__) || defined(__i386__))
93 #error ns8250 early putc is x86 specific as it uses inb/outb
94 #endif
95 static void
uart_ns8250_early_putc(int c)96 uart_ns8250_early_putc(int c)
97 {
98 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR;
99 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA;
100 int limit = 10000; /* 10ms is plenty of time */
101
102 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0)
103 continue;
104 outb(tx, c);
105 }
106 early_putc_t *early_putc = uart_ns8250_early_putc;
107 #endif /* EARLY_PRINTF */
108
109 /*
110 * Clear pending interrupts. THRE is cleared by reading IIR. Data
111 * that may have been received gets lost here.
112 */
113 static void
ns8250_clrint(struct uart_bas * bas)114 ns8250_clrint(struct uart_bas *bas)
115 {
116 uint8_t iir, lsr;
117
118 iir = uart_getreg(bas, REG_IIR);
119 while ((iir & IIR_NOPEND) == 0) {
120 iir &= IIR_IMASK;
121 if (iir == IIR_RLS) {
122 lsr = uart_getreg(bas, REG_LSR);
123 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
124 (void)uart_getreg(bas, REG_DATA);
125 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
126 (void)uart_getreg(bas, REG_DATA);
127 else if (iir == IIR_MLSC)
128 (void)uart_getreg(bas, REG_MSR);
129 uart_barrier(bas);
130 iir = uart_getreg(bas, REG_IIR);
131 }
132 }
133
134 static uint32_t
ns8250_get_divisor(struct uart_bas * bas)135 ns8250_get_divisor(struct uart_bas *bas)
136 {
137 uint32_t divisor;
138 uint8_t lcr;
139
140 lcr = uart_getreg(bas, REG_LCR);
141 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
142 uart_barrier(bas);
143 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
144 uart_barrier(bas);
145 uart_setreg(bas, REG_LCR, lcr);
146 uart_barrier(bas);
147
148 return (divisor);
149 }
150
151 static int
ns8250_delay(struct uart_bas * bas)152 ns8250_delay(struct uart_bas *bas)
153 {
154 int divisor;
155
156 divisor = ns8250_get_divisor(bas);
157
158 /* 1/10th the time to transmit 1 character (estimate). */
159 if (divisor <= 134)
160 return (16000000 * divisor / bas->rclk);
161 return (16000 * divisor / (bas->rclk / 1000));
162 }
163
164 static int
ns8250_divisor(int rclk,int baudrate)165 ns8250_divisor(int rclk, int baudrate)
166 {
167 int actual_baud, divisor;
168 int error;
169
170 if (baudrate == 0)
171 return (0);
172
173 divisor = (rclk / (baudrate << 3) + 1) >> 1;
174 if (divisor == 0 || divisor >= 65536)
175 return (0);
176 actual_baud = rclk / (divisor << 4);
177
178 /* 10 times error in percent: */
179 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
180
181 /* enforce maximum error tolerance: */
182 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
183 return (0);
184
185 return (divisor);
186 }
187
188 static int
ns8250_drain(struct uart_bas * bas,int what)189 ns8250_drain(struct uart_bas *bas, int what)
190 {
191 int delay, limit;
192
193 delay = ns8250_delay(bas);
194
195 if (what & UART_DRAIN_TRANSMITTER) {
196 /*
197 * Pick an arbitrary high limit to avoid getting stuck in
198 * an infinite loop when the hardware is broken. Make the
199 * limit high enough to handle large FIFOs.
200 */
201 limit = 10*1024;
202 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
203 DELAY(delay);
204 if (limit == 0) {
205 /* printf("uart: ns8250: transmitter appears stuck... "); */
206 return (EIO);
207 }
208 }
209
210 if (what & UART_DRAIN_RECEIVER) {
211 /*
212 * Pick an arbitrary high limit to avoid getting stuck in
213 * an infinite loop when the hardware is broken. Make the
214 * limit high enough to handle large FIFOs and integrated
215 * UARTs. The HP rx2600 for example has 3 UARTs on the
216 * management board that tend to get a lot of data send
217 * to it when the UART is first activated. Assume that we
218 * have finished draining if LSR_RXRDY is not asserted both
219 * prior to and after a DELAY; but as long as LSR_RXRDY is
220 * asserted, read (and discard) characters as quickly as
221 * possible.
222 */
223 limit=10*4096;
224 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
225 do {
226 (void)uart_getreg(bas, REG_DATA);
227 uart_barrier(bas);
228 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit);
229 uart_barrier(bas);
230 DELAY(delay << 2);
231 }
232 if (limit == 0) {
233 /* printf("uart: ns8250: receiver appears broken... "); */
234 return (EIO);
235 }
236 }
237
238 return (0);
239 }
240
241 /*
242 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
243 * drained. WARNING: this function clobbers the FIFO setting!
244 */
245 static void
ns8250_flush(struct uart_bas * bas,int what)246 ns8250_flush(struct uart_bas *bas, int what)
247 {
248 uint8_t fcr;
249 uint8_t lsr;
250 int drain = 0;
251
252 fcr = FCR_ENABLE;
253 if (what & UART_FLUSH_TRANSMITTER)
254 fcr |= FCR_XMT_RST;
255 if (what & UART_FLUSH_RECEIVER)
256 fcr |= FCR_RCV_RST;
257 uart_setreg(bas, REG_FCR, fcr);
258 uart_barrier(bas);
259
260 /*
261 * Detect and work around emulated UARTs which don't implement the
262 * FCR register; on these systems we need to drain the FIFO since
263 * the flush we request doesn't happen. One such system is the
264 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code:
265 * https://github.com/rust-vmm/vm-superio/issues/83
266 */
267 lsr = uart_getreg(bas, REG_LSR);
268 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER))
269 drain |= UART_DRAIN_TRANSMITTER;
270 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER))
271 drain |= UART_DRAIN_RECEIVER;
272 if (drain != 0) {
273 printf("uart: ns8250: UART FCR is broken\n");
274 ns8250_drain(bas, drain);
275 }
276 }
277
278 static int
ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)279 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
280 int parity)
281 {
282 int divisor;
283 uint8_t lcr;
284
285 /* Don't change settings when running on Hyper-V */
286 if (vm_guest == VM_GUEST_HV)
287 return (0);
288
289 lcr = 0;
290 if (databits >= 8)
291 lcr |= LCR_8BITS;
292 else if (databits == 7)
293 lcr |= LCR_7BITS;
294 else if (databits == 6)
295 lcr |= LCR_6BITS;
296 else
297 lcr |= LCR_5BITS;
298 if (stopbits > 1)
299 lcr |= LCR_STOPB;
300 lcr |= parity << 3;
301
302 /* Set baudrate if we know a rclk and both are not 0. */
303 if (baudrate > 0 && bas->rclk > 0) {
304 divisor = ns8250_divisor(bas->rclk, baudrate);
305 if (divisor == 0)
306 return (EINVAL);
307 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
308 uart_barrier(bas);
309 uart_setreg(bas, REG_DLL, divisor & 0xff);
310 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
311 uart_barrier(bas);
312 }
313
314 /* Set LCR and clear DLAB. */
315 uart_setreg(bas, REG_LCR, lcr);
316 uart_barrier(bas);
317 return (0);
318 }
319
320 /*
321 * Low-level UART interface.
322 */
323 static int ns8250_probe(struct uart_bas *bas);
324 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
325 static void ns8250_term(struct uart_bas *bas);
326 static void ns8250_putc(struct uart_bas *bas, int);
327 static int ns8250_rxready(struct uart_bas *bas);
328 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
329
330 struct uart_ops uart_ns8250_ops = {
331 .probe = ns8250_probe,
332 .init = ns8250_init,
333 .term = ns8250_term,
334 .putc = ns8250_putc,
335 .rxready = ns8250_rxready,
336 .getc = ns8250_getc,
337 };
338
339 static int
ns8250_probe(struct uart_bas * bas)340 ns8250_probe(struct uart_bas *bas)
341 {
342 u_char val;
343
344 /* Check known 0 bits that don't depend on DLAB. */
345 val = uart_getreg(bas, REG_IIR);
346 if (val & 0x30)
347 return (ENXIO);
348 /*
349 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
350 * chip, but otherwise doesn't seem to have a function. In
351 * other words, uart(4) works regardless. Ignore that bit so
352 * the probe succeeds.
353 */
354 val = uart_getreg(bas, REG_MCR);
355 if (val & 0xa0)
356 return (ENXIO);
357
358 return (0);
359 }
360
361 static void
ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)362 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
363 int parity)
364 {
365 u_char ier;
366
367 /* Disable all interrupt sources. */
368 /*
369 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
370 * UARTs split the receive time-out interrupt bit out separately as
371 * 0x10. This gets handled by ier_mask and ier_rxbits below.
372 */
373 ier = uart_getreg(bas, REG_IER) & 0xe0;
374 uart_setreg(bas, REG_IER, ier);
375 uart_barrier(bas);
376
377 /*
378 * Loader tells us to infer the rclk when it sets xo to 0 in
379 * hw.uart.console. We know the baudrate was set by the firmware, so
380 * calculate rclk from baudrate and the divisor register. If 'div' is
381 * actually 0, the resulting 0 value will have us fall back to other
382 * rclk methods.
383 */
384 if (bas->rclk_guess && bas->rclk == 0 && baudrate != 0) {
385 uint32_t div;
386
387 div = ns8250_get_divisor(bas);
388 bas->rclk = baudrate * div * 16;
389 }
390
391 /*
392 * Pick a default because we just don't know. This likely needs future
393 * refinement, but that's hard outside of consoles to know what to use.
394 * But defer as long as possible if there's no defined baud rate.
395 */
396 if (bas->rclk == 0 && baudrate != 0)
397 bas->rclk = DEFAULT_RCLK;
398
399 ns8250_param(bas, baudrate, databits, stopbits, parity);
400
401 /* Disable the FIFO (if present). */
402 uart_setreg(bas, REG_FCR, 0);
403 uart_barrier(bas);
404
405 /* Set RTS & DTR. */
406 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
407 uart_barrier(bas);
408
409 ns8250_clrint(bas);
410 }
411
412 static void
ns8250_term(struct uart_bas * bas)413 ns8250_term(struct uart_bas *bas)
414 {
415
416 /* Clear RTS & DTR. */
417 uart_setreg(bas, REG_MCR, MCR_IE);
418 uart_barrier(bas);
419 }
420
421 static void
ns8250_putc(struct uart_bas * bas,int c)422 ns8250_putc(struct uart_bas *bas, int c)
423 {
424 int limit;
425
426 if (vm_guest != VM_GUEST_HV) {
427 limit = 250000;
428 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
429 DELAY(4);
430 }
431 uart_setreg(bas, REG_DATA, c);
432 uart_barrier(bas);
433 }
434
435 static int
ns8250_rxready(struct uart_bas * bas)436 ns8250_rxready(struct uart_bas *bas)
437 {
438
439 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
440 }
441
442 static int
ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)443 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
444 {
445 int c;
446
447 uart_lock(hwmtx);
448
449 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
450 uart_unlock(hwmtx);
451 DELAY(4);
452 uart_lock(hwmtx);
453 }
454
455 c = uart_getreg(bas, REG_DATA);
456
457 uart_unlock(hwmtx);
458
459 return (c);
460 }
461
462 static kobj_method_t ns8250_methods[] = {
463 KOBJMETHOD(uart_attach, ns8250_bus_attach),
464 KOBJMETHOD(uart_detach, ns8250_bus_detach),
465 KOBJMETHOD(uart_flush, ns8250_bus_flush),
466 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
467 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
468 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
469 KOBJMETHOD(uart_param, ns8250_bus_param),
470 KOBJMETHOD(uart_probe, ns8250_bus_probe),
471 KOBJMETHOD(uart_receive, ns8250_bus_receive),
472 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
473 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
474 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy),
475 KOBJMETHOD(uart_grab, ns8250_bus_grab),
476 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
477 KOBJMETHOD_END
478 };
479
480 struct uart_class uart_ns8250_class = {
481 "ns8250",
482 ns8250_methods,
483 sizeof(struct ns8250_softc),
484 .uc_ops = &uart_ns8250_ops,
485 .uc_range = 8,
486 .uc_rclk = DEFAULT_RCLK,
487 .uc_rshift = 0
488 };
489 UART_CLASS(uart_ns8250_class);
490
491 /*
492 * XXX -- refactor out ACPI and FDT ifdefs
493 */
494 #ifdef DEV_ACPI
495 static struct acpi_uart_compat_data acpi_compat_data[] = {
496 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
497 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
498 {"APMC0D08", &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE, 2, 4, 0, 0, "APM compatible UART"},
499 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
500 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
501 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
502 {"INTC1006", &uart_ns8250_class, 0, 2, 0, 25000000, 0, "Intel ARM64 UART"},
503 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"},
504 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
505 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
506 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
507 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
508 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
509 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
510 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
511 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
512 {NULL, NULL, 0, 0 , 0, 0, 0, NULL},
513 };
514 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
515 #endif
516
517 #ifdef FDT
518 static struct ofw_compat_data compat_data[] = {
519 {"ns16550", (uintptr_t)&uart_ns8250_class},
520 {"ns16550a", (uintptr_t)&uart_ns8250_class},
521 {NULL, (uintptr_t)NULL},
522 };
523 UART_FDT_CLASS_AND_DEVICE(compat_data);
524 #endif
525
526 /* Use token-pasting to form SER_ and MSR_ named constants. */
527 #define SER(sig) SER_##sig
528 #define SERD(sig) SER_D##sig
529 #define MSR(sig) MSR_##sig
530 #define MSRD(sig) MSR_D##sig
531
532 /*
533 * Detect signal changes using software delta detection. The previous state of
534 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
535 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
536 * new state of both the signal and the delta bits.
537 */
538 #define SIGCHGSW(var, msr, sig) \
539 if ((msr) & MSR(sig)) { \
540 if ((var & SER(sig)) == 0) \
541 var |= SERD(sig) | SER(sig); \
542 } else { \
543 if ((var & SER(sig)) != 0) \
544 var = SERD(sig) | (var & ~SER(sig)); \
545 }
546
547 /*
548 * Detect signal changes using the hardware msr delta bits. This is currently
549 * used only when PPS timing information is being captured using the "narrow
550 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
551 * by time the interrupt handler is invoked. The hardware will latch the fact
552 * that it changed in the delta bits.
553 */
554 #define SIGCHGHW(var, msr, sig) \
555 if ((msr) & MSRD(sig)) { \
556 if (((msr) & MSR(sig)) != 0) \
557 var |= SERD(sig) | SER(sig); \
558 else \
559 var = SERD(sig) | (var & ~SER(sig)); \
560 }
561
562 int
ns8250_bus_attach(struct uart_softc * sc)563 ns8250_bus_attach(struct uart_softc *sc)
564 {
565 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
566 struct uart_bas *bas;
567 unsigned int ivar;
568 #ifdef FDT
569 phandle_t node;
570 pcell_t cell;
571 #endif
572
573 #ifdef FDT
574 /* Check whether uart has a broken txfifo. */
575 node = ofw_bus_get_node(sc->sc_dev);
576 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
577 broken_txfifo = cell ? 1 : 0;
578 #endif
579
580 bas = &sc->sc_bas;
581
582 ns8250->busy_detect = bas->busy_detect;
583 ns8250->mcr = uart_getreg(bas, REG_MCR);
584 ns8250->fcr = FCR_ENABLE;
585 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
586 &ivar)) {
587 if (UART_FLAGS_FCR_RX_LOW(ivar))
588 ns8250->fcr |= FCR_RX_LOW;
589 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
590 ns8250->fcr |= FCR_RX_MEDL;
591 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
592 ns8250->fcr |= FCR_RX_HIGH;
593 else
594 ns8250->fcr |= FCR_RX_MEDH;
595 } else
596 ns8250->fcr |= FCR_RX_MEDH;
597
598 /* Get IER mask */
599 ivar = 0xf0;
600 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
601 &ivar);
602 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
603
604 /* Get IER RX interrupt bits */
605 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
606 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
607 &ivar);
608 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
609
610 uart_setreg(bas, REG_FCR, ns8250->fcr);
611 uart_barrier(bas);
612 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
613
614 if (ns8250->mcr & MCR_DTR)
615 sc->sc_hwsig |= SER_DTR;
616 if (ns8250->mcr & MCR_RTS)
617 sc->sc_hwsig |= SER_RTS;
618 ns8250_bus_getsig(sc);
619
620 ns8250_clrint(bas);
621 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
622 ns8250->ier |= ns8250->ier_rxbits;
623 uart_setreg(bas, REG_IER, ns8250->ier);
624 uart_barrier(bas);
625
626 /*
627 * Timing of the H/W access was changed with r253161 of uart_core.c
628 * It has been observed that an ITE IT8513E would signal a break
629 * condition with pretty much every character it received, unless
630 * it had enough time to settle between ns8250_bus_attach() and
631 * ns8250_bus_ipend() -- which it accidentally had before r253161.
632 * It's not understood why the UART chip behaves this way and it
633 * could very well be that the DELAY make the H/W work in the same
634 * accidental manner as before. More analysis is warranted, but
635 * at least now we fixed a known regression.
636 */
637 DELAY(200);
638 return (0);
639 }
640
641 int
ns8250_bus_detach(struct uart_softc * sc)642 ns8250_bus_detach(struct uart_softc *sc)
643 {
644 struct ns8250_softc *ns8250;
645 struct uart_bas *bas;
646 u_char ier;
647
648 ns8250 = (struct ns8250_softc *)sc;
649 bas = &sc->sc_bas;
650 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
651 uart_setreg(bas, REG_IER, ier);
652 uart_barrier(bas);
653 ns8250_clrint(bas);
654 return (0);
655 }
656
657 int
ns8250_bus_flush(struct uart_softc * sc,int what)658 ns8250_bus_flush(struct uart_softc *sc, int what)
659 {
660 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
661 struct uart_bas *bas;
662 int error;
663
664 bas = &sc->sc_bas;
665 uart_lock(sc->sc_hwmtx);
666 if (sc->sc_rxfifosz > 1) {
667 ns8250_flush(bas, what);
668 uart_setreg(bas, REG_FCR, ns8250->fcr);
669 uart_barrier(bas);
670 error = 0;
671 } else
672 error = ns8250_drain(bas, what);
673 uart_unlock(sc->sc_hwmtx);
674 return (error);
675 }
676
677 int
ns8250_bus_getsig(struct uart_softc * sc)678 ns8250_bus_getsig(struct uart_softc *sc)
679 {
680 uint32_t old, sig;
681 uint8_t msr;
682
683 /*
684 * The delta bits are reputed to be broken on some hardware, so use
685 * software delta detection by default. Use the hardware delta bits
686 * when capturing PPS pulses which are too narrow for software detection
687 * to see the edges. Hardware delta for RI doesn't work like the
688 * others, so always use software for it. Other threads may be changing
689 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
690 * update without other changes happening. Note that the SIGCHGxx()
691 * macros carefully preserve the delta bits when we have to loop several
692 * times and a signal transitions between iterations.
693 */
694 do {
695 old = sc->sc_hwsig;
696 sig = old;
697 uart_lock(sc->sc_hwmtx);
698 msr = uart_getreg(&sc->sc_bas, REG_MSR);
699 uart_unlock(sc->sc_hwmtx);
700 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
701 SIGCHGHW(sig, msr, DSR);
702 SIGCHGHW(sig, msr, CTS);
703 SIGCHGHW(sig, msr, DCD);
704 } else {
705 SIGCHGSW(sig, msr, DSR);
706 SIGCHGSW(sig, msr, CTS);
707 SIGCHGSW(sig, msr, DCD);
708 }
709 SIGCHGSW(sig, msr, RI);
710 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
711 return (sig);
712 }
713
714 int
ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)715 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
716 {
717 struct uart_bas *bas;
718 int baudrate, divisor, error;
719 uint8_t efr, lcr;
720
721 bas = &sc->sc_bas;
722 error = 0;
723 uart_lock(sc->sc_hwmtx);
724 switch (request) {
725 case UART_IOCTL_BREAK:
726 lcr = uart_getreg(bas, REG_LCR);
727 if (data)
728 lcr |= LCR_SBREAK;
729 else
730 lcr &= ~LCR_SBREAK;
731 uart_setreg(bas, REG_LCR, lcr);
732 uart_barrier(bas);
733 break;
734 case UART_IOCTL_IFLOW:
735 lcr = uart_getreg(bas, REG_LCR);
736 uart_barrier(bas);
737 uart_setreg(bas, REG_LCR, 0xbf);
738 uart_barrier(bas);
739 efr = uart_getreg(bas, REG_EFR);
740 if (data)
741 efr |= EFR_RTS;
742 else
743 efr &= ~EFR_RTS;
744 uart_setreg(bas, REG_EFR, efr);
745 uart_barrier(bas);
746 uart_setreg(bas, REG_LCR, lcr);
747 uart_barrier(bas);
748 break;
749 case UART_IOCTL_OFLOW:
750 lcr = uart_getreg(bas, REG_LCR);
751 uart_barrier(bas);
752 uart_setreg(bas, REG_LCR, 0xbf);
753 uart_barrier(bas);
754 efr = uart_getreg(bas, REG_EFR);
755 if (data)
756 efr |= EFR_CTS;
757 else
758 efr &= ~EFR_CTS;
759 uart_setreg(bas, REG_EFR, efr);
760 uart_barrier(bas);
761 uart_setreg(bas, REG_LCR, lcr);
762 uart_barrier(bas);
763 break;
764 case UART_IOCTL_BAUD:
765 divisor = ns8250_get_divisor(bas);
766 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
767 if (baudrate > 0)
768 *(int*)data = baudrate;
769 else
770 error = ENXIO;
771 break;
772 default:
773 error = EINVAL;
774 break;
775 }
776 uart_unlock(sc->sc_hwmtx);
777 return (error);
778 }
779
780 int
ns8250_bus_ipend(struct uart_softc * sc)781 ns8250_bus_ipend(struct uart_softc *sc)
782 {
783 struct uart_bas *bas;
784 struct ns8250_softc *ns8250;
785 int ipend;
786 uint8_t iir, lsr;
787
788 ns8250 = (struct ns8250_softc *)sc;
789 bas = &sc->sc_bas;
790 uart_lock(sc->sc_hwmtx);
791 iir = uart_getreg(bas, REG_IIR);
792
793 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
794 (void)uart_getreg(bas, DW_REG_USR);
795 uart_unlock(sc->sc_hwmtx);
796 return (0);
797 }
798 if (iir & IIR_NOPEND) {
799 uart_unlock(sc->sc_hwmtx);
800 return (0);
801 }
802 ipend = 0;
803 if (iir & IIR_RXRDY) {
804 lsr = uart_getreg(bas, REG_LSR);
805 if (lsr & LSR_OE)
806 ipend |= SER_INT_OVERRUN;
807 if (lsr & LSR_BI)
808 ipend |= SER_INT_BREAK;
809 if (lsr & LSR_RXRDY)
810 ipend |= SER_INT_RXREADY;
811 } else {
812 if (iir & IIR_TXRDY) {
813 ipend |= SER_INT_TXIDLE;
814 ns8250->ier &= ~IER_ETXRDY;
815 uart_setreg(bas, REG_IER, ns8250->ier);
816 uart_barrier(bas);
817 } else
818 ipend |= SER_INT_SIGCHG;
819 }
820 if (ipend == 0)
821 ns8250_clrint(bas);
822 uart_unlock(sc->sc_hwmtx);
823 return (ipend);
824 }
825
826 int
ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)827 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
828 int stopbits, int parity)
829 {
830 struct ns8250_softc *ns8250;
831 struct uart_bas *bas;
832 int error, limit;
833
834 ns8250 = (struct ns8250_softc*)sc;
835 bas = &sc->sc_bas;
836 uart_lock(sc->sc_hwmtx);
837 /*
838 * When using DW UART with BUSY detection it is necessary to wait
839 * until all serial transfers are finished before manipulating the
840 * line control. LCR will not be affected when UART is busy.
841 */
842 if (ns8250->busy_detect != 0) {
843 /*
844 * Pick an arbitrary high limit to avoid getting stuck in
845 * an infinite loop in case when the hardware is broken.
846 */
847 limit = 10 * 1024;
848 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
849 --limit)
850 DELAY(4);
851
852 if (limit <= 0) {
853 /* UART appears to be stuck */
854 uart_unlock(sc->sc_hwmtx);
855 return (EIO);
856 }
857 }
858
859 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
860 uart_unlock(sc->sc_hwmtx);
861 return (error);
862 }
863
864 int
ns8250_bus_probe(struct uart_softc * sc)865 ns8250_bus_probe(struct uart_softc *sc)
866 {
867 struct uart_bas *bas;
868 int count, delay, error, limit;
869 uint8_t lsr, mcr, ier;
870
871 bas = &sc->sc_bas;
872
873 error = ns8250_probe(bas);
874 if (error)
875 return (error);
876
877 mcr = MCR_IE;
878 if (sc->sc_sysdev == NULL) {
879 /* By using ns8250_init() we also set DTR and RTS. */
880 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
881 } else
882 mcr |= MCR_DTR | MCR_RTS;
883
884 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
885 if (error)
886 return (error);
887
888 /*
889 * Set loopback mode. This avoids having garbage on the wire and
890 * also allows us send and receive data. We set DTR and RTS to
891 * avoid the possibility that automatic flow-control prevents
892 * any data from being sent.
893 */
894 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
895 uart_barrier(bas);
896
897 /*
898 * Enable FIFOs. And check that the UART has them. If not, we're
899 * done. Since this is the first time we enable the FIFOs, we reset
900 * them.
901 */
902 uart_setreg(bas, REG_FCR, FCR_ENABLE);
903 uart_barrier(bas);
904 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
905 /*
906 * NS16450 or INS8250. We don't bother to differentiate
907 * between them. They're too old to be interesting.
908 */
909 uart_setreg(bas, REG_MCR, mcr);
910 uart_barrier(bas);
911 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
912 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
913 return (0);
914 }
915
916 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
917 uart_barrier(bas);
918
919 count = 0;
920 delay = ns8250_delay(bas);
921
922 /* We have FIFOs. Drain the transmitter and receiver. */
923 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
924 if (error) {
925 uart_setreg(bas, REG_MCR, mcr);
926 uart_setreg(bas, REG_FCR, 0);
927 uart_barrier(bas);
928 goto describe;
929 }
930
931 /*
932 * We should have a sufficiently clean "pipe" to determine the
933 * size of the FIFOs. We send as much characters as is reasonable
934 * and wait for the overflow bit in the LSR register to be
935 * asserted, counting the characters as we send them. Based on
936 * that count we know the FIFO size.
937 */
938 do {
939 uart_setreg(bas, REG_DATA, 0);
940 uart_barrier(bas);
941 count++;
942
943 limit = 30;
944 lsr = 0;
945 /*
946 * LSR bits are cleared upon read, so we must accumulate
947 * them to be able to test LSR_OE below.
948 */
949 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
950 --limit)
951 DELAY(delay);
952 if (limit == 0) {
953 /* See the comment in ns8250_init(). */
954 ier = uart_getreg(bas, REG_IER) & 0xe0;
955 uart_setreg(bas, REG_IER, ier);
956 uart_setreg(bas, REG_MCR, mcr);
957 uart_setreg(bas, REG_FCR, 0);
958 uart_barrier(bas);
959 count = 0;
960 goto describe;
961 }
962 } while ((lsr & LSR_OE) == 0 && count < 260);
963 count--;
964
965 uart_setreg(bas, REG_MCR, mcr);
966
967 /* Reset FIFOs. */
968 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
969
970 describe:
971 if (count >= 14 && count <= 16) {
972 sc->sc_rxfifosz = 16;
973 device_set_desc(sc->sc_dev, "16550 or compatible");
974 } else if (count >= 28 && count <= 32) {
975 sc->sc_rxfifosz = 32;
976 device_set_desc(sc->sc_dev, "16650 or compatible");
977 } else if (count >= 56 && count <= 64) {
978 sc->sc_rxfifosz = 64;
979 device_set_desc(sc->sc_dev, "16750 or compatible");
980 } else if (count >= 112 && count <= 128) {
981 sc->sc_rxfifosz = 128;
982 device_set_desc(sc->sc_dev, "16950 or compatible");
983 } else if (count >= 224 && count <= 256) {
984 sc->sc_rxfifosz = 256;
985 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
986 } else {
987 sc->sc_rxfifosz = 16;
988 device_set_desc(sc->sc_dev,
989 "Non-standard ns8250 class UART with FIFOs");
990 }
991
992 /*
993 * Force the Tx FIFO size to 16 bytes for now. We don't program the
994 * Tx trigger. Also, we assume that all data has been sent when the
995 * interrupt happens.
996 */
997 sc->sc_txfifosz = 16;
998
999 #if 0
1000 /*
1001 * XXX there are some issues related to hardware flow control and
1002 * it's likely that uart(4) is the cause. This basically needs more
1003 * investigation, but we avoid using for hardware flow control
1004 * until then.
1005 */
1006 /* 16650s or higher have automatic flow control. */
1007 if (sc->sc_rxfifosz > 16) {
1008 sc->sc_hwiflow = 1;
1009 sc->sc_hwoflow = 1;
1010 }
1011 #endif
1012
1013 return (0);
1014 }
1015
1016 int
ns8250_bus_receive(struct uart_softc * sc)1017 ns8250_bus_receive(struct uart_softc *sc)
1018 {
1019 struct uart_bas *bas;
1020 struct ns8250_softc *ns8250 = (struct ns8250_softc *)sc;
1021 int xc;
1022 uint8_t lsr;
1023
1024 bas = &sc->sc_bas;
1025 uart_lock(sc->sc_hwmtx);
1026 lsr = uart_getreg(bas, REG_LSR);
1027 while (lsr & LSR_RXRDY) {
1028 if (uart_rx_full(sc)) {
1029 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
1030 break;
1031 }
1032 /* Filter out possible noise on the line.
1033 * Expect that the device should be able to transmit as well as
1034 * receive, so if we receive too many characters before transmit
1035 * is ready, it's probably noise.
1036 */
1037 if ((lsr & (LSR_TXRDY | LSR_TEMT)) == 0 &&
1038 uart_noise_threshold > 0) {
1039 if (++ns8250->noise_count >= uart_noise_threshold)
1040 break;
1041 } else
1042 ns8250->noise_count = 0;
1043 xc = uart_getreg(bas, REG_DATA);
1044 if (lsr & LSR_FE)
1045 xc |= UART_STAT_FRAMERR;
1046 if (lsr & LSR_PE)
1047 xc |= UART_STAT_PARERR;
1048 uart_rx_put(sc, xc);
1049 lsr = uart_getreg(bas, REG_LSR);
1050 }
1051 /* Discard everything left in the Rx FIFO. */
1052 while (lsr & LSR_RXRDY) {
1053 (void)uart_getreg(bas, REG_DATA);
1054 uart_barrier(bas);
1055 lsr = uart_getreg(bas, REG_LSR);
1056 }
1057 uart_unlock(sc->sc_hwmtx);
1058 return (0);
1059 }
1060
1061 int
ns8250_bus_setsig(struct uart_softc * sc,int sig)1062 ns8250_bus_setsig(struct uart_softc *sc, int sig)
1063 {
1064 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1065 struct uart_bas *bas;
1066 uint32_t new, old;
1067
1068 bas = &sc->sc_bas;
1069 do {
1070 old = sc->sc_hwsig;
1071 new = old;
1072 if (sig & SER_DDTR) {
1073 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
1074 }
1075 if (sig & SER_DRTS) {
1076 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
1077 }
1078 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
1079 uart_lock(sc->sc_hwmtx);
1080 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
1081 if (new & SER_DTR)
1082 ns8250->mcr |= MCR_DTR;
1083 if (new & SER_RTS)
1084 ns8250->mcr |= MCR_RTS;
1085 uart_setreg(bas, REG_MCR, ns8250->mcr);
1086 uart_barrier(bas);
1087 uart_unlock(sc->sc_hwmtx);
1088 return (0);
1089 }
1090
1091 int
ns8250_bus_transmit(struct uart_softc * sc)1092 ns8250_bus_transmit(struct uart_softc *sc)
1093 {
1094 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1095 struct uart_bas *bas;
1096 int i;
1097
1098 bas = &sc->sc_bas;
1099 uart_lock(sc->sc_hwmtx);
1100 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1101 DELAY(4);
1102 for (i = 0; i < sc->sc_txdatasz; i++) {
1103 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1104 uart_barrier(bas);
1105 }
1106 if (!broken_txfifo)
1107 ns8250->ier |= IER_ETXRDY;
1108 uart_setreg(bas, REG_IER, ns8250->ier);
1109 uart_barrier(bas);
1110 if (broken_txfifo)
1111 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1112 else
1113 sc->sc_txbusy = 1;
1114 uart_unlock(sc->sc_hwmtx);
1115 if (broken_txfifo)
1116 uart_sched_softih(sc, SER_INT_TXIDLE);
1117 return (0);
1118 }
1119
1120 bool
ns8250_bus_txbusy(struct uart_softc * sc)1121 ns8250_bus_txbusy(struct uart_softc *sc)
1122 {
1123 struct uart_bas *bas = &sc->sc_bas;
1124
1125 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=
1126 (LSR_TEMT | LSR_THRE))
1127 return (true);
1128 return (false);
1129 }
1130
1131 void
ns8250_bus_grab(struct uart_softc * sc)1132 ns8250_bus_grab(struct uart_softc *sc)
1133 {
1134 struct uart_bas *bas = &sc->sc_bas;
1135 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1136 u_char ier;
1137
1138 /*
1139 * turn off all interrupts to enter polling mode. Leave the
1140 * saved mask alone. We'll restore whatever it was in ungrab.
1141 * All pending interrupt signals are reset when IER is set to 0.
1142 */
1143 uart_lock(sc->sc_hwmtx);
1144 ier = uart_getreg(bas, REG_IER);
1145 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1146 uart_barrier(bas);
1147 uart_unlock(sc->sc_hwmtx);
1148 }
1149
1150 void
ns8250_bus_ungrab(struct uart_softc * sc)1151 ns8250_bus_ungrab(struct uart_softc *sc)
1152 {
1153 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1154 struct uart_bas *bas = &sc->sc_bas;
1155
1156 /*
1157 * Restore previous interrupt mask
1158 */
1159 uart_lock(sc->sc_hwmtx);
1160 uart_setreg(bas, REG_IER, ns8250->ier);
1161 uart_barrier(bas);
1162 uart_unlock(sc->sc_hwmtx);
1163 }
1164