1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Slow Path Operators (header)
37 *
38 */
39
40 #ifndef __BNXT_RE_H__
41 #define __BNXT_RE_H__
42 #include <rdma/uverbs_ioctl.h>
43 #include "hw_counters.h"
44 #include <linux/hashtable.h>
45 #define ROCE_DRV_MODULE_NAME "bnxt_re"
46
47 #define BNXT_RE_DESC "Broadcom NetXtreme-C/E RoCE Driver"
48
49 #define BNXT_RE_PAGE_SHIFT_1G (30)
50 #define BNXT_RE_PAGE_SIZE_SUPPORTED 0x7FFFF000 /* 4kb - 1G */
51
52 #define BNXT_RE_MAX_MR_SIZE_LOW BIT_ULL(BNXT_RE_PAGE_SHIFT_1G)
53 #define BNXT_RE_MAX_MR_SIZE_HIGH BIT_ULL(39)
54 #define BNXT_RE_MAX_MR_SIZE BNXT_RE_MAX_MR_SIZE_HIGH
55
56 #define BNXT_RE_MAX_QPC_COUNT (64 * 1024)
57 #define BNXT_RE_MAX_MRW_COUNT (64 * 1024)
58 #define BNXT_RE_MAX_SRQC_COUNT (64 * 1024)
59 #define BNXT_RE_MAX_CQ_COUNT (64 * 1024)
60 #define BNXT_RE_MAX_MRW_COUNT_64K (64 * 1024)
61 #define BNXT_RE_MAX_MRW_COUNT_256K (256 * 1024)
62
63 /* Number of MRs to reserve for PF, leaving remainder for VFs */
64 #define BNXT_RE_RESVD_MR_FOR_PF (32 * 1024)
65 #define BNXT_RE_MAX_GID_PER_VF 128
66
67 /*
68 * Percentage of resources of each type reserved for PF.
69 * Remaining resources are divided equally among VFs.
70 * [0, 100]
71 */
72 #define BNXT_RE_PCT_RSVD_FOR_PF 50
73
74 #define BNXT_RE_UD_QP_HW_STALL 0x400000
75
76 #define BNXT_RE_RQ_WQE_THRESHOLD 32
77
78 /*
79 * Setting the default ack delay value to 16, which means
80 * the default timeout is approx. 260ms(4 usec * 2 ^(timeout))
81 */
82
83 #define BNXT_RE_DEFAULT_ACK_DELAY 16
84
85 struct bnxt_re_ring_attr {
86 dma_addr_t *dma_arr;
87 int pages;
88 int type;
89 u32 depth;
90 u32 lrid; /* Logical ring id */
91 u8 mode;
92 };
93
94 /*
95 * Data structure and defines to handle
96 * recovery
97 */
98 #define BNXT_RE_PRE_RECOVERY_REMOVE 0x1
99 #define BNXT_RE_COMPLETE_REMOVE 0x2
100 #define BNXT_RE_POST_RECOVERY_INIT 0x4
101 #define BNXT_RE_COMPLETE_INIT 0x8
102
103 struct bnxt_re_sqp_entries {
104 struct bnxt_qplib_sge sge;
105 u64 wrid;
106 /* For storing the actual qp1 cqe */
107 struct bnxt_qplib_cqe cqe;
108 struct bnxt_re_qp *qp1_qp;
109 };
110
111 #define BNXT_RE_MAX_GSI_SQP_ENTRIES 1024
112 struct bnxt_re_gsi_context {
113 struct bnxt_re_qp *gsi_qp;
114 struct bnxt_re_qp *gsi_sqp;
115 struct bnxt_re_ah *gsi_sah;
116 struct bnxt_re_sqp_entries *sqp_tbl;
117 };
118
119 struct bnxt_re_en_dev_info {
120 struct bnxt_en_dev *en_dev;
121 struct bnxt_re_dev *rdev;
122 };
123
124 #define BNXT_RE_AEQ_IDX 0
125 #define BNXT_RE_NQ_IDX 1
126 #define BNXT_RE_GEN_P5_MAX_VF 64
127
128 struct bnxt_re_pacing {
129 u64 dbr_db_fifo_reg_off;
130 void *dbr_page;
131 u64 dbr_bar_addr;
132 u32 pacing_algo_th;
133 u32 do_pacing_save;
134 u32 dbq_pacing_time; /* ms */
135 u32 dbr_def_do_pacing;
136 bool dbr_pacing;
137 struct mutex dbq_lock; /* synchronize db pacing algo */
138 };
139
140 #define BNXT_RE_MAX_DBR_DO_PACING 0xFFFF
141 #define BNXT_RE_DBR_PACING_TIME 5 /* ms */
142 #define BNXT_RE_PACING_ALGO_THRESHOLD 250 /* Entries in DB FIFO */
143 #define BNXT_RE_PACING_ALARM_TH_MULTIPLE 2 /* Multiple of pacing algo threshold */
144 /* Default do_pacing value when there is no congestion */
145 #define BNXT_RE_DBR_DO_PACING_NO_CONGESTION 0x7F /* 1 in 512 probability */
146
147 #define BNXT_RE_MAX_FIFO_DEPTH_P5 0x2c00
148 #define BNXT_RE_MAX_FIFO_DEPTH_P7 0x8000
149
150 #define BNXT_RE_MAX_FIFO_DEPTH(ctx) \
151 (bnxt_qplib_is_chip_gen_p7((ctx)) ? \
152 BNXT_RE_MAX_FIFO_DEPTH_P7 :\
153 BNXT_RE_MAX_FIFO_DEPTH_P5)
154
155 #define BNXT_RE_GRC_FIFO_REG_BASE 0x2000
156
157 #define BNXT_RE_MIN_MSIX 2
158 #define BNXT_RE_MAX_MSIX BNXT_MAX_ROCE_MSIX
159 struct bnxt_re_nq_record {
160 struct bnxt_msix_entry msix_entries[BNXT_RE_MAX_MSIX];
161 struct bnxt_qplib_nq nq[BNXT_RE_MAX_MSIX];
162 int num_msix;
163 /* serialize NQ access */
164 struct mutex load_lock;
165 };
166
167 #define MAX_CQ_HASH_BITS (16)
168 #define MAX_SRQ_HASH_BITS (16)
169
bnxt_re_chip_gen_p7(u16 chip_num)170 static inline bool bnxt_re_chip_gen_p7(u16 chip_num)
171 {
172 return (chip_num == CHIP_NUM_58818 ||
173 chip_num == CHIP_NUM_57608);
174 }
175
176 struct bnxt_re_dev {
177 struct ib_device ibdev;
178 struct list_head list;
179 unsigned long flags;
180 #define BNXT_RE_FLAG_NETDEV_REGISTERED 0
181 #define BNXT_RE_FLAG_HAVE_L2_REF 3
182 #define BNXT_RE_FLAG_RCFW_CHANNEL_EN 4
183 #define BNXT_RE_FLAG_QOS_WORK_REG 5
184 #define BNXT_RE_FLAG_RESOURCES_ALLOCATED 7
185 #define BNXT_RE_FLAG_RESOURCES_INITIALIZED 8
186 #define BNXT_RE_FLAG_ERR_DEVICE_DETACHED 17
187 #define BNXT_RE_FLAG_ISSUE_ROCE_STATS 29
188 struct net_device *netdev;
189 struct auxiliary_device *adev;
190 unsigned int version, major, minor;
191 struct bnxt_qplib_chip_ctx *chip_ctx;
192 struct bnxt_en_dev *en_dev;
193
194 int id;
195
196 struct delayed_work worker;
197 u8 cur_prio_map;
198
199 /* RCFW Channel */
200 struct bnxt_qplib_rcfw rcfw;
201
202 /* NQ record */
203 struct bnxt_re_nq_record *nqr;
204
205 /* Device Resources */
206 struct bnxt_qplib_dev_attr *dev_attr;
207 struct bnxt_qplib_ctx qplib_ctx;
208 struct bnxt_qplib_res qplib_res;
209 struct bnxt_qplib_dpi dpi_privileged;
210 struct bnxt_qplib_cq_coal_param cq_coalescing;
211
212 struct mutex qp_lock; /* protect qp list */
213 struct list_head qp_list;
214
215 /* Max of 2 lossless traffic class supported per port */
216 u16 cosq[2];
217
218 /* QP for handling QP1 packets */
219 struct bnxt_re_gsi_context gsi_ctx;
220 struct bnxt_re_stats stats;
221 atomic_t nq_alloc_cnt;
222 u32 is_virtfn;
223 u32 num_vfs;
224 struct bnxt_re_pacing pacing;
225 struct work_struct dbq_fifo_check_work;
226 struct delayed_work dbq_pacing_work;
227 DECLARE_HASHTABLE(cq_hash, MAX_CQ_HASH_BITS);
228 DECLARE_HASHTABLE(srq_hash, MAX_SRQ_HASH_BITS);
229 struct dentry *dbg_root;
230 struct dentry *qp_debugfs;
231 unsigned long event_bitmap;
232 struct bnxt_qplib_cc_param cc_param;
233 struct workqueue_struct *dcb_wq;
234 };
235
236 #define to_bnxt_re_dev(ptr, member) \
237 container_of((ptr), struct bnxt_re_dev, member)
238
239 #define BNXT_RE_ROCE_V1_PACKET 0
240 #define BNXT_RE_ROCEV2_IPV4_PACKET 2
241 #define BNXT_RE_ROCEV2_IPV6_PACKET 3
242
243 #define BNXT_RE_CHECK_RC(x) ((x) && ((x) != -ETIMEDOUT))
244 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev);
245
rdev_to_dev(struct bnxt_re_dev * rdev)246 static inline struct device *rdev_to_dev(struct bnxt_re_dev *rdev)
247 {
248 if (rdev)
249 return &rdev->ibdev.dev;
250 return NULL;
251 }
252
253 extern const struct uapi_definition bnxt_re_uapi_defs[];
254
bnxt_re_set_pacing_dev_state(struct bnxt_re_dev * rdev)255 static inline void bnxt_re_set_pacing_dev_state(struct bnxt_re_dev *rdev)
256 {
257 rdev->qplib_res.pacing_data->dev_err_state =
258 test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
259 }
260
bnxt_re_read_context_allowed(struct bnxt_re_dev * rdev)261 static inline int bnxt_re_read_context_allowed(struct bnxt_re_dev *rdev)
262 {
263 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ||
264 rdev->rcfw.res->cctx->hwrm_intf_ver < HWRM_VERSION_READ_CTX)
265 return -EOPNOTSUPP;
266 return 0;
267 }
268
269 #define BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P5 1088
270 #define BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P5 128
271 #define BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P5 128
272 #define BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P5 192
273
274 #define BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P7 1088
275 #define BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P7 192
276 #define BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P7 192
277 #define BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P7 192
278
279 #endif
280