xref: /linux/drivers/gpu/drm/radeon/radeon_cs.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright 2008 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *    Jerome Glisse <glisse@freedesktop.org>
26  */
27 
28 #include <linux/list_sort.h>
29 #include <linux/pci.h>
30 #include <linux/uaccess.h>
31 
32 #include <drm/drm_device.h>
33 #include <drm/drm_file.h>
34 #include <drm/radeon_drm.h>
35 
36 #include "radeon.h"
37 #include "radeon_reg.h"
38 #include "radeon_trace.h"
39 
40 #define RADEON_CS_MAX_PRIORITY		32u
41 #define RADEON_CS_NUM_BUCKETS		(RADEON_CS_MAX_PRIORITY + 1)
42 
43 /* This is based on the bucket sort with O(n) time complexity.
44  * An item with priority "i" is added to bucket[i]. The lists are then
45  * concatenated in descending order.
46  */
47 struct radeon_cs_buckets {
48 	struct list_head bucket[RADEON_CS_NUM_BUCKETS];
49 };
50 
radeon_cs_buckets_init(struct radeon_cs_buckets * b)51 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
52 {
53 	unsigned i;
54 
55 	for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
56 		INIT_LIST_HEAD(&b->bucket[i]);
57 }
58 
radeon_cs_buckets_add(struct radeon_cs_buckets * b,struct list_head * item,unsigned priority)59 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
60 				  struct list_head *item, unsigned priority)
61 {
62 	/* Since buffers which appear sooner in the relocation list are
63 	 * likely to be used more often than buffers which appear later
64 	 * in the list, the sort mustn't change the ordering of buffers
65 	 * with the same priority, i.e. it must be stable.
66 	 */
67 	list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
68 }
69 
radeon_cs_buckets_get_list(struct radeon_cs_buckets * b,struct list_head * out_list)70 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
71 				       struct list_head *out_list)
72 {
73 	unsigned i;
74 
75 	/* Connect the sorted buckets in the output list. */
76 	for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
77 		list_splice(&b->bucket[i], out_list);
78 	}
79 }
80 
radeon_cs_parser_relocs(struct radeon_cs_parser * p)81 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
82 {
83 	struct radeon_cs_chunk *chunk;
84 	struct radeon_cs_buckets buckets;
85 	unsigned i;
86 	bool need_mmap_lock = false;
87 	int r;
88 
89 	if (p->chunk_relocs == NULL) {
90 		return 0;
91 	}
92 	chunk = p->chunk_relocs;
93 	p->dma_reloc_idx = 0;
94 	/* FIXME: we assume that each relocs use 4 dwords */
95 	p->nrelocs = chunk->length_dw / 4;
96 	p->relocs = kvcalloc(p->nrelocs, sizeof(struct radeon_bo_list),
97 			GFP_KERNEL);
98 	if (p->relocs == NULL) {
99 		return -ENOMEM;
100 	}
101 
102 	radeon_cs_buckets_init(&buckets);
103 
104 	for (i = 0; i < p->nrelocs; i++) {
105 		struct drm_radeon_cs_reloc *r;
106 		struct drm_gem_object *gobj;
107 		unsigned priority;
108 
109 		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
110 		gobj = drm_gem_object_lookup(p->filp, r->handle);
111 		if (gobj == NULL) {
112 			DRM_ERROR("gem object lookup failed 0x%x\n",
113 				  r->handle);
114 			return -ENOENT;
115 		}
116 		p->relocs[i].robj = gem_to_radeon_bo(gobj);
117 
118 		/* The userspace buffer priorities are from 0 to 15. A higher
119 		 * number means the buffer is more important.
120 		 * Also, the buffers used for write have a higher priority than
121 		 * the buffers used for read only, which doubles the range
122 		 * to 0 to 31. 32 is reserved for the kernel driver.
123 		 */
124 		priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
125 			   + !!r->write_domain;
126 
127 		/* The first reloc of an UVD job is the msg and that must be in
128 		 * VRAM, the second reloc is the DPB and for WMV that must be in
129 		 * VRAM as well. Also put everything into VRAM on AGP cards and older
130 		 * IGP chips to avoid image corruptions
131 		 */
132 		if (p->ring == R600_RING_TYPE_UVD_INDEX &&
133 		    (i <= 0 || pci_find_capability(p->rdev->pdev, PCI_CAP_ID_AGP) ||
134 		     p->rdev->family == CHIP_RS780 ||
135 		     p->rdev->family == CHIP_RS880)) {
136 
137 			/* TODO: is this still needed for NI+ ? */
138 			p->relocs[i].preferred_domains =
139 				RADEON_GEM_DOMAIN_VRAM;
140 
141 			p->relocs[i].allowed_domains =
142 				RADEON_GEM_DOMAIN_VRAM;
143 
144 			/* prioritize this over any other relocation */
145 			priority = RADEON_CS_MAX_PRIORITY;
146 		} else {
147 			uint32_t domain = r->write_domain ?
148 				r->write_domain : r->read_domains;
149 
150 			if (domain & RADEON_GEM_DOMAIN_CPU) {
151 				DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
152 					  "for command submission\n");
153 				return -EINVAL;
154 			}
155 
156 			p->relocs[i].preferred_domains = domain;
157 			if (domain == RADEON_GEM_DOMAIN_VRAM)
158 				domain |= RADEON_GEM_DOMAIN_GTT;
159 			p->relocs[i].allowed_domains = domain;
160 		}
161 
162 		if (radeon_ttm_tt_has_userptr(p->rdev, p->relocs[i].robj->tbo.ttm)) {
163 			uint32_t domain = p->relocs[i].preferred_domains;
164 			if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
165 				DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
166 					  "allowed for userptr BOs\n");
167 				return -EINVAL;
168 			}
169 			need_mmap_lock = true;
170 			domain = RADEON_GEM_DOMAIN_GTT;
171 			p->relocs[i].preferred_domains = domain;
172 			p->relocs[i].allowed_domains = domain;
173 		}
174 
175 		/* Objects shared as dma-bufs cannot be moved to VRAM */
176 		if (p->relocs[i].robj->prime_shared_count) {
177 			p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
178 			if (!p->relocs[i].allowed_domains) {
179 				DRM_ERROR("BO associated with dma-buf cannot "
180 					  "be moved to VRAM\n");
181 				return -EINVAL;
182 			}
183 		}
184 
185 		p->relocs[i].shared = !r->write_domain;
186 		radeon_cs_buckets_add(&buckets, &p->relocs[i].list, priority);
187 	}
188 
189 	radeon_cs_buckets_get_list(&buckets, &p->validated);
190 
191 	if (p->cs_flags & RADEON_CS_USE_VM)
192 		p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
193 					      &p->validated);
194 	if (need_mmap_lock)
195 		mmap_read_lock(current->mm);
196 
197 	r = radeon_bo_list_validate(p->rdev, &p->exec, &p->validated, p->ring);
198 
199 	if (need_mmap_lock)
200 		mmap_read_unlock(current->mm);
201 
202 	return r;
203 }
204 
radeon_cs_get_ring(struct radeon_cs_parser * p,u32 ring,s32 priority)205 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
206 {
207 	p->priority = priority;
208 
209 	switch (ring) {
210 	default:
211 		DRM_ERROR("unknown ring id: %d\n", ring);
212 		return -EINVAL;
213 	case RADEON_CS_RING_GFX:
214 		p->ring = RADEON_RING_TYPE_GFX_INDEX;
215 		break;
216 	case RADEON_CS_RING_COMPUTE:
217 		if (p->rdev->family >= CHIP_TAHITI) {
218 			if (p->priority > 0)
219 				p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
220 			else
221 				p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
222 		} else
223 			p->ring = RADEON_RING_TYPE_GFX_INDEX;
224 		break;
225 	case RADEON_CS_RING_DMA:
226 		if (p->rdev->family >= CHIP_CAYMAN) {
227 			if (p->priority > 0)
228 				p->ring = R600_RING_TYPE_DMA_INDEX;
229 			else
230 				p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
231 		} else if (p->rdev->family >= CHIP_RV770) {
232 			p->ring = R600_RING_TYPE_DMA_INDEX;
233 		} else {
234 			return -EINVAL;
235 		}
236 		break;
237 	case RADEON_CS_RING_UVD:
238 		p->ring = R600_RING_TYPE_UVD_INDEX;
239 		break;
240 	case RADEON_CS_RING_VCE:
241 		/* TODO: only use the low priority ring for now */
242 		p->ring = TN_RING_TYPE_VCE1_INDEX;
243 		break;
244 	}
245 	return 0;
246 }
247 
radeon_cs_sync_rings(struct radeon_cs_parser * p)248 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
249 {
250 	struct radeon_bo_list *reloc;
251 	int r;
252 
253 	list_for_each_entry(reloc, &p->validated, list) {
254 		struct dma_resv *resv;
255 
256 		resv = reloc->robj->tbo.base.resv;
257 		r = radeon_sync_resv(p->rdev, &p->ib.sync, resv, reloc->shared);
258 		if (r)
259 			return r;
260 	}
261 	return 0;
262 }
263 
264 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
radeon_cs_parser_init(struct radeon_cs_parser * p,void * data)265 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
266 {
267 	struct drm_radeon_cs *cs = data;
268 	uint64_t *chunk_array_ptr;
269 	u64 size;
270 	unsigned i;
271 	u32 ring = RADEON_CS_RING_GFX;
272 	s32 priority = 0;
273 
274 	INIT_LIST_HEAD(&p->validated);
275 	drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
276 
277 	if (!cs->num_chunks) {
278 		return 0;
279 	}
280 
281 	/* get chunks */
282 	p->idx = 0;
283 	p->ib.sa_bo = NULL;
284 	p->const_ib.sa_bo = NULL;
285 	p->chunk_ib = NULL;
286 	p->chunk_relocs = NULL;
287 	p->chunk_flags = NULL;
288 	p->chunk_const_ib = NULL;
289 	p->chunks_array = kvmalloc_array(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
290 	if (p->chunks_array == NULL) {
291 		return -ENOMEM;
292 	}
293 	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
294 	if (copy_from_user(p->chunks_array, chunk_array_ptr,
295 			       sizeof(uint64_t)*cs->num_chunks)) {
296 		return -EFAULT;
297 	}
298 	p->cs_flags = 0;
299 	p->nchunks = cs->num_chunks;
300 	p->chunks = kvcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
301 	if (p->chunks == NULL) {
302 		return -ENOMEM;
303 	}
304 	for (i = 0; i < p->nchunks; i++) {
305 		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
306 		struct drm_radeon_cs_chunk user_chunk;
307 		uint32_t __user *cdata;
308 
309 		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
310 		if (copy_from_user(&user_chunk, chunk_ptr,
311 				       sizeof(struct drm_radeon_cs_chunk))) {
312 			return -EFAULT;
313 		}
314 		p->chunks[i].length_dw = user_chunk.length_dw;
315 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) {
316 			p->chunk_relocs = &p->chunks[i];
317 		}
318 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
319 			p->chunk_ib = &p->chunks[i];
320 			/* zero length IB isn't useful */
321 			if (p->chunks[i].length_dw == 0)
322 				return -EINVAL;
323 		}
324 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) {
325 			p->chunk_const_ib = &p->chunks[i];
326 			/* zero length CONST IB isn't useful */
327 			if (p->chunks[i].length_dw == 0)
328 				return -EINVAL;
329 		}
330 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
331 			p->chunk_flags = &p->chunks[i];
332 			/* zero length flags aren't useful */
333 			if (p->chunks[i].length_dw == 0)
334 				return -EINVAL;
335 		}
336 
337 		size = p->chunks[i].length_dw;
338 		cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
339 		p->chunks[i].user_ptr = cdata;
340 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB)
341 			continue;
342 
343 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
344 			if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
345 				continue;
346 		}
347 
348 		p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
349 		size *= sizeof(uint32_t);
350 		if (p->chunks[i].kdata == NULL) {
351 			return -ENOMEM;
352 		}
353 		if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
354 			return -EFAULT;
355 		}
356 		if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
357 			p->cs_flags = p->chunks[i].kdata[0];
358 			if (p->chunks[i].length_dw > 1)
359 				ring = p->chunks[i].kdata[1];
360 			if (p->chunks[i].length_dw > 2)
361 				priority = (s32)p->chunks[i].kdata[2];
362 		}
363 	}
364 
365 	/* these are KMS only */
366 	if (p->rdev) {
367 		if ((p->cs_flags & RADEON_CS_USE_VM) &&
368 		    !p->rdev->vm_manager.enabled) {
369 			DRM_ERROR("VM not active on asic!\n");
370 			return -EINVAL;
371 		}
372 
373 		if (radeon_cs_get_ring(p, ring, priority))
374 			return -EINVAL;
375 
376 		/* we only support VM on some SI+ rings */
377 		if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
378 			if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
379 				DRM_ERROR("Ring %d requires VM!\n", p->ring);
380 				return -EINVAL;
381 			}
382 		} else {
383 			if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
384 				DRM_ERROR("VM not supported on ring %d!\n",
385 					  p->ring);
386 				return -EINVAL;
387 			}
388 		}
389 	}
390 
391 	return 0;
392 }
393 
cmp_size_smaller_first(void * priv,const struct list_head * a,const struct list_head * b)394 static int cmp_size_smaller_first(void *priv, const struct list_head *a,
395 				  const struct list_head *b)
396 {
397 	struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, list);
398 	struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, list);
399 
400 	/* Sort A before B if A is smaller. */
401 	if (la->robj->tbo.base.size > lb->robj->tbo.base.size)
402 		return 1;
403 	if (la->robj->tbo.base.size < lb->robj->tbo.base.size)
404 		return -1;
405 	return 0;
406 }
407 
408 /**
409  * radeon_cs_parser_fini() - clean parser states
410  * @parser:	parser structure holding parsing context.
411  * @error:	error number
412  * @backoff:	indicator to backoff the reservation
413  *
414  * If error is set than unvalidate buffer, otherwise just free memory
415  * used by parsing context.
416  **/
radeon_cs_parser_fini(struct radeon_cs_parser * parser,int error)417 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
418 {
419 	unsigned i;
420 
421 	if (!error) {
422 		struct radeon_bo_list *reloc;
423 
424 		/* Sort the buffer list from the smallest to largest buffer,
425 		 * which affects the order of buffers in the LRU list.
426 		 * This assures that the smallest buffers are added first
427 		 * to the LRU list, so they are likely to be later evicted
428 		 * first, instead of large buffers whose eviction is more
429 		 * expensive.
430 		 *
431 		 * This slightly lowers the number of bytes moved by TTM
432 		 * per frame under memory pressure.
433 		 */
434 		list_sort(NULL, &parser->validated, cmp_size_smaller_first);
435 		list_for_each_entry(reloc, &parser->validated, list) {
436 			dma_resv_add_fence(reloc->robj->tbo.base.resv,
437 					   &parser->ib.fence->base,
438 					   reloc->shared ?
439 					   DMA_RESV_USAGE_READ :
440 					   DMA_RESV_USAGE_WRITE);
441 		}
442 	}
443 
444 	drm_exec_fini(&parser->exec);
445 
446 	if (parser->relocs != NULL) {
447 		for (i = 0; i < parser->nrelocs; i++) {
448 			struct radeon_bo *bo = parser->relocs[i].robj;
449 			if (bo == NULL)
450 				continue;
451 
452 			drm_gem_object_put(&bo->tbo.base);
453 		}
454 	}
455 	kfree(parser->track);
456 	kvfree(parser->relocs);
457 	kvfree(parser->vm_bos);
458 	for (i = 0; i < parser->nchunks; i++)
459 		kvfree(parser->chunks[i].kdata);
460 	kvfree(parser->chunks);
461 	kvfree(parser->chunks_array);
462 	radeon_ib_free(parser->rdev, &parser->ib);
463 	radeon_ib_free(parser->rdev, &parser->const_ib);
464 }
465 
radeon_cs_ib_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)466 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
467 			      struct radeon_cs_parser *parser)
468 {
469 	int r;
470 
471 	if (parser->chunk_ib == NULL)
472 		return 0;
473 
474 	if (parser->cs_flags & RADEON_CS_USE_VM)
475 		return 0;
476 
477 	r = radeon_cs_parse(rdev, parser->ring, parser);
478 	if (r || parser->parser_error) {
479 		DRM_ERROR("Invalid command stream !\n");
480 		return r;
481 	}
482 
483 	r = radeon_cs_sync_rings(parser);
484 	if (r) {
485 		if (r != -ERESTARTSYS)
486 			DRM_ERROR("Failed to sync rings: %i\n", r);
487 		return r;
488 	}
489 
490 	if (parser->ring == R600_RING_TYPE_UVD_INDEX)
491 		radeon_uvd_note_usage(rdev);
492 	else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
493 		 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
494 		radeon_vce_note_usage(rdev);
495 
496 	r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
497 	if (r) {
498 		DRM_ERROR("Failed to schedule IB !\n");
499 	}
500 	return r;
501 }
502 
radeon_bo_vm_update_pte(struct radeon_cs_parser * p,struct radeon_vm * vm)503 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
504 				   struct radeon_vm *vm)
505 {
506 	struct radeon_device *rdev = p->rdev;
507 	struct radeon_bo_va *bo_va;
508 	int i, r;
509 
510 	r = radeon_vm_update_page_directory(rdev, vm);
511 	if (r)
512 		return r;
513 
514 	r = radeon_vm_clear_freed(rdev, vm);
515 	if (r)
516 		return r;
517 
518 	if (vm->ib_bo_va == NULL) {
519 		DRM_ERROR("Tmp BO not in VM!\n");
520 		return -EINVAL;
521 	}
522 
523 	r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
524 				rdev->ring_tmp_bo.bo->tbo.resource);
525 	if (r)
526 		return r;
527 
528 	for (i = 0; i < p->nrelocs; i++) {
529 		struct radeon_bo *bo;
530 
531 		bo = p->relocs[i].robj;
532 		bo_va = radeon_vm_bo_find(vm, bo);
533 		if (bo_va == NULL) {
534 			dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
535 			return -EINVAL;
536 		}
537 
538 		r = radeon_vm_bo_update(rdev, bo_va, bo->tbo.resource);
539 		if (r)
540 			return r;
541 
542 		radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update);
543 
544 		r = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
545 		if (r)
546 			return r;
547 	}
548 
549 	return radeon_vm_clear_invalids(rdev, vm);
550 }
551 
radeon_cs_ib_vm_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)552 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
553 				 struct radeon_cs_parser *parser)
554 {
555 	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
556 	struct radeon_vm *vm = &fpriv->vm;
557 	int r;
558 
559 	if (parser->chunk_ib == NULL)
560 		return 0;
561 	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
562 		return 0;
563 
564 	if (parser->const_ib.length_dw) {
565 		r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
566 		if (r) {
567 			return r;
568 		}
569 	}
570 
571 	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
572 	if (r) {
573 		return r;
574 	}
575 
576 	if (parser->ring == R600_RING_TYPE_UVD_INDEX)
577 		radeon_uvd_note_usage(rdev);
578 
579 	mutex_lock(&vm->mutex);
580 	r = radeon_bo_vm_update_pte(parser, vm);
581 	if (r) {
582 		goto out;
583 	}
584 
585 	r = radeon_cs_sync_rings(parser);
586 	if (r) {
587 		if (r != -ERESTARTSYS)
588 			DRM_ERROR("Failed to sync rings: %i\n", r);
589 		goto out;
590 	}
591 
592 	if ((rdev->family >= CHIP_TAHITI) &&
593 	    (parser->chunk_const_ib != NULL)) {
594 		r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
595 	} else {
596 		r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
597 	}
598 
599 out:
600 	mutex_unlock(&vm->mutex);
601 	return r;
602 }
603 
radeon_cs_handle_lockup(struct radeon_device * rdev,int r)604 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
605 {
606 	if (r == -EDEADLK) {
607 		r = radeon_gpu_reset(rdev);
608 		if (!r)
609 			r = -EAGAIN;
610 	}
611 	return r;
612 }
613 
radeon_cs_ib_fill(struct radeon_device * rdev,struct radeon_cs_parser * parser)614 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
615 {
616 	struct radeon_cs_chunk *ib_chunk;
617 	struct radeon_vm *vm = NULL;
618 	int r;
619 
620 	if (parser->chunk_ib == NULL)
621 		return 0;
622 
623 	if (parser->cs_flags & RADEON_CS_USE_VM) {
624 		struct radeon_fpriv *fpriv = parser->filp->driver_priv;
625 		vm = &fpriv->vm;
626 
627 		if ((rdev->family >= CHIP_TAHITI) &&
628 		    (parser->chunk_const_ib != NULL)) {
629 			ib_chunk = parser->chunk_const_ib;
630 			if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
631 				DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
632 				return -EINVAL;
633 			}
634 			r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
635 					   vm, ib_chunk->length_dw * 4);
636 			if (r) {
637 				DRM_ERROR("Failed to get const ib !\n");
638 				return r;
639 			}
640 			parser->const_ib.is_const_ib = true;
641 			parser->const_ib.length_dw = ib_chunk->length_dw;
642 			if (copy_from_user(parser->const_ib.ptr,
643 					       ib_chunk->user_ptr,
644 					       ib_chunk->length_dw * 4))
645 				return -EFAULT;
646 		}
647 
648 		ib_chunk = parser->chunk_ib;
649 		if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
650 			DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
651 			return -EINVAL;
652 		}
653 	}
654 	ib_chunk = parser->chunk_ib;
655 
656 	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
657 			   vm, ib_chunk->length_dw * 4);
658 	if (r) {
659 		DRM_ERROR("Failed to get ib !\n");
660 		return r;
661 	}
662 	parser->ib.length_dw = ib_chunk->length_dw;
663 	if (ib_chunk->kdata)
664 		memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
665 	else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
666 		return -EFAULT;
667 	return 0;
668 }
669 
radeon_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)670 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
671 {
672 	struct radeon_device *rdev = dev->dev_private;
673 	struct radeon_cs_parser parser;
674 	int r;
675 
676 	down_read(&rdev->exclusive_lock);
677 	if (!rdev->accel_working) {
678 		up_read(&rdev->exclusive_lock);
679 		return -EBUSY;
680 	}
681 	if (rdev->in_reset) {
682 		up_read(&rdev->exclusive_lock);
683 		r = radeon_gpu_reset(rdev);
684 		if (!r)
685 			r = -EAGAIN;
686 		return r;
687 	}
688 	/* initialize parser */
689 	memset(&parser, 0, sizeof(struct radeon_cs_parser));
690 	parser.filp = filp;
691 	parser.rdev = rdev;
692 	parser.dev = rdev->dev;
693 	parser.family = rdev->family;
694 	r = radeon_cs_parser_init(&parser, data);
695 	if (r) {
696 		DRM_ERROR("Failed to initialize parser !\n");
697 		radeon_cs_parser_fini(&parser, r);
698 		up_read(&rdev->exclusive_lock);
699 		r = radeon_cs_handle_lockup(rdev, r);
700 		return r;
701 	}
702 
703 	r = radeon_cs_ib_fill(rdev, &parser);
704 	if (!r) {
705 		r = radeon_cs_parser_relocs(&parser);
706 		if (r && r != -ERESTARTSYS)
707 			DRM_ERROR("Failed to parse relocation %d!\n", r);
708 	}
709 
710 	if (r) {
711 		radeon_cs_parser_fini(&parser, r);
712 		up_read(&rdev->exclusive_lock);
713 		r = radeon_cs_handle_lockup(rdev, r);
714 		return r;
715 	}
716 
717 	trace_radeon_cs(&parser);
718 
719 	r = radeon_cs_ib_chunk(rdev, &parser);
720 	if (r) {
721 		goto out;
722 	}
723 	r = radeon_cs_ib_vm_chunk(rdev, &parser);
724 	if (r) {
725 		goto out;
726 	}
727 out:
728 	radeon_cs_parser_fini(&parser, r);
729 	up_read(&rdev->exclusive_lock);
730 	r = radeon_cs_handle_lockup(rdev, r);
731 	return r;
732 }
733 
734 /**
735  * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
736  * @p:		parser structure holding parsing context.
737  * @pkt:	where to store packet information
738  * @idx:	packet index
739  *
740  * Assume that chunk_ib_index is properly set. Will return -EINVAL
741  * if packet is bigger than remaining ib size. or if packets is unknown.
742  **/
radeon_cs_packet_parse(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx)743 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
744 			   struct radeon_cs_packet *pkt,
745 			   unsigned idx)
746 {
747 	struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
748 	struct radeon_device *rdev = p->rdev;
749 	uint32_t header;
750 	int ret = 0, i;
751 
752 	if (idx >= ib_chunk->length_dw) {
753 		DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
754 			  idx, ib_chunk->length_dw);
755 		return -EINVAL;
756 	}
757 	header = radeon_get_ib_value(p, idx);
758 	pkt->idx = idx;
759 	pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
760 	pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
761 	pkt->one_reg_wr = 0;
762 	switch (pkt->type) {
763 	case RADEON_PACKET_TYPE0:
764 		if (rdev->family < CHIP_R600) {
765 			pkt->reg = R100_CP_PACKET0_GET_REG(header);
766 			pkt->one_reg_wr =
767 				RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
768 		} else
769 			pkt->reg = R600_CP_PACKET0_GET_REG(header);
770 		break;
771 	case RADEON_PACKET_TYPE3:
772 		pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
773 		break;
774 	case RADEON_PACKET_TYPE2:
775 		pkt->count = -1;
776 		break;
777 	default:
778 		DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
779 		ret = -EINVAL;
780 		goto dump_ib;
781 	}
782 	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
783 		DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
784 			  pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
785 		ret = -EINVAL;
786 		goto dump_ib;
787 	}
788 	return 0;
789 
790 dump_ib:
791 	for (i = 0; i < ib_chunk->length_dw; i++) {
792 		if (i == idx)
793 			printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
794 		else
795 			printk("\t0x%08x\n", radeon_get_ib_value(p, i));
796 	}
797 	return ret;
798 }
799 
800 /**
801  * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
802  * @p:		structure holding the parser context.
803  *
804  * Check if the next packet is NOP relocation packet3.
805  **/
radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser * p)806 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
807 {
808 	struct radeon_cs_packet p3reloc;
809 	int r;
810 
811 	r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
812 	if (r)
813 		return false;
814 	if (p3reloc.type != RADEON_PACKET_TYPE3)
815 		return false;
816 	if (p3reloc.opcode != RADEON_PACKET3_NOP)
817 		return false;
818 	return true;
819 }
820 
821 /**
822  * radeon_cs_dump_packet() - dump raw packet context
823  * @p:		structure holding the parser context.
824  * @pkt:	structure holding the packet.
825  *
826  * Used mostly for debugging and error reporting.
827  **/
radeon_cs_dump_packet(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)828 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
829 			   struct radeon_cs_packet *pkt)
830 {
831 	volatile uint32_t *ib;
832 	unsigned i;
833 	unsigned idx;
834 
835 	ib = p->ib.ptr;
836 	idx = pkt->idx;
837 	for (i = 0; i <= (pkt->count + 1); i++, idx++)
838 		DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
839 }
840 
841 /**
842  * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
843  * @p:			parser structure holding parsing context.
844  * @cs_reloc:		reloc informations
845  * @nomm:		no memory management for debugging
846  *
847  * Check if next packet is relocation packet3, do bo validation and compute
848  * GPU offset using the provided start.
849  **/
radeon_cs_packet_next_reloc(struct radeon_cs_parser * p,struct radeon_bo_list ** cs_reloc,int nomm)850 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
851 				struct radeon_bo_list **cs_reloc,
852 				int nomm)
853 {
854 	struct radeon_cs_chunk *relocs_chunk;
855 	struct radeon_cs_packet p3reloc;
856 	unsigned idx;
857 	int r;
858 
859 	if (p->chunk_relocs == NULL) {
860 		DRM_ERROR("No relocation chunk !\n");
861 		return -EINVAL;
862 	}
863 	*cs_reloc = NULL;
864 	relocs_chunk = p->chunk_relocs;
865 	r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
866 	if (r)
867 		return r;
868 	p->idx += p3reloc.count + 2;
869 	if (p3reloc.type != RADEON_PACKET_TYPE3 ||
870 	    p3reloc.opcode != RADEON_PACKET3_NOP) {
871 		DRM_ERROR("No packet3 for relocation for packet at %d.\n",
872 			  p3reloc.idx);
873 		radeon_cs_dump_packet(p, &p3reloc);
874 		return -EINVAL;
875 	}
876 	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
877 	if (idx >= relocs_chunk->length_dw) {
878 		DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
879 			  idx, relocs_chunk->length_dw);
880 		radeon_cs_dump_packet(p, &p3reloc);
881 		return -EINVAL;
882 	}
883 	/* FIXME: we assume reloc size is 4 dwords */
884 	if (nomm) {
885 		*cs_reloc = p->relocs;
886 		(*cs_reloc)->gpu_offset =
887 			(u64)relocs_chunk->kdata[idx + 3] << 32;
888 		(*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
889 	} else
890 		*cs_reloc = &p->relocs[(idx / 4)];
891 	return 0;
892 }
893