xref: /titanic_51/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h (revision 56b2bdd1f04d465cfe4a95b88ae5cba5884154e4)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Chelsio Terminator 4 (T4) Firmware interface header file.
14  *
15  * Copyright (C) 2009-2013 Chelsio Communications.  All rights reserved.
16  *
17  * Written by felix marti (felix@chelsio.com)
18  *
19  * This program is distributed in the hope that it will be useful, but WITHOUT
20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
22  * release for licensing terms and conditions.
23  */
24 #ifndef _T4FW_INTERFACE_H_
25 #define	_T4FW_INTERFACE_H_
26 
27 /*
28  *	******************************
29  *	   R E T U R N   V A L U E S
30  *	******************************
31  */
32 
33 enum fw_retval {
34 	FW_SUCCESS		= 0,	/* completed sucessfully */
35 	FW_EPERM		= 1,	/* operation not permitted */
36 	FW_ENOENT		= 2,	/* no such file or directory */
37 	FW_EIO			= 5,	/* input/output error; hw bad */
38 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
39 	FW_EAGAIN		= 11,	/* try again */
40 	FW_ENOMEM		= 12,	/* out of memory */
41 	FW_EFAULT		= 14,	/* bad address; fw bad */
42 	FW_EBUSY		= 16,	/* resource busy */
43 	FW_EEXIST		= 17,	/* file exists */
44 	FW_EINVAL		= 22,	/* invalid argument */
45 	FW_ENOSPC		= 28,	/* no space left on device */
46 	FW_ENOSYS		= 38,	/* functionality not implemented */
47 	FW_EPROTO		= 71,	/* protocol error */
48 	FW_EADDRINUSE		= 98,	/* address already in use */
49 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
50 	FW_ENETDOWN		= 100,	/* network is down */
51 	FW_ENETUNREACH		= 101,	/* network is unreachable */
52 	FW_ENOBUFS		= 105,	/* no buffer space available */
53 	FW_ETIMEDOUT		= 110,	/* timeout */
54 	FW_EINPROGRESS		= 115,	/* fw internal */
55 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
56 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
57 	FW_SCSI_ABORTED		= 130,	/* */
58 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
59 	FW_ERR_LINK_DOWN	= 132,	/* */
60 	FW_RDEV_NOT_READY	= 133,	/* */
61 	FW_ERR_RDEV_LOST	= 134,	/* */
62 	FW_ERR_RDEV_LOGO	= 135,	/* */
63 	FW_FCOE_NO_XCHG		= 136,	/* */
64 	FW_SCSI_RSP_ERR		= 137,	/* */
65 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
66 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
67 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
68 	FW_SCSI_DDP_ERR		= 141,	/* DDP error */
69 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
70 };
71 
72 /*
73  *	******************************
74  *	   W O R K   R E Q U E S T s
75  *	******************************
76  */
77 
78 enum fw_wr_opcodes {
79 	FW_FILTER_WR		= 0x02,
80 	FW_ULPTX_WR		= 0x04,
81 	FW_TP_WR		= 0x05,
82 	FW_ETH_TX_PKT_WR	= 0x08,
83 	FW_ETH_TX_PKTS_WR	= 0x09,
84 	FW_ETH_TX_UO_WR		= 0x1c,
85 	FW_EQ_FLUSH_WR		= 0x1b,
86 	FW_OFLD_CONNECTION_WR	= 0x2f,
87 	FW_FLOWC_WR		= 0x0a,
88 	FW_OFLD_TX_DATA_WR	= 0x0b,
89 	FW_CMD_WR		= 0x10,
90 	FW_ETH_TX_PKT_VM_WR	= 0x11,
91 	FW_RI_RES_WR		= 0x0c,
92 	FW_RI_RDMA_WRITE_WR	= 0x14,
93 	FW_RI_SEND_WR		= 0x15,
94 	FW_RI_RDMA_READ_WR	= 0x16,
95 	FW_RI_RECV_WR		= 0x17,
96 	FW_RI_BIND_MW_WR	= 0x18,
97 	FW_RI_FR_NSMR_WR	= 0x19,
98 	FW_RI_INV_LSTAG_WR	= 0x1a,
99 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
100 	FW_RI_ATOMIC_WR		= 0x16,
101 	FW_RI_WR		= 0x0d,
102 	FW_CHNET_IFCONF_WR	= 0x6b,
103 	FW_RDEV_WR		= 0x38,
104 	FW_FOISCSI_NODE_WR	= 0x60,
105 	FW_FOISCSI_CTRL_WR	= 0x6a,
106 	FW_FOISCSI_CHAP_WR	= 0x6c,
107 	FW_FCOE_ELS_CT_WR	= 0x30,
108 	FW_SCSI_WRITE_WR	= 0x31,
109 	FW_SCSI_READ_WR		= 0x32,
110 	FW_SCSI_CMD_WR		= 0x33,
111 	FW_SCSI_ABRT_CLS_WR	= 0x34,
112 	FW_SCSI_TGT_ACC_WR	= 0x35,
113 	FW_SCSI_TGT_XMIT_WR	= 0x36,
114 	FW_SCSI_TGT_RSP_WR	= 0x37,
115 	FW_LASTC2E_WR		= 0x70
116 };
117 
118 /*
119  * Generic work request header flit0
120  */
121 struct fw_wr_hdr {
122 	__be32 hi;
123 	__be32 lo;
124 };
125 
126 /* work request opcode (hi) */
127 #define	S_FW_WR_OP		24
128 #define	M_FW_WR_OP		0xff
129 #define	V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
130 #define	G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
131 
132 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
133 #define	S_FW_WR_ATOMIC		23
134 #define	M_FW_WR_ATOMIC		0x1
135 #define	V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
136 #define	G_FW_WR_ATOMIC(x)	\
137 	(((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
138 #define	F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
139 
140 /*
141  *	flush flag (hi) - firmware flushes flushable work request buffered
142  *	in the flow context.
143  */
144 #define	S_FW_WR_FLUSH	22
145 #define	M_FW_WR_FLUSH	0x1
146 #define	V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
147 #define	G_FW_WR_FLUSH(x)  \
148 	(((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
149 #define	F_FW_WR_FLUSH	V_FW_WR_FLUSH(1U)
150 
151 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
152 #define	S_FW_WR_COMPL	21
153 #define	M_FW_WR_COMPL	0x1
154 #define	V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
155 #define	G_FW_WR_COMPL(x)  \
156 	(((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
157 #define	F_FW_WR_COMPL	V_FW_WR_COMPL(1U)
158 
159 /* work request immediate data lengh (hi) */
160 #define	S_FW_WR_IMMDLEN	0
161 #define	M_FW_WR_IMMDLEN	0xff
162 #define	V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
163 #define	G_FW_WR_IMMDLEN(x)	\
164 	(((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
165 
166 /* egress queue status update to associated ingress queue entry (lo) */
167 #define	S_FW_WR_EQUIQ		31
168 #define	M_FW_WR_EQUIQ		0x1
169 #define	V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
170 #define	G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
171 #define	F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
172 
173 /* egress queue status update to egress queue status entry (lo) */
174 #define	S_FW_WR_EQUEQ		30
175 #define	M_FW_WR_EQUEQ		0x1
176 #define	V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
177 #define	G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
178 #define	F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
179 
180 /* flow context identifier (lo) */
181 #define	S_FW_WR_FLOWID		8
182 #define	M_FW_WR_FLOWID		0xfffff
183 #define	V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
184 #define	G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
185 
186 /* length in units of 16-bytes (lo) */
187 #define	S_FW_WR_LEN16		0
188 #define	M_FW_WR_LEN16		0xff
189 #define	V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
190 #define	G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
191 
192 /*
193  * valid filter configurations for compressed tuple
194  * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
195  * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
196  * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
197  * OV - Outer VLAN/VNIC_ID,
198  */
199 #define	HW_TPL_FR_MT_M_E_P_FC		0x3C3
200 #define	HW_TPL_FR_MT_M_PR_T_FC		0x3B3
201 #define	HW_TPL_FR_MT_M_IV_P_FC		0x38B
202 #define	HW_TPL_FR_MT_M_OV_P_FC		0x387
203 #define	HW_TPL_FR_MT_E_PR_T		0x370
204 #define	HW_TPL_FR_MT_E_PR_P_FC		0X363
205 #define	HW_TPL_FR_MT_E_T_P_FC		0X353
206 #define	HW_TPL_FR_MT_PR_IV_P_FC		0X32B
207 #define	HW_TPL_FR_MT_PR_OV_P_FC		0X327
208 #define	HW_TPL_FR_MT_T_IV_P_FC		0X31B
209 #define	HW_TPL_FR_MT_T_OV_P_FC		0X317
210 #define	HW_TPL_FR_M_E_PR_FC		0X2E1
211 #define	HW_TPL_FR_M_E_T_FC		0X2D1
212 #define	HW_TPL_FR_M_PR_IV_FC		0X2A9
213 #define	HW_TPL_FR_M_PR_OV_FC		0X2A5
214 #define	HW_TPL_FR_M_T_IV_FC		0X299
215 #define	HW_TPL_FR_M_T_OV_FC		0X295
216 #define	HW_TPL_FR_E_PR_T_P		0X272
217 #define	HW_TPL_FR_E_PR_T_FC		0X271
218 #define	HW_TPL_FR_E_IV_FC		0X249
219 #define	HW_TPL_FR_E_OV_FC		0X245
220 #define	HW_TPL_FR_PR_T_IV_FC		0X239
221 #define	HW_TPL_FR_PR_T_OV_FC		0X235
222 #define	HW_TPL_FR_IV_OV_FC		0X20D
223 #define	HW_TPL_MT_M_E_PR		0X1E0
224 #define	HW_TPL_MT_M_E_T			0X1D0
225 #define	HW_TPL_MT_E_PR_T_FC		0X171
226 #define	HW_TPL_MT_E_IV			0X148
227 #define	HW_TPL_MT_E_OV			0X144
228 #define	HW_TPL_MT_PR_T_IV		0X138
229 #define	HW_TPL_MT_PR_T_OV		0X134
230 #define	HW_TPL_M_E_PR_P			0X0E2
231 #define	HW_TPL_M_E_T_P			0X0D2
232 #define	HW_TPL_E_PR_T_P_FC		0X073
233 #define	HW_TPL_E_IV_P			0X04A
234 #define	HW_TPL_E_OV_P			0X046
235 #define	HW_TPL_PR_T_IV_P		0X03A
236 #define	HW_TPL_PR_T_OV_P		0X036
237 
238 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
239 enum fw_filter_wr_cookie {
240 	FW_FILTER_WR_SUCCESS,
241 	FW_FILTER_WR_FLT_ADDED,
242 	FW_FILTER_WR_FLT_DELETED,
243 	FW_FILTER_WR_SMT_TBL_FULL,
244 	FW_FILTER_WR_EINVAL,
245 };
246 
247 struct fw_filter_wr {
248 	__be32 op_pkd;
249 	__be32 len16_pkd;
250 	__be64 r3;
251 	__be32 tid_to_iq;
252 	__be32 del_filter_to_l2tix;
253 	__be16 ethtype;
254 	__be16 ethtypem;
255 	__u8   frag_to_ovlan_vldm;
256 	__u8   smac_sel;
257 	__be16 rx_chan_rx_rpl_iq;
258 	__be32 maci_to_matchtypem;
259 	__u8   ptcl;
260 	__u8   ptclm;
261 	__u8   ttyp;
262 	__u8   ttypm;
263 	__be16 ivlan;
264 	__be16 ivlanm;
265 	__be16 ovlan;
266 	__be16 ovlanm;
267 	__u8   lip[16];
268 	__u8   lipm[16];
269 	__u8   fip[16];
270 	__u8   fipm[16];
271 	__be16 lp;
272 	__be16 lpm;
273 	__be16 fp;
274 	__be16 fpm;
275 	__be16 r7;
276 	__u8   sma[6];
277 };
278 
279 #define	S_FW_FILTER_WR_TID	12
280 #define	M_FW_FILTER_WR_TID	0xfffff
281 #define	V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
282 #define	G_FW_FILTER_WR_TID(x)	\
283 	(((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
284 
285 #define	S_FW_FILTER_WR_RQTYPE		11
286 #define	M_FW_FILTER_WR_RQTYPE		0x1
287 #define	V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
288 #define	G_FW_FILTER_WR_RQTYPE(x)	\
289 	(((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
290 #define	F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
291 
292 #define	S_FW_FILTER_WR_NOREPLY		10
293 #define	M_FW_FILTER_WR_NOREPLY		0x1
294 #define	V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
295 #define	G_FW_FILTER_WR_NOREPLY(x)	\
296 	(((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
297 #define	F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
298 
299 #define	S_FW_FILTER_WR_IQ	0
300 #define	M_FW_FILTER_WR_IQ	0x3ff
301 #define	V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
302 #define	G_FW_FILTER_WR_IQ(x)	\
303 	(((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
304 
305 #define	S_FW_FILTER_WR_DEL_FILTER	31
306 #define	M_FW_FILTER_WR_DEL_FILTER	0x1
307 #define	V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
308 #define	G_FW_FILTER_WR_DEL_FILTER(x)	\
309 	(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
310 #define	F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
311 
312 #define	S_FW_FILTER_WR_RPTTID		25
313 #define	M_FW_FILTER_WR_RPTTID		0x1
314 #define	V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
315 #define	G_FW_FILTER_WR_RPTTID(x)	\
316 	(((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
317 #define	F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
318 
319 #define	S_FW_FILTER_WR_DROP	24
320 #define	M_FW_FILTER_WR_DROP	0x1
321 #define	V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
322 #define	G_FW_FILTER_WR_DROP(x)	\
323 	(((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
324 #define	F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
325 
326 #define	S_FW_FILTER_WR_DIRSTEER		23
327 #define	M_FW_FILTER_WR_DIRSTEER		0x1
328 #define	V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
329 #define	G_FW_FILTER_WR_DIRSTEER(x)	\
330 	(((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
331 #define	F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
332 
333 #define	S_FW_FILTER_WR_MASKHASH		22
334 #define	M_FW_FILTER_WR_MASKHASH		0x1
335 #define	V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
336 #define	G_FW_FILTER_WR_MASKHASH(x)	\
337 	(((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
338 #define	F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
339 
340 #define	S_FW_FILTER_WR_DIRSTEERHASH	21
341 #define	M_FW_FILTER_WR_DIRSTEERHASH	0x1
342 #define	V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
343 #define	G_FW_FILTER_WR_DIRSTEERHASH(x)	\
344 	(((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
345 #define	F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
346 
347 #define	S_FW_FILTER_WR_LPBK	20
348 #define	M_FW_FILTER_WR_LPBK	0x1
349 #define	V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
350 #define	G_FW_FILTER_WR_LPBK(x)	\
351 	(((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
352 #define	F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
353 
354 #define	S_FW_FILTER_WR_DMAC	19
355 #define	M_FW_FILTER_WR_DMAC	0x1
356 #define	V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
357 #define	G_FW_FILTER_WR_DMAC(x)	\
358 	(((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
359 #define	F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
360 
361 #define	S_FW_FILTER_WR_SMAC	18
362 #define	M_FW_FILTER_WR_SMAC	0x1
363 #define	V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
364 #define	G_FW_FILTER_WR_SMAC(x)	\
365 	(((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
366 #define	F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
367 
368 #define	S_FW_FILTER_WR_INSVLAN		17
369 #define	M_FW_FILTER_WR_INSVLAN		0x1
370 #define	V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
371 #define	G_FW_FILTER_WR_INSVLAN(x)	\
372 	(((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
373 #define	F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
374 
375 #define	S_FW_FILTER_WR_RMVLAN		16
376 #define	M_FW_FILTER_WR_RMVLAN		0x1
377 #define	V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
378 #define	G_FW_FILTER_WR_RMVLAN(x)	\
379 	(((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
380 #define	F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
381 
382 #define	S_FW_FILTER_WR_HITCNTS		15
383 #define	M_FW_FILTER_WR_HITCNTS		0x1
384 #define	V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
385 #define	G_FW_FILTER_WR_HITCNTS(x)	\
386 	(((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
387 #define	F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
388 
389 #define	S_FW_FILTER_WR_TXCHAN		13
390 #define	M_FW_FILTER_WR_TXCHAN		0x3
391 #define	V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
392 #define	G_FW_FILTER_WR_TXCHAN(x)	\
393 	(((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
394 
395 #define	S_FW_FILTER_WR_PRIO	12
396 #define	M_FW_FILTER_WR_PRIO	0x1
397 #define	V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
398 #define	G_FW_FILTER_WR_PRIO(x)	\
399 	(((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
400 #define	F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
401 
402 #define	S_FW_FILTER_WR_L2TIX	0
403 #define	M_FW_FILTER_WR_L2TIX	0xfff
404 #define	V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
405 #define	G_FW_FILTER_WR_L2TIX(x)	\
406 	(((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
407 
408 #define	S_FW_FILTER_WR_FRAG	7
409 #define	M_FW_FILTER_WR_FRAG	0x1
410 #define	V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
411 #define	G_FW_FILTER_WR_FRAG(x)	\
412 	(((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
413 #define	F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
414 
415 #define	S_FW_FILTER_WR_FRAGM	6
416 #define	M_FW_FILTER_WR_FRAGM	0x1
417 #define	V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
418 #define	G_FW_FILTER_WR_FRAGM(x)	\
419 	(((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
420 #define	F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
421 
422 #define	S_FW_FILTER_WR_IVLAN_VLD	5
423 #define	M_FW_FILTER_WR_IVLAN_VLD	0x1
424 #define	V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
425 #define	G_FW_FILTER_WR_IVLAN_VLD(x)	\
426 	(((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
427 #define	F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
428 
429 #define	S_FW_FILTER_WR_OVLAN_VLD	4
430 #define	M_FW_FILTER_WR_OVLAN_VLD	0x1
431 #define	V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
432 #define	G_FW_FILTER_WR_OVLAN_VLD(x)	\
433 	(((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
434 #define	F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
435 
436 #define	S_FW_FILTER_WR_IVLAN_VLDM	3
437 #define	M_FW_FILTER_WR_IVLAN_VLDM	0x1
438 #define	V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
439 #define	G_FW_FILTER_WR_IVLAN_VLDM(x)	\
440 	(((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
441 #define	F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
442 
443 #define	S_FW_FILTER_WR_OVLAN_VLDM	2
444 #define	M_FW_FILTER_WR_OVLAN_VLDM	0x1
445 #define	V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
446 #define	G_FW_FILTER_WR_OVLAN_VLDM(x)	\
447 	(((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
448 #define	F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
449 
450 #define	S_FW_FILTER_WR_RX_CHAN		15
451 #define	M_FW_FILTER_WR_RX_CHAN		0x1
452 #define	V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
453 #define	G_FW_FILTER_WR_RX_CHAN(x)	\
454 	(((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
455 #define	F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
456 
457 #define	S_FW_FILTER_WR_RX_RPL_IQ	0
458 #define	M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
459 #define	V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
460 #define	G_FW_FILTER_WR_RX_RPL_IQ(x)	\
461 	(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
462 
463 #define	S_FW_FILTER_WR_MACI	23
464 #define	M_FW_FILTER_WR_MACI	0x1ff
465 #define	V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
466 #define	G_FW_FILTER_WR_MACI(x)	\
467 	(((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
468 
469 #define	S_FW_FILTER_WR_MACIM	14
470 #define	M_FW_FILTER_WR_MACIM	0x1ff
471 #define	V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
472 #define	G_FW_FILTER_WR_MACIM(x)	\
473 	(((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
474 
475 #define	S_FW_FILTER_WR_FCOE	13
476 #define	M_FW_FILTER_WR_FCOE	0x1
477 #define	V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
478 #define	G_FW_FILTER_WR_FCOE(x)	\
479 	(((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
480 #define	F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
481 
482 #define	S_FW_FILTER_WR_FCOEM	12
483 #define	M_FW_FILTER_WR_FCOEM	0x1
484 #define	V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
485 #define	G_FW_FILTER_WR_FCOEM(x)	\
486 	(((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
487 #define	F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
488 
489 #define	S_FW_FILTER_WR_PORT	9
490 #define	M_FW_FILTER_WR_PORT	0x7
491 #define	V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
492 #define	G_FW_FILTER_WR_PORT(x)	\
493 	(((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
494 
495 #define	S_FW_FILTER_WR_PORTM	6
496 #define	M_FW_FILTER_WR_PORTM	0x7
497 #define	V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
498 #define	G_FW_FILTER_WR_PORTM(x)	\
499 	(((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
500 
501 #define	S_FW_FILTER_WR_MATCHTYPE	3
502 #define	M_FW_FILTER_WR_MATCHTYPE	0x7
503 #define	V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
504 #define	G_FW_FILTER_WR_MATCHTYPE(x)	\
505 	(((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
506 
507 #define	S_FW_FILTER_WR_MATCHTYPEM	0
508 #define	M_FW_FILTER_WR_MATCHTYPEM	0x7
509 #define	V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
510 #define	G_FW_FILTER_WR_MATCHTYPEM(x)	\
511 	(((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
512 
513 struct fw_ulptx_wr {
514 	__be32 op_to_compl;
515 	__be32 flowid_len16;
516 	__u64  cookie;
517 };
518 
519 struct fw_tp_wr {
520 	__be32 op_to_immdlen;
521 	__be32 flowid_len16;
522 	__u64  cookie;
523 };
524 
525 struct fw_eth_tx_pkt_wr {
526 	__be32 op_immdlen;
527 	__be32 equiq_to_len16;
528 	__be64 r3;
529 };
530 
531 #define	S_FW_ETH_TX_PKT_WR_IMMDLEN	0
532 #define	M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
533 #define	V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
534 #define	G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
535 	(((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
536 
537 struct fw_eth_tx_pkts_wr {
538 	__be32 op_pkd;
539 	__be32 equiq_to_len16;
540 	__be32 r3;
541 	__be16 plen;
542 	__u8   npkt;
543 	__u8   type;
544 };
545 
546 struct fw_eth_tx_uo_wr {
547 	__be32 op_immdlen;
548 	__be32 equiq_to_len16;
549 	__be64 r3;
550 	__be16 ethlen;
551 	__be16 iplen;
552 	__be16 udplen;
553 	__be16 mss;
554 	__be32 length;
555 	__be32 r4;
556 };
557 
558 struct fw_eq_flush_wr {
559 	__u8   opcode;
560 	__u8   r1[3];
561 	__be32 equiq_to_len16;
562 	__be64 r3;
563 };
564 
565 struct fw_ofld_connection_wr {
566 	__be32 op_compl;
567 	__be32 len16_pkd;
568 	__u64  cookie;
569 	__be64 r2;
570 	__be64 r3;
571 	struct fw_ofld_connection_le {
572 		__be32 version_cpl;
573 		__be32 filter;
574 		__be32 r1;
575 		__be16 lport;
576 		__be16 pport;
577 		union fw_ofld_connection_leip {
578 			struct fw_ofld_connection_le_ipv4 {
579 				__be32 pip;
580 				__be32 lip;
581 				__be64 r0;
582 				__be64 r1;
583 				__be64 r2;
584 			} ipv4;
585 			struct fw_ofld_connection_le_ipv6 {
586 				__be64 pip_hi;
587 				__be64 pip_lo;
588 				__be64 lip_hi;
589 				__be64 lip_lo;
590 			} ipv6;
591 		} u;
592 	} le;
593 	struct fw_ofld_connection_tcb {
594 		__be32 t_state_to_astid;
595 		__be16 cplrxdataack_cplpassacceptrpl;
596 		__be16 rcv_adv;
597 		__be32 rcv_nxt;
598 		__be32 tx_max;
599 		__be64 opt0;
600 		__be32 opt2;
601 		__be32 r1;
602 		__be64 r2;
603 		__be64 r3;
604 	} tcb;
605 };
606 
607 #define	S_FW_OFLD_CONNECTION_WR_VERSION		31
608 #define	M_FW_OFLD_CONNECTION_WR_VERSION		0x1
609 #define	V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
610 	((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
611 #define	G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
612 	(((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
613 	M_FW_OFLD_CONNECTION_WR_VERSION)
614 #define	F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
615 
616 #define	S_FW_OFLD_CONNECTION_WR_CPL	30
617 #define	M_FW_OFLD_CONNECTION_WR_CPL	0x1
618 #define	V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
619 #define	G_FW_OFLD_CONNECTION_WR_CPL(x)	\
620 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
621 #define	F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
622 
623 #define	S_FW_OFLD_CONNECTION_WR_T_STATE		28
624 #define	M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
625 #define	V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
626 	((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
627 #define	G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
628 	(((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
629 	M_FW_OFLD_CONNECTION_WR_T_STATE)
630 
631 #define	S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
632 #define	M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
633 #define	V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
634 	((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
635 #define	G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
636 	(((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
637 	M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
638 
639 #define	S_FW_OFLD_CONNECTION_WR_ASTID		0
640 #define	M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
641 #define	V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
642 	((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
643 #define	G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
644 	(((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
645 
646 #define	S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
647 #define	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
648 #define	V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
649 	((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
650 #define	G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
651 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
652 	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
653 #define	F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
654     V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
655 
656 #define	S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
657 #define	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
658 #define	V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
659 	((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
660 #define	G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
661 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
662 	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
663 #define	F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
664     V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
665 
666 enum fw_flowc_mnem_tcpstate {
667 	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0,	/* illegal */
668 	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1,	/* illegal */
669 	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2,	/* illegal */
670 	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3,	/* illegal */
671 	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4,	/* default */
672 	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5,	/* got peer close already */
673 	/* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */
674 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6,
675 	/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
676 	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7,
677 	/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
678 	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8,
679 	/* sent FIN and got FIN + ACK, waiting for FIN */
680 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9,
681 	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10,	/* not expected */
682 };
683 
684 enum fw_flowc_mnem_uostate {
685 	FW_FLOWC_MNEM_UOSTATE_CLOSED	= 0,	/* illegal */
686 	FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1,	/* default */
687 	/* graceful close, after sending outstanding payload */
688 	FW_FLOWC_MNEM_UOSTATE_CLOSING	= 2,
689 	/* immediate close, after discarding outstanding payload */
690 	FW_FLOWC_MNEM_UOSTATE_ABORTING	= 3,
691 };
692 
693 enum fw_flowc_mnem {
694 	FW_FLOWC_MNEM_PFNVFN,		/* PFN [15:8] VFN [7:0] */
695 	FW_FLOWC_MNEM_CH,
696 	FW_FLOWC_MNEM_PORT,
697 	FW_FLOWC_MNEM_IQID,
698 	FW_FLOWC_MNEM_SNDNXT,
699 	FW_FLOWC_MNEM_RCVNXT,
700 	FW_FLOWC_MNEM_SNDBUF,
701 	FW_FLOWC_MNEM_MSS,
702 	FW_FLOWC_MNEM_TXDATAPLEN_MAX,
703 	FW_FLOWC_MNEM_TCPSTATE,
704 	FW_FLOWC_MNEM_UOSTATE,
705 	FW_FLOWC_MNEM_SCHEDCLASS,
706 };
707 
708 struct fw_flowc_mnemval {
709 	__u8   mnemonic;
710 	__u8   r4[3];
711 	__be32 val;
712 };
713 
714 struct fw_flowc_wr {
715 	__be32 op_to_nparams;
716 	__be32 flowid_len16;
717 #ifndef C99_NOT_SUPPORTED
718 	struct fw_flowc_mnemval mnemval[];
719 #endif
720 };
721 
722 #define	S_FW_FLOWC_WR_NPARAMS		0
723 #define	M_FW_FLOWC_WR_NPARAMS		0xff
724 #define	V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
725 #define	G_FW_FLOWC_WR_NPARAMS(x)	\
726 	(((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
727 
728 struct fw_ofld_tx_data_wr {
729 	__be32 op_to_immdlen;
730 	__be32 flowid_len16;
731 	__be32 plen;
732 	__be32 tunnel_to_proxy;
733 };
734 
735 #define	S_FW_OFLD_TX_DATA_WR_TUNNEL	19
736 #define	M_FW_OFLD_TX_DATA_WR_TUNNEL	0x1
737 #define	V_FW_OFLD_TX_DATA_WR_TUNNEL(x)	((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL)
738 #define	G_FW_OFLD_TX_DATA_WR_TUNNEL(x)	\
739 	(((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL)
740 #define	F_FW_OFLD_TX_DATA_WR_TUNNEL	V_FW_OFLD_TX_DATA_WR_TUNNEL(1U)
741 
742 #define	S_FW_OFLD_TX_DATA_WR_SAVE	18
743 #define	M_FW_OFLD_TX_DATA_WR_SAVE	0x1
744 #define	V_FW_OFLD_TX_DATA_WR_SAVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SAVE)
745 #define	G_FW_OFLD_TX_DATA_WR_SAVE(x)	\
746 	(((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE)
747 #define	F_FW_OFLD_TX_DATA_WR_SAVE	V_FW_OFLD_TX_DATA_WR_SAVE(1U)
748 
749 #define	S_FW_OFLD_TX_DATA_WR_FLUSH	17
750 #define	M_FW_OFLD_TX_DATA_WR_FLUSH	0x1
751 #define	V_FW_OFLD_TX_DATA_WR_FLUSH(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLUSH)
752 #define	G_FW_OFLD_TX_DATA_WR_FLUSH(x)	\
753 	(((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH)
754 #define	F_FW_OFLD_TX_DATA_WR_FLUSH	V_FW_OFLD_TX_DATA_WR_FLUSH(1U)
755 
756 #define	S_FW_OFLD_TX_DATA_WR_URGENT	16
757 #define	M_FW_OFLD_TX_DATA_WR_URGENT	0x1
758 #define	V_FW_OFLD_TX_DATA_WR_URGENT(x)	((x) << S_FW_OFLD_TX_DATA_WR_URGENT)
759 #define	G_FW_OFLD_TX_DATA_WR_URGENT(x)	\
760 	(((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT)
761 #define	F_FW_OFLD_TX_DATA_WR_URGENT	V_FW_OFLD_TX_DATA_WR_URGENT(1U)
762 
763 #define	S_FW_OFLD_TX_DATA_WR_MORE	15
764 #define	M_FW_OFLD_TX_DATA_WR_MORE	0x1
765 #define	V_FW_OFLD_TX_DATA_WR_MORE(x)	((x) << S_FW_OFLD_TX_DATA_WR_MORE)
766 #define	G_FW_OFLD_TX_DATA_WR_MORE(x)	\
767 	(((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE)
768 #define	F_FW_OFLD_TX_DATA_WR_MORE	V_FW_OFLD_TX_DATA_WR_MORE(1U)
769 
770 #define	S_FW_OFLD_TX_DATA_WR_SHOVE	14
771 #define	M_FW_OFLD_TX_DATA_WR_SHOVE	0x1
772 #define	V_FW_OFLD_TX_DATA_WR_SHOVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SHOVE)
773 #define	G_FW_OFLD_TX_DATA_WR_SHOVE(x)	\
774 	(((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE)
775 #define	F_FW_OFLD_TX_DATA_WR_SHOVE	V_FW_OFLD_TX_DATA_WR_SHOVE(1U)
776 
777 #define	S_FW_OFLD_TX_DATA_WR_ULPMODE	10
778 #define	M_FW_OFLD_TX_DATA_WR_ULPMODE	0xf
779 #define	V_FW_OFLD_TX_DATA_WR_ULPMODE(x)	((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE)
780 #define	G_FW_OFLD_TX_DATA_WR_ULPMODE(x)	\
781 	(((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE)
782 
783 #define	S_FW_OFLD_TX_DATA_WR_ULPSUBMODE		6
784 #define	M_FW_OFLD_TX_DATA_WR_ULPSUBMODE		0xf
785 #define	V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
786 	((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
787 #define	G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
788 	(((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \
789 	M_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
790 
791 #define	S_FW_OFLD_TX_DATA_WR_PROXY	5
792 #define	M_FW_OFLD_TX_DATA_WR_PROXY	0x1
793 #define	V_FW_OFLD_TX_DATA_WR_PROXY(x)	((x) << S_FW_OFLD_TX_DATA_WR_PROXY)
794 #define	G_FW_OFLD_TX_DATA_WR_PROXY(x)	\
795 	(((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY)
796 #define	F_FW_OFLD_TX_DATA_WR_PROXY	V_FW_OFLD_TX_DATA_WR_PROXY(1U)
797 
798 struct fw_cmd_wr {
799 	__be32 op_dma;
800 	__be32 len16_pkd;
801 	__be64 cookie_daddr;
802 };
803 
804 #define	S_FW_CMD_WR_DMA		17
805 #define	M_FW_CMD_WR_DMA		0x1
806 #define	V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
807 #define	G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
808 #define	F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
809 
810 struct fw_eth_tx_pkt_vm_wr {
811 	__be32 op_immdlen;
812 	__be32 equiq_to_len16;
813 	__be32 r3[2];
814 	__u8   ethmacdst[6];
815 	__u8   ethmacsrc[6];
816 	__be16 ethtype;
817 	__be16 vlantci;
818 };
819 
820 /*
821  *	************************************
822  *	   R I   W O R K   R E Q U E S T s
823  *	************************************
824  */
825 
826 enum fw_ri_wr_opcode {
827 	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
828 	FW_RI_READ_REQ			= 0x1,
829 	FW_RI_READ_RESP			= 0x2,
830 	FW_RI_SEND			= 0x3,
831 	FW_RI_SEND_WITH_INV		= 0x4,
832 	FW_RI_SEND_WITH_SE		= 0x5,
833 	FW_RI_SEND_WITH_SE_INV		= 0x6,
834 	FW_RI_TERMINATE			= 0x7,
835 	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
836 	FW_RI_BIND_MW			= 0x9,
837 	FW_RI_FAST_REGISTER		= 0xa,
838 	FW_RI_LOCAL_INV			= 0xb,
839 	FW_RI_QP_MODIFY			= 0xc,
840 	FW_RI_BYPASS			= 0xd,
841 	FW_RI_RECEIVE			= 0xe,
842 	FW_RI_SGE_EC_CR_RETURN		= 0xf
843 
844 };
845 
846 enum fw_ri_wr_flags {
847 	FW_RI_COMPLETION_FLAG		= 0x01,
848 	FW_RI_NOTIFICATION_FLAG		= 0x02,
849 	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
850 	FW_RI_READ_FENCE_FLAG		= 0x08,
851 	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
852 	FW_RI_RDMA_READ_INVALIDATE	= 0x20
853 };
854 
855 enum fw_ri_mpa_attrs {
856 	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
857 	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
858 	FW_RI_MPA_CRC_ENABLE		= 0x04,
859 	FW_RI_MPA_IETF_ENABLE		= 0x08
860 };
861 
862 enum fw_ri_qp_caps {
863 	FW_RI_QP_RDMA_READ_ENABLE	 = 0x01,
864 	FW_RI_QP_RDMA_WRITE_ENABLE	 = 0x02,
865 	FW_RI_QP_BIND_ENABLE		 = 0x04,
866 	FW_RI_QP_FAST_REGISTER_ENABLE	 = 0x08,
867 	FW_RI_QP_STAG0_ENABLE		 = 0x10,
868 	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE = 0x80,
869 };
870 
871 enum fw_ri_addr_type {
872 	FW_RI_ZERO_BASED_TO		= 0x00,
873 	FW_RI_VA_BASED_TO		= 0x01
874 };
875 
876 enum fw_ri_mem_perms {
877 	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
878 	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
879 	FW_RI_MEM_ACCESS_REM		= 0x03,
880 	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
881 	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
882 	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
883 };
884 
885 enum fw_ri_stag_type {
886 	FW_RI_STAG_NSMR			= 0x00,
887 	FW_RI_STAG_SMR			= 0x01,
888 	FW_RI_STAG_MW			= 0x02,
889 	FW_RI_STAG_MW_RELAXED		= 0x03
890 };
891 
892 enum fw_ri_data_op {
893 	FW_RI_DATA_IMMD			= 0x81,
894 	FW_RI_DATA_DSGL			= 0x82,
895 	FW_RI_DATA_ISGL			= 0x83
896 };
897 
898 enum fw_ri_sgl_depth {
899 	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
900 	FW_RI_SGL_DEPTH_MAX_RQ		= 4
901 };
902 
903 enum fw_ri_cqe_err {
904 	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
905 	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
906 	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
907 	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
908 	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
909 	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
910 	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
911 	/* attempt to invalidate a SMR */
912 	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07,
913 	/* attempt to invalidate a MR w MW */
914 	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08,
915 	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
916 	/* ECC error detected when reading the PSTAG for a MW Invalidate */
917 	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A,
918 	/* pbl address out of bound : software error */
919 	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B,
920 	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
921 	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
922 	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
923 	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
924 	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
925 	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
926 	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
927 	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
928 	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
929 	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
930 	/* MO not zero for TERMINATE or READ_REQ */
931 	FW_RI_CQE_ERR_MO		= 0x1A,
932 	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
933 	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
934 	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
935 	/* RQE address out of bound : software error */
936 	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E,
937 	/* internel error (opcode mismatch) */
938 	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F
939 
940 };
941 
942 struct fw_ri_dsge_pair {
943 	__be32	len[2];
944 	__be64	addr[2];
945 };
946 
947 struct fw_ri_dsgl {
948 	__u8	op;
949 	__u8	r1;
950 	__be16	nsge;
951 	__be32	len0;
952 	__be64	addr0;
953 #ifndef C99_NOT_SUPPORTED
954 	struct fw_ri_dsge_pair sge[];
955 #endif
956 };
957 
958 struct fw_ri_sge {
959 	__be32 stag;
960 	__be32 len;
961 	__be64 to;
962 };
963 
964 struct fw_ri_isgl {
965 	__u8	op;
966 	__u8	r1;
967 	__be16	nsge;
968 	__be32	r2;
969 #ifndef C99_NOT_SUPPORTED
970 	struct fw_ri_sge sge[];
971 #endif
972 };
973 
974 struct fw_ri_immd {
975 	__u8	op;
976 	__u8	r1;
977 	__be16	r2;
978 	__be32	immdlen;
979 #ifndef C99_NOT_SUPPORTED
980 	__u8	data[];
981 #endif
982 };
983 
984 struct fw_ri_tpte {
985 	__be32 valid_to_pdid;
986 	__be32 locread_to_qpid;
987 	__be32 nosnoop_pbladdr;
988 	__be32 len_lo;
989 	__be32 va_hi;
990 	__be32 va_lo_fbo;
991 	__be32 dca_mwbcnt_pstag;
992 	__be32 len_hi;
993 };
994 
995 #define	S_FW_RI_TPTE_VALID		31
996 #define	M_FW_RI_TPTE_VALID		0x1
997 #define	V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
998 #define	G_FW_RI_TPTE_VALID(x)		\
999 	(((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1000 #define	F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
1001 
1002 #define	S_FW_RI_TPTE_STAGKEY		23
1003 #define	M_FW_RI_TPTE_STAGKEY		0xff
1004 #define	V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
1005 #define	G_FW_RI_TPTE_STAGKEY(x)		\
1006 	(((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1007 
1008 #define	S_FW_RI_TPTE_STAGSTATE		22
1009 #define	M_FW_RI_TPTE_STAGSTATE		0x1
1010 #define	V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
1011 #define	G_FW_RI_TPTE_STAGSTATE(x)	\
1012 	(((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1013 #define	F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
1014 
1015 #define	S_FW_RI_TPTE_STAGTYPE		20
1016 #define	M_FW_RI_TPTE_STAGTYPE		0x3
1017 #define	V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
1018 #define	G_FW_RI_TPTE_STAGTYPE(x)	\
1019 	(((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1020 
1021 #define	S_FW_RI_TPTE_PDID		0
1022 #define	M_FW_RI_TPTE_PDID		0xfffff
1023 #define	V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
1024 #define	G_FW_RI_TPTE_PDID(x)		\
1025 	(((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1026 
1027 #define	S_FW_RI_TPTE_PERM		28
1028 #define	M_FW_RI_TPTE_PERM		0xf
1029 #define	V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
1030 #define	G_FW_RI_TPTE_PERM(x)		\
1031 	(((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1032 
1033 #define	S_FW_RI_TPTE_REMINVDIS		27
1034 #define	M_FW_RI_TPTE_REMINVDIS		0x1
1035 #define	V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
1036 #define	G_FW_RI_TPTE_REMINVDIS(x)	\
1037 	(((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1038 #define	F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
1039 
1040 #define	S_FW_RI_TPTE_ADDRTYPE		26
1041 #define	M_FW_RI_TPTE_ADDRTYPE		1
1042 #define	V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
1043 #define	G_FW_RI_TPTE_ADDRTYPE(x)	\
1044 	(((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1045 #define	F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
1046 
1047 #define	S_FW_RI_TPTE_MWBINDEN		25
1048 #define	M_FW_RI_TPTE_MWBINDEN		0x1
1049 #define	V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
1050 #define	G_FW_RI_TPTE_MWBINDEN(x)	\
1051 	(((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1052 #define	F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
1053 
1054 #define	S_FW_RI_TPTE_PS			20
1055 #define	M_FW_RI_TPTE_PS			0x1f
1056 #define	V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
1057 #define	G_FW_RI_TPTE_PS(x)		\
1058 	(((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1059 
1060 #define	S_FW_RI_TPTE_QPID		0
1061 #define	M_FW_RI_TPTE_QPID		0xfffff
1062 #define	V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
1063 #define	G_FW_RI_TPTE_QPID(x)		\
1064 	(((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1065 
1066 #define	S_FW_RI_TPTE_NOSNOOP		31
1067 #define	M_FW_RI_TPTE_NOSNOOP		0x1
1068 #define	V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
1069 #define	G_FW_RI_TPTE_NOSNOOP(x)		\
1070 	(((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1071 #define	F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
1072 
1073 #define	S_FW_RI_TPTE_PBLADDR		0
1074 #define	M_FW_RI_TPTE_PBLADDR		0x1fffffff
1075 #define	V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
1076 #define	G_FW_RI_TPTE_PBLADDR(x)		\
1077 	(((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1078 
1079 #define	S_FW_RI_TPTE_DCA		24
1080 #define	M_FW_RI_TPTE_DCA		0x1f
1081 #define	V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
1082 #define	G_FW_RI_TPTE_DCA(x)		\
1083 	(((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1084 
1085 #define	S_FW_RI_TPTE_MWBCNT_PSTAG	0
1086 #define	M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
1087 #define	V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
1088 	((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1089 #define	G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
1090 	(((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1091 
1092 enum fw_ri_cqe_rxtx {
1093 	FW_RI_CQE_RXTX_RX = 0x0,
1094 	FW_RI_CQE_RXTX_TX = 0x1,
1095 };
1096 
1097 struct fw_ri_cqe {
1098 	union fw_ri_rxtx {
1099 		struct fw_ri_scqe {
1100 		__be32	qpid_n_stat_rxtx_type;
1101 		__be32	plen;
1102 		__be32	reserved;
1103 		__be32	wrid;
1104 		} scqe;
1105 		struct fw_ri_rcqe {
1106 		__be32	qpid_n_stat_rxtx_type;
1107 		__be32	plen;
1108 		__be32	stag;
1109 		__be32	msn;
1110 		} rcqe;
1111 	} u;
1112 };
1113 
1114 #define	S_FW_RI_CQE_QPID	12
1115 #define	M_FW_RI_CQE_QPID	0xfffff
1116 #define	V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
1117 #define	G_FW_RI_CQE_QPID(x)   \
1118 	(((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
1119 
1120 #define	S_FW_RI_CQE_NOTIFY    10
1121 #define	M_FW_RI_CQE_NOTIFY    0x1
1122 #define	V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1123 #define	G_FW_RI_CQE_NOTIFY(x) \
1124 	(((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
1125 
1126 #define	S_FW_RI_CQE_STATUS    5
1127 #define	M_FW_RI_CQE_STATUS    0x1f
1128 #define	V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1129 #define	G_FW_RI_CQE_STATUS(x) \
1130 	(((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
1131 
1132 #define	S_FW_RI_CQE_RXTX	4
1133 #define	M_FW_RI_CQE_RXTX	0x1
1134 #define	V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
1135 #define	G_FW_RI_CQE_RXTX(x)   \
1136 	(((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
1137 
1138 #define	S_FW_RI_CQE_TYPE	0
1139 #define	M_FW_RI_CQE_TYPE	0xf
1140 #define	V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
1141 #define	G_FW_RI_CQE_TYPE(x)   \
1142 	(((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
1143 
1144 enum fw_ri_res_type {
1145 	FW_RI_RES_TYPE_SQ,
1146 	FW_RI_RES_TYPE_RQ,
1147 	FW_RI_RES_TYPE_CQ,
1148 };
1149 
1150 enum fw_ri_res_op {
1151 	FW_RI_RES_OP_WRITE,
1152 	FW_RI_RES_OP_RESET,
1153 };
1154 
1155 struct fw_ri_res {
1156 	union fw_ri_restype {
1157 		struct fw_ri_res_sqrq {
1158 			__u8   restype;
1159 			__u8   op;
1160 			__be16 r3;
1161 			__be32 eqid;
1162 			__be32 r4[2];
1163 			__be32 fetchszm_to_iqid;
1164 			__be32 dcaen_to_eqsize;
1165 			__be64 eqaddr;
1166 		} sqrq;
1167 		struct fw_ri_res_cq {
1168 			__u8   restype;
1169 			__u8   op;
1170 			__be16 r3;
1171 			__be32 iqid;
1172 			__be32 r4[2];
1173 			__be32 iqandst_to_iqandstindex;
1174 			__be16 iqdroprss_to_iqesize;
1175 			__be16 iqsize;
1176 			__be64 iqaddr;
1177 			__be32 iqns_iqro;
1178 			__be32 r6_lo;
1179 			__be64 r7;
1180 		} cq;
1181 	} u;
1182 };
1183 
1184 struct fw_ri_res_wr {
1185 	__be32 op_nres;
1186 	__be32 len16_pkd;
1187 	__u64  cookie;
1188 #ifndef C99_NOT_SUPPORTED
1189 	struct fw_ri_res res[];
1190 #endif
1191 };
1192 
1193 #define	S_FW_RI_RES_WR_NRES	0
1194 #define	M_FW_RI_RES_WR_NRES	0xff
1195 #define	V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
1196 #define	G_FW_RI_RES_WR_NRES(x)	\
1197 	(((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1198 
1199 #define	S_FW_RI_RES_WR_FETCHSZM		26
1200 #define	M_FW_RI_RES_WR_FETCHSZM		0x1
1201 #define	V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
1202 #define	G_FW_RI_RES_WR_FETCHSZM(x)	\
1203 	(((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1204 #define	F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
1205 
1206 #define	S_FW_RI_RES_WR_STATUSPGNS	25
1207 #define	M_FW_RI_RES_WR_STATUSPGNS	0x1
1208 #define	V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
1209 #define	G_FW_RI_RES_WR_STATUSPGNS(x)	\
1210 	(((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1211 #define	F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
1212 
1213 #define	S_FW_RI_RES_WR_STATUSPGRO	24
1214 #define	M_FW_RI_RES_WR_STATUSPGRO	0x1
1215 #define	V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
1216 #define	G_FW_RI_RES_WR_STATUSPGRO(x)	\
1217 	(((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1218 #define	F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
1219 
1220 #define	S_FW_RI_RES_WR_FETCHNS		23
1221 #define	M_FW_RI_RES_WR_FETCHNS		0x1
1222 #define	V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
1223 #define	G_FW_RI_RES_WR_FETCHNS(x)	\
1224 	(((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1225 #define	F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
1226 
1227 #define	S_FW_RI_RES_WR_FETCHRO		22
1228 #define	M_FW_RI_RES_WR_FETCHRO		0x1
1229 #define	V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
1230 #define	G_FW_RI_RES_WR_FETCHRO(x)	\
1231 	(((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1232 #define	F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
1233 
1234 #define	S_FW_RI_RES_WR_HOSTFCMODE	20
1235 #define	M_FW_RI_RES_WR_HOSTFCMODE	0x3
1236 #define	V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1237 #define	G_FW_RI_RES_WR_HOSTFCMODE(x)	\
1238 	(((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1239 
1240 #define	S_FW_RI_RES_WR_CPRIO	19
1241 #define	M_FW_RI_RES_WR_CPRIO	0x1
1242 #define	V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
1243 #define	G_FW_RI_RES_WR_CPRIO(x)	\
1244 	(((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1245 #define	F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
1246 
1247 #define	S_FW_RI_RES_WR_ONCHIP		18
1248 #define	M_FW_RI_RES_WR_ONCHIP		0x1
1249 #define	V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
1250 #define	G_FW_RI_RES_WR_ONCHIP(x)	\
1251 	(((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1252 #define	F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
1253 
1254 #define	S_FW_RI_RES_WR_PCIECHN		16
1255 #define	M_FW_RI_RES_WR_PCIECHN		0x3
1256 #define	V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
1257 #define	G_FW_RI_RES_WR_PCIECHN(x)	\
1258 	(((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1259 
1260 #define	S_FW_RI_RES_WR_IQID	0
1261 #define	M_FW_RI_RES_WR_IQID	0xffff
1262 #define	V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
1263 #define	G_FW_RI_RES_WR_IQID(x)	\
1264 	(((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1265 
1266 #define	S_FW_RI_RES_WR_DCAEN	31
1267 #define	M_FW_RI_RES_WR_DCAEN	0x1
1268 #define	V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
1269 #define	G_FW_RI_RES_WR_DCAEN(x)	\
1270 	(((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1271 #define	F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
1272 
1273 #define	S_FW_RI_RES_WR_DCACPU		26
1274 #define	M_FW_RI_RES_WR_DCACPU		0x1f
1275 #define	V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
1276 #define	G_FW_RI_RES_WR_DCACPU(x)	\
1277 	(((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1278 
1279 #define	S_FW_RI_RES_WR_FBMIN	23
1280 #define	M_FW_RI_RES_WR_FBMIN	0x7
1281 #define	V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
1282 #define	G_FW_RI_RES_WR_FBMIN(x)	\
1283 	(((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1284 
1285 #define	S_FW_RI_RES_WR_FBMAX	20
1286 #define	M_FW_RI_RES_WR_FBMAX	0x7
1287 #define	V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
1288 #define	G_FW_RI_RES_WR_FBMAX(x)	\
1289 	(((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1290 
1291 #define	S_FW_RI_RES_WR_CIDXFTHRESHO	19
1292 #define	M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
1293 #define	V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1294 #define	G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
1295 	(((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1296 #define	F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1297 
1298 #define	S_FW_RI_RES_WR_CIDXFTHRESH	16
1299 #define	M_FW_RI_RES_WR_CIDXFTHRESH	0x7
1300 #define	V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1301 #define	G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
1302 	(((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1303 
1304 #define	S_FW_RI_RES_WR_EQSIZE		0
1305 #define	M_FW_RI_RES_WR_EQSIZE		0xffff
1306 #define	V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
1307 #define	G_FW_RI_RES_WR_EQSIZE(x)	\
1308 	(((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1309 
1310 #define	S_FW_RI_RES_WR_IQANDST		15
1311 #define	M_FW_RI_RES_WR_IQANDST		0x1
1312 #define	V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
1313 #define	G_FW_RI_RES_WR_IQANDST(x)	\
1314 	(((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1315 #define	F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
1316 
1317 #define	S_FW_RI_RES_WR_IQANUS		14
1318 #define	M_FW_RI_RES_WR_IQANUS		0x1
1319 #define	V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
1320 #define	G_FW_RI_RES_WR_IQANUS(x)	\
1321 	(((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1322 #define	F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
1323 
1324 #define	S_FW_RI_RES_WR_IQANUD		12
1325 #define	M_FW_RI_RES_WR_IQANUD		0x3
1326 #define	V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
1327 #define	G_FW_RI_RES_WR_IQANUD(x)	\
1328 	(((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1329 
1330 #define	S_FW_RI_RES_WR_IQANDSTINDEX	0
1331 #define	M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
1332 #define	V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1333 #define	G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
1334 	(((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1335 
1336 #define	S_FW_RI_RES_WR_IQDROPRSS	15
1337 #define	M_FW_RI_RES_WR_IQDROPRSS	0x1
1338 #define	V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
1339 #define	G_FW_RI_RES_WR_IQDROPRSS(x)	\
1340 	(((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1341 #define	F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
1342 
1343 #define	S_FW_RI_RES_WR_IQGTSMODE	14
1344 #define	M_FW_RI_RES_WR_IQGTSMODE	0x1
1345 #define	V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
1346 #define	G_FW_RI_RES_WR_IQGTSMODE(x)	\
1347 	(((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1348 #define	F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
1349 
1350 #define	S_FW_RI_RES_WR_IQPCIECH		12
1351 #define	M_FW_RI_RES_WR_IQPCIECH		0x3
1352 #define	V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
1353 #define	G_FW_RI_RES_WR_IQPCIECH(x)	\
1354 	(((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1355 
1356 #define	S_FW_RI_RES_WR_IQDCAEN		11
1357 #define	M_FW_RI_RES_WR_IQDCAEN		0x1
1358 #define	V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
1359 #define	G_FW_RI_RES_WR_IQDCAEN(x)	\
1360 	(((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1361 #define	F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
1362 
1363 #define	S_FW_RI_RES_WR_IQDCACPU		6
1364 #define	M_FW_RI_RES_WR_IQDCACPU		0x1f
1365 #define	V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
1366 #define	G_FW_RI_RES_WR_IQDCACPU(x)	\
1367 	(((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1368 
1369 #define	S_FW_RI_RES_WR_IQINTCNTTHRESH		4
1370 #define	M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
1371 #define	V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1372 	((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1373 #define	G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1374 	(((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1375 
1376 #define	S_FW_RI_RES_WR_IQO	3
1377 #define	M_FW_RI_RES_WR_IQO	0x1
1378 #define	V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
1379 #define	G_FW_RI_RES_WR_IQO(x)	\
1380 	(((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1381 #define	F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
1382 
1383 #define	S_FW_RI_RES_WR_IQCPRIO		2
1384 #define	M_FW_RI_RES_WR_IQCPRIO		0x1
1385 #define	V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
1386 #define	G_FW_RI_RES_WR_IQCPRIO(x)	\
1387 	(((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1388 #define	F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
1389 
1390 #define	S_FW_RI_RES_WR_IQESIZE		0
1391 #define	M_FW_RI_RES_WR_IQESIZE		0x3
1392 #define	V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
1393 #define	G_FW_RI_RES_WR_IQESIZE(x)	\
1394 	(((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1395 
1396 #define	S_FW_RI_RES_WR_IQNS	31
1397 #define	M_FW_RI_RES_WR_IQNS	0x1
1398 #define	V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
1399 #define	G_FW_RI_RES_WR_IQNS(x)	\
1400 	(((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1401 #define	F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
1402 
1403 #define	S_FW_RI_RES_WR_IQRO	30
1404 #define	M_FW_RI_RES_WR_IQRO	0x1
1405 #define	V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
1406 #define	G_FW_RI_RES_WR_IQRO(x)	\
1407 	(((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1408 #define	F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
1409 
1410 struct fw_ri_rdma_write_wr {
1411 	__u8   opcode;
1412 	__u8   flags;
1413 	__u16  wrid;
1414 	__u8   r1[3];
1415 	__u8   len16;
1416 	__be64 r2;
1417 	__be32 plen;
1418 	__be32 stag_sink;
1419 	__be64 to_sink;
1420 };
1421 
1422 struct fw_ri_send_wr {
1423 	__u8   opcode;
1424 	__u8   flags;
1425 	__u16  wrid;
1426 	__u8   r1[3];
1427 	__u8   len16;
1428 	__be32 sendop_pkd;
1429 	__be32 stag_inv;
1430 	__be32 plen;
1431 	__be32 r3;
1432 	__be64 r4;
1433 };
1434 
1435 #define	S_FW_RI_SEND_WR_SENDOP		0
1436 #define	M_FW_RI_SEND_WR_SENDOP		0xf
1437 #define	V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
1438 #define	G_FW_RI_SEND_WR_SENDOP(x)	\
1439 	(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1440 
1441 struct fw_ri_rdma_read_wr {
1442 	__u8   opcode;
1443 	__u8   flags;
1444 	__u16  wrid;
1445 	__u8   r1[3];
1446 	__u8   len16;
1447 	__be64 r2;
1448 	__be32 stag_sink;
1449 	__be32 to_sink_hi;
1450 	__be32 to_sink_lo;
1451 	__be32 plen;
1452 	__be32 stag_src;
1453 	__be32 to_src_hi;
1454 	__be32 to_src_lo;
1455 	__be32 r5;
1456 };
1457 
1458 struct fw_ri_recv_wr {
1459 	__u8   opcode;
1460 	__u8   r1;
1461 	__u16  wrid;
1462 	__u8   r2[3];
1463 	__u8   len16;
1464 };
1465 
1466 struct fw_ri_bind_mw_wr {
1467 	__u8   opcode;
1468 	__u8   flags;
1469 	__u16  wrid;
1470 	__u8   r1[3];
1471 	__u8   len16;
1472 	__u8   qpbinde_to_dcacpu;
1473 	__u8   pgsz_shift;
1474 	__u8   addr_type;
1475 	__u8   mem_perms;
1476 	__be32 stag_mr;
1477 	__be32 stag_mw;
1478 	__be32 r3;
1479 	__be64 len_mw;
1480 	__be64 va_fbo;
1481 	__be64 r4;
1482 };
1483 
1484 #define	S_FW_RI_BIND_MW_WR_QPBINDE	6
1485 #define	M_FW_RI_BIND_MW_WR_QPBINDE	0x1
1486 #define	V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1487 #define	G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
1488 	(((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1489 #define	F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1490 
1491 #define	S_FW_RI_BIND_MW_WR_NS		5
1492 #define	M_FW_RI_BIND_MW_WR_NS		0x1
1493 #define	V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
1494 #define	G_FW_RI_BIND_MW_WR_NS(x)	\
1495 	(((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1496 #define	F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
1497 
1498 #define	S_FW_RI_BIND_MW_WR_DCACPU	0
1499 #define	M_FW_RI_BIND_MW_WR_DCACPU	0x1f
1500 #define	V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1501 #define	G_FW_RI_BIND_MW_WR_DCACPU(x)	\
1502 	(((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1503 
1504 struct fw_ri_fr_nsmr_wr {
1505 	__u8   opcode;
1506 	__u8   flags;
1507 	__u16  wrid;
1508 	__u8   r1[3];
1509 	__u8   len16;
1510 	__u8   qpbinde_to_dcacpu;
1511 	__u8   pgsz_shift;
1512 	__u8   addr_type;
1513 	__u8   mem_perms;
1514 	__be32 stag;
1515 	__be32 len_hi;
1516 	__be32 len_lo;
1517 	__be32 va_hi;
1518 	__be32 va_lo_fbo;
1519 };
1520 
1521 #define	S_FW_RI_FR_NSMR_WR_QPBINDE	6
1522 #define	M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
1523 #define	V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1524 #define	G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
1525 	(((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1526 #define	F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1527 
1528 #define	S_FW_RI_FR_NSMR_WR_NS		5
1529 #define	M_FW_RI_FR_NSMR_WR_NS		0x1
1530 #define	V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
1531 #define	G_FW_RI_FR_NSMR_WR_NS(x)	\
1532 	(((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1533 #define	F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
1534 
1535 #define	S_FW_RI_FR_NSMR_WR_DCACPU	0
1536 #define	M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
1537 #define	V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1538 #define	G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
1539 	(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1540 
1541 struct fw_ri_inv_lstag_wr {
1542 	__u8   opcode;
1543 	__u8   flags;
1544 	__u16  wrid;
1545 	__u8   r1[3];
1546 	__u8   len16;
1547 	__be32 r2;
1548 	__be32 stag_inv;
1549 };
1550 
1551 struct fw_ri_send_immediate_wr {
1552 	__u8   opcode;
1553 	__u8   flags;
1554 	__u16  wrid;
1555 	__u8   r1[3];
1556 	__u8   len16;
1557 	__be32 sendimmop_pkd;
1558 	__be32 r3;
1559 	__be32 plen;
1560 	__be32 r4;
1561 	__be64 r5;
1562 };
1563 
1564 #define	S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
1565 #define	M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
1566 #define	V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1567 	((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1568 #define	G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1569 	(((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1570 	M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1571 
1572 enum fw_ri_atomic_op {
1573 	FW_RI_ATOMIC_OP_FETCHADD,
1574 	FW_RI_ATOMIC_OP_SWAP,
1575 	FW_RI_ATOMIC_OP_CMDSWAP,
1576 };
1577 
1578 struct fw_ri_atomic_wr {
1579 	__u8   opcode;
1580 	__u8   flags;
1581 	__u16  wrid;
1582 	__u8   r1[3];
1583 	__u8   len16;
1584 	__be32 atomicop_pkd;
1585 	__be64 r3;
1586 	__be32 aopcode_pkd;
1587 	__be32 reqid;
1588 	__be32 stag;
1589 	__be32 to_hi;
1590 	__be32 to_lo;
1591 	__be32 addswap_data_hi;
1592 	__be32 addswap_data_lo;
1593 	__be32 addswap_mask_hi;
1594 	__be32 addswap_mask_lo;
1595 	__be32 compare_data_hi;
1596 	__be32 compare_data_lo;
1597 	__be32 compare_mask_hi;
1598 	__be32 compare_mask_lo;
1599 	__be32 r5;
1600 };
1601 
1602 #define	S_FW_RI_ATOMIC_WR_ATOMICOP	0
1603 #define	M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
1604 #define	V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1605 #define	G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
1606 	(((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1607 
1608 #define	S_FW_RI_ATOMIC_WR_AOPCODE	0
1609 #define	M_FW_RI_ATOMIC_WR_AOPCODE	0xf
1610 #define	V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
1611 #define	G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
1612 	(((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
1613 
1614 enum fw_ri_type {
1615 	FW_RI_TYPE_INIT,
1616 	FW_RI_TYPE_FINI,
1617 	FW_RI_TYPE_TERMINATE
1618 };
1619 
1620 enum fw_ri_init_p2ptype {
1621 	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
1622 	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
1623 	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
1624 	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
1625 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
1626 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
1627 	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
1628 };
1629 
1630 struct fw_ri_wr {
1631 	__be32 op_compl;
1632 	__be32 flowid_len16;
1633 	__u64  cookie;
1634 	union fw_ri {
1635 		struct fw_ri_init {
1636 			__u8   type;
1637 			__u8   mpareqbit_p2ptype;
1638 			__u8   r4[2];
1639 			__u8   mpa_attrs;
1640 			__u8   qp_caps;
1641 			__be16 nrqe;
1642 			__be32 pdid;
1643 			__be32 qpid;
1644 			__be32 sq_eqid;
1645 			__be32 rq_eqid;
1646 			__be32 scqid;
1647 			__be32 rcqid;
1648 			__be32 ord_max;
1649 			__be32 ird_max;
1650 			__be32 iss;
1651 			__be32 irs;
1652 			__be32 hwrqsize;
1653 			__be32 hwrqaddr;
1654 			__be64 r5;
1655 			union fw_ri_init_p2p {
1656 				struct fw_ri_rdma_write_wr write;
1657 				struct fw_ri_rdma_read_wr read;
1658 				struct fw_ri_send_wr send;
1659 			} u;
1660 		} init;
1661 		struct fw_ri_fini {
1662 			__u8   type;
1663 			__u8   r3[7];
1664 			__be64 r4;
1665 		} fini;
1666 		struct fw_ri_terminate {
1667 			__u8   type;
1668 			__u8   r3[3];
1669 			__be32 immdlen;
1670 			__u8   termmsg[40];
1671 		} terminate;
1672 	} u;
1673 };
1674 
1675 #define	S_FW_RI_WR_MPAREQBIT	7
1676 #define	M_FW_RI_WR_MPAREQBIT	0x1
1677 #define	V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
1678 #define	G_FW_RI_WR_MPAREQBIT(x)	\
1679 	(((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
1680 #define	F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
1681 
1682 #define	S_FW_RI_WR_0BRRBIT	6
1683 #define	M_FW_RI_WR_0BRRBIT	0x1
1684 #define	V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
1685 #define	G_FW_RI_WR_0BRRBIT(x)	\
1686 	(((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
1687 #define	F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
1688 
1689 #define	S_FW_RI_WR_P2PTYPE	0
1690 #define	M_FW_RI_WR_P2PTYPE	0xf
1691 #define	V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
1692 #define	G_FW_RI_WR_P2PTYPE(x)	\
1693 	(((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
1694 
1695 /*
1696  *	*******************************************
1697  *	  F O i S C S I   W O R K R E Q U E S T s
1698  *	*******************************************
1699  */
1700 
1701 #define	FW_FOISCSI_NAME_MAX_LEN		224
1702 #define	FW_FOISCSI_ALIAS_MAX_LEN	224
1703 #define	FW_FOISCSI_MAX_CHAP_NAME_LEN	64
1704 #define	FW_FOISCSI_INIT_NODE_MAX	8
1705 
1706 enum fw_chnet_ifconf_wr_subop {
1707 	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
1708 
1709 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
1710 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
1711 
1712 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
1713 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
1714 
1715 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
1716 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
1717 
1718 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
1719 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
1720 
1721 	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
1722 	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
1723 
1724 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
1725 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
1726 
1727 	FW_CHNET_IFCONF_WR_SUBOP_MAX,
1728 };
1729 
1730 struct fw_chnet_ifconf_wr {
1731 	__be32 op_compl;
1732 	__be32 flowid_len16;
1733 	__be64 cookie;
1734 	__be32 if_flowid;
1735 	__u8   idx;
1736 	__u8   subop;
1737 	__u8   retval;
1738 	__u8   r2;
1739 	__be64 r3;
1740 	struct fw_chnet_ifconf_params {
1741 		__be32 r0;
1742 		__be16 vlanid;
1743 		__be16 mtu;
1744 		union fw_chnet_ifconf_addr_type {
1745 			struct fw_chnet_ifconf_ipv4 {
1746 				__be32 addr;
1747 				__be32 mask;
1748 				__be32 router;
1749 				__be32 r0;
1750 				__be64 r1;
1751 			} ipv4;
1752 			struct fw_chnet_ifconf_ipv6 {
1753 				__be64 linklocal_lo;
1754 				__be64 linklocal_hi;
1755 				__be64 router_hi;
1756 				__be64 router_lo;
1757 				__be64 aconf_hi;
1758 				__be64 aconf_lo;
1759 				__be64 linklocal_aconf_hi;
1760 				__be64 linklocal_aconf_lo;
1761 				__be64 router_aconf_hi;
1762 				__be64 router_aconf_lo;
1763 				__be64 r0;
1764 			} ipv6;
1765 		} in_attr;
1766 	} param;
1767 };
1768 
1769 enum fw_foiscsi_session_type {
1770 	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
1771 	FW_FOISCSI_SESSION_TYPE_NORMAL,
1772 };
1773 
1774 enum fw_foiscsi_auth_policy {
1775 	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
1776 	FW_FOISCSI_AUTH_POLICY_MUTUAL,
1777 };
1778 
1779 enum fw_foiscsi_auth_method {
1780 	FW_FOISCSI_AUTH_METHOD_NONE = 0,
1781 	FW_FOISCSI_AUTH_METHOD_CHAP,
1782 	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
1783 	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
1784 };
1785 
1786 enum fw_foiscsi_digest_type {
1787 	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
1788 	FW_FOISCSI_DIGEST_TYPE_CRC32,
1789 	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
1790 	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
1791 };
1792 
1793 enum fw_foiscsi_wr_subop {
1794 	FW_FOISCSI_WR_SUBOP_ADD = 1,
1795 	FW_FOISCSI_WR_SUBOP_DEL = 2,
1796 	FW_FOISCSI_WR_SUBOP_MOD = 4,
1797 };
1798 
1799 enum fw_foiscsi_ctrl_state {
1800 	FW_FOISCSI_CTRL_STATE_FREE = 0,
1801 	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
1802 	FW_FOISCSI_CTRL_STATE_FAILED,
1803 	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
1804 	FW_FOISCSI_CTRL_STATE_REDIRECT,
1805 };
1806 
1807 struct fw_rdev_wr {
1808 	__be32 op_to_immdlen;
1809 	__be32 alloc_to_len16;
1810 	__be64 cookie;
1811 	__u8   protocol;
1812 	__u8   event_cause;
1813 	__u8   cur_state;
1814 	__u8   prev_state;
1815 	__be32 flags_to_assoc_flowid;
1816 	union rdev_entry {
1817 		struct fcoe_rdev_entry {
1818 			__be32 flowid;
1819 			__u8   protocol;
1820 			__u8   event_cause;
1821 			__u8   flags;
1822 			__u8   rjt_reason;
1823 			__u8   cur_login_st;
1824 			__u8   prev_login_st;
1825 			__be16 rcv_fr_sz;
1826 			__u8   rd_xfer_rdy_to_rport_type;
1827 			__u8   vft_to_qos;
1828 			__u8   org_proc_assoc_to_acc_rsp_code;
1829 			__u8   enh_disc_to_tgt;
1830 			__u8   wwnn[8];
1831 			__u8   wwpn[8];
1832 			__be16 iqid;
1833 			__u8   fc_oui[3];
1834 			__u8   r_id[3];
1835 		} fcoe_rdev;
1836 		struct iscsi_rdev_entry {
1837 			__be32 flowid;
1838 			__u8   protocol;
1839 			__u8   event_cause;
1840 			__u8   flags;
1841 			__u8   r3;
1842 			__be16 iscsi_opts;
1843 			__be16 tcp_opts;
1844 			__be16 ip_opts;
1845 			__be16 max_rcv_len;
1846 			__be16 max_snd_len;
1847 			__be16 first_brst_len;
1848 			__be16 max_brst_len;
1849 			__be16 r4;
1850 			__be16 def_time2wait;
1851 			__be16 def_time2ret;
1852 			__be16 nop_out_intrvl;
1853 			__be16 non_scsi_to;
1854 			__be16 isid;
1855 			__be16 tsid;
1856 			__be16 port;
1857 			__be16 tpgt;
1858 			__u8   r5[6];
1859 			__be16 iqid;
1860 		} iscsi_rdev;
1861 	} u;
1862 };
1863 
1864 #define	S_FW_RDEV_WR_IMMDLEN	0
1865 #define	M_FW_RDEV_WR_IMMDLEN	0xff
1866 #define	V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
1867 #define	G_FW_RDEV_WR_IMMDLEN(x)	\
1868 	(((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
1869 
1870 #define	S_FW_RDEV_WR_ALLOC	31
1871 #define	M_FW_RDEV_WR_ALLOC	0x1
1872 #define	V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
1873 #define	G_FW_RDEV_WR_ALLOC(x)	\
1874 	(((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
1875 #define	F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
1876 
1877 #define	S_FW_RDEV_WR_FREE	30
1878 #define	M_FW_RDEV_WR_FREE	0x1
1879 #define	V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
1880 #define	G_FW_RDEV_WR_FREE(x)	\
1881 	(((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
1882 #define	F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
1883 
1884 #define	S_FW_RDEV_WR_MODIFY	29
1885 #define	M_FW_RDEV_WR_MODIFY	0x1
1886 #define	V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
1887 #define	G_FW_RDEV_WR_MODIFY(x)	\
1888 	(((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
1889 #define	F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
1890 
1891 #define	S_FW_RDEV_WR_FLOWID	8
1892 #define	M_FW_RDEV_WR_FLOWID	0xfffff
1893 #define	V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
1894 #define	G_FW_RDEV_WR_FLOWID(x)	\
1895 	(((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
1896 
1897 #define	S_FW_RDEV_WR_LEN16	0
1898 #define	M_FW_RDEV_WR_LEN16	0xff
1899 #define	V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
1900 #define	G_FW_RDEV_WR_LEN16(x)	\
1901 	(((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
1902 
1903 #define	S_FW_RDEV_WR_FLAGS	24
1904 #define	M_FW_RDEV_WR_FLAGS	0xff
1905 #define	V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
1906 #define	G_FW_RDEV_WR_FLAGS(x)	\
1907 	(((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
1908 
1909 #define	S_FW_RDEV_WR_GET_NEXT		20
1910 #define	M_FW_RDEV_WR_GET_NEXT		0xf
1911 #define	V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
1912 #define	G_FW_RDEV_WR_GET_NEXT(x)	\
1913 	(((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
1914 
1915 #define	S_FW_RDEV_WR_ASSOC_FLOWID	0
1916 #define	M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
1917 #define	V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
1918 #define	G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
1919 	(((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
1920 
1921 #define	S_FW_RDEV_WR_RJT	7
1922 #define	M_FW_RDEV_WR_RJT	0x1
1923 #define	V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
1924 #define	G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
1925 #define	F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
1926 
1927 #define	S_FW_RDEV_WR_REASON	0
1928 #define	M_FW_RDEV_WR_REASON	0x7f
1929 #define	V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
1930 #define	G_FW_RDEV_WR_REASON(x)	\
1931 	(((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
1932 
1933 #define	S_FW_RDEV_WR_RD_XFER_RDY	7
1934 #define	M_FW_RDEV_WR_RD_XFER_RDY	0x1
1935 #define	V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
1936 #define	G_FW_RDEV_WR_RD_XFER_RDY(x)	\
1937 	(((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
1938 #define	F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
1939 
1940 #define	S_FW_RDEV_WR_WR_XFER_RDY	6
1941 #define	M_FW_RDEV_WR_WR_XFER_RDY	0x1
1942 #define	V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
1943 #define	G_FW_RDEV_WR_WR_XFER_RDY(x)	\
1944 	(((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
1945 #define	F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
1946 
1947 #define	S_FW_RDEV_WR_FC_SP	5
1948 #define	M_FW_RDEV_WR_FC_SP	0x1
1949 #define	V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
1950 #define	G_FW_RDEV_WR_FC_SP(x)	\
1951 	(((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
1952 #define	F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
1953 
1954 #define	S_FW_RDEV_WR_RPORT_TYPE		0
1955 #define	M_FW_RDEV_WR_RPORT_TYPE		0x1f
1956 #define	V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
1957 #define	G_FW_RDEV_WR_RPORT_TYPE(x)	\
1958 	(((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
1959 
1960 #define	S_FW_RDEV_WR_VFT	7
1961 #define	M_FW_RDEV_WR_VFT	0x1
1962 #define	V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
1963 #define	G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
1964 #define	F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
1965 
1966 #define	S_FW_RDEV_WR_NPIV	6
1967 #define	M_FW_RDEV_WR_NPIV	0x1
1968 #define	V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
1969 #define	G_FW_RDEV_WR_NPIV(x)	\
1970 	(((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
1971 #define	F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
1972 
1973 #define	S_FW_RDEV_WR_CLASS	4
1974 #define	M_FW_RDEV_WR_CLASS	0x3
1975 #define	V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
1976 #define	G_FW_RDEV_WR_CLASS(x)	\
1977 	(((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
1978 
1979 #define	S_FW_RDEV_WR_SEQ_DEL	3
1980 #define	M_FW_RDEV_WR_SEQ_DEL	0x1
1981 #define	V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
1982 #define	G_FW_RDEV_WR_SEQ_DEL(x)	\
1983 	(((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
1984 #define	F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
1985 
1986 #define	S_FW_RDEV_WR_PRIO_PREEMP	2
1987 #define	M_FW_RDEV_WR_PRIO_PREEMP	0x1
1988 #define	V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
1989 #define	G_FW_RDEV_WR_PRIO_PREEMP(x)	\
1990 	(((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
1991 #define	F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
1992 
1993 #define	S_FW_RDEV_WR_PREF	1
1994 #define	M_FW_RDEV_WR_PREF	0x1
1995 #define	V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
1996 #define	G_FW_RDEV_WR_PREF(x)	\
1997 	(((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
1998 #define	F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
1999 
2000 #define	S_FW_RDEV_WR_QOS	0
2001 #define	M_FW_RDEV_WR_QOS	0x1
2002 #define	V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
2003 #define	G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2004 #define	F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
2005 
2006 #define	S_FW_RDEV_WR_ORG_PROC_ASSOC	7
2007 #define	M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
2008 #define	V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2009 #define	G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
2010 	(((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2011 #define	F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2012 
2013 #define	S_FW_RDEV_WR_RSP_PROC_ASSOC	6
2014 #define	M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
2015 #define	V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2016 #define	G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
2017 	(((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2018 #define	F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2019 
2020 #define	S_FW_RDEV_WR_IMAGE_PAIR		5
2021 #define	M_FW_RDEV_WR_IMAGE_PAIR		0x1
2022 #define	V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2023 #define	G_FW_RDEV_WR_IMAGE_PAIR(x)	\
2024 	(((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2025 #define	F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
2026 
2027 #define	S_FW_RDEV_WR_ACC_RSP_CODE	0
2028 #define	M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
2029 #define	V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2030 #define	G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
2031 	(((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2032 
2033 #define	S_FW_RDEV_WR_ENH_DISC		7
2034 #define	M_FW_RDEV_WR_ENH_DISC		0x1
2035 #define	V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
2036 #define	G_FW_RDEV_WR_ENH_DISC(x)	\
2037 	(((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2038 #define	F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
2039 
2040 #define	S_FW_RDEV_WR_REC	6
2041 #define	M_FW_RDEV_WR_REC	0x1
2042 #define	V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
2043 #define	G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2044 #define	F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
2045 
2046 #define	S_FW_RDEV_WR_TASK_RETRY_ID	5
2047 #define	M_FW_RDEV_WR_TASK_RETRY_ID	0x1
2048 #define	V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2049 #define	G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
2050 	(((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2051 #define	F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2052 
2053 #define	S_FW_RDEV_WR_RETRY	4
2054 #define	M_FW_RDEV_WR_RETRY	0x1
2055 #define	V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
2056 #define	G_FW_RDEV_WR_RETRY(x)	\
2057 	(((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2058 #define	F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
2059 
2060 #define	S_FW_RDEV_WR_CONF_CMPL		3
2061 #define	M_FW_RDEV_WR_CONF_CMPL		0x1
2062 #define	V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
2063 #define	G_FW_RDEV_WR_CONF_CMPL(x)	\
2064 	(((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2065 #define	F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
2066 
2067 #define	S_FW_RDEV_WR_DATA_OVLY		2
2068 #define	M_FW_RDEV_WR_DATA_OVLY		0x1
2069 #define	V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
2070 #define	G_FW_RDEV_WR_DATA_OVLY(x)	\
2071 	(((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2072 #define	F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
2073 
2074 #define	S_FW_RDEV_WR_INI	1
2075 #define	M_FW_RDEV_WR_INI	0x1
2076 #define	V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
2077 #define	G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2078 #define	F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
2079 
2080 #define	S_FW_RDEV_WR_TGT	0
2081 #define	M_FW_RDEV_WR_TGT	0x1
2082 #define	V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
2083 #define	G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2084 #define	F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
2085 
2086 struct fw_foiscsi_node_wr {
2087 	__be32 op_to_immdlen;
2088 	__be32 flowid_len16;
2089 	__u64  cookie;
2090 	__u8   subop;
2091 	__u8   status;
2092 	__u8   alias_len;
2093 	__u8   iqn_len;
2094 	__be32 node_flowid;
2095 	__be16 nodeid;
2096 	__be16 login_retry;
2097 	__be16 retry_timeout;
2098 	__be16 r3;
2099 	__u8   iqn[224];
2100 	__u8   alias[224];
2101 };
2102 
2103 #define	S_FW_FOISCSI_NODE_WR_IMMDLEN	0
2104 #define	M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
2105 #define	V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2106 #define	G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
2107 	(((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2108 
2109 struct fw_foiscsi_ctrl_wr {
2110 	__be32 op_compl;
2111 	__be32 flowid_len16;
2112 	__u64  cookie;
2113 	__u8   subop;
2114 	__u8   status;
2115 	__u8   ctrl_state;
2116 	__u8   io_state;
2117 	__be32 node_id;
2118 	__be32 ctrl_id;
2119 	__be32 io_id;
2120 	struct fw_foiscsi_sess_attr {
2121 		__be32 sess_type_to_erl;
2122 		__be16 max_conn;
2123 		__be16 max_r2t;
2124 		__be16 time2wait;
2125 		__be16 time2retain;
2126 		__be32 max_burst;
2127 		__be32 first_burst;
2128 		__be32 r1;
2129 	} sess_attr;
2130 	struct fw_foiscsi_conn_attr {
2131 		__be32 hdigest_to_auth_policy;
2132 		__be32 max_rcv_dsl;
2133 		__be32 ping_tmo;
2134 		__be16 dst_port;
2135 		__be16 src_port;
2136 		union fw_foiscsi_conn_attr_addr {
2137 			struct fw_foiscsi_conn_attr_ipv6 {
2138 				__be64 dst_addr[2];
2139 				__be64 src_addr[2];
2140 			} ipv6_addr;
2141 			struct fw_foiscsi_conn_attr_ipv4 {
2142 				__be32 dst_addr;
2143 				__be32 src_addr;
2144 			} ipv4_addr;
2145 		} u;
2146 	} conn_attr;
2147 	__u8   tgt_name_len;
2148 	__u8   r3[7];
2149 	__u8   tgt_name[224];
2150 };
2151 
2152 #define	S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
2153 #define	M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
2154 #define	V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2155 	((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2156 #define	G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2157 	(((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \
2158 	M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2159 
2160 #define	S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
2161 #define	M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
2162 #define	V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2163 	((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2164 #define	G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2165 	(((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2166 	M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2167 #define	F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
2168     V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2169 
2170 #define	S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
2171 #define	M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
2172 #define	V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2173 	((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2174 #define	G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2175 	(((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2176 	M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2177 #define	F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
2178     V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2179 
2180 #define	S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
2181 #define	M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
2182 #define	V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2183 	((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2184 #define	G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2185 	(((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2186 	M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2187 #define	F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
2188     V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2189 
2190 #define	S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
2191 #define	M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
2192 #define	V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2193 	((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2194 #define	G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2195 	(((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2196 	M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2197 #define	F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
2198     V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2199 
2200 #define	S_FW_FOISCSI_CTRL_WR_ERL	24
2201 #define	M_FW_FOISCSI_CTRL_WR_ERL	0x3
2202 #define	V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2203 #define	G_FW_FOISCSI_CTRL_WR_ERL(x)	\
2204 	(((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2205 
2206 #define	S_FW_FOISCSI_CTRL_WR_HDIGEST	30
2207 #define	M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
2208 #define	V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2209 #define	G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
2210 	(((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2211 
2212 #define	S_FW_FOISCSI_CTRL_WR_DDIGEST	28
2213 #define	M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
2214 #define	V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2215 #define	G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
2216 	(((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2217 
2218 #define	S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
2219 #define	M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
2220 #define	V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2221 	((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2222 #define	G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2223 	(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2224 	M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2225 
2226 #define	S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
2227 #define	M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
2228 #define	V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2229 	((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2230 #define	G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2231 	(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2232 	M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2233 
2234 struct fw_foiscsi_chap_wr {
2235 	__be32 op_compl;
2236 	__be32 flowid_len16;
2237 	__u64  cookie;
2238 	__u8   status;
2239 	__u8   id_len;
2240 	__u8   sec_len;
2241 	__u8   tgt_id_len;
2242 	__u8   tgt_sec_len;
2243 	__be16 node_id;
2244 	__u8   r2;
2245 	__u8   chap_id[64];
2246 	__u8   chap_sec[16];
2247 	__u8   tgt_id[64];
2248 	__u8   tgt_sec[16];
2249 };
2250 
2251 /*
2252  *	*****************************************
2253  *	  F O F C O E   W O R K R E Q U E S T s
2254  *	*****************************************
2255  */
2256 
2257 struct fw_fcoe_els_ct_wr {
2258 	__be32 op_immdlen;
2259 	__be32 flowid_len16;
2260 	__be64 cookie;
2261 	__be16 iqid;
2262 	__u8   tmo_val;
2263 	__u8   els_ct_type;
2264 	__u8   ctl_pri;
2265 	__u8   cp_en_class;
2266 	__be16 xfer_cnt;
2267 	__u8   fl_to_sp;
2268 	__u8   l_id[3];
2269 	__u8   r5;
2270 	__u8   r_id[3];
2271 	__be64 rsp_dmaaddr;
2272 	__be32 rsp_dmalen;
2273 	__be32 r6;
2274 };
2275 
2276 #define	S_FW_FCOE_ELS_CT_WR_OPCODE	24
2277 #define	M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
2278 #define	V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2279 #define	G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
2280 	(((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2281 
2282 #define	S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
2283 #define	M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
2284 #define	V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2285 #define	G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
2286 	(((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2287 
2288 #define	S_FW_FCOE_ELS_CT_WR_FLOWID	8
2289 #define	M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
2290 #define	V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2291 #define	G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
2292 	(((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2293 
2294 #define	S_FW_FCOE_ELS_CT_WR_LEN16	0
2295 #define	M_FW_FCOE_ELS_CT_WR_LEN16	0xff
2296 #define	V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2297 #define	G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
2298 	(((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2299 
2300 #define	S_FW_FCOE_ELS_CT_WR_CP_EN	6
2301 #define	M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
2302 #define	V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2303 #define	G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
2304 	(((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2305 
2306 #define	S_FW_FCOE_ELS_CT_WR_CLASS	4
2307 #define	M_FW_FCOE_ELS_CT_WR_CLASS	0x3
2308 #define	V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2309 #define	G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
2310 	(((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2311 
2312 #define	S_FW_FCOE_ELS_CT_WR_FL		2
2313 #define	M_FW_FCOE_ELS_CT_WR_FL		0x1
2314 #define	V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
2315 #define	G_FW_FCOE_ELS_CT_WR_FL(x)	\
2316 	(((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2317 #define	F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
2318 
2319 #define	S_FW_FCOE_ELS_CT_WR_NPIV	1
2320 #define	M_FW_FCOE_ELS_CT_WR_NPIV	0x1
2321 #define	V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2322 #define	G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
2323 	(((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2324 #define	F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2325 
2326 #define	S_FW_FCOE_ELS_CT_WR_SP		0
2327 #define	M_FW_FCOE_ELS_CT_WR_SP		0x1
2328 #define	V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
2329 #define	G_FW_FCOE_ELS_CT_WR_SP(x)	\
2330 	(((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2331 #define	F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
2332 
2333 /*
2334  *	****************************************
2335  *	  S C S I   W O R K R E Q U E S T s
2336  *	  (FOiSCSI and FCOE unified data path)
2337  *	****************************************
2338  */
2339 
2340 struct fw_scsi_write_wr {
2341 	__be32 op_immdlen;
2342 	__be32 flowid_len16;
2343 	__be64 cookie;
2344 	__be16 iqid;
2345 	__u8   tmo_val;
2346 	__u8   use_xfer_cnt;
2347 	union fw_scsi_write_priv {
2348 		struct fcoe_write_priv {
2349 			__u8   ctl_pri;
2350 			__u8   cp_en_class;
2351 			__u8   r3_lo[2];
2352 		} fcoe;
2353 		struct iscsi_write_priv {
2354 			__u8   r3[4];
2355 		} iscsi;
2356 	} u;
2357 	__be32 xfer_cnt;
2358 	__be32 ini_xfer_cnt;
2359 	__be64 rsp_dmaaddr;
2360 	__be32 rsp_dmalen;
2361 	__be32 r4;
2362 };
2363 
2364 #define	S_FW_SCSI_WRITE_WR_OPCODE	24
2365 #define	M_FW_SCSI_WRITE_WR_OPCODE	0xff
2366 #define	V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2367 #define	G_FW_SCSI_WRITE_WR_OPCODE(x)	\
2368 	(((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2369 
2370 #define	S_FW_SCSI_WRITE_WR_IMMDLEN	0
2371 #define	M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
2372 #define	V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2373 #define	G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
2374 	(((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2375 
2376 #define	S_FW_SCSI_WRITE_WR_FLOWID	8
2377 #define	M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
2378 #define	V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2379 #define	G_FW_SCSI_WRITE_WR_FLOWID(x)	\
2380 	(((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2381 
2382 #define	S_FW_SCSI_WRITE_WR_LEN16	0
2383 #define	M_FW_SCSI_WRITE_WR_LEN16	0xff
2384 #define	V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
2385 #define	G_FW_SCSI_WRITE_WR_LEN16(x)	\
2386 	(((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2387 
2388 #define	S_FW_SCSI_WRITE_WR_CP_EN	6
2389 #define	M_FW_SCSI_WRITE_WR_CP_EN	0x3
2390 #define	V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2391 #define	G_FW_SCSI_WRITE_WR_CP_EN(x)	\
2392 	(((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2393 
2394 #define	S_FW_SCSI_WRITE_WR_CLASS	4
2395 #define	M_FW_SCSI_WRITE_WR_CLASS	0x3
2396 #define	V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
2397 #define	G_FW_SCSI_WRITE_WR_CLASS(x)	\
2398 	(((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2399 
2400 struct fw_scsi_read_wr {
2401 	__be32 op_immdlen;
2402 	__be32 flowid_len16;
2403 	__be64 cookie;
2404 	__be16 iqid;
2405 	__u8   tmo_val;
2406 	__u8   use_xfer_cnt;
2407 	union fw_scsi_read_priv {
2408 		struct fcoe_read_priv {
2409 			__u8   ctl_pri;
2410 			__u8   cp_en_class;
2411 			__u8   r3_lo[2];
2412 		} fcoe;
2413 		struct iscsi_read_priv {
2414 			__u8   r3[4];
2415 		} iscsi;
2416 	} u;
2417 	__be32 xfer_cnt;
2418 	__be32 ini_xfer_cnt;
2419 	__be64 rsp_dmaaddr;
2420 	__be32 rsp_dmalen;
2421 	__be32 r4;
2422 };
2423 
2424 #define	S_FW_SCSI_READ_WR_OPCODE	24
2425 #define	M_FW_SCSI_READ_WR_OPCODE	0xff
2426 #define	V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
2427 #define	G_FW_SCSI_READ_WR_OPCODE(x)	\
2428 	(((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
2429 
2430 #define	S_FW_SCSI_READ_WR_IMMDLEN	0
2431 #define	M_FW_SCSI_READ_WR_IMMDLEN	0xff
2432 #define	V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
2433 #define	G_FW_SCSI_READ_WR_IMMDLEN(x)	\
2434 	(((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
2435 
2436 #define	S_FW_SCSI_READ_WR_FLOWID	8
2437 #define	M_FW_SCSI_READ_WR_FLOWID	0xfffff
2438 #define	V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
2439 #define	G_FW_SCSI_READ_WR_FLOWID(x)	\
2440 	(((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
2441 
2442 #define	S_FW_SCSI_READ_WR_LEN16		0
2443 #define	M_FW_SCSI_READ_WR_LEN16		0xff
2444 #define	V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
2445 #define	G_FW_SCSI_READ_WR_LEN16(x)	\
2446 	(((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
2447 
2448 #define	S_FW_SCSI_READ_WR_CP_EN		6
2449 #define	M_FW_SCSI_READ_WR_CP_EN		0x3
2450 #define	V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
2451 #define	G_FW_SCSI_READ_WR_CP_EN(x)	\
2452 	(((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
2453 
2454 #define	S_FW_SCSI_READ_WR_CLASS		4
2455 #define	M_FW_SCSI_READ_WR_CLASS		0x3
2456 #define	V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
2457 #define	G_FW_SCSI_READ_WR_CLASS(x)	\
2458 	(((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
2459 
2460 struct fw_scsi_cmd_wr {
2461 	__be32 op_immdlen;
2462 	__be32 flowid_len16;
2463 	__be64 cookie;
2464 	__be16 iqid;
2465 	__u8   tmo_val;
2466 	__u8   r3;
2467 	union fw_scsi_cmd_priv {
2468 		struct fcoe_cmd_priv {
2469 			__u8   ctl_pri;
2470 			__u8   cp_en_class;
2471 			__u8   r4_lo[2];
2472 		} fcoe;
2473 		struct iscsi_cmd_priv {
2474 			__u8   r4[4];
2475 		} iscsi;
2476 	} u;
2477 	__u8   r5[8];
2478 	__be64 rsp_dmaaddr;
2479 	__be32 rsp_dmalen;
2480 	__be32 r6;
2481 };
2482 
2483 #define	S_FW_SCSI_CMD_WR_OPCODE		24
2484 #define	M_FW_SCSI_CMD_WR_OPCODE		0xff
2485 #define	V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
2486 #define	G_FW_SCSI_CMD_WR_OPCODE(x)	\
2487 	(((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
2488 
2489 #define	S_FW_SCSI_CMD_WR_IMMDLEN	0
2490 #define	M_FW_SCSI_CMD_WR_IMMDLEN	0xff
2491 #define	V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
2492 #define	G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
2493 	(((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
2494 
2495 #define	S_FW_SCSI_CMD_WR_FLOWID		8
2496 #define	M_FW_SCSI_CMD_WR_FLOWID		0xfffff
2497 #define	V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
2498 #define	G_FW_SCSI_CMD_WR_FLOWID(x)	\
2499 	(((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
2500 
2501 #define	S_FW_SCSI_CMD_WR_LEN16		0
2502 #define	M_FW_SCSI_CMD_WR_LEN16		0xff
2503 #define	V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
2504 #define	G_FW_SCSI_CMD_WR_LEN16(x)	\
2505 	(((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
2506 
2507 #define	S_FW_SCSI_CMD_WR_CP_EN		6
2508 #define	M_FW_SCSI_CMD_WR_CP_EN		0x3
2509 #define	V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
2510 #define	G_FW_SCSI_CMD_WR_CP_EN(x)	\
2511 	(((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
2512 
2513 #define	S_FW_SCSI_CMD_WR_CLASS		4
2514 #define	M_FW_SCSI_CMD_WR_CLASS		0x3
2515 #define	V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
2516 #define	G_FW_SCSI_CMD_WR_CLASS(x)	\
2517 	(((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
2518 
2519 struct fw_scsi_abrt_cls_wr {
2520 	__be32 op_immdlen;
2521 	__be32 flowid_len16;
2522 	__be64 cookie;
2523 	__be16 iqid;
2524 	__u8   tmo_val;
2525 	__u8   sub_opcode_to_chk_all_io;
2526 	__u8   r3[4];
2527 	__be64 t_cookie;
2528 };
2529 
2530 #define	S_FW_SCSI_ABRT_CLS_WR_OPCODE	24
2531 #define	M_FW_SCSI_ABRT_CLS_WR_OPCODE	0xff
2532 #define	V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
2533 #define	G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
2534 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
2535 
2536 #define	S_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0
2537 #define	M_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0xff
2538 #define	V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
2539 	((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
2540 #define	G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
2541 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
2542 
2543 #define	S_FW_SCSI_ABRT_CLS_WR_FLOWID	8
2544 #define	M_FW_SCSI_ABRT_CLS_WR_FLOWID	0xfffff
2545 #define	V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
2546 #define	G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
2547 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
2548 
2549 #define	S_FW_SCSI_ABRT_CLS_WR_LEN16	0
2550 #define	M_FW_SCSI_ABRT_CLS_WR_LEN16	0xff
2551 #define	V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
2552 #define	G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
2553 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
2554 
2555 #define	S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	2
2556 #define	M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	0x3f
2557 #define	V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
2558 	((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
2559 #define	G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
2560 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
2561 	M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
2562 
2563 #define	S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
2564 #define	M_FW_SCSI_ABRT_CLS_WR_UNSOL	0x1
2565 #define	V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
2566 #define	G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
2567 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
2568 #define	F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
2569 
2570 #define	S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0
2571 #define	M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0x1
2572 #define	V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
2573 	((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
2574 #define	G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
2575 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
2576 	M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
2577 #define	F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	\
2578     V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
2579 
2580 struct fw_scsi_tgt_acc_wr {
2581 	__be32 op_immdlen;
2582 	__be32 flowid_len16;
2583 	__be64 cookie;
2584 	__be16 iqid;
2585 	__u8   r3;
2586 	__u8   use_burst_len;
2587 	union fw_scsi_tgt_acc_priv {
2588 		struct fcoe_tgt_acc_priv {
2589 			__u8   ctl_pri;
2590 			__u8   cp_en_class;
2591 			__u8   r4_lo[2];
2592 		} fcoe;
2593 		struct iscsi_tgt_acc_priv {
2594 			__u8   r4[4];
2595 		} iscsi;
2596 	} u;
2597 	__be32 burst_len;
2598 	__be32 rel_off;
2599 	__be64 r5;
2600 	__be32 r6;
2601 	__be32 tot_xfer_len;
2602 };
2603 
2604 #define	S_FW_SCSI_TGT_ACC_WR_OPCODE	24
2605 #define	M_FW_SCSI_TGT_ACC_WR_OPCODE	0xff
2606 #define	V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
2607 #define	G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
2608 	(((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
2609 
2610 #define	S_FW_SCSI_TGT_ACC_WR_IMMDLEN	0
2611 #define	M_FW_SCSI_TGT_ACC_WR_IMMDLEN	0xff
2612 #define	V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
2613 #define	G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
2614 	(((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
2615 
2616 #define	S_FW_SCSI_TGT_ACC_WR_FLOWID	8
2617 #define	M_FW_SCSI_TGT_ACC_WR_FLOWID	0xfffff
2618 #define	V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
2619 #define	G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
2620 	(((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
2621 
2622 #define	S_FW_SCSI_TGT_ACC_WR_LEN16	0
2623 #define	M_FW_SCSI_TGT_ACC_WR_LEN16	0xff
2624 #define	V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
2625 #define	G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
2626 	(((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
2627 
2628 #define	S_FW_SCSI_TGT_ACC_WR_CP_EN	6
2629 #define	M_FW_SCSI_TGT_ACC_WR_CP_EN	0x3
2630 #define	V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
2631 #define	G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
2632 	(((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
2633 
2634 #define	S_FW_SCSI_TGT_ACC_WR_CLASS	4
2635 #define	M_FW_SCSI_TGT_ACC_WR_CLASS	0x3
2636 #define	V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
2637 #define	G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
2638 	(((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
2639 
2640 struct fw_scsi_tgt_xmit_wr {
2641 	__be32 op_immdlen;
2642 	__be32 flowid_len16;
2643 	__be64 cookie;
2644 	__be16 iqid;
2645 	__u8   auto_rsp;
2646 	__u8   use_xfer_cnt;
2647 	union fw_scsi_tgt_xmit_priv {
2648 		struct fcoe_tgt_xmit_priv {
2649 			__u8   ctl_pri;
2650 			__u8   cp_en_class;
2651 			__u8   r3_lo[2];
2652 		} fcoe;
2653 		struct iscsi_tgt_xmit_priv {
2654 			__u8   r3[4];
2655 		} iscsi;
2656 	} u;
2657 	__be32 xfer_cnt;
2658 	__be32 r4;
2659 	__be64 r5;
2660 	__be32 r6;
2661 	__be32 tot_xfer_len;
2662 };
2663 
2664 #define	S_FW_SCSI_TGT_XMIT_WR_OPCODE	24
2665 #define	M_FW_SCSI_TGT_XMIT_WR_OPCODE	0xff
2666 #define	V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
2667 #define	G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
2668 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
2669 
2670 #define	S_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0
2671 #define	M_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0xff
2672 #define	V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2673 	((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
2674 #define	G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2675 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
2676 
2677 #define	S_FW_SCSI_TGT_XMIT_WR_FLOWID	8
2678 #define	M_FW_SCSI_TGT_XMIT_WR_FLOWID	0xfffff
2679 #define	V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
2680 #define	G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
2681 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
2682 
2683 #define	S_FW_SCSI_TGT_XMIT_WR_LEN16	0
2684 #define	M_FW_SCSI_TGT_XMIT_WR_LEN16	0xff
2685 #define	V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
2686 #define	G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
2687 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
2688 
2689 #define	S_FW_SCSI_TGT_XMIT_WR_CP_EN	6
2690 #define	M_FW_SCSI_TGT_XMIT_WR_CP_EN	0x3
2691 #define	V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
2692 #define	G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
2693 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
2694 
2695 #define	S_FW_SCSI_TGT_XMIT_WR_CLASS	4
2696 #define	M_FW_SCSI_TGT_XMIT_WR_CLASS	0x3
2697 #define	V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
2698 #define	G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
2699 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
2700 
2701 struct fw_scsi_tgt_rsp_wr {
2702 	__be32 op_immdlen;
2703 	__be32 flowid_len16;
2704 	__be64 cookie;
2705 	__be16 iqid;
2706 	__u8   r3[2];
2707 	union fw_scsi_tgt_rsp_priv {
2708 		struct fcoe_tgt_rsp_priv {
2709 			__u8   ctl_pri;
2710 			__u8   cp_en_class;
2711 			__u8   r4_lo[2];
2712 		} fcoe;
2713 		struct iscsi_tgt_rsp_priv {
2714 			__u8   r4[4];
2715 		} iscsi;
2716 	} u;
2717 	__u8   r5[8];
2718 };
2719 
2720 #define	S_FW_SCSI_TGT_RSP_WR_OPCODE	24
2721 #define	M_FW_SCSI_TGT_RSP_WR_OPCODE	0xff
2722 #define	V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
2723 #define	G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
2724 	(((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
2725 
2726 #define	S_FW_SCSI_TGT_RSP_WR_IMMDLEN	0
2727 #define	M_FW_SCSI_TGT_RSP_WR_IMMDLEN	0xff
2728 #define	V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
2729 #define	G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
2730 	(((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
2731 
2732 #define	S_FW_SCSI_TGT_RSP_WR_FLOWID	8
2733 #define	M_FW_SCSI_TGT_RSP_WR_FLOWID	0xfffff
2734 #define	V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
2735 #define	G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
2736 	(((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
2737 
2738 #define	S_FW_SCSI_TGT_RSP_WR_LEN16	0
2739 #define	M_FW_SCSI_TGT_RSP_WR_LEN16	0xff
2740 #define	V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
2741 #define	G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
2742 	(((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
2743 
2744 #define	S_FW_SCSI_TGT_RSP_WR_CP_EN	6
2745 #define	M_FW_SCSI_TGT_RSP_WR_CP_EN	0x3
2746 #define	V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
2747 #define	G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
2748 	(((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
2749 
2750 #define	S_FW_SCSI_TGT_RSP_WR_CLASS	4
2751 #define	M_FW_SCSI_TGT_RSP_WR_CLASS	0x3
2752 #define	V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
2753 #define	G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
2754 	(((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
2755 
2756 /*
2757  *	*******************
2758  *	  C O M M A N D s
2759  *	*******************
2760  */
2761 
2762 /*
2763  * The maximum length of time, in miliseconds, that we expect any firmware
2764  * command to take to execute and return a reply to the host.  The RESET
2765  * and INITIALIZE commands can take a fair amount of time to execute but
2766  * most execute in far less time than this maximum.  This constant is used
2767  * by host software to determine how long to wait for a firmware command
2768  * reply before declaring the firmware as dead/unreachable ...
2769  */
2770 #define	FW_CMD_MAX_TIMEOUT	10000
2771 
2772 /*
2773  * If a host driver does a HELLO and discovers that there's already a MASTER
2774  * selected, we may have to wait for that MASTER to finish issuing RESET,
2775  * configuration and INITIALIZE commands.  Also, there's a possibility that
2776  * our own HELLO may get lost if it happens right as the MASTER is issuign a
2777  * RESET command, so we need to be willing to make a few retries of our HELLO.
2778  */
2779 #define	FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
2780 #define	FW_CMD_HELLO_RETRIES	3
2781 
2782 enum fw_cmd_opcodes {
2783 	FW_LDST_CMD		= 0x01,
2784 	FW_RESET_CMD		= 0x03,
2785 	FW_HELLO_CMD		= 0x04,
2786 	FW_BYE_CMD		= 0x05,
2787 	FW_INITIALIZE_CMD	= 0x06,
2788 	FW_CAPS_CONFIG_CMD	= 0x07,
2789 	FW_PARAMS_CMD		= 0x08,
2790 	FW_PFVF_CMD		= 0x09,
2791 	FW_IQ_CMD		= 0x10,
2792 	FW_EQ_MNGT_CMD		= 0x11,
2793 	FW_EQ_ETH_CMD		= 0x12,
2794 	FW_EQ_CTRL_CMD		= 0x13,
2795 	FW_EQ_OFLD_CMD		= 0x21,
2796 	FW_VI_CMD		= 0x14,
2797 	FW_VI_MAC_CMD		= 0x15,
2798 	FW_VI_RXMODE_CMD	= 0x16,
2799 	FW_VI_ENABLE_CMD	= 0x17,
2800 	FW_VI_STATS_CMD		= 0x1a,
2801 	FW_ACL_MAC_CMD		= 0x18,
2802 	FW_ACL_VLAN_CMD		= 0x19,
2803 	FW_PORT_CMD		= 0x1b,
2804 	FW_PORT_STATS_CMD	= 0x1c,
2805 	FW_PORT_LB_STATS_CMD	= 0x1d,
2806 	FW_PORT_TRACE_CMD	= 0x1e,
2807 	FW_PORT_TRACE_MMAP_CMD	= 0x1f,
2808 	FW_RSS_IND_TBL_CMD	= 0x20,
2809 	FW_RSS_GLB_CONFIG_CMD	= 0x22,
2810 	FW_RSS_VI_CONFIG_CMD	= 0x23,
2811 	FW_SCHED_CMD		= 0x24,
2812 	FW_DEVLOG_CMD		= 0x25,
2813 	FW_WATCHDOG_CMD		= 0x27,
2814 	FW_CLIP_CMD		= 0x28,
2815 	FW_CHNET_IFACE_CMD	= 0x26,
2816 	FW_FCOE_RES_INFO_CMD	= 0x31,
2817 	FW_FCOE_LINK_CMD	= 0x32,
2818 	FW_FCOE_VNP_CMD		= 0x33,
2819 	FW_FCOE_SPARAMS_CMD	= 0x35,
2820 	FW_FCOE_STATS_CMD	= 0x37,
2821 	FW_FCOE_FCF_CMD		= 0x38,
2822 	FW_LASTC2E_CMD		= 0x40,
2823 	FW_ERROR_CMD		= 0x80,
2824 	FW_DEBUG_CMD		= 0x81,
2825 };
2826 
2827 enum fw_cmd_cap {
2828 	FW_CMD_CAP_PF		= 0x01,
2829 	FW_CMD_CAP_DMAQ		= 0x02,
2830 	FW_CMD_CAP_PORT		= 0x04,
2831 	FW_CMD_CAP_PORTPROMISC	= 0x08,
2832 	FW_CMD_CAP_PORTSTATS	= 0x10,
2833 	FW_CMD_CAP_VF		= 0x80,
2834 };
2835 
2836 /*
2837  * Generic command header flit0
2838  */
2839 struct fw_cmd_hdr {
2840 	__be32 hi;
2841 	__be32 lo;
2842 };
2843 
2844 #define	S_FW_CMD_OP		24
2845 #define	M_FW_CMD_OP		0xff
2846 #define	V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
2847 #define	G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
2848 
2849 #define	S_FW_CMD_REQUEST	23
2850 #define	M_FW_CMD_REQUEST	0x1
2851 #define	V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
2852 #define	G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
2853 #define	F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)
2854 
2855 #define	S_FW_CMD_READ		22
2856 #define	M_FW_CMD_READ		0x1
2857 #define	V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
2858 #define	G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
2859 #define	F_FW_CMD_READ		V_FW_CMD_READ(1U)
2860 
2861 #define	S_FW_CMD_WRITE		21
2862 #define	M_FW_CMD_WRITE		0x1
2863 #define	V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
2864 #define	G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
2865 #define	F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)
2866 
2867 #define	S_FW_CMD_EXEC		20
2868 #define	M_FW_CMD_EXEC		0x1
2869 #define	V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
2870 #define	G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
2871 #define	F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)
2872 
2873 #define	S_FW_CMD_RAMASK		20
2874 #define	M_FW_CMD_RAMASK		0xf
2875 #define	V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
2876 #define	G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
2877 
2878 #define	S_FW_CMD_RETVAL		8
2879 #define	M_FW_CMD_RETVAL		0xff
2880 #define	V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
2881 #define	G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
2882 
2883 #define	S_FW_CMD_LEN16		0
2884 #define	M_FW_CMD_LEN16		0xff
2885 #define	V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
2886 #define	G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
2887 
2888 #define	FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof (fw_struct) / 16)
2889 
2890 /*
2891  *	address spaces
2892  */
2893 enum fw_ldst_addrspc {
2894 	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
2895 	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
2896 	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
2897 	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
2898 	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
2899 	FW_LDST_ADDRSPC_TP_PIO	  = 0x0010,
2900 	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
2901 	FW_LDST_ADDRSPC_TP_MIB	  = 0x0012,
2902 	FW_LDST_ADDRSPC_MDIO	  = 0x0018,
2903 	FW_LDST_ADDRSPC_MPS	  = 0x0020,
2904 	FW_LDST_ADDRSPC_FUNC	  = 0x0028,
2905 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
2906 	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A,
2907 	FW_LDST_ADDRSPC_LE	  = 0x0030,
2908 };
2909 
2910 /*
2911  *	MDIO VSC8634 register access control field
2912  */
2913 enum fw_ldst_mdio_vsc8634_aid {
2914 	FW_LDST_MDIO_VS_STANDARD,
2915 	FW_LDST_MDIO_VS_EXTENDED,
2916 	FW_LDST_MDIO_VS_GPIO
2917 };
2918 
2919 enum fw_ldst_mps_fid {
2920 	FW_LDST_MPS_ATRB,
2921 	FW_LDST_MPS_RPLC
2922 };
2923 
2924 enum fw_ldst_func_access_ctl {
2925 	FW_LDST_FUNC_ACC_CTL_VIID,
2926 	FW_LDST_FUNC_ACC_CTL_FID
2927 };
2928 
2929 enum fw_ldst_func_mod_index {
2930 	FW_LDST_FUNC_MPS
2931 };
2932 
2933 struct fw_ldst_cmd {
2934 	__be32 op_to_addrspace;
2935 	__be32 cycles_to_len16;
2936 	union fw_ldst {
2937 		struct fw_ldst_addrval {
2938 			__be32 addr;
2939 			__be32 val;
2940 		} addrval;
2941 		struct fw_ldst_idctxt {
2942 			__be32 physid;
2943 			__be32 msg_ctxtflush;
2944 			__be32 ctxt_data7;
2945 			__be32 ctxt_data6;
2946 			__be32 ctxt_data5;
2947 			__be32 ctxt_data4;
2948 			__be32 ctxt_data3;
2949 			__be32 ctxt_data2;
2950 			__be32 ctxt_data1;
2951 			__be32 ctxt_data0;
2952 		} idctxt;
2953 		struct fw_ldst_mdio {
2954 			__be16 paddr_mmd;
2955 			__be16 raddr;
2956 			__be16 vctl;
2957 			__be16 rval;
2958 		} mdio;
2959 		struct fw_ldst_mps {
2960 			__be16 fid_ctl;
2961 			__be16 rplcpf_pkd;
2962 			__be32 rplc127_96;
2963 			__be32 rplc95_64;
2964 			__be32 rplc63_32;
2965 			__be32 rplc31_0;
2966 			__be32 atrb;
2967 			__be16 vlan[16];
2968 		} mps;
2969 		struct fw_ldst_func {
2970 			__u8   access_ctl;
2971 			__u8   mod_index;
2972 			__be16 ctl_id;
2973 			__be32 offset;
2974 			__be64 data0;
2975 			__be64 data1;
2976 		} func;
2977 		struct fw_ldst_pcie {
2978 			__u8   ctrl_to_fn;
2979 			__u8   bnum;
2980 			__u8   r;
2981 			__u8   ext_r;
2982 			__u8   select_naccess;
2983 			__u8   pcie_fn;
2984 			__be16 nset_pkd;
2985 			__be32 data[12];
2986 		} pcie;
2987 		struct fw_ldst_i2c {
2988 			__u8   pid_pkd;
2989 			__u8   base;
2990 			__u8   boffset;
2991 			__u8   data;
2992 			__be32 r9;
2993 		} i2c;
2994 		struct fw_ldst_le {
2995 			__be16	region;
2996 			__be16	nval;
2997 			__u32	val[12];
2998 		} le;
2999 	} u;
3000 };
3001 
3002 #define	S_FW_LDST_CMD_ADDRSPACE		0
3003 #define	M_FW_LDST_CMD_ADDRSPACE		0xff
3004 #define	V_FW_LDST_CMD_ADDRSPACE(x)	((x) << S_FW_LDST_CMD_ADDRSPACE)
3005 #define	G_FW_LDST_CMD_ADDRSPACE(x)	\
3006 	(((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
3007 
3008 #define	S_FW_LDST_CMD_CYCLES	16
3009 #define	M_FW_LDST_CMD_CYCLES	0xffff
3010 #define	V_FW_LDST_CMD_CYCLES(x)	((x) << S_FW_LDST_CMD_CYCLES)
3011 #define	G_FW_LDST_CMD_CYCLES(x)	\
3012 	(((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
3013 
3014 #define	S_FW_LDST_CMD_MSG	31
3015 #define	M_FW_LDST_CMD_MSG	0x1
3016 #define	V_FW_LDST_CMD_MSG(x)	((x) << S_FW_LDST_CMD_MSG)
3017 #define	G_FW_LDST_CMD_MSG(x)	\
3018 	(((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
3019 #define	F_FW_LDST_CMD_MSG	V_FW_LDST_CMD_MSG(1U)
3020 
3021 #define	S_FW_LDST_CMD_CTXTFLUSH		30
3022 #define	M_FW_LDST_CMD_CTXTFLUSH		0x1
3023 #define	V_FW_LDST_CMD_CTXTFLUSH(x)	((x) << S_FW_LDST_CMD_CTXTFLUSH)
3024 #define	G_FW_LDST_CMD_CTXTFLUSH(x)	\
3025 	(((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
3026 #define	F_FW_LDST_CMD_CTXTFLUSH	V_FW_LDST_CMD_CTXTFLUSH(1U)
3027 
3028 #define	S_FW_LDST_CMD_PADDR	8
3029 #define	M_FW_LDST_CMD_PADDR	0x1f
3030 #define	V_FW_LDST_CMD_PADDR(x)	((x) << S_FW_LDST_CMD_PADDR)
3031 #define	G_FW_LDST_CMD_PADDR(x)	\
3032 	(((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
3033 
3034 #define	S_FW_LDST_CMD_MMD	0
3035 #define	M_FW_LDST_CMD_MMD	0x1f
3036 #define	V_FW_LDST_CMD_MMD(x)	((x) << S_FW_LDST_CMD_MMD)
3037 #define	G_FW_LDST_CMD_MMD(x)	\
3038 	(((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
3039 
3040 #define	S_FW_LDST_CMD_FID	15
3041 #define	M_FW_LDST_CMD_FID	0x1
3042 #define	V_FW_LDST_CMD_FID(x)	((x) << S_FW_LDST_CMD_FID)
3043 #define	G_FW_LDST_CMD_FID(x)	\
3044 	(((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
3045 #define	F_FW_LDST_CMD_FID	V_FW_LDST_CMD_FID(1U)
3046 
3047 #define	S_FW_LDST_CMD_CTL	0
3048 #define	M_FW_LDST_CMD_CTL	0x7fff
3049 #define	V_FW_LDST_CMD_CTL(x)	((x) << S_FW_LDST_CMD_CTL)
3050 #define	G_FW_LDST_CMD_CTL(x)	\
3051 	(((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL)
3052 
3053 #define	S_FW_LDST_CMD_RPLCPF	0
3054 #define	M_FW_LDST_CMD_RPLCPF	0xff
3055 #define	V_FW_LDST_CMD_RPLCPF(x)	((x) << S_FW_LDST_CMD_RPLCPF)
3056 #define	G_FW_LDST_CMD_RPLCPF(x)	\
3057 	(((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
3058 
3059 #define	S_FW_LDST_CMD_CTRL	7
3060 #define	M_FW_LDST_CMD_CTRL	0x1
3061 #define	V_FW_LDST_CMD_CTRL(x)	((x) << S_FW_LDST_CMD_CTRL)
3062 #define	G_FW_LDST_CMD_CTRL(x)	\
3063 	(((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
3064 #define	F_FW_LDST_CMD_CTRL	V_FW_LDST_CMD_CTRL(1U)
3065 
3066 #define	S_FW_LDST_CMD_LC	4
3067 #define	M_FW_LDST_CMD_LC	0x1
3068 #define	V_FW_LDST_CMD_LC(x)	((x) << S_FW_LDST_CMD_LC)
3069 #define	G_FW_LDST_CMD_LC(x)	(((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
3070 #define	F_FW_LDST_CMD_LC	V_FW_LDST_CMD_LC(1U)
3071 
3072 #define	S_FW_LDST_CMD_AI	3
3073 #define	M_FW_LDST_CMD_AI	0x1
3074 #define	V_FW_LDST_CMD_AI(x)	((x) << S_FW_LDST_CMD_AI)
3075 #define	G_FW_LDST_CMD_AI(x)	(((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
3076 #define	F_FW_LDST_CMD_AI	V_FW_LDST_CMD_AI(1U)
3077 
3078 #define	S_FW_LDST_CMD_FN	0
3079 #define	M_FW_LDST_CMD_FN	0x7
3080 #define	V_FW_LDST_CMD_FN(x)	((x) << S_FW_LDST_CMD_FN)
3081 #define	G_FW_LDST_CMD_FN(x)	(((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
3082 
3083 #define	S_FW_LDST_CMD_SELECT	4
3084 #define	M_FW_LDST_CMD_SELECT	0xf
3085 #define	V_FW_LDST_CMD_SELECT(x)	((x) << S_FW_LDST_CMD_SELECT)
3086 #define	G_FW_LDST_CMD_SELECT(x)	\
3087 	(((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
3088 
3089 #define	S_FW_LDST_CMD_NACCESS		0
3090 #define	M_FW_LDST_CMD_NACCESS		0xf
3091 #define	V_FW_LDST_CMD_NACCESS(x)	((x) << S_FW_LDST_CMD_NACCESS)
3092 #define	G_FW_LDST_CMD_NACCESS(x)	\
3093 	(((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
3094 
3095 #define	S_FW_LDST_CMD_NSET	14
3096 #define	M_FW_LDST_CMD_NSET	0x3
3097 #define	V_FW_LDST_CMD_NSET(x)	((x) << S_FW_LDST_CMD_NSET)
3098 #define	G_FW_LDST_CMD_NSET(x)	\
3099 	(((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
3100 
3101 #define	S_FW_LDST_CMD_PID	6
3102 #define	M_FW_LDST_CMD_PID	0x3
3103 #define	V_FW_LDST_CMD_PID(x)	((x) << S_FW_LDST_CMD_PID)
3104 #define	G_FW_LDST_CMD_PID(x)	\
3105 	(((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
3106 
3107 struct fw_reset_cmd {
3108 	__be32 op_to_write;
3109 	__be32 retval_len16;
3110 	__be32 val;
3111 	__be32 halt_pkd;
3112 };
3113 
3114 #define	S_FW_RESET_CMD_HALT	31
3115 #define	M_FW_RESET_CMD_HALT	0x1
3116 #define	V_FW_RESET_CMD_HALT(x)	((x) << S_FW_RESET_CMD_HALT)
3117 #define	G_FW_RESET_CMD_HALT(x)	\
3118 	(((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
3119 #define	F_FW_RESET_CMD_HALT	V_FW_RESET_CMD_HALT(1U)
3120 
3121 enum {
3122 	FW_HELLO_CMD_STAGE_OS		= 0,
3123 	FW_HELLO_CMD_STAGE_PREOS0	= 1,
3124 	FW_HELLO_CMD_STAGE_PREOS1	= 2,
3125 	FW_HELLO_CMD_STAGE_POSTOS	= 3,
3126 };
3127 
3128 struct fw_hello_cmd {
3129 	__be32 op_to_write;
3130 	__be32 retval_len16;
3131 	__be32 err_to_clearinit;
3132 	__be32 fwrev;
3133 };
3134 
3135 #define	S_FW_HELLO_CMD_ERR	31
3136 #define	M_FW_HELLO_CMD_ERR	0x1
3137 #define	V_FW_HELLO_CMD_ERR(x)	((x) << S_FW_HELLO_CMD_ERR)
3138 #define	G_FW_HELLO_CMD_ERR(x)	\
3139 	(((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
3140 #define	F_FW_HELLO_CMD_ERR	V_FW_HELLO_CMD_ERR(1U)
3141 
3142 #define	S_FW_HELLO_CMD_INIT	30
3143 #define	M_FW_HELLO_CMD_INIT	0x1
3144 #define	V_FW_HELLO_CMD_INIT(x)	((x) << S_FW_HELLO_CMD_INIT)
3145 #define	G_FW_HELLO_CMD_INIT(x)	\
3146 	(((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
3147 #define	F_FW_HELLO_CMD_INIT	V_FW_HELLO_CMD_INIT(1U)
3148 
3149 #define	S_FW_HELLO_CMD_MASTERDIS	29
3150 #define	M_FW_HELLO_CMD_MASTERDIS	0x1
3151 #define	V_FW_HELLO_CMD_MASTERDIS(x)	((x) << S_FW_HELLO_CMD_MASTERDIS)
3152 #define	G_FW_HELLO_CMD_MASTERDIS(x)	\
3153 	(((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
3154 #define	F_FW_HELLO_CMD_MASTERDIS	V_FW_HELLO_CMD_MASTERDIS(1U)
3155 
3156 #define	S_FW_HELLO_CMD_MASTERFORCE	28
3157 #define	M_FW_HELLO_CMD_MASTERFORCE	0x1
3158 #define	V_FW_HELLO_CMD_MASTERFORCE(x)	((x) << S_FW_HELLO_CMD_MASTERFORCE)
3159 #define	G_FW_HELLO_CMD_MASTERFORCE(x)	\
3160 	(((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
3161 #define	F_FW_HELLO_CMD_MASTERFORCE	V_FW_HELLO_CMD_MASTERFORCE(1U)
3162 
3163 #define	S_FW_HELLO_CMD_MBMASTER		24
3164 #define	M_FW_HELLO_CMD_MBMASTER		0xf
3165 #define	V_FW_HELLO_CMD_MBMASTER(x)	((x) << S_FW_HELLO_CMD_MBMASTER)
3166 #define	G_FW_HELLO_CMD_MBMASTER(x)	\
3167 	(((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
3168 
3169 #define	S_FW_HELLO_CMD_MBASYNCNOTINT	23
3170 #define	M_FW_HELLO_CMD_MBASYNCNOTINT	0x1
3171 #define	V_FW_HELLO_CMD_MBASYNCNOTINT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
3172 #define	G_FW_HELLO_CMD_MBASYNCNOTINT(x)	\
3173 	(((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
3174 #define	F_FW_HELLO_CMD_MBASYNCNOTINT	V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
3175 
3176 #define	S_FW_HELLO_CMD_MBASYNCNOT	20
3177 #define	M_FW_HELLO_CMD_MBASYNCNOT	0x7
3178 #define	V_FW_HELLO_CMD_MBASYNCNOT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOT)
3179 #define	G_FW_HELLO_CMD_MBASYNCNOT(x)	\
3180 	(((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
3181 
3182 #define	S_FW_HELLO_CMD_STAGE	17
3183 #define	M_FW_HELLO_CMD_STAGE	0x7
3184 #define	V_FW_HELLO_CMD_STAGE(x)	((x) << S_FW_HELLO_CMD_STAGE)
3185 #define	G_FW_HELLO_CMD_STAGE(x)	\
3186 	(((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
3187 
3188 #define	S_FW_HELLO_CMD_CLEARINIT	16
3189 #define	M_FW_HELLO_CMD_CLEARINIT	0x1
3190 #define	V_FW_HELLO_CMD_CLEARINIT(x)	((x) << S_FW_HELLO_CMD_CLEARINIT)
3191 #define	G_FW_HELLO_CMD_CLEARINIT(x)	\
3192 	(((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
3193 #define	F_FW_HELLO_CMD_CLEARINIT	V_FW_HELLO_CMD_CLEARINIT(1U)
3194 
3195 struct fw_bye_cmd {
3196 	__be32 op_to_write;
3197 	__be32 retval_len16;
3198 	__be64 r3;
3199 };
3200 
3201 struct fw_initialize_cmd {
3202 	__be32 op_to_write;
3203 	__be32 retval_len16;
3204 	__be64 r3;
3205 };
3206 
3207 enum fw_caps_config_hm {
3208 	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
3209 	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
3210 	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
3211 	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
3212 	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
3213 	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
3214 	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
3215 	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
3216 	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
3217 	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
3218 	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
3219 	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
3220 	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
3221 	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
3222 	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
3223 	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
3224 	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
3225 	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
3226 	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
3227 	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
3228 	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
3229 	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
3230 	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
3231 	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
3232 };
3233 
3234 /*
3235  * The VF Register Map.
3236  *
3237  * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
3238  * bus module (PL) and CPU Interface Module (CIM) components are mapped via
3239  * the Slice to Module Map Table (see below) in the Physical Function Register
3240  * Map.  The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
3241  * and Offset registers in the PF Register Map.  The MBDATA base address is
3242  * quite constrained as it determines the Mailbox Data addresses for both PFs
3243  * and VFs, and therefore must fit in both the VF and PF Register Maps without
3244  * overlapping other registers.
3245  */
3246 #define	FW_T4VF_SGE_BASE_ADDR		0x0000
3247 #define	FW_T4VF_MPS_BASE_ADDR		0x0100
3248 #define	FW_T4VF_PL_BASE_ADDR		0x0200
3249 #define	FW_T4VF_MBDATA_BASE_ADDR	0x0240
3250 #define	FW_T4VF_CIM_BASE_ADDR		0x0300
3251 
3252 #define	FW_T4VF_REGMAP_START		0x0000
3253 #define	FW_T4VF_REGMAP_SIZE		0x0400
3254 
3255 enum fw_caps_config_nbm {
3256 	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
3257 	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
3258 };
3259 
3260 enum fw_caps_config_link {
3261 	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
3262 	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
3263 	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
3264 };
3265 
3266 enum fw_caps_config_switch {
3267 	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
3268 	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
3269 };
3270 
3271 enum fw_caps_config_nic {
3272 	FW_CAPS_CONFIG_NIC		= 0x00000001,
3273 	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
3274 	FW_CAPS_CONFIG_NIC_IDS		= 0x00000004,
3275 	FW_CAPS_CONFIG_NIC_UM		= 0x00000008,
3276 	FW_CAPS_CONFIG_NIC_UM_ISGL	= 0x00000010,
3277 };
3278 
3279 enum fw_caps_config_toe {
3280 	FW_CAPS_CONFIG_TOE		= 0x00000001,
3281 };
3282 
3283 enum fw_caps_config_rdma {
3284 	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
3285 	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
3286 };
3287 
3288 enum fw_caps_config_iscsi {
3289 	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
3290 	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
3291 	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
3292 	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
3293 	FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
3294 	FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
3295 
3296 };
3297 
3298 enum fw_caps_config_fcoe {
3299 	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
3300 	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
3301 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
3302 };
3303 
3304 enum fw_memtype_cf {
3305 	FW_MEMTYPE_CF_EDC0		= 0x0,
3306 	FW_MEMTYPE_CF_EDC1		= 0x1,
3307 	FW_MEMTYPE_CF_EXTMEM		= 0x2,
3308 	FW_MEMTYPE_CF_FLASH		= 0x4,
3309 	FW_MEMTYPE_CF_INTERNAL		= 0x5,
3310 };
3311 
3312 struct fw_caps_config_cmd {
3313 	__be32 op_to_write;
3314 	__be32 cfvalid_to_len16;
3315 	__be32 r2;
3316 	__be32 hwmbitmap;
3317 	__be16 nbmcaps;
3318 	__be16 linkcaps;
3319 	__be16 switchcaps;
3320 	__be16 r3;
3321 	__be16 niccaps;
3322 	__be16 toecaps;
3323 	__be16 rdmacaps;
3324 	__be16 r4;
3325 	__be16 iscsicaps;
3326 	__be16 fcoecaps;
3327 	__be32 cfcsum;
3328 	__be32 finiver;
3329 	__be32 finicsum;
3330 };
3331 
3332 #define	S_FW_CAPS_CONFIG_CMD_CFVALID	27
3333 #define	M_FW_CAPS_CONFIG_CMD_CFVALID	0x1
3334 #define	V_FW_CAPS_CONFIG_CMD_CFVALID(x)	((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
3335 #define	G_FW_CAPS_CONFIG_CMD_CFVALID(x)	\
3336 	(((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
3337 #define	F_FW_CAPS_CONFIG_CMD_CFVALID	V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
3338 
3339 #define	S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF		24
3340 #define	M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF		0x7
3341 #define	V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)	\
3342 	((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
3343 #define	G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)	\
3344 	(((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
3345 	M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
3346 
3347 #define	S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF	16
3348 #define	M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF	0xff
3349 #define	V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)	\
3350 	((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
3351 #define	G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)	\
3352 	(((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
3353 	M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
3354 
3355 /*
3356  * params command mnemonics
3357  */
3358 enum fw_params_mnem {
3359 	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
3360 	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
3361 	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
3362 	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
3363 	FW_PARAMS_MNEM_LAST
3364 };
3365 
3366 /*
3367  * device parameters
3368  */
3369 enum fw_params_param_dev {
3370 	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
3371 	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
3372 	/* reads the number of TIDs allocated by the device's Lookup Engine */
3373 	FW_PARAMS_PARAM_DEV_NTID	= 0x02,
3374 	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
3375 	FW_PARAMS_PARAM_DEV_INTFVER_NIC	= 0x04,
3376 	FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
3377 	FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
3378 	FW_PARAMS_PARAM_DEV_INTFVER_RI	= 0x07,
3379 	FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
3380 	FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
3381 	FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
3382 	FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
3383 	FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
3384 	FW_PARAMS_PARAM_DEV_CF = 0x0D,
3385 	FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
3386 };
3387 
3388 /*
3389  * physical and virtual function parameters
3390  */
3391 enum fw_params_param_pfvf {
3392 	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
3393 	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
3394 	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
3395 	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
3396 	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
3397 	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
3398 	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
3399 	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
3400 	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
3401 	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
3402 	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
3403 	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
3404 	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
3405 	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
3406 	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
3407 	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
3408 	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
3409 	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
3410 	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
3411 	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
3412 	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
3413 	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
3414 	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
3415 	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
3416 	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
3417 	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
3418 	FW_PARAMS_PARAM_PFVF_VIID	= 0x24,
3419 	FW_PARAMS_PARAM_PFVF_CPMASK	= 0x25,
3420 	FW_PARAMS_PARAM_PFVF_OCQ_START	= 0x26,
3421 	FW_PARAMS_PARAM_PFVF_OCQ_END	= 0x27,
3422 	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
3423 	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
3424 	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
3425 	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
3426 	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
3427 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
3428 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
3429 	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
3430 	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30
3431 };
3432 
3433 /*
3434  * dma queue parameters
3435  */
3436 enum fw_params_param_dmaq {
3437 	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
3438 	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
3439 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
3440 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
3441 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
3442 	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13
3443 };
3444 
3445 /*
3446  * dev bypass parameters; actions and modes
3447  */
3448 enum fw_params_param_dev_bypass {
3449 
3450 	/* actions */
3451 	FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
3452 	FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
3453 
3454 	/* modes */
3455 	FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
3456 	FW_PARAMS_PARAM_DEV_BYPASS_DROP	= 0x1,
3457 	FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
3458 };
3459 
3460 #define	S_FW_PARAMS_MNEM	24
3461 #define	M_FW_PARAMS_MNEM	0xff
3462 #define	V_FW_PARAMS_MNEM(x)	((x) << S_FW_PARAMS_MNEM)
3463 #define	G_FW_PARAMS_MNEM(x)	\
3464 	(((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
3465 
3466 #define	S_FW_PARAMS_PARAM_X	16
3467 #define	M_FW_PARAMS_PARAM_X	0xff
3468 #define	V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
3469 #define	G_FW_PARAMS_PARAM_X(x) \
3470 	(((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
3471 
3472 #define	S_FW_PARAMS_PARAM_Y	8
3473 #define	M_FW_PARAMS_PARAM_Y	0xff
3474 #define	V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
3475 #define	G_FW_PARAMS_PARAM_Y(x) \
3476 	(((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
3477 
3478 #define	S_FW_PARAMS_PARAM_Z	0
3479 #define	M_FW_PARAMS_PARAM_Z	0xff
3480 #define	V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
3481 #define	G_FW_PARAMS_PARAM_Z(x) \
3482 	(((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
3483 
3484 #define	S_FW_PARAMS_PARAM_XYZ	0
3485 #define	M_FW_PARAMS_PARAM_XYZ	0xffffff
3486 #define	V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
3487 #define	G_FW_PARAMS_PARAM_XYZ(x) \
3488 	(((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
3489 
3490 #define	S_FW_PARAMS_PARAM_YZ	0
3491 #define	M_FW_PARAMS_PARAM_YZ	0xffff
3492 #define	V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
3493 #define	G_FW_PARAMS_PARAM_YZ(x) \
3494 	(((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
3495 
3496 struct fw_params_cmd {
3497 	__be32 op_to_vfn;
3498 	__be32 retval_len16;
3499 	struct fw_params_param {
3500 		__be32 mnem;
3501 		__be32 val;
3502 	} param[7];
3503 };
3504 
3505 #define	S_FW_PARAMS_CMD_PFN	8
3506 #define	M_FW_PARAMS_CMD_PFN	0x7
3507 #define	V_FW_PARAMS_CMD_PFN(x)	((x) << S_FW_PARAMS_CMD_PFN)
3508 #define	G_FW_PARAMS_CMD_PFN(x)	\
3509 	(((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
3510 
3511 #define	S_FW_PARAMS_CMD_VFN	0
3512 #define	M_FW_PARAMS_CMD_VFN	0xff
3513 #define	V_FW_PARAMS_CMD_VFN(x)	((x) << S_FW_PARAMS_CMD_VFN)
3514 #define	G_FW_PARAMS_CMD_VFN(x)	\
3515 	(((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
3516 
3517 struct fw_pfvf_cmd {
3518 	__be32 op_to_vfn;
3519 	__be32 retval_len16;
3520 	__be32 niqflint_niq;
3521 	__be32 type_to_neq;
3522 	__be32 tc_to_nexactf;
3523 	__be32 r_caps_to_nethctrl;
3524 	__be16 nricq;
3525 	__be16 nriqp;
3526 	__be32 r4;
3527 };
3528 
3529 #define	S_FW_PFVF_CMD_PFN	8
3530 #define	M_FW_PFVF_CMD_PFN	0x7
3531 #define	V_FW_PFVF_CMD_PFN(x)	((x) << S_FW_PFVF_CMD_PFN)
3532 #define	G_FW_PFVF_CMD_PFN(x)	\
3533 	(((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
3534 
3535 #define	S_FW_PFVF_CMD_VFN	0
3536 #define	M_FW_PFVF_CMD_VFN	0xff
3537 #define	V_FW_PFVF_CMD_VFN(x)	((x) << S_FW_PFVF_CMD_VFN)
3538 #define	G_FW_PFVF_CMD_VFN(x)	\
3539 	(((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
3540 
3541 #define	S_FW_PFVF_CMD_NIQFLINT		20
3542 #define	M_FW_PFVF_CMD_NIQFLINT		0xfff
3543 #define	V_FW_PFVF_CMD_NIQFLINT(x)	((x) << S_FW_PFVF_CMD_NIQFLINT)
3544 #define	G_FW_PFVF_CMD_NIQFLINT(x)	\
3545 	(((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
3546 
3547 #define	S_FW_PFVF_CMD_NIQ	0
3548 #define	M_FW_PFVF_CMD_NIQ	0xfffff
3549 #define	V_FW_PFVF_CMD_NIQ(x)	((x) << S_FW_PFVF_CMD_NIQ)
3550 #define	G_FW_PFVF_CMD_NIQ(x)	\
3551 	(((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
3552 
3553 #define	S_FW_PFVF_CMD_TYPE	31
3554 #define	M_FW_PFVF_CMD_TYPE	0x1
3555 #define	V_FW_PFVF_CMD_TYPE(x)	((x) << S_FW_PFVF_CMD_TYPE)
3556 #define	G_FW_PFVF_CMD_TYPE(x)	\
3557 	(((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
3558 #define	F_FW_PFVF_CMD_TYPE	V_FW_PFVF_CMD_TYPE(1U)
3559 
3560 #define	S_FW_PFVF_CMD_CMASK	24
3561 #define	M_FW_PFVF_CMD_CMASK	0xf
3562 #define	V_FW_PFVF_CMD_CMASK(x)	((x) << S_FW_PFVF_CMD_CMASK)
3563 #define	G_FW_PFVF_CMD_CMASK(x)	\
3564 	(((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
3565 
3566 #define	S_FW_PFVF_CMD_PMASK	20
3567 #define	M_FW_PFVF_CMD_PMASK	0xf
3568 #define	V_FW_PFVF_CMD_PMASK(x)	((x) << S_FW_PFVF_CMD_PMASK)
3569 #define	G_FW_PFVF_CMD_PMASK(x)	\
3570 	(((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
3571 
3572 #define	S_FW_PFVF_CMD_NEQ	0
3573 #define	M_FW_PFVF_CMD_NEQ	0xfffff
3574 #define	V_FW_PFVF_CMD_NEQ(x)	((x) << S_FW_PFVF_CMD_NEQ)
3575 #define	G_FW_PFVF_CMD_NEQ(x)	\
3576 	(((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
3577 
3578 #define	S_FW_PFVF_CMD_TC	24
3579 #define	M_FW_PFVF_CMD_TC	0xff
3580 #define	V_FW_PFVF_CMD_TC(x)	((x) << S_FW_PFVF_CMD_TC)
3581 #define	G_FW_PFVF_CMD_TC(x)	(((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
3582 
3583 #define	S_FW_PFVF_CMD_NVI	16
3584 #define	M_FW_PFVF_CMD_NVI	0xff
3585 #define	V_FW_PFVF_CMD_NVI(x)	((x) << S_FW_PFVF_CMD_NVI)
3586 #define	G_FW_PFVF_CMD_NVI(x)	\
3587 	(((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
3588 
3589 #define	S_FW_PFVF_CMD_NEXACTF		0
3590 #define	M_FW_PFVF_CMD_NEXACTF		0xffff
3591 #define	V_FW_PFVF_CMD_NEXACTF(x)	((x) << S_FW_PFVF_CMD_NEXACTF)
3592 #define	G_FW_PFVF_CMD_NEXACTF(x)	\
3593 	(((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
3594 
3595 #define	S_FW_PFVF_CMD_R_CAPS	24
3596 #define	M_FW_PFVF_CMD_R_CAPS	0xff
3597 #define	V_FW_PFVF_CMD_R_CAPS(x)	((x) << S_FW_PFVF_CMD_R_CAPS)
3598 #define	G_FW_PFVF_CMD_R_CAPS(x)	\
3599 	(((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
3600 
3601 #define	S_FW_PFVF_CMD_WX_CAPS		16
3602 #define	M_FW_PFVF_CMD_WX_CAPS		0xff
3603 #define	V_FW_PFVF_CMD_WX_CAPS(x)	((x) << S_FW_PFVF_CMD_WX_CAPS)
3604 #define	G_FW_PFVF_CMD_WX_CAPS(x)	\
3605 	(((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
3606 
3607 #define	S_FW_PFVF_CMD_NETHCTRL		0
3608 #define	M_FW_PFVF_CMD_NETHCTRL		0xffff
3609 #define	V_FW_PFVF_CMD_NETHCTRL(x)	((x) << S_FW_PFVF_CMD_NETHCTRL)
3610 #define	G_FW_PFVF_CMD_NETHCTRL(x)	\
3611 	(((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
3612 
3613 /*
3614  *	ingress queue type; the first 1K ingress queues can have associated 0,
3615  *	1 or 2 free lists and an interrupt, all other ingress queues lack these
3616  *	capabilities
3617  */
3618 enum fw_iq_type {
3619 	FW_IQ_TYPE_FL_INT_CAP,
3620 	FW_IQ_TYPE_NO_FL_INT_CAP
3621 };
3622 
3623 struct fw_iq_cmd {
3624 	__be32 op_to_vfn;
3625 	__be32 alloc_to_len16;
3626 	__be16 physiqid;
3627 	__be16 iqid;
3628 	__be16 fl0id;
3629 	__be16 fl1id;
3630 	__be32 type_to_iqandstindex;
3631 	__be16 iqdroprss_to_iqesize;
3632 	__be16 iqsize;
3633 	__be64 iqaddr;
3634 	__be32 iqns_to_fl0congen;
3635 	__be16 fl0dcaen_to_fl0cidxfthresh;
3636 	__be16 fl0size;
3637 	__be64 fl0addr;
3638 	__be32 fl1cngchmap_to_fl1congen;
3639 	__be16 fl1dcaen_to_fl1cidxfthresh;
3640 	__be16 fl1size;
3641 	__be64 fl1addr;
3642 };
3643 
3644 #define	S_FW_IQ_CMD_PFN		8
3645 #define	M_FW_IQ_CMD_PFN		0x7
3646 #define	V_FW_IQ_CMD_PFN(x)	((x) << S_FW_IQ_CMD_PFN)
3647 #define	G_FW_IQ_CMD_PFN(x)	(((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
3648 
3649 #define	S_FW_IQ_CMD_VFN		0
3650 #define	M_FW_IQ_CMD_VFN		0xff
3651 #define	V_FW_IQ_CMD_VFN(x)	((x) << S_FW_IQ_CMD_VFN)
3652 #define	G_FW_IQ_CMD_VFN(x)	(((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
3653 
3654 #define	S_FW_IQ_CMD_ALLOC	31
3655 #define	M_FW_IQ_CMD_ALLOC	0x1
3656 #define	V_FW_IQ_CMD_ALLOC(x)	((x) << S_FW_IQ_CMD_ALLOC)
3657 #define	G_FW_IQ_CMD_ALLOC(x)	\
3658 	(((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
3659 #define	F_FW_IQ_CMD_ALLOC	V_FW_IQ_CMD_ALLOC(1U)
3660 
3661 #define	S_FW_IQ_CMD_FREE	30
3662 #define	M_FW_IQ_CMD_FREE	0x1
3663 #define	V_FW_IQ_CMD_FREE(x)	((x) << S_FW_IQ_CMD_FREE)
3664 #define	G_FW_IQ_CMD_FREE(x)	(((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
3665 #define	F_FW_IQ_CMD_FREE	V_FW_IQ_CMD_FREE(1U)
3666 
3667 #define	S_FW_IQ_CMD_MODIFY	29
3668 #define	M_FW_IQ_CMD_MODIFY	0x1
3669 #define	V_FW_IQ_CMD_MODIFY(x)	((x) << S_FW_IQ_CMD_MODIFY)
3670 #define	G_FW_IQ_CMD_MODIFY(x)	\
3671 	(((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
3672 #define	F_FW_IQ_CMD_MODIFY	V_FW_IQ_CMD_MODIFY(1U)
3673 
3674 #define	S_FW_IQ_CMD_IQSTART	28
3675 #define	M_FW_IQ_CMD_IQSTART	0x1
3676 #define	V_FW_IQ_CMD_IQSTART(x)	((x) << S_FW_IQ_CMD_IQSTART)
3677 #define	G_FW_IQ_CMD_IQSTART(x)	\
3678 	(((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
3679 #define	F_FW_IQ_CMD_IQSTART	V_FW_IQ_CMD_IQSTART(1U)
3680 
3681 #define	S_FW_IQ_CMD_IQSTOP	27
3682 #define	M_FW_IQ_CMD_IQSTOP	0x1
3683 #define	V_FW_IQ_CMD_IQSTOP(x)	((x) << S_FW_IQ_CMD_IQSTOP)
3684 #define	G_FW_IQ_CMD_IQSTOP(x)	\
3685 	(((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
3686 #define	F_FW_IQ_CMD_IQSTOP	V_FW_IQ_CMD_IQSTOP(1U)
3687 
3688 #define	S_FW_IQ_CMD_TYPE	29
3689 #define	M_FW_IQ_CMD_TYPE	0x7
3690 #define	V_FW_IQ_CMD_TYPE(x)	((x) << S_FW_IQ_CMD_TYPE)
3691 #define	G_FW_IQ_CMD_TYPE(x)	(((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
3692 
3693 #define	S_FW_IQ_CMD_IQASYNCH	28
3694 #define	M_FW_IQ_CMD_IQASYNCH	0x1
3695 #define	V_FW_IQ_CMD_IQASYNCH(x)	((x) << S_FW_IQ_CMD_IQASYNCH)
3696 #define	G_FW_IQ_CMD_IQASYNCH(x)	\
3697 	(((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
3698 #define	F_FW_IQ_CMD_IQASYNCH	V_FW_IQ_CMD_IQASYNCH(1U)
3699 
3700 #define	S_FW_IQ_CMD_VIID	16
3701 #define	M_FW_IQ_CMD_VIID	0xfff
3702 #define	V_FW_IQ_CMD_VIID(x)	((x) << S_FW_IQ_CMD_VIID)
3703 #define	G_FW_IQ_CMD_VIID(x)	(((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
3704 
3705 #define	S_FW_IQ_CMD_IQANDST	15
3706 #define	M_FW_IQ_CMD_IQANDST	0x1
3707 #define	V_FW_IQ_CMD_IQANDST(x)	((x) << S_FW_IQ_CMD_IQANDST)
3708 #define	G_FW_IQ_CMD_IQANDST(x)	\
3709 	(((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
3710 #define	F_FW_IQ_CMD_IQANDST	V_FW_IQ_CMD_IQANDST(1U)
3711 
3712 #define	S_FW_IQ_CMD_IQANUS	14
3713 #define	M_FW_IQ_CMD_IQANUS	0x1
3714 #define	V_FW_IQ_CMD_IQANUS(x)	((x) << S_FW_IQ_CMD_IQANUS)
3715 #define	G_FW_IQ_CMD_IQANUS(x)	\
3716 	(((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
3717 #define	F_FW_IQ_CMD_IQANUS	V_FW_IQ_CMD_IQANUS(1U)
3718 
3719 #define	S_FW_IQ_CMD_IQANUD	12
3720 #define	M_FW_IQ_CMD_IQANUD	0x3
3721 #define	V_FW_IQ_CMD_IQANUD(x)	((x) << S_FW_IQ_CMD_IQANUD)
3722 #define	G_FW_IQ_CMD_IQANUD(x)	\
3723 	(((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
3724 
3725 #define	S_FW_IQ_CMD_IQANDSTINDEX	0
3726 #define	M_FW_IQ_CMD_IQANDSTINDEX	0xfff
3727 #define	V_FW_IQ_CMD_IQANDSTINDEX(x)	((x) << S_FW_IQ_CMD_IQANDSTINDEX)
3728 #define	G_FW_IQ_CMD_IQANDSTINDEX(x)	\
3729 	(((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
3730 
3731 #define	S_FW_IQ_CMD_IQDROPRSS		15
3732 #define	M_FW_IQ_CMD_IQDROPRSS		0x1
3733 #define	V_FW_IQ_CMD_IQDROPRSS(x)	((x) << S_FW_IQ_CMD_IQDROPRSS)
3734 #define	G_FW_IQ_CMD_IQDROPRSS(x)	\
3735 	(((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
3736 #define	F_FW_IQ_CMD_IQDROPRSS	V_FW_IQ_CMD_IQDROPRSS(1U)
3737 
3738 #define	S_FW_IQ_CMD_IQGTSMODE		14
3739 #define	M_FW_IQ_CMD_IQGTSMODE		0x1
3740 #define	V_FW_IQ_CMD_IQGTSMODE(x)	((x) << S_FW_IQ_CMD_IQGTSMODE)
3741 #define	G_FW_IQ_CMD_IQGTSMODE(x)	\
3742 	(((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
3743 #define	F_FW_IQ_CMD_IQGTSMODE	V_FW_IQ_CMD_IQGTSMODE(1U)
3744 
3745 #define	S_FW_IQ_CMD_IQPCIECH	12
3746 #define	M_FW_IQ_CMD_IQPCIECH	0x3
3747 #define	V_FW_IQ_CMD_IQPCIECH(x)	((x) << S_FW_IQ_CMD_IQPCIECH)
3748 #define	G_FW_IQ_CMD_IQPCIECH(x)	\
3749 	(((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
3750 
3751 #define	S_FW_IQ_CMD_IQDCAEN	11
3752 #define	M_FW_IQ_CMD_IQDCAEN	0x1
3753 #define	V_FW_IQ_CMD_IQDCAEN(x)	((x) << S_FW_IQ_CMD_IQDCAEN)
3754 #define	G_FW_IQ_CMD_IQDCAEN(x)	\
3755 	(((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
3756 #define	F_FW_IQ_CMD_IQDCAEN	V_FW_IQ_CMD_IQDCAEN(1U)
3757 
3758 #define	S_FW_IQ_CMD_IQDCACPU	6
3759 #define	M_FW_IQ_CMD_IQDCACPU	0x1f
3760 #define	V_FW_IQ_CMD_IQDCACPU(x)	((x) << S_FW_IQ_CMD_IQDCACPU)
3761 #define	G_FW_IQ_CMD_IQDCACPU(x)	\
3762 	(((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
3763 
3764 #define	S_FW_IQ_CMD_IQINTCNTTHRESH	4
3765 #define	M_FW_IQ_CMD_IQINTCNTTHRESH	0x3
3766 #define	V_FW_IQ_CMD_IQINTCNTTHRESH(x)	((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
3767 #define	G_FW_IQ_CMD_IQINTCNTTHRESH(x)	\
3768 	(((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
3769 
3770 #define	S_FW_IQ_CMD_IQO		3
3771 #define	M_FW_IQ_CMD_IQO		0x1
3772 #define	V_FW_IQ_CMD_IQO(x)	((x) << S_FW_IQ_CMD_IQO)
3773 #define	G_FW_IQ_CMD_IQO(x)	(((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
3774 #define	F_FW_IQ_CMD_IQO	V_FW_IQ_CMD_IQO(1U)
3775 
3776 #define	S_FW_IQ_CMD_IQCPRIO	2
3777 #define	M_FW_IQ_CMD_IQCPRIO	0x1
3778 #define	V_FW_IQ_CMD_IQCPRIO(x)	((x) << S_FW_IQ_CMD_IQCPRIO)
3779 #define	G_FW_IQ_CMD_IQCPRIO(x)	\
3780 	(((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
3781 #define	F_FW_IQ_CMD_IQCPRIO	V_FW_IQ_CMD_IQCPRIO(1U)
3782 
3783 #define	S_FW_IQ_CMD_IQESIZE	0
3784 #define	M_FW_IQ_CMD_IQESIZE	0x3
3785 #define	V_FW_IQ_CMD_IQESIZE(x)	((x) << S_FW_IQ_CMD_IQESIZE)
3786 #define	G_FW_IQ_CMD_IQESIZE(x)	\
3787 	(((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
3788 
3789 #define	S_FW_IQ_CMD_IQNS	31
3790 #define	M_FW_IQ_CMD_IQNS	0x1
3791 #define	V_FW_IQ_CMD_IQNS(x)	((x) << S_FW_IQ_CMD_IQNS)
3792 #define	G_FW_IQ_CMD_IQNS(x)	(((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
3793 #define	F_FW_IQ_CMD_IQNS	V_FW_IQ_CMD_IQNS(1U)
3794 
3795 #define	S_FW_IQ_CMD_IQRO	30
3796 #define	M_FW_IQ_CMD_IQRO	0x1
3797 #define	V_FW_IQ_CMD_IQRO(x)	((x) << S_FW_IQ_CMD_IQRO)
3798 #define	G_FW_IQ_CMD_IQRO(x)	(((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
3799 #define	F_FW_IQ_CMD_IQRO	V_FW_IQ_CMD_IQRO(1U)
3800 
3801 #define	S_FW_IQ_CMD_IQFLINTIQHSEN	28
3802 #define	M_FW_IQ_CMD_IQFLINTIQHSEN	0x3
3803 #define	V_FW_IQ_CMD_IQFLINTIQHSEN(x)	((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
3804 #define	G_FW_IQ_CMD_IQFLINTIQHSEN(x)	\
3805 	(((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
3806 
3807 #define	S_FW_IQ_CMD_IQFLINTCONGEN	27
3808 #define	M_FW_IQ_CMD_IQFLINTCONGEN	0x1
3809 #define	V_FW_IQ_CMD_IQFLINTCONGEN(x)	((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
3810 #define	G_FW_IQ_CMD_IQFLINTCONGEN(x)	\
3811 	(((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
3812 #define	F_FW_IQ_CMD_IQFLINTCONGEN	V_FW_IQ_CMD_IQFLINTCONGEN(1U)
3813 
3814 #define	S_FW_IQ_CMD_IQFLINTISCSIC	26
3815 #define	M_FW_IQ_CMD_IQFLINTISCSIC	0x1
3816 #define	V_FW_IQ_CMD_IQFLINTISCSIC(x)	((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
3817 #define	G_FW_IQ_CMD_IQFLINTISCSIC(x)	\
3818 	(((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
3819 #define	F_FW_IQ_CMD_IQFLINTISCSIC	V_FW_IQ_CMD_IQFLINTISCSIC(1U)
3820 
3821 #define	S_FW_IQ_CMD_FL0CNGCHMAP		20
3822 #define	M_FW_IQ_CMD_FL0CNGCHMAP		0xf
3823 #define	V_FW_IQ_CMD_FL0CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
3824 #define	G_FW_IQ_CMD_FL0CNGCHMAP(x)	\
3825 	(((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
3826 
3827 #define	S_FW_IQ_CMD_FL0CACHELOCK	15
3828 #define	M_FW_IQ_CMD_FL0CACHELOCK	0x1
3829 #define	V_FW_IQ_CMD_FL0CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL0CACHELOCK)
3830 #define	G_FW_IQ_CMD_FL0CACHELOCK(x)	\
3831 	(((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
3832 #define	F_FW_IQ_CMD_FL0CACHELOCK	V_FW_IQ_CMD_FL0CACHELOCK(1U)
3833 
3834 #define	S_FW_IQ_CMD_FL0DBP	14
3835 #define	M_FW_IQ_CMD_FL0DBP	0x1
3836 #define	V_FW_IQ_CMD_FL0DBP(x)	((x) << S_FW_IQ_CMD_FL0DBP)
3837 #define	G_FW_IQ_CMD_FL0DBP(x)	\
3838 	(((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
3839 #define	F_FW_IQ_CMD_FL0DBP	V_FW_IQ_CMD_FL0DBP(1U)
3840 
3841 #define	S_FW_IQ_CMD_FL0DATANS		13
3842 #define	M_FW_IQ_CMD_FL0DATANS		0x1
3843 #define	V_FW_IQ_CMD_FL0DATANS(x)	((x) << S_FW_IQ_CMD_FL0DATANS)
3844 #define	G_FW_IQ_CMD_FL0DATANS(x)	\
3845 	(((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
3846 #define	F_FW_IQ_CMD_FL0DATANS	V_FW_IQ_CMD_FL0DATANS(1U)
3847 
3848 #define	S_FW_IQ_CMD_FL0DATARO		12
3849 #define	M_FW_IQ_CMD_FL0DATARO		0x1
3850 #define	V_FW_IQ_CMD_FL0DATARO(x)	((x) << S_FW_IQ_CMD_FL0DATARO)
3851 #define	G_FW_IQ_CMD_FL0DATARO(x)	\
3852 	(((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
3853 #define	F_FW_IQ_CMD_FL0DATARO	V_FW_IQ_CMD_FL0DATARO(1U)
3854 
3855 #define	S_FW_IQ_CMD_FL0CONGCIF		11
3856 #define	M_FW_IQ_CMD_FL0CONGCIF		0x1
3857 #define	V_FW_IQ_CMD_FL0CONGCIF(x)	((x) << S_FW_IQ_CMD_FL0CONGCIF)
3858 #define	G_FW_IQ_CMD_FL0CONGCIF(x)	\
3859 	(((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
3860 #define	F_FW_IQ_CMD_FL0CONGCIF	V_FW_IQ_CMD_FL0CONGCIF(1U)
3861 
3862 #define	S_FW_IQ_CMD_FL0ONCHIP		10
3863 #define	M_FW_IQ_CMD_FL0ONCHIP		0x1
3864 #define	V_FW_IQ_CMD_FL0ONCHIP(x)	((x) << S_FW_IQ_CMD_FL0ONCHIP)
3865 #define	G_FW_IQ_CMD_FL0ONCHIP(x)	\
3866 	(((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
3867 #define	F_FW_IQ_CMD_FL0ONCHIP	V_FW_IQ_CMD_FL0ONCHIP(1U)
3868 
3869 #define	S_FW_IQ_CMD_FL0STATUSPGNS	9
3870 #define	M_FW_IQ_CMD_FL0STATUSPGNS	0x1
3871 #define	V_FW_IQ_CMD_FL0STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
3872 #define	G_FW_IQ_CMD_FL0STATUSPGNS(x)	\
3873 	(((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
3874 #define	F_FW_IQ_CMD_FL0STATUSPGNS	V_FW_IQ_CMD_FL0STATUSPGNS(1U)
3875 
3876 #define	S_FW_IQ_CMD_FL0STATUSPGRO	8
3877 #define	M_FW_IQ_CMD_FL0STATUSPGRO	0x1
3878 #define	V_FW_IQ_CMD_FL0STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
3879 #define	G_FW_IQ_CMD_FL0STATUSPGRO(x)	\
3880 	(((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
3881 #define	F_FW_IQ_CMD_FL0STATUSPGRO	V_FW_IQ_CMD_FL0STATUSPGRO(1U)
3882 
3883 #define	S_FW_IQ_CMD_FL0FETCHNS		7
3884 #define	M_FW_IQ_CMD_FL0FETCHNS		0x1
3885 #define	V_FW_IQ_CMD_FL0FETCHNS(x)	((x) << S_FW_IQ_CMD_FL0FETCHNS)
3886 #define	G_FW_IQ_CMD_FL0FETCHNS(x)	\
3887 	(((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
3888 #define	F_FW_IQ_CMD_FL0FETCHNS	V_FW_IQ_CMD_FL0FETCHNS(1U)
3889 
3890 #define	S_FW_IQ_CMD_FL0FETCHRO		6
3891 #define	M_FW_IQ_CMD_FL0FETCHRO		0x1
3892 #define	V_FW_IQ_CMD_FL0FETCHRO(x)	((x) << S_FW_IQ_CMD_FL0FETCHRO)
3893 #define	G_FW_IQ_CMD_FL0FETCHRO(x)	\
3894 	(((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
3895 #define	F_FW_IQ_CMD_FL0FETCHRO	V_FW_IQ_CMD_FL0FETCHRO(1U)
3896 
3897 #define	S_FW_IQ_CMD_FL0HOSTFCMODE	4
3898 #define	M_FW_IQ_CMD_FL0HOSTFCMODE	0x3
3899 #define	V_FW_IQ_CMD_FL0HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
3900 #define	G_FW_IQ_CMD_FL0HOSTFCMODE(x)	\
3901 	(((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
3902 
3903 #define	S_FW_IQ_CMD_FL0CPRIO	3
3904 #define	M_FW_IQ_CMD_FL0CPRIO	0x1
3905 #define	V_FW_IQ_CMD_FL0CPRIO(x)	((x) << S_FW_IQ_CMD_FL0CPRIO)
3906 #define	G_FW_IQ_CMD_FL0CPRIO(x)	\
3907 	(((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
3908 #define	F_FW_IQ_CMD_FL0CPRIO	V_FW_IQ_CMD_FL0CPRIO(1U)
3909 
3910 #define	S_FW_IQ_CMD_FL0PADEN	2
3911 #define	M_FW_IQ_CMD_FL0PADEN	0x1
3912 #define	V_FW_IQ_CMD_FL0PADEN(x)	((x) << S_FW_IQ_CMD_FL0PADEN)
3913 #define	G_FW_IQ_CMD_FL0PADEN(x)	\
3914 	(((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
3915 #define	F_FW_IQ_CMD_FL0PADEN	V_FW_IQ_CMD_FL0PADEN(1U)
3916 
3917 #define	S_FW_IQ_CMD_FL0PACKEN		1
3918 #define	M_FW_IQ_CMD_FL0PACKEN		0x1
3919 #define	V_FW_IQ_CMD_FL0PACKEN(x)	((x) << S_FW_IQ_CMD_FL0PACKEN)
3920 #define	G_FW_IQ_CMD_FL0PACKEN(x)	\
3921 	(((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
3922 #define	F_FW_IQ_CMD_FL0PACKEN	V_FW_IQ_CMD_FL0PACKEN(1U)
3923 
3924 #define	S_FW_IQ_CMD_FL0CONGEN		0
3925 #define	M_FW_IQ_CMD_FL0CONGEN		0x1
3926 #define	V_FW_IQ_CMD_FL0CONGEN(x)	((x) << S_FW_IQ_CMD_FL0CONGEN)
3927 #define	G_FW_IQ_CMD_FL0CONGEN(x)	\
3928 	(((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
3929 #define	F_FW_IQ_CMD_FL0CONGEN	V_FW_IQ_CMD_FL0CONGEN(1U)
3930 
3931 #define	S_FW_IQ_CMD_FL0DCAEN	15
3932 #define	M_FW_IQ_CMD_FL0DCAEN	0x1
3933 #define	V_FW_IQ_CMD_FL0DCAEN(x)	((x) << S_FW_IQ_CMD_FL0DCAEN)
3934 #define	G_FW_IQ_CMD_FL0DCAEN(x)	\
3935 	(((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
3936 #define	F_FW_IQ_CMD_FL0DCAEN	V_FW_IQ_CMD_FL0DCAEN(1U)
3937 
3938 #define	S_FW_IQ_CMD_FL0DCACPU		10
3939 #define	M_FW_IQ_CMD_FL0DCACPU		0x1f
3940 #define	V_FW_IQ_CMD_FL0DCACPU(x)	((x) << S_FW_IQ_CMD_FL0DCACPU)
3941 #define	G_FW_IQ_CMD_FL0DCACPU(x)	\
3942 	(((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
3943 
3944 #define	S_FW_IQ_CMD_FL0FBMIN	7
3945 #define	M_FW_IQ_CMD_FL0FBMIN	0x7
3946 #define	V_FW_IQ_CMD_FL0FBMIN(x)	((x) << S_FW_IQ_CMD_FL0FBMIN)
3947 #define	G_FW_IQ_CMD_FL0FBMIN(x)	\
3948 	(((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
3949 
3950 #define	S_FW_IQ_CMD_FL0FBMAX	4
3951 #define	M_FW_IQ_CMD_FL0FBMAX	0x7
3952 #define	V_FW_IQ_CMD_FL0FBMAX(x)	((x) << S_FW_IQ_CMD_FL0FBMAX)
3953 #define	G_FW_IQ_CMD_FL0FBMAX(x)	\
3954 	(((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
3955 
3956 #define	S_FW_IQ_CMD_FL0CIDXFTHRESHO	3
3957 #define	M_FW_IQ_CMD_FL0CIDXFTHRESHO	0x1
3958 #define	V_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
3959 #define	G_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	\
3960 	(((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
3961 #define	F_FW_IQ_CMD_FL0CIDXFTHRESHO	V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
3962 
3963 #define	S_FW_IQ_CMD_FL0CIDXFTHRESH	0
3964 #define	M_FW_IQ_CMD_FL0CIDXFTHRESH	0x7
3965 #define	V_FW_IQ_CMD_FL0CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
3966 #define	G_FW_IQ_CMD_FL0CIDXFTHRESH(x)	\
3967 	(((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
3968 
3969 #define	S_FW_IQ_CMD_FL1CNGCHMAP		20
3970 #define	M_FW_IQ_CMD_FL1CNGCHMAP		0xf
3971 #define	V_FW_IQ_CMD_FL1CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
3972 #define	G_FW_IQ_CMD_FL1CNGCHMAP(x)	\
3973 	(((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
3974 
3975 #define	S_FW_IQ_CMD_FL1CACHELOCK	15
3976 #define	M_FW_IQ_CMD_FL1CACHELOCK	0x1
3977 #define	V_FW_IQ_CMD_FL1CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL1CACHELOCK)
3978 #define	G_FW_IQ_CMD_FL1CACHELOCK(x)	\
3979 	(((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
3980 #define	F_FW_IQ_CMD_FL1CACHELOCK	V_FW_IQ_CMD_FL1CACHELOCK(1U)
3981 
3982 #define	S_FW_IQ_CMD_FL1DBP	14
3983 #define	M_FW_IQ_CMD_FL1DBP	0x1
3984 #define	V_FW_IQ_CMD_FL1DBP(x)	((x) << S_FW_IQ_CMD_FL1DBP)
3985 #define	G_FW_IQ_CMD_FL1DBP(x)	\
3986 	(((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
3987 #define	F_FW_IQ_CMD_FL1DBP	V_FW_IQ_CMD_FL1DBP(1U)
3988 
3989 #define	S_FW_IQ_CMD_FL1DATANS		13
3990 #define	M_FW_IQ_CMD_FL1DATANS		0x1
3991 #define	V_FW_IQ_CMD_FL1DATANS(x)	((x) << S_FW_IQ_CMD_FL1DATANS)
3992 #define	G_FW_IQ_CMD_FL1DATANS(x)	\
3993 	(((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
3994 #define	F_FW_IQ_CMD_FL1DATANS	V_FW_IQ_CMD_FL1DATANS(1U)
3995 
3996 #define	S_FW_IQ_CMD_FL1DATARO		12
3997 #define	M_FW_IQ_CMD_FL1DATARO		0x1
3998 #define	V_FW_IQ_CMD_FL1DATARO(x)	((x) << S_FW_IQ_CMD_FL1DATARO)
3999 #define	G_FW_IQ_CMD_FL1DATARO(x)	\
4000 	(((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
4001 #define	F_FW_IQ_CMD_FL1DATARO	V_FW_IQ_CMD_FL1DATARO(1U)
4002 
4003 #define	S_FW_IQ_CMD_FL1CONGCIF		11
4004 #define	M_FW_IQ_CMD_FL1CONGCIF		0x1
4005 #define	V_FW_IQ_CMD_FL1CONGCIF(x)	((x) << S_FW_IQ_CMD_FL1CONGCIF)
4006 #define	G_FW_IQ_CMD_FL1CONGCIF(x)	\
4007 	(((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
4008 #define	F_FW_IQ_CMD_FL1CONGCIF	V_FW_IQ_CMD_FL1CONGCIF(1U)
4009 
4010 #define	S_FW_IQ_CMD_FL1ONCHIP		10
4011 #define	M_FW_IQ_CMD_FL1ONCHIP		0x1
4012 #define	V_FW_IQ_CMD_FL1ONCHIP(x)	((x) << S_FW_IQ_CMD_FL1ONCHIP)
4013 #define	G_FW_IQ_CMD_FL1ONCHIP(x)	\
4014 	(((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
4015 #define	F_FW_IQ_CMD_FL1ONCHIP	V_FW_IQ_CMD_FL1ONCHIP(1U)
4016 
4017 #define	S_FW_IQ_CMD_FL1STATUSPGNS	9
4018 #define	M_FW_IQ_CMD_FL1STATUSPGNS	0x1
4019 #define	V_FW_IQ_CMD_FL1STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
4020 #define	G_FW_IQ_CMD_FL1STATUSPGNS(x)	\
4021 	(((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
4022 #define	F_FW_IQ_CMD_FL1STATUSPGNS	V_FW_IQ_CMD_FL1STATUSPGNS(1U)
4023 
4024 #define	S_FW_IQ_CMD_FL1STATUSPGRO	8
4025 #define	M_FW_IQ_CMD_FL1STATUSPGRO	0x1
4026 #define	V_FW_IQ_CMD_FL1STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
4027 #define	G_FW_IQ_CMD_FL1STATUSPGRO(x)	\
4028 	(((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
4029 #define	F_FW_IQ_CMD_FL1STATUSPGRO	V_FW_IQ_CMD_FL1STATUSPGRO(1U)
4030 
4031 #define	S_FW_IQ_CMD_FL1FETCHNS		7
4032 #define	M_FW_IQ_CMD_FL1FETCHNS		0x1
4033 #define	V_FW_IQ_CMD_FL1FETCHNS(x)	((x) << S_FW_IQ_CMD_FL1FETCHNS)
4034 #define	G_FW_IQ_CMD_FL1FETCHNS(x)	\
4035 	(((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
4036 #define	F_FW_IQ_CMD_FL1FETCHNS	V_FW_IQ_CMD_FL1FETCHNS(1U)
4037 
4038 #define	S_FW_IQ_CMD_FL1FETCHRO		6
4039 #define	M_FW_IQ_CMD_FL1FETCHRO		0x1
4040 #define	V_FW_IQ_CMD_FL1FETCHRO(x)	((x) << S_FW_IQ_CMD_FL1FETCHRO)
4041 #define	G_FW_IQ_CMD_FL1FETCHRO(x)	\
4042 	(((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
4043 #define	F_FW_IQ_CMD_FL1FETCHRO	V_FW_IQ_CMD_FL1FETCHRO(1U)
4044 
4045 #define	S_FW_IQ_CMD_FL1HOSTFCMODE	4
4046 #define	M_FW_IQ_CMD_FL1HOSTFCMODE	0x3
4047 #define	V_FW_IQ_CMD_FL1HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
4048 #define	G_FW_IQ_CMD_FL1HOSTFCMODE(x)	\
4049 	(((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
4050 
4051 #define	S_FW_IQ_CMD_FL1CPRIO	3
4052 #define	M_FW_IQ_CMD_FL1CPRIO	0x1
4053 #define	V_FW_IQ_CMD_FL1CPRIO(x)	((x) << S_FW_IQ_CMD_FL1CPRIO)
4054 #define	G_FW_IQ_CMD_FL1CPRIO(x)	\
4055 	(((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
4056 #define	F_FW_IQ_CMD_FL1CPRIO	V_FW_IQ_CMD_FL1CPRIO(1U)
4057 
4058 #define	S_FW_IQ_CMD_FL1PADEN	2
4059 #define	M_FW_IQ_CMD_FL1PADEN	0x1
4060 #define	V_FW_IQ_CMD_FL1PADEN(x)	((x) << S_FW_IQ_CMD_FL1PADEN)
4061 #define	G_FW_IQ_CMD_FL1PADEN(x)	\
4062 	(((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
4063 #define	F_FW_IQ_CMD_FL1PADEN	V_FW_IQ_CMD_FL1PADEN(1U)
4064 
4065 #define	S_FW_IQ_CMD_FL1PACKEN		1
4066 #define	M_FW_IQ_CMD_FL1PACKEN		0x1
4067 #define	V_FW_IQ_CMD_FL1PACKEN(x)	((x) << S_FW_IQ_CMD_FL1PACKEN)
4068 #define	G_FW_IQ_CMD_FL1PACKEN(x)	\
4069 	(((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
4070 #define	F_FW_IQ_CMD_FL1PACKEN	V_FW_IQ_CMD_FL1PACKEN(1U)
4071 
4072 #define	S_FW_IQ_CMD_FL1CONGEN		0
4073 #define	M_FW_IQ_CMD_FL1CONGEN		0x1
4074 #define	V_FW_IQ_CMD_FL1CONGEN(x)	((x) << S_FW_IQ_CMD_FL1CONGEN)
4075 #define	G_FW_IQ_CMD_FL1CONGEN(x)	\
4076 	(((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
4077 #define	F_FW_IQ_CMD_FL1CONGEN	V_FW_IQ_CMD_FL1CONGEN(1U)
4078 
4079 #define	S_FW_IQ_CMD_FL1DCAEN	15
4080 #define	M_FW_IQ_CMD_FL1DCAEN	0x1
4081 #define	V_FW_IQ_CMD_FL1DCAEN(x)	((x) << S_FW_IQ_CMD_FL1DCAEN)
4082 #define	G_FW_IQ_CMD_FL1DCAEN(x)	\
4083 	(((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
4084 #define	F_FW_IQ_CMD_FL1DCAEN	V_FW_IQ_CMD_FL1DCAEN(1U)
4085 
4086 #define	S_FW_IQ_CMD_FL1DCACPU		10
4087 #define	M_FW_IQ_CMD_FL1DCACPU		0x1f
4088 #define	V_FW_IQ_CMD_FL1DCACPU(x)	((x) << S_FW_IQ_CMD_FL1DCACPU)
4089 #define	G_FW_IQ_CMD_FL1DCACPU(x)	\
4090 	(((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
4091 
4092 #define	S_FW_IQ_CMD_FL1FBMIN	7
4093 #define	M_FW_IQ_CMD_FL1FBMIN	0x7
4094 #define	V_FW_IQ_CMD_FL1FBMIN(x)	((x) << S_FW_IQ_CMD_FL1FBMIN)
4095 #define	G_FW_IQ_CMD_FL1FBMIN(x)	\
4096 	(((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
4097 
4098 #define	S_FW_IQ_CMD_FL1FBMAX	4
4099 #define	M_FW_IQ_CMD_FL1FBMAX	0x7
4100 #define	V_FW_IQ_CMD_FL1FBMAX(x)	((x) << S_FW_IQ_CMD_FL1FBMAX)
4101 #define	G_FW_IQ_CMD_FL1FBMAX(x)	\
4102 	(((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
4103 
4104 #define	S_FW_IQ_CMD_FL1CIDXFTHRESHO	3
4105 #define	M_FW_IQ_CMD_FL1CIDXFTHRESHO	0x1
4106 #define	V_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
4107 #define	G_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	\
4108 	(((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
4109 #define	F_FW_IQ_CMD_FL1CIDXFTHRESHO	V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
4110 
4111 #define	S_FW_IQ_CMD_FL1CIDXFTHRESH	0
4112 #define	M_FW_IQ_CMD_FL1CIDXFTHRESH	0x7
4113 #define	V_FW_IQ_CMD_FL1CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
4114 #define	G_FW_IQ_CMD_FL1CIDXFTHRESH(x)	\
4115 	(((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
4116 
4117 struct fw_eq_mngt_cmd {
4118 	__be32 op_to_vfn;
4119 	__be32 alloc_to_len16;
4120 	__be32 cmpliqid_eqid;
4121 	__be32 physeqid_pkd;
4122 	__be32 fetchszm_to_iqid;
4123 	__be32 dcaen_to_eqsize;
4124 	__be64 eqaddr;
4125 };
4126 
4127 #define	S_FW_EQ_MNGT_CMD_PFN	8
4128 #define	M_FW_EQ_MNGT_CMD_PFN	0x7
4129 #define	V_FW_EQ_MNGT_CMD_PFN(x)	((x) << S_FW_EQ_MNGT_CMD_PFN)
4130 #define	G_FW_EQ_MNGT_CMD_PFN(x)	\
4131 	(((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
4132 
4133 #define	S_FW_EQ_MNGT_CMD_VFN	0
4134 #define	M_FW_EQ_MNGT_CMD_VFN	0xff
4135 #define	V_FW_EQ_MNGT_CMD_VFN(x)	((x) << S_FW_EQ_MNGT_CMD_VFN)
4136 #define	G_FW_EQ_MNGT_CMD_VFN(x)	\
4137 	(((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
4138 
4139 #define	S_FW_EQ_MNGT_CMD_ALLOC		31
4140 #define	M_FW_EQ_MNGT_CMD_ALLOC		0x1
4141 #define	V_FW_EQ_MNGT_CMD_ALLOC(x)	((x) << S_FW_EQ_MNGT_CMD_ALLOC)
4142 #define	G_FW_EQ_MNGT_CMD_ALLOC(x)	\
4143 	(((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
4144 #define	F_FW_EQ_MNGT_CMD_ALLOC	V_FW_EQ_MNGT_CMD_ALLOC(1U)
4145 
4146 #define	S_FW_EQ_MNGT_CMD_FREE		30
4147 #define	M_FW_EQ_MNGT_CMD_FREE		0x1
4148 #define	V_FW_EQ_MNGT_CMD_FREE(x)	((x) << S_FW_EQ_MNGT_CMD_FREE)
4149 #define	G_FW_EQ_MNGT_CMD_FREE(x)	\
4150 	(((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
4151 #define	F_FW_EQ_MNGT_CMD_FREE	V_FW_EQ_MNGT_CMD_FREE(1U)
4152 
4153 #define	S_FW_EQ_MNGT_CMD_MODIFY		29
4154 #define	M_FW_EQ_MNGT_CMD_MODIFY		0x1
4155 #define	V_FW_EQ_MNGT_CMD_MODIFY(x)	((x) << S_FW_EQ_MNGT_CMD_MODIFY)
4156 #define	G_FW_EQ_MNGT_CMD_MODIFY(x)	\
4157 	(((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
4158 #define	F_FW_EQ_MNGT_CMD_MODIFY	V_FW_EQ_MNGT_CMD_MODIFY(1U)
4159 
4160 #define	S_FW_EQ_MNGT_CMD_EQSTART	28
4161 #define	M_FW_EQ_MNGT_CMD_EQSTART	0x1
4162 #define	V_FW_EQ_MNGT_CMD_EQSTART(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTART)
4163 #define	G_FW_EQ_MNGT_CMD_EQSTART(x)	\
4164 	(((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
4165 #define	F_FW_EQ_MNGT_CMD_EQSTART	V_FW_EQ_MNGT_CMD_EQSTART(1U)
4166 
4167 #define	S_FW_EQ_MNGT_CMD_EQSTOP		27
4168 #define	M_FW_EQ_MNGT_CMD_EQSTOP		0x1
4169 #define	V_FW_EQ_MNGT_CMD_EQSTOP(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
4170 #define	G_FW_EQ_MNGT_CMD_EQSTOP(x)	\
4171 	(((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
4172 #define	F_FW_EQ_MNGT_CMD_EQSTOP	V_FW_EQ_MNGT_CMD_EQSTOP(1U)
4173 
4174 #define	S_FW_EQ_MNGT_CMD_CMPLIQID	20
4175 #define	M_FW_EQ_MNGT_CMD_CMPLIQID	0xfff
4176 #define	V_FW_EQ_MNGT_CMD_CMPLIQID(x)	((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
4177 #define	G_FW_EQ_MNGT_CMD_CMPLIQID(x)	\
4178 	(((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
4179 
4180 #define	S_FW_EQ_MNGT_CMD_EQID		0
4181 #define	M_FW_EQ_MNGT_CMD_EQID		0xfffff
4182 #define	V_FW_EQ_MNGT_CMD_EQID(x)	((x) << S_FW_EQ_MNGT_CMD_EQID)
4183 #define	G_FW_EQ_MNGT_CMD_EQID(x)	\
4184 	(((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
4185 
4186 #define	S_FW_EQ_MNGT_CMD_PHYSEQID	0
4187 #define	M_FW_EQ_MNGT_CMD_PHYSEQID	0xfffff
4188 #define	V_FW_EQ_MNGT_CMD_PHYSEQID(x)	((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
4189 #define	G_FW_EQ_MNGT_CMD_PHYSEQID(x)	\
4190 	(((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
4191 
4192 #define	S_FW_EQ_MNGT_CMD_FETCHSZM	26
4193 #define	M_FW_EQ_MNGT_CMD_FETCHSZM	0x1
4194 #define	V_FW_EQ_MNGT_CMD_FETCHSZM(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
4195 #define	G_FW_EQ_MNGT_CMD_FETCHSZM(x)	\
4196 	(((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
4197 #define	F_FW_EQ_MNGT_CMD_FETCHSZM	V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
4198 
4199 #define	S_FW_EQ_MNGT_CMD_STATUSPGNS	25
4200 #define	M_FW_EQ_MNGT_CMD_STATUSPGNS	0x1
4201 #define	V_FW_EQ_MNGT_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
4202 #define	G_FW_EQ_MNGT_CMD_STATUSPGNS(x)	\
4203 	(((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
4204 #define	F_FW_EQ_MNGT_CMD_STATUSPGNS	V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
4205 
4206 #define	S_FW_EQ_MNGT_CMD_STATUSPGRO	24
4207 #define	M_FW_EQ_MNGT_CMD_STATUSPGRO	0x1
4208 #define	V_FW_EQ_MNGT_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
4209 #define	G_FW_EQ_MNGT_CMD_STATUSPGRO(x)	\
4210 	(((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
4211 #define	F_FW_EQ_MNGT_CMD_STATUSPGRO	V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
4212 
4213 #define	S_FW_EQ_MNGT_CMD_FETCHNS	23
4214 #define	M_FW_EQ_MNGT_CMD_FETCHNS	0x1
4215 #define	V_FW_EQ_MNGT_CMD_FETCHNS(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
4216 #define	G_FW_EQ_MNGT_CMD_FETCHNS(x)	\
4217 	(((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
4218 #define	F_FW_EQ_MNGT_CMD_FETCHNS	V_FW_EQ_MNGT_CMD_FETCHNS(1U)
4219 
4220 #define	S_FW_EQ_MNGT_CMD_FETCHRO	22
4221 #define	M_FW_EQ_MNGT_CMD_FETCHRO	0x1
4222 #define	V_FW_EQ_MNGT_CMD_FETCHRO(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
4223 #define	G_FW_EQ_MNGT_CMD_FETCHRO(x)	\
4224 	(((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
4225 #define	F_FW_EQ_MNGT_CMD_FETCHRO	V_FW_EQ_MNGT_CMD_FETCHRO(1U)
4226 
4227 #define	S_FW_EQ_MNGT_CMD_HOSTFCMODE	20
4228 #define	M_FW_EQ_MNGT_CMD_HOSTFCMODE	0x3
4229 #define	V_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
4230 #define	G_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	\
4231 	(((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
4232 
4233 #define	S_FW_EQ_MNGT_CMD_CPRIO		19
4234 #define	M_FW_EQ_MNGT_CMD_CPRIO		0x1
4235 #define	V_FW_EQ_MNGT_CMD_CPRIO(x)	((x) << S_FW_EQ_MNGT_CMD_CPRIO)
4236 #define	G_FW_EQ_MNGT_CMD_CPRIO(x)	\
4237 	(((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
4238 #define	F_FW_EQ_MNGT_CMD_CPRIO	V_FW_EQ_MNGT_CMD_CPRIO(1U)
4239 
4240 #define	S_FW_EQ_MNGT_CMD_ONCHIP		18
4241 #define	M_FW_EQ_MNGT_CMD_ONCHIP		0x1
4242 #define	V_FW_EQ_MNGT_CMD_ONCHIP(x)	((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
4243 #define	G_FW_EQ_MNGT_CMD_ONCHIP(x)	\
4244 	(((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
4245 #define	F_FW_EQ_MNGT_CMD_ONCHIP	V_FW_EQ_MNGT_CMD_ONCHIP(1U)
4246 
4247 #define	S_FW_EQ_MNGT_CMD_PCIECHN	16
4248 #define	M_FW_EQ_MNGT_CMD_PCIECHN	0x3
4249 #define	V_FW_EQ_MNGT_CMD_PCIECHN(x)	((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
4250 #define	G_FW_EQ_MNGT_CMD_PCIECHN(x)	\
4251 	(((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
4252 
4253 #define	S_FW_EQ_MNGT_CMD_IQID		0
4254 #define	M_FW_EQ_MNGT_CMD_IQID		0xffff
4255 #define	V_FW_EQ_MNGT_CMD_IQID(x)	((x) << S_FW_EQ_MNGT_CMD_IQID)
4256 #define	G_FW_EQ_MNGT_CMD_IQID(x)	\
4257 	(((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
4258 
4259 #define	S_FW_EQ_MNGT_CMD_DCAEN		31
4260 #define	M_FW_EQ_MNGT_CMD_DCAEN		0x1
4261 #define	V_FW_EQ_MNGT_CMD_DCAEN(x)	((x) << S_FW_EQ_MNGT_CMD_DCAEN)
4262 #define	G_FW_EQ_MNGT_CMD_DCAEN(x)	\
4263 	(((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
4264 #define	F_FW_EQ_MNGT_CMD_DCAEN	V_FW_EQ_MNGT_CMD_DCAEN(1U)
4265 
4266 #define	S_FW_EQ_MNGT_CMD_DCACPU		26
4267 #define	M_FW_EQ_MNGT_CMD_DCACPU		0x1f
4268 #define	V_FW_EQ_MNGT_CMD_DCACPU(x)	((x) << S_FW_EQ_MNGT_CMD_DCACPU)
4269 #define	G_FW_EQ_MNGT_CMD_DCACPU(x)	\
4270 	(((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
4271 
4272 #define	S_FW_EQ_MNGT_CMD_FBMIN		23
4273 #define	M_FW_EQ_MNGT_CMD_FBMIN		0x7
4274 #define	V_FW_EQ_MNGT_CMD_FBMIN(x)	((x) << S_FW_EQ_MNGT_CMD_FBMIN)
4275 #define	G_FW_EQ_MNGT_CMD_FBMIN(x)	\
4276 	(((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
4277 
4278 #define	S_FW_EQ_MNGT_CMD_FBMAX		20
4279 #define	M_FW_EQ_MNGT_CMD_FBMAX		0x7
4280 #define	V_FW_EQ_MNGT_CMD_FBMAX(x)	((x) << S_FW_EQ_MNGT_CMD_FBMAX)
4281 #define	G_FW_EQ_MNGT_CMD_FBMAX(x)	\
4282 	(((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
4283 
4284 #define	S_FW_EQ_MNGT_CMD_CIDXFTHRESHO		19
4285 #define	M_FW_EQ_MNGT_CMD_CIDXFTHRESHO		0x1
4286 #define	V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x)	\
4287 	((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
4288 #define	G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x)	\
4289 	(((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
4290 #define	F_FW_EQ_MNGT_CMD_CIDXFTHRESHO	V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
4291 
4292 #define	S_FW_EQ_MNGT_CMD_CIDXFTHRESH	16
4293 #define	M_FW_EQ_MNGT_CMD_CIDXFTHRESH	0x7
4294 #define	V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
4295 #define	G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	\
4296 	(((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
4297 
4298 #define	S_FW_EQ_MNGT_CMD_EQSIZE		0
4299 #define	M_FW_EQ_MNGT_CMD_EQSIZE		0xffff
4300 #define	V_FW_EQ_MNGT_CMD_EQSIZE(x)	((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
4301 #define	G_FW_EQ_MNGT_CMD_EQSIZE(x)	\
4302 	(((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
4303 
4304 struct fw_eq_eth_cmd {
4305 	__be32 op_to_vfn;
4306 	__be32 alloc_to_len16;
4307 	__be32 eqid_pkd;
4308 	__be32 physeqid_pkd;
4309 	__be32 fetchszm_to_iqid;
4310 	__be32 dcaen_to_eqsize;
4311 	__be64 eqaddr;
4312 	__be32 viid_pkd;
4313 	__be32 r8_lo;
4314 	__be64 r9;
4315 };
4316 
4317 #define	S_FW_EQ_ETH_CMD_PFN	8
4318 #define	M_FW_EQ_ETH_CMD_PFN	0x7
4319 #define	V_FW_EQ_ETH_CMD_PFN(x)	((x) << S_FW_EQ_ETH_CMD_PFN)
4320 #define	G_FW_EQ_ETH_CMD_PFN(x)	\
4321 	(((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
4322 
4323 #define	S_FW_EQ_ETH_CMD_VFN	0
4324 #define	M_FW_EQ_ETH_CMD_VFN	0xff
4325 #define	V_FW_EQ_ETH_CMD_VFN(x)	((x) << S_FW_EQ_ETH_CMD_VFN)
4326 #define	G_FW_EQ_ETH_CMD_VFN(x)	\
4327 	(((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
4328 
4329 #define	S_FW_EQ_ETH_CMD_ALLOC		31
4330 #define	M_FW_EQ_ETH_CMD_ALLOC		0x1
4331 #define	V_FW_EQ_ETH_CMD_ALLOC(x)	((x) << S_FW_EQ_ETH_CMD_ALLOC)
4332 #define	G_FW_EQ_ETH_CMD_ALLOC(x)	\
4333 	(((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
4334 #define	F_FW_EQ_ETH_CMD_ALLOC	V_FW_EQ_ETH_CMD_ALLOC(1U)
4335 
4336 #define	S_FW_EQ_ETH_CMD_FREE	30
4337 #define	M_FW_EQ_ETH_CMD_FREE	0x1
4338 #define	V_FW_EQ_ETH_CMD_FREE(x)	((x) << S_FW_EQ_ETH_CMD_FREE)
4339 #define	G_FW_EQ_ETH_CMD_FREE(x)	\
4340 	(((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
4341 #define	F_FW_EQ_ETH_CMD_FREE	V_FW_EQ_ETH_CMD_FREE(1U)
4342 
4343 #define	S_FW_EQ_ETH_CMD_MODIFY		29
4344 #define	M_FW_EQ_ETH_CMD_MODIFY		0x1
4345 #define	V_FW_EQ_ETH_CMD_MODIFY(x)	((x) << S_FW_EQ_ETH_CMD_MODIFY)
4346 #define	G_FW_EQ_ETH_CMD_MODIFY(x)	\
4347 	(((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
4348 #define	F_FW_EQ_ETH_CMD_MODIFY	V_FW_EQ_ETH_CMD_MODIFY(1U)
4349 
4350 #define	S_FW_EQ_ETH_CMD_EQSTART		28
4351 #define	M_FW_EQ_ETH_CMD_EQSTART		0x1
4352 #define	V_FW_EQ_ETH_CMD_EQSTART(x)	((x) << S_FW_EQ_ETH_CMD_EQSTART)
4353 #define	G_FW_EQ_ETH_CMD_EQSTART(x)	\
4354 	(((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
4355 #define	F_FW_EQ_ETH_CMD_EQSTART	V_FW_EQ_ETH_CMD_EQSTART(1U)
4356 
4357 #define	S_FW_EQ_ETH_CMD_EQSTOP		27
4358 #define	M_FW_EQ_ETH_CMD_EQSTOP		0x1
4359 #define	V_FW_EQ_ETH_CMD_EQSTOP(x)	((x) << S_FW_EQ_ETH_CMD_EQSTOP)
4360 #define	G_FW_EQ_ETH_CMD_EQSTOP(x)	\
4361 	(((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
4362 #define	F_FW_EQ_ETH_CMD_EQSTOP	V_FW_EQ_ETH_CMD_EQSTOP(1U)
4363 
4364 #define	S_FW_EQ_ETH_CMD_EQID	0
4365 #define	M_FW_EQ_ETH_CMD_EQID	0xfffff
4366 #define	V_FW_EQ_ETH_CMD_EQID(x)	((x) << S_FW_EQ_ETH_CMD_EQID)
4367 #define	G_FW_EQ_ETH_CMD_EQID(x)	\
4368 	(((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
4369 
4370 #define	S_FW_EQ_ETH_CMD_PHYSEQID	0
4371 #define	M_FW_EQ_ETH_CMD_PHYSEQID	0xfffff
4372 #define	V_FW_EQ_ETH_CMD_PHYSEQID(x)	((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
4373 #define	G_FW_EQ_ETH_CMD_PHYSEQID(x)	\
4374 	(((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
4375 
4376 #define	S_FW_EQ_ETH_CMD_FETCHSZM	26
4377 #define	M_FW_EQ_ETH_CMD_FETCHSZM	0x1
4378 #define	V_FW_EQ_ETH_CMD_FETCHSZM(x)	((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
4379 #define	G_FW_EQ_ETH_CMD_FETCHSZM(x)	\
4380 	(((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
4381 #define	F_FW_EQ_ETH_CMD_FETCHSZM	V_FW_EQ_ETH_CMD_FETCHSZM(1U)
4382 
4383 #define	S_FW_EQ_ETH_CMD_STATUSPGNS	25
4384 #define	M_FW_EQ_ETH_CMD_STATUSPGNS	0x1
4385 #define	V_FW_EQ_ETH_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
4386 #define	G_FW_EQ_ETH_CMD_STATUSPGNS(x)	\
4387 	(((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
4388 #define	F_FW_EQ_ETH_CMD_STATUSPGNS	V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
4389 
4390 #define	S_FW_EQ_ETH_CMD_STATUSPGRO	24
4391 #define	M_FW_EQ_ETH_CMD_STATUSPGRO	0x1
4392 #define	V_FW_EQ_ETH_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
4393 #define	G_FW_EQ_ETH_CMD_STATUSPGRO(x)	\
4394 	(((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
4395 #define	F_FW_EQ_ETH_CMD_STATUSPGRO	V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
4396 
4397 #define	S_FW_EQ_ETH_CMD_FETCHNS		23
4398 #define	M_FW_EQ_ETH_CMD_FETCHNS		0x1
4399 #define	V_FW_EQ_ETH_CMD_FETCHNS(x)	((x) << S_FW_EQ_ETH_CMD_FETCHNS)
4400 #define	G_FW_EQ_ETH_CMD_FETCHNS(x)	\
4401 	(((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
4402 #define	F_FW_EQ_ETH_CMD_FETCHNS	V_FW_EQ_ETH_CMD_FETCHNS(1U)
4403 
4404 #define	S_FW_EQ_ETH_CMD_FETCHRO		22
4405 #define	M_FW_EQ_ETH_CMD_FETCHRO		0x1
4406 #define	V_FW_EQ_ETH_CMD_FETCHRO(x)	((x) << S_FW_EQ_ETH_CMD_FETCHRO)
4407 #define	G_FW_EQ_ETH_CMD_FETCHRO(x)	\
4408 	(((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
4409 #define	F_FW_EQ_ETH_CMD_FETCHRO	V_FW_EQ_ETH_CMD_FETCHRO(1U)
4410 
4411 #define	S_FW_EQ_ETH_CMD_HOSTFCMODE	20
4412 #define	M_FW_EQ_ETH_CMD_HOSTFCMODE	0x3
4413 #define	V_FW_EQ_ETH_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
4414 #define	G_FW_EQ_ETH_CMD_HOSTFCMODE(x)	\
4415 	(((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
4416 
4417 #define	S_FW_EQ_ETH_CMD_CPRIO		19
4418 #define	M_FW_EQ_ETH_CMD_CPRIO		0x1
4419 #define	V_FW_EQ_ETH_CMD_CPRIO(x)	((x) << S_FW_EQ_ETH_CMD_CPRIO)
4420 #define	G_FW_EQ_ETH_CMD_CPRIO(x)	\
4421 	(((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
4422 #define	F_FW_EQ_ETH_CMD_CPRIO	V_FW_EQ_ETH_CMD_CPRIO(1U)
4423 
4424 #define	S_FW_EQ_ETH_CMD_ONCHIP		18
4425 #define	M_FW_EQ_ETH_CMD_ONCHIP		0x1
4426 #define	V_FW_EQ_ETH_CMD_ONCHIP(x)	((x) << S_FW_EQ_ETH_CMD_ONCHIP)
4427 #define	G_FW_EQ_ETH_CMD_ONCHIP(x)	\
4428 	(((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
4429 #define	F_FW_EQ_ETH_CMD_ONCHIP	V_FW_EQ_ETH_CMD_ONCHIP(1U)
4430 
4431 #define	S_FW_EQ_ETH_CMD_PCIECHN		16
4432 #define	M_FW_EQ_ETH_CMD_PCIECHN		0x3
4433 #define	V_FW_EQ_ETH_CMD_PCIECHN(x)	((x) << S_FW_EQ_ETH_CMD_PCIECHN)
4434 #define	G_FW_EQ_ETH_CMD_PCIECHN(x)	\
4435 	(((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
4436 
4437 #define	S_FW_EQ_ETH_CMD_IQID	0
4438 #define	M_FW_EQ_ETH_CMD_IQID	0xffff
4439 #define	V_FW_EQ_ETH_CMD_IQID(x)	((x) << S_FW_EQ_ETH_CMD_IQID)
4440 #define	G_FW_EQ_ETH_CMD_IQID(x)	\
4441 	(((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
4442 
4443 #define	S_FW_EQ_ETH_CMD_DCAEN		31
4444 #define	M_FW_EQ_ETH_CMD_DCAEN		0x1
4445 #define	V_FW_EQ_ETH_CMD_DCAEN(x)	((x) << S_FW_EQ_ETH_CMD_DCAEN)
4446 #define	G_FW_EQ_ETH_CMD_DCAEN(x)	\
4447 	(((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
4448 #define	F_FW_EQ_ETH_CMD_DCAEN	V_FW_EQ_ETH_CMD_DCAEN(1U)
4449 
4450 #define	S_FW_EQ_ETH_CMD_DCACPU		26
4451 #define	M_FW_EQ_ETH_CMD_DCACPU		0x1f
4452 #define	V_FW_EQ_ETH_CMD_DCACPU(x)	((x) << S_FW_EQ_ETH_CMD_DCACPU)
4453 #define	G_FW_EQ_ETH_CMD_DCACPU(x)	\
4454 	(((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
4455 
4456 #define	S_FW_EQ_ETH_CMD_FBMIN		23
4457 #define	M_FW_EQ_ETH_CMD_FBMIN		0x7
4458 #define	V_FW_EQ_ETH_CMD_FBMIN(x)	((x) << S_FW_EQ_ETH_CMD_FBMIN)
4459 #define	G_FW_EQ_ETH_CMD_FBMIN(x)	\
4460 	(((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
4461 
4462 #define	S_FW_EQ_ETH_CMD_FBMAX		20
4463 #define	M_FW_EQ_ETH_CMD_FBMAX		0x7
4464 #define	V_FW_EQ_ETH_CMD_FBMAX(x)	((x) << S_FW_EQ_ETH_CMD_FBMAX)
4465 #define	G_FW_EQ_ETH_CMD_FBMAX(x)	\
4466 	(((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
4467 
4468 #define	S_FW_EQ_ETH_CMD_CIDXFTHRESHO	19
4469 #define	M_FW_EQ_ETH_CMD_CIDXFTHRESHO	0x1
4470 #define	V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
4471 #define	G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	\
4472 	(((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
4473 #define	F_FW_EQ_ETH_CMD_CIDXFTHRESHO	V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
4474 
4475 #define	S_FW_EQ_ETH_CMD_CIDXFTHRESH	16
4476 #define	M_FW_EQ_ETH_CMD_CIDXFTHRESH	0x7
4477 #define	V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
4478 #define	G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	\
4479 	(((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
4480 
4481 #define	S_FW_EQ_ETH_CMD_EQSIZE		0
4482 #define	M_FW_EQ_ETH_CMD_EQSIZE		0xffff
4483 #define	V_FW_EQ_ETH_CMD_EQSIZE(x)	((x) << S_FW_EQ_ETH_CMD_EQSIZE)
4484 #define	G_FW_EQ_ETH_CMD_EQSIZE(x)	\
4485 	(((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
4486 
4487 #define	S_FW_EQ_ETH_CMD_VIID	16
4488 #define	M_FW_EQ_ETH_CMD_VIID	0xfff
4489 #define	V_FW_EQ_ETH_CMD_VIID(x)	((x) << S_FW_EQ_ETH_CMD_VIID)
4490 #define	G_FW_EQ_ETH_CMD_VIID(x)	\
4491 	(((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
4492 
4493 struct fw_eq_ctrl_cmd {
4494 	__be32 op_to_vfn;
4495 	__be32 alloc_to_len16;
4496 	__be32 cmpliqid_eqid;
4497 	__be32 physeqid_pkd;
4498 	__be32 fetchszm_to_iqid;
4499 	__be32 dcaen_to_eqsize;
4500 	__be64 eqaddr;
4501 };
4502 
4503 #define	S_FW_EQ_CTRL_CMD_PFN	8
4504 #define	M_FW_EQ_CTRL_CMD_PFN	0x7
4505 #define	V_FW_EQ_CTRL_CMD_PFN(x)	((x) << S_FW_EQ_CTRL_CMD_PFN)
4506 #define	G_FW_EQ_CTRL_CMD_PFN(x)	\
4507 	(((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
4508 
4509 #define	S_FW_EQ_CTRL_CMD_VFN	0
4510 #define	M_FW_EQ_CTRL_CMD_VFN	0xff
4511 #define	V_FW_EQ_CTRL_CMD_VFN(x)	((x) << S_FW_EQ_CTRL_CMD_VFN)
4512 #define	G_FW_EQ_CTRL_CMD_VFN(x)	\
4513 	(((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
4514 
4515 #define	S_FW_EQ_CTRL_CMD_ALLOC		31
4516 #define	M_FW_EQ_CTRL_CMD_ALLOC		0x1
4517 #define	V_FW_EQ_CTRL_CMD_ALLOC(x)	((x) << S_FW_EQ_CTRL_CMD_ALLOC)
4518 #define	G_FW_EQ_CTRL_CMD_ALLOC(x)	\
4519 	(((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
4520 #define	F_FW_EQ_CTRL_CMD_ALLOC	V_FW_EQ_CTRL_CMD_ALLOC(1U)
4521 
4522 #define	S_FW_EQ_CTRL_CMD_FREE		30
4523 #define	M_FW_EQ_CTRL_CMD_FREE		0x1
4524 #define	V_FW_EQ_CTRL_CMD_FREE(x)	((x) << S_FW_EQ_CTRL_CMD_FREE)
4525 #define	G_FW_EQ_CTRL_CMD_FREE(x)	\
4526 	(((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
4527 #define	F_FW_EQ_CTRL_CMD_FREE	V_FW_EQ_CTRL_CMD_FREE(1U)
4528 
4529 #define	S_FW_EQ_CTRL_CMD_MODIFY		29
4530 #define	M_FW_EQ_CTRL_CMD_MODIFY		0x1
4531 #define	V_FW_EQ_CTRL_CMD_MODIFY(x)	((x) << S_FW_EQ_CTRL_CMD_MODIFY)
4532 #define	G_FW_EQ_CTRL_CMD_MODIFY(x)	\
4533 	(((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
4534 #define	F_FW_EQ_CTRL_CMD_MODIFY	V_FW_EQ_CTRL_CMD_MODIFY(1U)
4535 
4536 #define	S_FW_EQ_CTRL_CMD_EQSTART	28
4537 #define	M_FW_EQ_CTRL_CMD_EQSTART	0x1
4538 #define	V_FW_EQ_CTRL_CMD_EQSTART(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTART)
4539 #define	G_FW_EQ_CTRL_CMD_EQSTART(x)	\
4540 	(((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
4541 #define	F_FW_EQ_CTRL_CMD_EQSTART	V_FW_EQ_CTRL_CMD_EQSTART(1U)
4542 
4543 #define	S_FW_EQ_CTRL_CMD_EQSTOP		27
4544 #define	M_FW_EQ_CTRL_CMD_EQSTOP		0x1
4545 #define	V_FW_EQ_CTRL_CMD_EQSTOP(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
4546 #define	G_FW_EQ_CTRL_CMD_EQSTOP(x)	\
4547 	(((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
4548 #define	F_FW_EQ_CTRL_CMD_EQSTOP	V_FW_EQ_CTRL_CMD_EQSTOP(1U)
4549 
4550 #define	S_FW_EQ_CTRL_CMD_CMPLIQID	20
4551 #define	M_FW_EQ_CTRL_CMD_CMPLIQID	0xfff
4552 #define	V_FW_EQ_CTRL_CMD_CMPLIQID(x)	((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
4553 #define	G_FW_EQ_CTRL_CMD_CMPLIQID(x)	\
4554 	(((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
4555 
4556 #define	S_FW_EQ_CTRL_CMD_EQID		0
4557 #define	M_FW_EQ_CTRL_CMD_EQID		0xfffff
4558 #define	V_FW_EQ_CTRL_CMD_EQID(x)	((x) << S_FW_EQ_CTRL_CMD_EQID)
4559 #define	G_FW_EQ_CTRL_CMD_EQID(x)	\
4560 	(((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
4561 
4562 #define	S_FW_EQ_CTRL_CMD_PHYSEQID	0
4563 #define	M_FW_EQ_CTRL_CMD_PHYSEQID	0xfffff
4564 #define	V_FW_EQ_CTRL_CMD_PHYSEQID(x)	((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
4565 #define	G_FW_EQ_CTRL_CMD_PHYSEQID(x)	\
4566 	(((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
4567 
4568 #define	S_FW_EQ_CTRL_CMD_FETCHSZM	26
4569 #define	M_FW_EQ_CTRL_CMD_FETCHSZM	0x1
4570 #define	V_FW_EQ_CTRL_CMD_FETCHSZM(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
4571 #define	G_FW_EQ_CTRL_CMD_FETCHSZM(x)	\
4572 	(((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
4573 #define	F_FW_EQ_CTRL_CMD_FETCHSZM	V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
4574 
4575 #define	S_FW_EQ_CTRL_CMD_STATUSPGNS	25
4576 #define	M_FW_EQ_CTRL_CMD_STATUSPGNS	0x1
4577 #define	V_FW_EQ_CTRL_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
4578 #define	G_FW_EQ_CTRL_CMD_STATUSPGNS(x)	\
4579 	(((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
4580 #define	F_FW_EQ_CTRL_CMD_STATUSPGNS	V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
4581 
4582 #define	S_FW_EQ_CTRL_CMD_STATUSPGRO	24
4583 #define	M_FW_EQ_CTRL_CMD_STATUSPGRO	0x1
4584 #define	V_FW_EQ_CTRL_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
4585 #define	G_FW_EQ_CTRL_CMD_STATUSPGRO(x)	\
4586 	(((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
4587 #define	F_FW_EQ_CTRL_CMD_STATUSPGRO	V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
4588 
4589 #define	S_FW_EQ_CTRL_CMD_FETCHNS	23
4590 #define	M_FW_EQ_CTRL_CMD_FETCHNS	0x1
4591 #define	V_FW_EQ_CTRL_CMD_FETCHNS(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
4592 #define	G_FW_EQ_CTRL_CMD_FETCHNS(x)	\
4593 	(((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
4594 #define	F_FW_EQ_CTRL_CMD_FETCHNS	V_FW_EQ_CTRL_CMD_FETCHNS(1U)
4595 
4596 #define	S_FW_EQ_CTRL_CMD_FETCHRO	22
4597 #define	M_FW_EQ_CTRL_CMD_FETCHRO	0x1
4598 #define	V_FW_EQ_CTRL_CMD_FETCHRO(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
4599 #define	G_FW_EQ_CTRL_CMD_FETCHRO(x)	\
4600 	(((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
4601 #define	F_FW_EQ_CTRL_CMD_FETCHRO	V_FW_EQ_CTRL_CMD_FETCHRO(1U)
4602 
4603 #define	S_FW_EQ_CTRL_CMD_HOSTFCMODE	20
4604 #define	M_FW_EQ_CTRL_CMD_HOSTFCMODE	0x3
4605 #define	V_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
4606 #define	G_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	\
4607 	(((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
4608 
4609 #define	S_FW_EQ_CTRL_CMD_CPRIO		19
4610 #define	M_FW_EQ_CTRL_CMD_CPRIO		0x1
4611 #define	V_FW_EQ_CTRL_CMD_CPRIO(x)	((x) << S_FW_EQ_CTRL_CMD_CPRIO)
4612 #define	G_FW_EQ_CTRL_CMD_CPRIO(x)	\
4613 	(((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
4614 #define	F_FW_EQ_CTRL_CMD_CPRIO	V_FW_EQ_CTRL_CMD_CPRIO(1U)
4615 
4616 #define	S_FW_EQ_CTRL_CMD_ONCHIP		18
4617 #define	M_FW_EQ_CTRL_CMD_ONCHIP		0x1
4618 #define	V_FW_EQ_CTRL_CMD_ONCHIP(x)	((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
4619 #define	G_FW_EQ_CTRL_CMD_ONCHIP(x)	\
4620 	(((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
4621 #define	F_FW_EQ_CTRL_CMD_ONCHIP	V_FW_EQ_CTRL_CMD_ONCHIP(1U)
4622 
4623 #define	S_FW_EQ_CTRL_CMD_PCIECHN	16
4624 #define	M_FW_EQ_CTRL_CMD_PCIECHN	0x3
4625 #define	V_FW_EQ_CTRL_CMD_PCIECHN(x)	((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
4626 #define	G_FW_EQ_CTRL_CMD_PCIECHN(x)	\
4627 	(((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
4628 
4629 #define	S_FW_EQ_CTRL_CMD_IQID		0
4630 #define	M_FW_EQ_CTRL_CMD_IQID		0xffff
4631 #define	V_FW_EQ_CTRL_CMD_IQID(x)	((x) << S_FW_EQ_CTRL_CMD_IQID)
4632 #define	G_FW_EQ_CTRL_CMD_IQID(x)	\
4633 	(((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
4634 
4635 #define	S_FW_EQ_CTRL_CMD_DCAEN		31
4636 #define	M_FW_EQ_CTRL_CMD_DCAEN		0x1
4637 #define	V_FW_EQ_CTRL_CMD_DCAEN(x)	((x) << S_FW_EQ_CTRL_CMD_DCAEN)
4638 #define	G_FW_EQ_CTRL_CMD_DCAEN(x)	\
4639 	(((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
4640 #define	F_FW_EQ_CTRL_CMD_DCAEN	V_FW_EQ_CTRL_CMD_DCAEN(1U)
4641 
4642 #define	S_FW_EQ_CTRL_CMD_DCACPU		26
4643 #define	M_FW_EQ_CTRL_CMD_DCACPU		0x1f
4644 #define	V_FW_EQ_CTRL_CMD_DCACPU(x)	((x) << S_FW_EQ_CTRL_CMD_DCACPU)
4645 #define	G_FW_EQ_CTRL_CMD_DCACPU(x)	\
4646 	(((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
4647 
4648 #define	S_FW_EQ_CTRL_CMD_FBMIN		23
4649 #define	M_FW_EQ_CTRL_CMD_FBMIN		0x7
4650 #define	V_FW_EQ_CTRL_CMD_FBMIN(x)	((x) << S_FW_EQ_CTRL_CMD_FBMIN)
4651 #define	G_FW_EQ_CTRL_CMD_FBMIN(x)	\
4652 	(((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
4653 
4654 #define	S_FW_EQ_CTRL_CMD_FBMAX		20
4655 #define	M_FW_EQ_CTRL_CMD_FBMAX		0x7
4656 #define	V_FW_EQ_CTRL_CMD_FBMAX(x)	((x) << S_FW_EQ_CTRL_CMD_FBMAX)
4657 #define	G_FW_EQ_CTRL_CMD_FBMAX(x)	\
4658 	(((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
4659 
4660 #define	S_FW_EQ_CTRL_CMD_CIDXFTHRESHO		19
4661 #define	M_FW_EQ_CTRL_CMD_CIDXFTHRESHO		0x1
4662 #define	V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x)	\
4663 	((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
4664 #define	G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x)	\
4665 	(((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
4666 #define	F_FW_EQ_CTRL_CMD_CIDXFTHRESHO	V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
4667 
4668 #define	S_FW_EQ_CTRL_CMD_CIDXFTHRESH	16
4669 #define	M_FW_EQ_CTRL_CMD_CIDXFTHRESH	0x7
4670 #define	V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
4671 #define	G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	\
4672 	(((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
4673 
4674 #define	S_FW_EQ_CTRL_CMD_EQSIZE		0
4675 #define	M_FW_EQ_CTRL_CMD_EQSIZE		0xffff
4676 #define	V_FW_EQ_CTRL_CMD_EQSIZE(x)	((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
4677 #define	G_FW_EQ_CTRL_CMD_EQSIZE(x)	\
4678 	(((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
4679 
4680 struct fw_eq_ofld_cmd {
4681 	__be32 op_to_vfn;
4682 	__be32 alloc_to_len16;
4683 	__be32 eqid_pkd;
4684 	__be32 physeqid_pkd;
4685 	__be32 fetchszm_to_iqid;
4686 	__be32 dcaen_to_eqsize;
4687 	__be64 eqaddr;
4688 };
4689 
4690 #define	S_FW_EQ_OFLD_CMD_PFN	8
4691 #define	M_FW_EQ_OFLD_CMD_PFN	0x7
4692 #define	V_FW_EQ_OFLD_CMD_PFN(x)	((x) << S_FW_EQ_OFLD_CMD_PFN)
4693 #define	G_FW_EQ_OFLD_CMD_PFN(x)	\
4694 	(((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
4695 
4696 #define	S_FW_EQ_OFLD_CMD_VFN	0
4697 #define	M_FW_EQ_OFLD_CMD_VFN	0xff
4698 #define	V_FW_EQ_OFLD_CMD_VFN(x)	((x) << S_FW_EQ_OFLD_CMD_VFN)
4699 #define	G_FW_EQ_OFLD_CMD_VFN(x)	\
4700 	(((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
4701 
4702 #define	S_FW_EQ_OFLD_CMD_ALLOC		31
4703 #define	M_FW_EQ_OFLD_CMD_ALLOC		0x1
4704 #define	V_FW_EQ_OFLD_CMD_ALLOC(x)	((x) << S_FW_EQ_OFLD_CMD_ALLOC)
4705 #define	G_FW_EQ_OFLD_CMD_ALLOC(x)	\
4706 	(((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
4707 #define	F_FW_EQ_OFLD_CMD_ALLOC	V_FW_EQ_OFLD_CMD_ALLOC(1U)
4708 
4709 #define	S_FW_EQ_OFLD_CMD_FREE		30
4710 #define	M_FW_EQ_OFLD_CMD_FREE		0x1
4711 #define	V_FW_EQ_OFLD_CMD_FREE(x)	((x) << S_FW_EQ_OFLD_CMD_FREE)
4712 #define	G_FW_EQ_OFLD_CMD_FREE(x)	\
4713 	(((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
4714 #define	F_FW_EQ_OFLD_CMD_FREE	V_FW_EQ_OFLD_CMD_FREE(1U)
4715 
4716 #define	S_FW_EQ_OFLD_CMD_MODIFY		29
4717 #define	M_FW_EQ_OFLD_CMD_MODIFY		0x1
4718 #define	V_FW_EQ_OFLD_CMD_MODIFY(x)	((x) << S_FW_EQ_OFLD_CMD_MODIFY)
4719 #define	G_FW_EQ_OFLD_CMD_MODIFY(x)	\
4720 	(((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
4721 #define	F_FW_EQ_OFLD_CMD_MODIFY	V_FW_EQ_OFLD_CMD_MODIFY(1U)
4722 
4723 #define	S_FW_EQ_OFLD_CMD_EQSTART	28
4724 #define	M_FW_EQ_OFLD_CMD_EQSTART	0x1
4725 #define	V_FW_EQ_OFLD_CMD_EQSTART(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTART)
4726 #define	G_FW_EQ_OFLD_CMD_EQSTART(x)	\
4727 	(((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
4728 #define	F_FW_EQ_OFLD_CMD_EQSTART	V_FW_EQ_OFLD_CMD_EQSTART(1U)
4729 
4730 #define	S_FW_EQ_OFLD_CMD_EQSTOP		27
4731 #define	M_FW_EQ_OFLD_CMD_EQSTOP		0x1
4732 #define	V_FW_EQ_OFLD_CMD_EQSTOP(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
4733 #define	G_FW_EQ_OFLD_CMD_EQSTOP(x)	\
4734 	(((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
4735 #define	F_FW_EQ_OFLD_CMD_EQSTOP	V_FW_EQ_OFLD_CMD_EQSTOP(1U)
4736 
4737 #define	S_FW_EQ_OFLD_CMD_EQID		0
4738 #define	M_FW_EQ_OFLD_CMD_EQID		0xfffff
4739 #define	V_FW_EQ_OFLD_CMD_EQID(x)	((x) << S_FW_EQ_OFLD_CMD_EQID)
4740 #define	G_FW_EQ_OFLD_CMD_EQID(x)	\
4741 	(((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
4742 
4743 #define	S_FW_EQ_OFLD_CMD_PHYSEQID	0
4744 #define	M_FW_EQ_OFLD_CMD_PHYSEQID	0xfffff
4745 #define	V_FW_EQ_OFLD_CMD_PHYSEQID(x)	((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
4746 #define	G_FW_EQ_OFLD_CMD_PHYSEQID(x)	\
4747 	(((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
4748 
4749 #define	S_FW_EQ_OFLD_CMD_FETCHSZM	26
4750 #define	M_FW_EQ_OFLD_CMD_FETCHSZM	0x1
4751 #define	V_FW_EQ_OFLD_CMD_FETCHSZM(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
4752 #define	G_FW_EQ_OFLD_CMD_FETCHSZM(x)	\
4753 	(((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
4754 #define	F_FW_EQ_OFLD_CMD_FETCHSZM	V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
4755 
4756 #define	S_FW_EQ_OFLD_CMD_STATUSPGNS	25
4757 #define	M_FW_EQ_OFLD_CMD_STATUSPGNS	0x1
4758 #define	V_FW_EQ_OFLD_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
4759 #define	G_FW_EQ_OFLD_CMD_STATUSPGNS(x)	\
4760 	(((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
4761 #define	F_FW_EQ_OFLD_CMD_STATUSPGNS	V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
4762 
4763 #define	S_FW_EQ_OFLD_CMD_STATUSPGRO	24
4764 #define	M_FW_EQ_OFLD_CMD_STATUSPGRO	0x1
4765 #define	V_FW_EQ_OFLD_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
4766 #define	G_FW_EQ_OFLD_CMD_STATUSPGRO(x)	\
4767 	(((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
4768 #define	F_FW_EQ_OFLD_CMD_STATUSPGRO	V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
4769 
4770 #define	S_FW_EQ_OFLD_CMD_FETCHNS	23
4771 #define	M_FW_EQ_OFLD_CMD_FETCHNS	0x1
4772 #define	V_FW_EQ_OFLD_CMD_FETCHNS(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
4773 #define	G_FW_EQ_OFLD_CMD_FETCHNS(x)	\
4774 	(((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
4775 #define	F_FW_EQ_OFLD_CMD_FETCHNS	V_FW_EQ_OFLD_CMD_FETCHNS(1U)
4776 
4777 #define	S_FW_EQ_OFLD_CMD_FETCHRO	22
4778 #define	M_FW_EQ_OFLD_CMD_FETCHRO	0x1
4779 #define	V_FW_EQ_OFLD_CMD_FETCHRO(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
4780 #define	G_FW_EQ_OFLD_CMD_FETCHRO(x)	\
4781 	(((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
4782 #define	F_FW_EQ_OFLD_CMD_FETCHRO	V_FW_EQ_OFLD_CMD_FETCHRO(1U)
4783 
4784 #define	S_FW_EQ_OFLD_CMD_HOSTFCMODE	20
4785 #define	M_FW_EQ_OFLD_CMD_HOSTFCMODE	0x3
4786 #define	V_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
4787 #define	G_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	\
4788 	(((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
4789 
4790 #define	S_FW_EQ_OFLD_CMD_CPRIO		19
4791 #define	M_FW_EQ_OFLD_CMD_CPRIO		0x1
4792 #define	V_FW_EQ_OFLD_CMD_CPRIO(x)	((x) << S_FW_EQ_OFLD_CMD_CPRIO)
4793 #define	G_FW_EQ_OFLD_CMD_CPRIO(x)	\
4794 	(((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
4795 #define	F_FW_EQ_OFLD_CMD_CPRIO	V_FW_EQ_OFLD_CMD_CPRIO(1U)
4796 
4797 #define	S_FW_EQ_OFLD_CMD_ONCHIP		18
4798 #define	M_FW_EQ_OFLD_CMD_ONCHIP		0x1
4799 #define	V_FW_EQ_OFLD_CMD_ONCHIP(x)	((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
4800 #define	G_FW_EQ_OFLD_CMD_ONCHIP(x)	\
4801 	(((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
4802 #define	F_FW_EQ_OFLD_CMD_ONCHIP	V_FW_EQ_OFLD_CMD_ONCHIP(1U)
4803 
4804 #define	S_FW_EQ_OFLD_CMD_PCIECHN	16
4805 #define	M_FW_EQ_OFLD_CMD_PCIECHN	0x3
4806 #define	V_FW_EQ_OFLD_CMD_PCIECHN(x)	((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
4807 #define	G_FW_EQ_OFLD_CMD_PCIECHN(x)	\
4808 	(((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
4809 
4810 #define	S_FW_EQ_OFLD_CMD_IQID		0
4811 #define	M_FW_EQ_OFLD_CMD_IQID		0xffff
4812 #define	V_FW_EQ_OFLD_CMD_IQID(x)	((x) << S_FW_EQ_OFLD_CMD_IQID)
4813 #define	G_FW_EQ_OFLD_CMD_IQID(x)	\
4814 	(((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
4815 
4816 #define	S_FW_EQ_OFLD_CMD_DCAEN		31
4817 #define	M_FW_EQ_OFLD_CMD_DCAEN		0x1
4818 #define	V_FW_EQ_OFLD_CMD_DCAEN(x)	((x) << S_FW_EQ_OFLD_CMD_DCAEN)
4819 #define	G_FW_EQ_OFLD_CMD_DCAEN(x)	\
4820 	(((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
4821 #define	F_FW_EQ_OFLD_CMD_DCAEN	V_FW_EQ_OFLD_CMD_DCAEN(1U)
4822 
4823 #define	S_FW_EQ_OFLD_CMD_DCACPU		26
4824 #define	M_FW_EQ_OFLD_CMD_DCACPU		0x1f
4825 #define	V_FW_EQ_OFLD_CMD_DCACPU(x)	((x) << S_FW_EQ_OFLD_CMD_DCACPU)
4826 #define	G_FW_EQ_OFLD_CMD_DCACPU(x)	\
4827 	(((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
4828 
4829 #define	S_FW_EQ_OFLD_CMD_FBMIN		23
4830 #define	M_FW_EQ_OFLD_CMD_FBMIN		0x7
4831 #define	V_FW_EQ_OFLD_CMD_FBMIN(x)	((x) << S_FW_EQ_OFLD_CMD_FBMIN)
4832 #define	G_FW_EQ_OFLD_CMD_FBMIN(x)	\
4833 	(((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
4834 
4835 #define	S_FW_EQ_OFLD_CMD_FBMAX		20
4836 #define	M_FW_EQ_OFLD_CMD_FBMAX		0x7
4837 #define	V_FW_EQ_OFLD_CMD_FBMAX(x)	((x) << S_FW_EQ_OFLD_CMD_FBMAX)
4838 #define	G_FW_EQ_OFLD_CMD_FBMAX(x)	\
4839 	(((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
4840 
4841 #define	S_FW_EQ_OFLD_CMD_CIDXFTHRESHO		19
4842 #define	M_FW_EQ_OFLD_CMD_CIDXFTHRESHO		0x1
4843 #define	V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x)	\
4844 	((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
4845 #define	G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x)	\
4846 	(((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
4847 #define	F_FW_EQ_OFLD_CMD_CIDXFTHRESHO	V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
4848 
4849 #define	S_FW_EQ_OFLD_CMD_CIDXFTHRESH	16
4850 #define	M_FW_EQ_OFLD_CMD_CIDXFTHRESH	0x7
4851 #define	V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
4852 #define	G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	\
4853 	(((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
4854 
4855 #define	S_FW_EQ_OFLD_CMD_EQSIZE		0
4856 #define	M_FW_EQ_OFLD_CMD_EQSIZE		0xffff
4857 #define	V_FW_EQ_OFLD_CMD_EQSIZE(x)	((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
4858 #define	G_FW_EQ_OFLD_CMD_EQSIZE(x)	\
4859 	(((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
4860 
4861 /*
4862  * Macros for VIID parsing:
4863  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
4864  */
4865 #define	S_FW_VIID_PFN		8
4866 #define	M_FW_VIID_PFN		0x7
4867 #define	V_FW_VIID_PFN(x)	((x) << S_FW_VIID_PFN)
4868 #define	G_FW_VIID_PFN(x)	(((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
4869 
4870 #define	S_FW_VIID_VIVLD		7
4871 #define	M_FW_VIID_VIVLD		0x1
4872 #define	V_FW_VIID_VIVLD(x)	((x) << S_FW_VIID_VIVLD)
4873 #define	G_FW_VIID_VIVLD(x)	(((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
4874 
4875 #define	S_FW_VIID_VIN		0
4876 #define	M_FW_VIID_VIN		0x7F
4877 #define	V_FW_VIID_VIN(x)	((x) << S_FW_VIID_VIN)
4878 #define	G_FW_VIID_VIN(x)	(((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
4879 
4880 enum fw_vi_func {
4881 	FW_VI_FUNC_ETH,
4882 	FW_VI_FUNC_OFLD,
4883 	FW_VI_FUNC_IWARP,
4884 	FW_VI_FUNC_OPENISCSI,
4885 	FW_VI_FUNC_OPENFCOE,
4886 	FW_VI_FUNC_FOISCSI,
4887 	FW_VI_FUNC_FOFCOE,
4888 	FW_VI_FUNC_FW,
4889 };
4890 
4891 struct fw_vi_cmd {
4892 	__be32 op_to_vfn;
4893 	__be32 alloc_to_len16;
4894 	__be16 type_to_viid;
4895 	__u8   mac[6];
4896 	__u8   portid_pkd;
4897 	__u8   nmac;
4898 	__u8   nmac0[6];
4899 	__be16 rsssize_pkd;
4900 	__u8   nmac1[6];
4901 	__be16 idsiiq_pkd;
4902 	__u8   nmac2[6];
4903 	__be16 idseiq_pkd;
4904 	__u8   nmac3[6];
4905 	__be64 r9;
4906 	__be64 r10;
4907 };
4908 
4909 #define	S_FW_VI_CMD_PFN		8
4910 #define	M_FW_VI_CMD_PFN		0x7
4911 #define	V_FW_VI_CMD_PFN(x)	((x) << S_FW_VI_CMD_PFN)
4912 #define	G_FW_VI_CMD_PFN(x)	(((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
4913 
4914 #define	S_FW_VI_CMD_VFN		0
4915 #define	M_FW_VI_CMD_VFN		0xff
4916 #define	V_FW_VI_CMD_VFN(x)	((x) << S_FW_VI_CMD_VFN)
4917 #define	G_FW_VI_CMD_VFN(x)	(((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
4918 
4919 #define	S_FW_VI_CMD_ALLOC	31
4920 #define	M_FW_VI_CMD_ALLOC	0x1
4921 #define	V_FW_VI_CMD_ALLOC(x)	((x) << S_FW_VI_CMD_ALLOC)
4922 #define	G_FW_VI_CMD_ALLOC(x)	\
4923 	(((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
4924 #define	F_FW_VI_CMD_ALLOC	V_FW_VI_CMD_ALLOC(1U)
4925 
4926 #define	S_FW_VI_CMD_FREE	30
4927 #define	M_FW_VI_CMD_FREE	0x1
4928 #define	V_FW_VI_CMD_FREE(x)	((x) << S_FW_VI_CMD_FREE)
4929 #define	G_FW_VI_CMD_FREE(x)	(((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
4930 #define	F_FW_VI_CMD_FREE	V_FW_VI_CMD_FREE(1U)
4931 
4932 #define	S_FW_VI_CMD_TYPE	15
4933 #define	M_FW_VI_CMD_TYPE	0x1
4934 #define	V_FW_VI_CMD_TYPE(x)	((x) << S_FW_VI_CMD_TYPE)
4935 #define	G_FW_VI_CMD_TYPE(x)	(((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
4936 #define	F_FW_VI_CMD_TYPE	V_FW_VI_CMD_TYPE(1U)
4937 
4938 #define	S_FW_VI_CMD_FUNC	12
4939 #define	M_FW_VI_CMD_FUNC	0x7
4940 #define	V_FW_VI_CMD_FUNC(x)	((x) << S_FW_VI_CMD_FUNC)
4941 #define	G_FW_VI_CMD_FUNC(x)	(((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
4942 
4943 #define	S_FW_VI_CMD_VIID	0
4944 #define	M_FW_VI_CMD_VIID	0xfff
4945 #define	V_FW_VI_CMD_VIID(x)	((x) << S_FW_VI_CMD_VIID)
4946 #define	G_FW_VI_CMD_VIID(x)	(((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
4947 
4948 #define	S_FW_VI_CMD_PORTID	4
4949 #define	M_FW_VI_CMD_PORTID	0xf
4950 #define	V_FW_VI_CMD_PORTID(x)	((x) << S_FW_VI_CMD_PORTID)
4951 #define	G_FW_VI_CMD_PORTID(x)	\
4952 	(((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
4953 
4954 #define	S_FW_VI_CMD_RSSSIZE	0
4955 #define	M_FW_VI_CMD_RSSSIZE	0x7ff
4956 #define	V_FW_VI_CMD_RSSSIZE(x)	((x) << S_FW_VI_CMD_RSSSIZE)
4957 #define	G_FW_VI_CMD_RSSSIZE(x)	\
4958 	(((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
4959 
4960 #define	S_FW_VI_CMD_IDSIIQ	0
4961 #define	M_FW_VI_CMD_IDSIIQ	0x3ff
4962 #define	V_FW_VI_CMD_IDSIIQ(x)	((x) << S_FW_VI_CMD_IDSIIQ)
4963 #define	G_FW_VI_CMD_IDSIIQ(x)	\
4964 	(((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
4965 
4966 #define	S_FW_VI_CMD_IDSEIQ	0
4967 #define	M_FW_VI_CMD_IDSEIQ	0x3ff
4968 #define	V_FW_VI_CMD_IDSEIQ(x)	((x) << S_FW_VI_CMD_IDSEIQ)
4969 #define	G_FW_VI_CMD_IDSEIQ(x)	\
4970 	(((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
4971 
4972 /* Special VI_MAC command index ids */
4973 #define	FW_VI_MAC_ADD_MAC		0x3FF
4974 #define	FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
4975 #define	FW_VI_MAC_MAC_BASED_FREE	0x3FD
4976 
4977 enum fw_vi_mac_smac {
4978 	FW_VI_MAC_MPS_TCAM_ENTRY,
4979 	FW_VI_MAC_MPS_TCAM_ONLY,
4980 	FW_VI_MAC_SMT_ONLY,
4981 	FW_VI_MAC_SMT_AND_MPSTCAM
4982 };
4983 
4984 enum fw_vi_mac_result {
4985 	FW_VI_MAC_R_SUCCESS,
4986 	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
4987 	FW_VI_MAC_R_SMAC_FAIL,
4988 	FW_VI_MAC_R_F_ACL_CHECK
4989 };
4990 
4991 struct fw_vi_mac_cmd {
4992 	__be32 op_to_viid;
4993 	__be32 freemacs_to_len16;
4994 	union fw_vi_mac {
4995 		struct fw_vi_mac_exact {
4996 			__be16 valid_to_idx;
4997 			__u8   macaddr[6];
4998 		} exact[7];
4999 		struct fw_vi_mac_hash {
5000 			__be64 hashvec;
5001 		} hash;
5002 	} u;
5003 };
5004 
5005 #define	S_FW_VI_MAC_CMD_VIID	0
5006 #define	M_FW_VI_MAC_CMD_VIID	0xfff
5007 #define	V_FW_VI_MAC_CMD_VIID(x)	((x) << S_FW_VI_MAC_CMD_VIID)
5008 #define	G_FW_VI_MAC_CMD_VIID(x)	\
5009 	(((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
5010 
5011 #define	S_FW_VI_MAC_CMD_FREEMACS	31
5012 #define	M_FW_VI_MAC_CMD_FREEMACS	0x1
5013 #define	V_FW_VI_MAC_CMD_FREEMACS(x)	((x) << S_FW_VI_MAC_CMD_FREEMACS)
5014 #define	G_FW_VI_MAC_CMD_FREEMACS(x)	\
5015 	(((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
5016 #define	F_FW_VI_MAC_CMD_FREEMACS	V_FW_VI_MAC_CMD_FREEMACS(1U)
5017 
5018 #define	S_FW_VI_MAC_CMD_HASHVECEN	23
5019 #define	M_FW_VI_MAC_CMD_HASHVECEN	0x1
5020 #define	V_FW_VI_MAC_CMD_HASHVECEN(x)	((x) << S_FW_VI_MAC_CMD_HASHVECEN)
5021 #define	G_FW_VI_MAC_CMD_HASHVECEN(x)	\
5022 	(((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN)
5023 #define	F_FW_VI_MAC_CMD_HASHVECEN	V_FW_VI_MAC_CMD_HASHVECEN(1U)
5024 
5025 #define	S_FW_VI_MAC_CMD_HASHUNIEN	22
5026 #define	M_FW_VI_MAC_CMD_HASHUNIEN	0x1
5027 #define	V_FW_VI_MAC_CMD_HASHUNIEN(x)	((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
5028 #define	G_FW_VI_MAC_CMD_HASHUNIEN(x)	\
5029 	(((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
5030 #define	F_FW_VI_MAC_CMD_HASHUNIEN	V_FW_VI_MAC_CMD_HASHUNIEN(1U)
5031 
5032 #define	S_FW_VI_MAC_CMD_VALID		15
5033 #define	M_FW_VI_MAC_CMD_VALID		0x1
5034 #define	V_FW_VI_MAC_CMD_VALID(x)	((x) << S_FW_VI_MAC_CMD_VALID)
5035 #define	G_FW_VI_MAC_CMD_VALID(x)	\
5036 	(((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
5037 #define	F_FW_VI_MAC_CMD_VALID	V_FW_VI_MAC_CMD_VALID(1U)
5038 
5039 #define	S_FW_VI_MAC_CMD_PRIO	12
5040 #define	M_FW_VI_MAC_CMD_PRIO	0x7
5041 #define	V_FW_VI_MAC_CMD_PRIO(x)	((x) << S_FW_VI_MAC_CMD_PRIO)
5042 #define	G_FW_VI_MAC_CMD_PRIO(x)	\
5043 	(((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
5044 
5045 #define	S_FW_VI_MAC_CMD_SMAC_RESULT	10
5046 #define	M_FW_VI_MAC_CMD_SMAC_RESULT	0x3
5047 #define	V_FW_VI_MAC_CMD_SMAC_RESULT(x)	((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
5048 #define	G_FW_VI_MAC_CMD_SMAC_RESULT(x)	\
5049 	(((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
5050 
5051 #define	S_FW_VI_MAC_CMD_IDX	0
5052 #define	M_FW_VI_MAC_CMD_IDX	0x3ff
5053 #define	V_FW_VI_MAC_CMD_IDX(x)	((x) << S_FW_VI_MAC_CMD_IDX)
5054 #define	G_FW_VI_MAC_CMD_IDX(x)	\
5055 	(((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
5056 
5057 /* T4 max MTU supported */
5058 #define	T4_MAX_MTU_SUPPORTED	9600
5059 #define	FW_RXMODE_MTU_NO_CHG	65535
5060 
5061 struct fw_vi_rxmode_cmd {
5062 	__be32 op_to_viid;
5063 	__be32 retval_len16;
5064 	__be32 mtu_to_vlanexen;
5065 	__be32 r4_lo;
5066 };
5067 
5068 #define	S_FW_VI_RXMODE_CMD_VIID		0
5069 #define	M_FW_VI_RXMODE_CMD_VIID		0xfff
5070 #define	V_FW_VI_RXMODE_CMD_VIID(x)	((x) << S_FW_VI_RXMODE_CMD_VIID)
5071 #define	G_FW_VI_RXMODE_CMD_VIID(x)	\
5072 	(((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
5073 
5074 #define	S_FW_VI_RXMODE_CMD_MTU		16
5075 #define	M_FW_VI_RXMODE_CMD_MTU		0xffff
5076 #define	V_FW_VI_RXMODE_CMD_MTU(x)	((x) << S_FW_VI_RXMODE_CMD_MTU)
5077 #define	G_FW_VI_RXMODE_CMD_MTU(x)	\
5078 	(((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
5079 
5080 #define	S_FW_VI_RXMODE_CMD_PROMISCEN	14
5081 #define	M_FW_VI_RXMODE_CMD_PROMISCEN	0x3
5082 #define	V_FW_VI_RXMODE_CMD_PROMISCEN(x)	((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
5083 #define	G_FW_VI_RXMODE_CMD_PROMISCEN(x)	\
5084 	(((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
5085 
5086 #define	S_FW_VI_RXMODE_CMD_ALLMULTIEN		12
5087 #define	M_FW_VI_RXMODE_CMD_ALLMULTIEN		0x3
5088 #define	V_FW_VI_RXMODE_CMD_ALLMULTIEN(x)	\
5089 	((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
5090 #define	G_FW_VI_RXMODE_CMD_ALLMULTIEN(x)	\
5091 	(((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
5092 
5093 #define	S_FW_VI_RXMODE_CMD_BROADCASTEN		10
5094 #define	M_FW_VI_RXMODE_CMD_BROADCASTEN		0x3
5095 #define	V_FW_VI_RXMODE_CMD_BROADCASTEN(x)	\
5096 	((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
5097 #define	G_FW_VI_RXMODE_CMD_BROADCASTEN(x)	\
5098 	(((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
5099 	M_FW_VI_RXMODE_CMD_BROADCASTEN)
5100 
5101 #define	S_FW_VI_RXMODE_CMD_VLANEXEN	8
5102 #define	M_FW_VI_RXMODE_CMD_VLANEXEN	0x3
5103 #define	V_FW_VI_RXMODE_CMD_VLANEXEN(x)	((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
5104 #define	G_FW_VI_RXMODE_CMD_VLANEXEN(x)	\
5105 	(((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
5106 
5107 struct fw_vi_enable_cmd {
5108 	__be32 op_to_viid;
5109 	__be32 ien_to_len16;
5110 	__be16 blinkdur;
5111 	__be16 r3;
5112 	__be32 r4;
5113 };
5114 
5115 #define	S_FW_VI_ENABLE_CMD_VIID		0
5116 #define	M_FW_VI_ENABLE_CMD_VIID		0xfff
5117 #define	V_FW_VI_ENABLE_CMD_VIID(x)	((x) << S_FW_VI_ENABLE_CMD_VIID)
5118 #define	G_FW_VI_ENABLE_CMD_VIID(x)	\
5119 	(((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
5120 
5121 #define	S_FW_VI_ENABLE_CMD_IEN		31
5122 #define	M_FW_VI_ENABLE_CMD_IEN		0x1
5123 #define	V_FW_VI_ENABLE_CMD_IEN(x)	((x) << S_FW_VI_ENABLE_CMD_IEN)
5124 #define	G_FW_VI_ENABLE_CMD_IEN(x)	\
5125 	(((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
5126 #define	F_FW_VI_ENABLE_CMD_IEN	V_FW_VI_ENABLE_CMD_IEN(1U)
5127 
5128 #define	S_FW_VI_ENABLE_CMD_EEN		30
5129 #define	M_FW_VI_ENABLE_CMD_EEN		0x1
5130 #define	V_FW_VI_ENABLE_CMD_EEN(x)	((x) << S_FW_VI_ENABLE_CMD_EEN)
5131 #define	G_FW_VI_ENABLE_CMD_EEN(x)	\
5132 	(((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
5133 #define	F_FW_VI_ENABLE_CMD_EEN	V_FW_VI_ENABLE_CMD_EEN(1U)
5134 
5135 #define	S_FW_VI_ENABLE_CMD_LED		29
5136 #define	M_FW_VI_ENABLE_CMD_LED		0x1
5137 #define	V_FW_VI_ENABLE_CMD_LED(x)	((x) << S_FW_VI_ENABLE_CMD_LED)
5138 #define	G_FW_VI_ENABLE_CMD_LED(x)	\
5139 	(((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
5140 #define	F_FW_VI_ENABLE_CMD_LED	V_FW_VI_ENABLE_CMD_LED(1U)
5141 
5142 /* VI VF stats offset definitions */
5143 #define	VI_VF_NUM_STATS	16
5144 enum fw_vi_stats_vf_index {
5145 	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
5146 	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
5147 	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
5148 	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
5149 	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
5150 	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
5151 	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
5152 	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
5153 	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
5154 	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
5155 	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
5156 	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
5157 	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
5158 	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
5159 	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
5160 	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
5161 };
5162 
5163 /* VI PF stats offset definitions */
5164 #define	VI_PF_NUM_STATS	17
5165 enum fw_vi_stats_pf_index {
5166 	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
5167 	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
5168 	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
5169 	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
5170 	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
5171 	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
5172 	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
5173 	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
5174 	FW_VI_PF_STAT_RX_BYTES_IX,
5175 	FW_VI_PF_STAT_RX_FRAMES_IX,
5176 	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
5177 	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
5178 	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
5179 	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
5180 	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
5181 	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
5182 	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
5183 };
5184 
5185 struct fw_vi_stats_cmd {
5186 	__be32 op_to_viid;
5187 	__be32 retval_len16;
5188 	union fw_vi_stats {
5189 		struct fw_vi_stats_ctl {
5190 			__be16 nstats_ix;
5191 			__be16 r6;
5192 			__be32 r7;
5193 			__be64 stat0;
5194 			__be64 stat1;
5195 			__be64 stat2;
5196 			__be64 stat3;
5197 			__be64 stat4;
5198 			__be64 stat5;
5199 		} ctl;
5200 		struct fw_vi_stats_pf {
5201 			__be64 tx_bcast_bytes;
5202 			__be64 tx_bcast_frames;
5203 			__be64 tx_mcast_bytes;
5204 			__be64 tx_mcast_frames;
5205 			__be64 tx_ucast_bytes;
5206 			__be64 tx_ucast_frames;
5207 			__be64 tx_offload_bytes;
5208 			__be64 tx_offload_frames;
5209 			__be64 rx_pf_bytes;
5210 			__be64 rx_pf_frames;
5211 			__be64 rx_bcast_bytes;
5212 			__be64 rx_bcast_frames;
5213 			__be64 rx_mcast_bytes;
5214 			__be64 rx_mcast_frames;
5215 			__be64 rx_ucast_bytes;
5216 			__be64 rx_ucast_frames;
5217 			__be64 rx_err_frames;
5218 		} pf;
5219 		struct fw_vi_stats_vf {
5220 			__be64 tx_bcast_bytes;
5221 			__be64 tx_bcast_frames;
5222 			__be64 tx_mcast_bytes;
5223 			__be64 tx_mcast_frames;
5224 			__be64 tx_ucast_bytes;
5225 			__be64 tx_ucast_frames;
5226 			__be64 tx_drop_frames;
5227 			__be64 tx_offload_bytes;
5228 			__be64 tx_offload_frames;
5229 			__be64 rx_bcast_bytes;
5230 			__be64 rx_bcast_frames;
5231 			__be64 rx_mcast_bytes;
5232 			__be64 rx_mcast_frames;
5233 			__be64 rx_ucast_bytes;
5234 			__be64 rx_ucast_frames;
5235 			__be64 rx_err_frames;
5236 		} vf;
5237 	} u;
5238 };
5239 
5240 #define	S_FW_VI_STATS_CMD_VIID		0
5241 #define	M_FW_VI_STATS_CMD_VIID		0xfff
5242 #define	V_FW_VI_STATS_CMD_VIID(x)	((x) << S_FW_VI_STATS_CMD_VIID)
5243 #define	G_FW_VI_STATS_CMD_VIID(x)	\
5244 	(((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
5245 
5246 #define	S_FW_VI_STATS_CMD_NSTATS	12
5247 #define	M_FW_VI_STATS_CMD_NSTATS	0x7
5248 #define	V_FW_VI_STATS_CMD_NSTATS(x)	((x) << S_FW_VI_STATS_CMD_NSTATS)
5249 #define	G_FW_VI_STATS_CMD_NSTATS(x)	\
5250 	(((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
5251 
5252 #define	S_FW_VI_STATS_CMD_IX	0
5253 #define	M_FW_VI_STATS_CMD_IX	0x1f
5254 #define	V_FW_VI_STATS_CMD_IX(x)	((x) << S_FW_VI_STATS_CMD_IX)
5255 #define	G_FW_VI_STATS_CMD_IX(x)	\
5256 	(((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
5257 
5258 struct fw_acl_mac_cmd {
5259 	__be32 op_to_vfn;
5260 	__be32 en_to_len16;
5261 	__u8   nmac;
5262 	__u8   r3[7];
5263 	__be16 r4;
5264 	__u8   macaddr0[6];
5265 	__be16 r5;
5266 	__u8   macaddr1[6];
5267 	__be16 r6;
5268 	__u8   macaddr2[6];
5269 	__be16 r7;
5270 	__u8   macaddr3[6];
5271 };
5272 
5273 #define	S_FW_ACL_MAC_CMD_PFN	8
5274 #define	M_FW_ACL_MAC_CMD_PFN	0x7
5275 #define	V_FW_ACL_MAC_CMD_PFN(x)	((x) << S_FW_ACL_MAC_CMD_PFN)
5276 #define	G_FW_ACL_MAC_CMD_PFN(x)	\
5277 	(((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
5278 
5279 #define	S_FW_ACL_MAC_CMD_VFN	0
5280 #define	M_FW_ACL_MAC_CMD_VFN	0xff
5281 #define	V_FW_ACL_MAC_CMD_VFN(x)	((x) << S_FW_ACL_MAC_CMD_VFN)
5282 #define	G_FW_ACL_MAC_CMD_VFN(x)	\
5283 	(((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
5284 
5285 #define	S_FW_ACL_MAC_CMD_EN	31
5286 #define	M_FW_ACL_MAC_CMD_EN	0x1
5287 #define	V_FW_ACL_MAC_CMD_EN(x)	((x) << S_FW_ACL_MAC_CMD_EN)
5288 #define	G_FW_ACL_MAC_CMD_EN(x)	\
5289 	(((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
5290 #define	F_FW_ACL_MAC_CMD_EN	V_FW_ACL_MAC_CMD_EN(1U)
5291 
5292 struct fw_acl_vlan_cmd {
5293 	__be32 op_to_vfn;
5294 	__be32 en_to_len16;
5295 	__u8   nvlan;
5296 	__u8   dropnovlan_fm;
5297 	__u8   r3_lo[6];
5298 	__be16 vlanid[16];
5299 };
5300 
5301 #define	S_FW_ACL_VLAN_CMD_PFN		8
5302 #define	M_FW_ACL_VLAN_CMD_PFN		0x7
5303 #define	V_FW_ACL_VLAN_CMD_PFN(x)	((x) << S_FW_ACL_VLAN_CMD_PFN)
5304 #define	G_FW_ACL_VLAN_CMD_PFN(x)	\
5305 	(((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
5306 
5307 #define	S_FW_ACL_VLAN_CMD_VFN		0
5308 #define	M_FW_ACL_VLAN_CMD_VFN		0xff
5309 #define	V_FW_ACL_VLAN_CMD_VFN(x)	((x) << S_FW_ACL_VLAN_CMD_VFN)
5310 #define	G_FW_ACL_VLAN_CMD_VFN(x)	\
5311 	(((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
5312 
5313 #define	S_FW_ACL_VLAN_CMD_EN	31
5314 #define	M_FW_ACL_VLAN_CMD_EN	0x1
5315 #define	V_FW_ACL_VLAN_CMD_EN(x)	((x) << S_FW_ACL_VLAN_CMD_EN)
5316 #define	G_FW_ACL_VLAN_CMD_EN(x)	\
5317 	(((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
5318 #define	F_FW_ACL_VLAN_CMD_EN	V_FW_ACL_VLAN_CMD_EN(1U)
5319 
5320 #define	S_FW_ACL_VLAN_CMD_DROPNOVLAN	7
5321 #define	M_FW_ACL_VLAN_CMD_DROPNOVLAN	0x1
5322 #define	V_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
5323 #define	G_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	\
5324 	(((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
5325 #define	F_FW_ACL_VLAN_CMD_DROPNOVLAN	V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
5326 
5327 #define	S_FW_ACL_VLAN_CMD_FM	6
5328 #define	M_FW_ACL_VLAN_CMD_FM	0x1
5329 #define	V_FW_ACL_VLAN_CMD_FM(x)	((x) << S_FW_ACL_VLAN_CMD_FM)
5330 #define	G_FW_ACL_VLAN_CMD_FM(x)	\
5331 	(((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
5332 #define	F_FW_ACL_VLAN_CMD_FM	V_FW_ACL_VLAN_CMD_FM(1U)
5333 
5334 /* port capabilities bitmap */
5335 enum fw_port_cap {
5336 	FW_PORT_CAP_SPEED_100M		= 0x0001,
5337 	FW_PORT_CAP_SPEED_1G		= 0x0002,
5338 	FW_PORT_CAP_SPEED_2_5G		= 0x0004,
5339 	FW_PORT_CAP_SPEED_10G		= 0x0008,
5340 	FW_PORT_CAP_SPEED_40G		= 0x0010,
5341 	FW_PORT_CAP_SPEED_100G		= 0x0020,
5342 	FW_PORT_CAP_FC_RX		= 0x0040,
5343 	FW_PORT_CAP_FC_TX		= 0x0080,
5344 	FW_PORT_CAP_ANEG		= 0x0100,
5345 	FW_PORT_CAP_MDIX		= 0x0200,
5346 	FW_PORT_CAP_MDIAUTO		= 0x0400,
5347 	FW_PORT_CAP_FEC			= 0x0800,
5348 	FW_PORT_CAP_TECHKR		= 0x1000,
5349 	FW_PORT_CAP_TECHKX4		= 0x2000,
5350 };
5351 
5352 #define	S_FW_PORT_AUXLINFO_MDI		3
5353 #define	M_FW_PORT_AUXLINFO_MDI		0x3
5354 #define	V_FW_PORT_AUXLINFO_MDI(x)	((x) << S_FW_PORT_AUXLINFO_MDI)
5355 #define	G_FW_PORT_AUXLINFO_MDI(x) \
5356 	(((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI)
5357 
5358 #define	S_FW_PORT_AUXLINFO_KX4		2
5359 #define	M_FW_PORT_AUXLINFO_KX4		0x1
5360 #define	V_FW_PORT_AUXLINFO_KX4(x)	((x) << S_FW_PORT_AUXLINFO_KX4)
5361 #define	G_FW_PORT_AUXLINFO_KX4(x) \
5362 	(((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
5363 #define	F_FW_PORT_AUXLINFO_KX4		V_FW_PORT_AUXLINFO_KX4(1U)
5364 
5365 #define	S_FW_PORT_AUXLINFO_KR		1
5366 #define	M_FW_PORT_AUXLINFO_KR		0x1
5367 #define	V_FW_PORT_AUXLINFO_KR(x)	((x) << S_FW_PORT_AUXLINFO_KR)
5368 #define	G_FW_PORT_AUXLINFO_KR(x) \
5369 	(((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
5370 #define	F_FW_PORT_AUXLINFO_KR		V_FW_PORT_AUXLINFO_KR(1U)
5371 
5372 #define	S_FW_PORT_AUXLINFO_FEC		0
5373 #define	M_FW_PORT_AUXLINFO_FEC		0x1
5374 #define	V_FW_PORT_AUXLINFO_FEC(x)	((x) << S_FW_PORT_AUXLINFO_FEC)
5375 #define	G_FW_PORT_AUXLINFO_FEC(x) \
5376 	(((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC)
5377 #define	F_FW_PORT_AUXLINFO_FEC		V_FW_PORT_AUXLINFO_FEC(1U)
5378 
5379 #define	S_FW_PORT_RCAP_AUX	11
5380 #define	M_FW_PORT_RCAP_AUX	0x7
5381 #define	V_FW_PORT_RCAP_AUX(x)	((x) << S_FW_PORT_RCAP_AUX)
5382 #define	G_FW_PORT_RCAP_AUX(x) \
5383 	(((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX)
5384 
5385 #define	S_FW_PORT_CAP_SPEED	0
5386 #define	M_FW_PORT_CAP_SPEED	0x3f
5387 #define	V_FW_PORT_CAP_SPEED(x)	((x) << S_FW_PORT_CAP_SPEED)
5388 #define	G_FW_PORT_CAP_SPEED(x) \
5389 	(((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
5390 
5391 #define	S_FW_PORT_CAP_FC	6
5392 #define	M_FW_PORT_CAP_FC	0x3
5393 #define	V_FW_PORT_CAP_FC(x)	((x) << S_FW_PORT_CAP_FC)
5394 #define	G_FW_PORT_CAP_FC(x) \
5395 	(((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
5396 
5397 #define	S_FW_PORT_CAP_ANEG	8
5398 #define	M_FW_PORT_CAP_ANEG	0x1
5399 #define	V_FW_PORT_CAP_ANEG(x)	((x) << S_FW_PORT_CAP_ANEG)
5400 #define	G_FW_PORT_CAP_ANEG(x) \
5401 	(((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
5402 
5403 enum fw_port_mdi {
5404 	FW_PORT_CAP_MDI_UNCHANGED,
5405 	FW_PORT_CAP_MDI_AUTO,
5406 	FW_PORT_CAP_MDI_F_STRAIGHT,
5407 	FW_PORT_CAP_MDI_F_CROSSOVER
5408 };
5409 
5410 #define	S_FW_PORT_CAP_MDI 9
5411 #define	M_FW_PORT_CAP_MDI 3
5412 #define	V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
5413 #define	G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
5414 
5415 enum fw_port_action {
5416 	FW_PORT_ACTION_L1_CFG		= 0x0001,
5417 	FW_PORT_ACTION_L2_CFG		= 0x0002,
5418 	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
5419 	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
5420 	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
5421 	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
5422 	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
5423 	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
5424 	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
5425 	FW_PORT_ACTION_L1_SS_LPBK_ASIC	= 0x0021,
5426 	FW_PORT_ACTION_MAC_LPBK		= 0x0022,
5427 	FW_PORT_ACTION_L1_WS_LPBK_ASIC	= 0x0023,
5428 	FW_PORT_ACTION_L1_EXT_LPBK	= 0x0026,
5429 	FW_PORT_ACTION_PCS_LPBK		= 0x0028,
5430 	FW_PORT_ACTION_PHY_RESET	= 0x0040,
5431 	FW_PORT_ACTION_PMA_RESET	= 0x0041,
5432 	FW_PORT_ACTION_PCS_RESET	= 0x0042,
5433 	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
5434 	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
5435 	FW_PORT_ACTION_AN_RESET		= 0x0045
5436 };
5437 
5438 enum fw_port_l2cfg_ctlbf {
5439 	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
5440 	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
5441 	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
5442 	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
5443 	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
5444 	FW_PORT_L2_CTLBF_TXIPG	= 0x20,
5445 	FW_PORT_L2_CTLBF_MTU	= 0x40
5446 };
5447 
5448 enum fw_port_dcb_cfg {
5449 	FW_PORT_DCB_CFG_PG	= 0x01,
5450 	FW_PORT_DCB_CFG_PFC	= 0x02,
5451 	FW_PORT_DCB_CFG_APPL	= 0x04
5452 };
5453 
5454 enum fw_port_dcb_cfg_rc {
5455 	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
5456 	FW_PORT_DCB_CFG_ERROR	= 0x1
5457 };
5458 
5459 enum fw_port_dcb_type {
5460 	FW_PORT_DCB_TYPE_PGID		= 0x00,
5461 	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
5462 	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
5463 	FW_PORT_DCB_TYPE_PFC		= 0x03,
5464 	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
5465 };
5466 
5467 struct fw_port_cmd {
5468 	__be32 op_to_portid;
5469 	__be32 action_to_len16;
5470 	union fw_port {
5471 		struct fw_port_l1cfg {
5472 			__be32 rcap;
5473 			__be32 r;
5474 		} l1cfg;
5475 		struct fw_port_l2cfg {
5476 			__u8   ctlbf;
5477 			__u8   ovlan3_to_ivlan0;
5478 			__be16 ivlantype;
5479 			__be16 txipg_force_pinfo;
5480 			__be16 mtu;
5481 			__be16 ovlan0mask;
5482 			__be16 ovlan0type;
5483 			__be16 ovlan1mask;
5484 			__be16 ovlan1type;
5485 			__be16 ovlan2mask;
5486 			__be16 ovlan2type;
5487 			__be16 ovlan3mask;
5488 			__be16 ovlan3type;
5489 		} l2cfg;
5490 		struct fw_port_info {
5491 			__be32 lstatus_to_modtype;
5492 			__be16 pcap;
5493 			__be16 acap;
5494 			__be16 mtu;
5495 			__u8   cbllen;
5496 			__u8   auxlinfo;
5497 			__be32 r8;
5498 			__be64 r9;
5499 		} info;
5500 		union fw_port_dcb {
5501 			struct fw_port_dcb_pgid {
5502 				__u8   type;
5503 				__u8   apply_pkd;
5504 				__u8   r10_lo[2];
5505 				__be32 pgid;
5506 				__be64 r11;
5507 			} pgid;
5508 			struct fw_port_dcb_pgrate {
5509 				__u8   type;
5510 				__u8   apply_pkd;
5511 				__u8   r10_lo[5];
5512 				__u8   num_tcs_supported;
5513 				__u8   pgrate[8];
5514 			} pgrate;
5515 			struct fw_port_dcb_priorate {
5516 				__u8   type;
5517 				__u8   apply_pkd;
5518 				__u8   r10_lo[6];
5519 				__u8   strict_priorate[8];
5520 			} priorate;
5521 			struct fw_port_dcb_pfc {
5522 				__u8   type;
5523 				__u8   pfcen;
5524 				__be16 r10[3];
5525 				__be64 r11;
5526 			} pfc;
5527 			struct fw_port_app_priority {
5528 				__u8   type;
5529 				__u8   r10[2];
5530 				__u8   idx;
5531 				__u8   user_prio_map;
5532 				__u8   sel_field;
5533 				__be16 protocolid;
5534 				__be64 r12;
5535 			} app_priority;
5536 		} dcb;
5537 	} u;
5538 };
5539 
5540 #define	S_FW_PORT_CMD_READ	22
5541 #define	M_FW_PORT_CMD_READ	0x1
5542 #define	V_FW_PORT_CMD_READ(x)	((x) << S_FW_PORT_CMD_READ)
5543 #define	G_FW_PORT_CMD_READ(x)	\
5544 	(((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
5545 #define	F_FW_PORT_CMD_READ	V_FW_PORT_CMD_READ(1U)
5546 
5547 #define	S_FW_PORT_CMD_PORTID	0
5548 #define	M_FW_PORT_CMD_PORTID	0xf
5549 #define	V_FW_PORT_CMD_PORTID(x)	((x) << S_FW_PORT_CMD_PORTID)
5550 #define	G_FW_PORT_CMD_PORTID(x)	\
5551 	(((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
5552 
5553 #define	S_FW_PORT_CMD_ACTION	16
5554 #define	M_FW_PORT_CMD_ACTION	0xffff
5555 #define	V_FW_PORT_CMD_ACTION(x)	((x) << S_FW_PORT_CMD_ACTION)
5556 #define	G_FW_PORT_CMD_ACTION(x)	\
5557 	(((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
5558 
5559 #define	S_FW_PORT_CMD_OVLAN3	7
5560 #define	M_FW_PORT_CMD_OVLAN3	0x1
5561 #define	V_FW_PORT_CMD_OVLAN3(x)	((x) << S_FW_PORT_CMD_OVLAN3)
5562 #define	G_FW_PORT_CMD_OVLAN3(x)	\
5563 	(((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
5564 #define	F_FW_PORT_CMD_OVLAN3	V_FW_PORT_CMD_OVLAN3(1U)
5565 
5566 #define	S_FW_PORT_CMD_OVLAN2	6
5567 #define	M_FW_PORT_CMD_OVLAN2	0x1
5568 #define	V_FW_PORT_CMD_OVLAN2(x)	((x) << S_FW_PORT_CMD_OVLAN2)
5569 #define	G_FW_PORT_CMD_OVLAN2(x)	\
5570 	(((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
5571 #define	F_FW_PORT_CMD_OVLAN2	V_FW_PORT_CMD_OVLAN2(1U)
5572 
5573 #define	S_FW_PORT_CMD_OVLAN1	5
5574 #define	M_FW_PORT_CMD_OVLAN1	0x1
5575 #define	V_FW_PORT_CMD_OVLAN1(x)	((x) << S_FW_PORT_CMD_OVLAN1)
5576 #define	G_FW_PORT_CMD_OVLAN1(x)	\
5577 	(((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
5578 #define	F_FW_PORT_CMD_OVLAN1	V_FW_PORT_CMD_OVLAN1(1U)
5579 
5580 #define	S_FW_PORT_CMD_OVLAN0	4
5581 #define	M_FW_PORT_CMD_OVLAN0	0x1
5582 #define	V_FW_PORT_CMD_OVLAN0(x)	((x) << S_FW_PORT_CMD_OVLAN0)
5583 #define	G_FW_PORT_CMD_OVLAN0(x)	\
5584 	(((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
5585 #define	F_FW_PORT_CMD_OVLAN0	V_FW_PORT_CMD_OVLAN0(1U)
5586 
5587 #define	S_FW_PORT_CMD_IVLAN0	3
5588 #define	M_FW_PORT_CMD_IVLAN0	0x1
5589 #define	V_FW_PORT_CMD_IVLAN0(x)	((x) << S_FW_PORT_CMD_IVLAN0)
5590 #define	G_FW_PORT_CMD_IVLAN0(x)	\
5591 	(((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
5592 #define	F_FW_PORT_CMD_IVLAN0	V_FW_PORT_CMD_IVLAN0(1U)
5593 
5594 #define	S_FW_PORT_CMD_TXIPG	3
5595 #define	M_FW_PORT_CMD_TXIPG	0x1fff
5596 #define	V_FW_PORT_CMD_TXIPG(x)	((x) << S_FW_PORT_CMD_TXIPG)
5597 #define	G_FW_PORT_CMD_TXIPG(x)	\
5598 	(((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
5599 
5600 #define	S_FW_PORT_CMD_FORCE_PINFO	0
5601 #define	M_FW_PORT_CMD_FORCE_PINFO	0x1
5602 #define	V_FW_PORT_CMD_FORCE_PINFO(x)	((x) << S_FW_PORT_CMD_FORCE_PINFO)
5603 #define	G_FW_PORT_CMD_FORCE_PINFO(x)	\
5604 	(((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
5605 #define	F_FW_PORT_CMD_FORCE_PINFO	V_FW_PORT_CMD_FORCE_PINFO(1U)
5606 
5607 #define	S_FW_PORT_CMD_LSTATUS		31
5608 #define	M_FW_PORT_CMD_LSTATUS		0x1
5609 #define	V_FW_PORT_CMD_LSTATUS(x)	((x) << S_FW_PORT_CMD_LSTATUS)
5610 #define	G_FW_PORT_CMD_LSTATUS(x)	\
5611 	(((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
5612 #define	F_FW_PORT_CMD_LSTATUS	V_FW_PORT_CMD_LSTATUS(1U)
5613 
5614 #define	S_FW_PORT_CMD_LSPEED	24
5615 #define	M_FW_PORT_CMD_LSPEED	0x3f
5616 #define	V_FW_PORT_CMD_LSPEED(x)	((x) << S_FW_PORT_CMD_LSPEED)
5617 #define	G_FW_PORT_CMD_LSPEED(x)	\
5618 	(((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
5619 
5620 #define	S_FW_PORT_CMD_TXPAUSE		23
5621 #define	M_FW_PORT_CMD_TXPAUSE		0x1
5622 #define	V_FW_PORT_CMD_TXPAUSE(x)	((x) << S_FW_PORT_CMD_TXPAUSE)
5623 #define	G_FW_PORT_CMD_TXPAUSE(x)	\
5624 	(((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
5625 #define	F_FW_PORT_CMD_TXPAUSE	V_FW_PORT_CMD_TXPAUSE(1U)
5626 
5627 #define	S_FW_PORT_CMD_RXPAUSE		22
5628 #define	M_FW_PORT_CMD_RXPAUSE		0x1
5629 #define	V_FW_PORT_CMD_RXPAUSE(x)	((x) << S_FW_PORT_CMD_RXPAUSE)
5630 #define	G_FW_PORT_CMD_RXPAUSE(x)	\
5631 	(((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
5632 #define	F_FW_PORT_CMD_RXPAUSE	V_FW_PORT_CMD_RXPAUSE(1U)
5633 
5634 #define	S_FW_PORT_CMD_MDIOCAP		21
5635 #define	M_FW_PORT_CMD_MDIOCAP		0x1
5636 #define	V_FW_PORT_CMD_MDIOCAP(x)	((x) << S_FW_PORT_CMD_MDIOCAP)
5637 #define	G_FW_PORT_CMD_MDIOCAP(x)	\
5638 	(((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
5639 #define	F_FW_PORT_CMD_MDIOCAP	V_FW_PORT_CMD_MDIOCAP(1U)
5640 
5641 #define	S_FW_PORT_CMD_MDIOADDR		16
5642 #define	M_FW_PORT_CMD_MDIOADDR		0x1f
5643 #define	V_FW_PORT_CMD_MDIOADDR(x)	((x) << S_FW_PORT_CMD_MDIOADDR)
5644 #define	G_FW_PORT_CMD_MDIOADDR(x)	\
5645 	(((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
5646 
5647 #define	S_FW_PORT_CMD_LPTXPAUSE		15
5648 #define	M_FW_PORT_CMD_LPTXPAUSE		0x1
5649 #define	V_FW_PORT_CMD_LPTXPAUSE(x)	((x) << S_FW_PORT_CMD_LPTXPAUSE)
5650 #define	G_FW_PORT_CMD_LPTXPAUSE(x)	\
5651 	(((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
5652 #define	F_FW_PORT_CMD_LPTXPAUSE	V_FW_PORT_CMD_LPTXPAUSE(1U)
5653 
5654 #define	S_FW_PORT_CMD_LPRXPAUSE		14
5655 #define	M_FW_PORT_CMD_LPRXPAUSE		0x1
5656 #define	V_FW_PORT_CMD_LPRXPAUSE(x)	((x) << S_FW_PORT_CMD_LPRXPAUSE)
5657 #define	G_FW_PORT_CMD_LPRXPAUSE(x)	\
5658 	(((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
5659 #define	F_FW_PORT_CMD_LPRXPAUSE	V_FW_PORT_CMD_LPRXPAUSE(1U)
5660 
5661 #define	S_FW_PORT_CMD_PTYPE	8
5662 #define	M_FW_PORT_CMD_PTYPE	0x1f
5663 #define	V_FW_PORT_CMD_PTYPE(x)	((x) << S_FW_PORT_CMD_PTYPE)
5664 #define	G_FW_PORT_CMD_PTYPE(x)	\
5665 	(((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
5666 
5667 #define	S_FW_PORT_CMD_LINKDNRC		5
5668 #define	M_FW_PORT_CMD_LINKDNRC		0x7
5669 #define	V_FW_PORT_CMD_LINKDNRC(x)	((x) << S_FW_PORT_CMD_LINKDNRC)
5670 #define	G_FW_PORT_CMD_LINKDNRC(x)	\
5671 	(((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
5672 
5673 #define	S_FW_PORT_CMD_MODTYPE		0
5674 #define	M_FW_PORT_CMD_MODTYPE		0x1f
5675 #define	V_FW_PORT_CMD_MODTYPE(x)	((x) << S_FW_PORT_CMD_MODTYPE)
5676 #define	G_FW_PORT_CMD_MODTYPE(x)	\
5677 	(((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
5678 
5679 #define	S_FW_PORT_CMD_APPLY	7
5680 #define	M_FW_PORT_CMD_APPLY	0x1
5681 #define	V_FW_PORT_CMD_APPLY(x)	((x) << S_FW_PORT_CMD_APPLY)
5682 #define	G_FW_PORT_CMD_APPLY(x)	\
5683 	(((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
5684 #define	F_FW_PORT_CMD_APPLY	V_FW_PORT_CMD_APPLY(1U)
5685 
5686 /*
5687  *	These are configured into the VPD and hence tools that generate
5688  *	VPD may use this enumeration.
5689  *	extPHY	#lanes	T4_I2C	extI2C	BP_Eq	BP_ANEG	Speed
5690  */
5691 enum fw_port_type {
5692 	FW_PORT_TYPE_FIBER_XFI	=  0,	/* Y, 1, N, Y, N, N, 10G */
5693 	FW_PORT_TYPE_FIBER_XAUI	=  1,	/* Y, 4, N, Y, N, N, 10G */
5694 	FW_PORT_TYPE_BT_SGMII	=  2,	/* Y, 1, No, No, No, No, 1G/100M */
5695 	FW_PORT_TYPE_BT_XFI	=  3,	/* Y, 1, No, No, No, No, 10G */
5696 	FW_PORT_TYPE_BT_XAUI	=  4,	/* Y, 4, No, No, No, No, 10G/1G/100M? */
5697 	FW_PORT_TYPE_KX4	=  5,	/* No, 4, No, No, Yes, Yes, 10G */
5698 	FW_PORT_TYPE_CX4	=  6,	/* No, 4, No, No, No, No, 10G */
5699 	FW_PORT_TYPE_KX		=  7,	/* No, 1, No, No, Yes, No, 1G */
5700 	FW_PORT_TYPE_KR		=  8,	/* No, 1, No, No, Yes, Yes, 10G */
5701 	FW_PORT_TYPE_SFP	=  9,	/* No, 1, Yes, No, No, No, 10G */
5702 	/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
5703 	FW_PORT_TYPE_BP_AP	= 10,
5704 	/* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
5705 	FW_PORT_TYPE_BP4_AP	= 11,
5706 
5707 	FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
5708 };
5709 
5710 /*
5711  * These are read from module's EEPROM and determined once the module is
5712  * inserted.
5713  */
5714 enum fw_port_module_type {
5715 	FW_PORT_MOD_TYPE_NA		= 0x0,
5716 	FW_PORT_MOD_TYPE_LR		= 0x1,
5717 	FW_PORT_MOD_TYPE_SR		= 0x2,
5718 	FW_PORT_MOD_TYPE_ER		= 0x3,
5719 	FW_PORT_MOD_TYPE_TWINAX_PASSIVE	= 0x4,
5720 	FW_PORT_MOD_TYPE_TWINAX_ACTIVE	= 0x5,
5721 	FW_PORT_MOD_TYPE_LRM		= 0x6,
5722 	FW_PORT_MOD_TYPE_ERROR		= M_FW_PORT_CMD_MODTYPE - 3,
5723 	FW_PORT_MOD_TYPE_UNKNOWN	= M_FW_PORT_CMD_MODTYPE - 2,
5724 	FW_PORT_MOD_TYPE_NOTSUPPORTED	= M_FW_PORT_CMD_MODTYPE - 1,
5725 	FW_PORT_MOD_TYPE_NONE		= M_FW_PORT_CMD_MODTYPE
5726 };
5727 
5728 /* used by FW and tools may use this to generate VPD */
5729 enum fw_port_mod_sub_type {
5730 	FW_PORT_MOD_SUB_TYPE_NA,
5731 	FW_PORT_MOD_SUB_TYPE_MV88E114X  = 0x1,
5732 	FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
5733 
5734 	/*
5735 	 * The following will never been in the VPD.  They are TWINAX cable
5736 	 * lengths decoded from SFP+ module i2c PROMs.  These should almost
5737 	 * certainly go somewhere else ...
5738 	 */
5739 	FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
5740 	FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
5741 	FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
5742 	FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
5743 };
5744 
5745 /* link down reason codes (3b) */
5746 enum fw_port_link_dn_rc {
5747 	FW_PORT_LINK_DN_RC_NONE,
5748 	FW_PORT_LINK_DN_RC_REMFLT,
5749 	FW_PORT_LINK_DN_ANEG_F,
5750 	FW_PORT_LINK_DN_MS_RES_F,
5751 	FW_PORT_LINK_DN_UNKNOWN
5752 };
5753 
5754 /* port stats */
5755 #define	FW_NUM_PORT_STATS 50
5756 #define	FW_NUM_PORT_TX_STATS 23
5757 #define	FW_NUM_PORT_RX_STATS 27
5758 
5759 enum fw_port_stats_tx_index {
5760 	FW_STAT_TX_PORT_BYTES_IX,
5761 	FW_STAT_TX_PORT_FRAMES_IX,
5762 	FW_STAT_TX_PORT_BCAST_IX,
5763 	FW_STAT_TX_PORT_MCAST_IX,
5764 	FW_STAT_TX_PORT_UCAST_IX,
5765 	FW_STAT_TX_PORT_ERROR_IX,
5766 	FW_STAT_TX_PORT_64B_IX,
5767 	FW_STAT_TX_PORT_65B_127B_IX,
5768 	FW_STAT_TX_PORT_128B_255B_IX,
5769 	FW_STAT_TX_PORT_256B_511B_IX,
5770 	FW_STAT_TX_PORT_512B_1023B_IX,
5771 	FW_STAT_TX_PORT_1024B_1518B_IX,
5772 	FW_STAT_TX_PORT_1519B_MAX_IX,
5773 	FW_STAT_TX_PORT_DROP_IX,
5774 	FW_STAT_TX_PORT_PAUSE_IX,
5775 	FW_STAT_TX_PORT_PPP0_IX,
5776 	FW_STAT_TX_PORT_PPP1_IX,
5777 	FW_STAT_TX_PORT_PPP2_IX,
5778 	FW_STAT_TX_PORT_PPP3_IX,
5779 	FW_STAT_TX_PORT_PPP4_IX,
5780 	FW_STAT_TX_PORT_PPP5_IX,
5781 	FW_STAT_TX_PORT_PPP6_IX,
5782 	FW_STAT_TX_PORT_PPP7_IX
5783 };
5784 
5785 enum fw_port_stat_rx_index {
5786 	FW_STAT_RX_PORT_BYTES_IX,
5787 	FW_STAT_RX_PORT_FRAMES_IX,
5788 	FW_STAT_RX_PORT_BCAST_IX,
5789 	FW_STAT_RX_PORT_MCAST_IX,
5790 	FW_STAT_RX_PORT_UCAST_IX,
5791 	FW_STAT_RX_PORT_MTU_ERROR_IX,
5792 	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
5793 	FW_STAT_RX_PORT_CRC_ERROR_IX,
5794 	FW_STAT_RX_PORT_LEN_ERROR_IX,
5795 	FW_STAT_RX_PORT_SYM_ERROR_IX,
5796 	FW_STAT_RX_PORT_64B_IX,
5797 	FW_STAT_RX_PORT_65B_127B_IX,
5798 	FW_STAT_RX_PORT_128B_255B_IX,
5799 	FW_STAT_RX_PORT_256B_511B_IX,
5800 	FW_STAT_RX_PORT_512B_1023B_IX,
5801 	FW_STAT_RX_PORT_1024B_1518B_IX,
5802 	FW_STAT_RX_PORT_1519B_MAX_IX,
5803 	FW_STAT_RX_PORT_PAUSE_IX,
5804 	FW_STAT_RX_PORT_PPP0_IX,
5805 	FW_STAT_RX_PORT_PPP1_IX,
5806 	FW_STAT_RX_PORT_PPP2_IX,
5807 	FW_STAT_RX_PORT_PPP3_IX,
5808 	FW_STAT_RX_PORT_PPP4_IX,
5809 	FW_STAT_RX_PORT_PPP5_IX,
5810 	FW_STAT_RX_PORT_PPP6_IX,
5811 	FW_STAT_RX_PORT_PPP7_IX,
5812 	FW_STAT_RX_PORT_LESS_64B_IX
5813 };
5814 
5815 struct fw_port_stats_cmd {
5816 	__be32 op_to_portid;
5817 	__be32 retval_len16;
5818 	union fw_port_stats {
5819 		struct fw_port_stats_ctl {
5820 			__u8   nstats_bg_bm;
5821 			__u8   tx_ix;
5822 			__be16 r6;
5823 			__be32 r7;
5824 			__be64 stat0;
5825 			__be64 stat1;
5826 			__be64 stat2;
5827 			__be64 stat3;
5828 			__be64 stat4;
5829 			__be64 stat5;
5830 		} ctl;
5831 		struct fw_port_stats_all {
5832 			__be64 tx_bytes;
5833 			__be64 tx_frames;
5834 			__be64 tx_bcast;
5835 			__be64 tx_mcast;
5836 			__be64 tx_ucast;
5837 			__be64 tx_error;
5838 			__be64 tx_64b;
5839 			__be64 tx_65b_127b;
5840 			__be64 tx_128b_255b;
5841 			__be64 tx_256b_511b;
5842 			__be64 tx_512b_1023b;
5843 			__be64 tx_1024b_1518b;
5844 			__be64 tx_1519b_max;
5845 			__be64 tx_drop;
5846 			__be64 tx_pause;
5847 			__be64 tx_ppp0;
5848 			__be64 tx_ppp1;
5849 			__be64 tx_ppp2;
5850 			__be64 tx_ppp3;
5851 			__be64 tx_ppp4;
5852 			__be64 tx_ppp5;
5853 			__be64 tx_ppp6;
5854 			__be64 tx_ppp7;
5855 			__be64 rx_bytes;
5856 			__be64 rx_frames;
5857 			__be64 rx_bcast;
5858 			__be64 rx_mcast;
5859 			__be64 rx_ucast;
5860 			__be64 rx_mtu_error;
5861 			__be64 rx_mtu_crc_error;
5862 			__be64 rx_crc_error;
5863 			__be64 rx_len_error;
5864 			__be64 rx_sym_error;
5865 			__be64 rx_64b;
5866 			__be64 rx_65b_127b;
5867 			__be64 rx_128b_255b;
5868 			__be64 rx_256b_511b;
5869 			__be64 rx_512b_1023b;
5870 			__be64 rx_1024b_1518b;
5871 			__be64 rx_1519b_max;
5872 			__be64 rx_pause;
5873 			__be64 rx_ppp0;
5874 			__be64 rx_ppp1;
5875 			__be64 rx_ppp2;
5876 			__be64 rx_ppp3;
5877 			__be64 rx_ppp4;
5878 			__be64 rx_ppp5;
5879 			__be64 rx_ppp6;
5880 			__be64 rx_ppp7;
5881 			__be64 rx_less_64b;
5882 			__be64 rx_bg_drop;
5883 			__be64 rx_bg_trunc;
5884 		} all;
5885 	} u;
5886 };
5887 
5888 #define	S_FW_PORT_STATS_CMD_NSTATS	4
5889 #define	M_FW_PORT_STATS_CMD_NSTATS	0x7
5890 #define	V_FW_PORT_STATS_CMD_NSTATS(x)	((x) << S_FW_PORT_STATS_CMD_NSTATS)
5891 #define	G_FW_PORT_STATS_CMD_NSTATS(x)	\
5892 	(((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
5893 
5894 #define	S_FW_PORT_STATS_CMD_BG_BM	0
5895 #define	M_FW_PORT_STATS_CMD_BG_BM	0x3
5896 #define	V_FW_PORT_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_STATS_CMD_BG_BM)
5897 #define	G_FW_PORT_STATS_CMD_BG_BM(x)	\
5898 	(((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
5899 
5900 #define	S_FW_PORT_STATS_CMD_TX		7
5901 #define	M_FW_PORT_STATS_CMD_TX		0x1
5902 #define	V_FW_PORT_STATS_CMD_TX(x)	((x) << S_FW_PORT_STATS_CMD_TX)
5903 #define	G_FW_PORT_STATS_CMD_TX(x)	\
5904 	(((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
5905 #define	F_FW_PORT_STATS_CMD_TX	V_FW_PORT_STATS_CMD_TX(1U)
5906 
5907 #define	S_FW_PORT_STATS_CMD_IX		0
5908 #define	M_FW_PORT_STATS_CMD_IX		0x3f
5909 #define	V_FW_PORT_STATS_CMD_IX(x)	((x) << S_FW_PORT_STATS_CMD_IX)
5910 #define	G_FW_PORT_STATS_CMD_IX(x)	\
5911 	(((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
5912 
5913 /* port loopback stats */
5914 #define	FW_NUM_LB_STATS 14
5915 enum fw_port_lb_stats_index {
5916 	FW_STAT_LB_PORT_BYTES_IX,
5917 	FW_STAT_LB_PORT_FRAMES_IX,
5918 	FW_STAT_LB_PORT_BCAST_IX,
5919 	FW_STAT_LB_PORT_MCAST_IX,
5920 	FW_STAT_LB_PORT_UCAST_IX,
5921 	FW_STAT_LB_PORT_ERROR_IX,
5922 	FW_STAT_LB_PORT_64B_IX,
5923 	FW_STAT_LB_PORT_65B_127B_IX,
5924 	FW_STAT_LB_PORT_128B_255B_IX,
5925 	FW_STAT_LB_PORT_256B_511B_IX,
5926 	FW_STAT_LB_PORT_512B_1023B_IX,
5927 	FW_STAT_LB_PORT_1024B_1518B_IX,
5928 	FW_STAT_LB_PORT_1519B_MAX_IX,
5929 	FW_STAT_LB_PORT_DROP_FRAMES_IX
5930 };
5931 
5932 struct fw_port_lb_stats_cmd {
5933 	__be32 op_to_lbport;
5934 	__be32 retval_len16;
5935 	union fw_port_lb_stats {
5936 		struct fw_port_lb_stats_ctl {
5937 			__u8   nstats_bg_bm;
5938 			__u8   ix_pkd;
5939 			__be16 r6;
5940 			__be32 r7;
5941 			__be64 stat0;
5942 			__be64 stat1;
5943 			__be64 stat2;
5944 			__be64 stat3;
5945 			__be64 stat4;
5946 			__be64 stat5;
5947 		} ctl;
5948 		struct fw_port_lb_stats_all {
5949 			__be64 tx_bytes;
5950 			__be64 tx_frames;
5951 			__be64 tx_bcast;
5952 			__be64 tx_mcast;
5953 			__be64 tx_ucast;
5954 			__be64 tx_error;
5955 			__be64 tx_64b;
5956 			__be64 tx_65b_127b;
5957 			__be64 tx_128b_255b;
5958 			__be64 tx_256b_511b;
5959 			__be64 tx_512b_1023b;
5960 			__be64 tx_1024b_1518b;
5961 			__be64 tx_1519b_max;
5962 			__be64 rx_lb_drop;
5963 			__be64 rx_lb_trunc;
5964 		} all;
5965 	} u;
5966 };
5967 
5968 #define	S_FW_PORT_LB_STATS_CMD_LBPORT		0
5969 #define	M_FW_PORT_LB_STATS_CMD_LBPORT		0xf
5970 #define	V_FW_PORT_LB_STATS_CMD_LBPORT(x)	\
5971 	((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
5972 #define	G_FW_PORT_LB_STATS_CMD_LBPORT(x)	\
5973 	(((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
5974 
5975 #define	S_FW_PORT_LB_STATS_CMD_NSTATS		4
5976 #define	M_FW_PORT_LB_STATS_CMD_NSTATS		0x7
5977 #define	V_FW_PORT_LB_STATS_CMD_NSTATS(x)	\
5978 	((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
5979 #define	G_FW_PORT_LB_STATS_CMD_NSTATS(x)	\
5980 	(((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
5981 
5982 #define	S_FW_PORT_LB_STATS_CMD_BG_BM	0
5983 #define	M_FW_PORT_LB_STATS_CMD_BG_BM	0x3
5984 #define	V_FW_PORT_LB_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
5985 #define	G_FW_PORT_LB_STATS_CMD_BG_BM(x)	\
5986 	(((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
5987 
5988 #define	S_FW_PORT_LB_STATS_CMD_IX	0
5989 #define	M_FW_PORT_LB_STATS_CMD_IX	0xf
5990 #define	V_FW_PORT_LB_STATS_CMD_IX(x)	((x) << S_FW_PORT_LB_STATS_CMD_IX)
5991 #define	G_FW_PORT_LB_STATS_CMD_IX(x)	\
5992 	(((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
5993 
5994 /* Trace related defines */
5995 #define	FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
5996 #define	FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE  2560
5997 
5998 struct fw_port_trace_cmd {
5999 	__be32 op_to_portid;
6000 	__be32 retval_len16;
6001 	__be16 traceen_to_pciech;
6002 	__be16 qnum;
6003 	__be32 r5;
6004 };
6005 
6006 #define	S_FW_PORT_TRACE_CMD_PORTID	0
6007 #define	M_FW_PORT_TRACE_CMD_PORTID	0xf
6008 #define	V_FW_PORT_TRACE_CMD_PORTID(x)	((x) << S_FW_PORT_TRACE_CMD_PORTID)
6009 #define	G_FW_PORT_TRACE_CMD_PORTID(x)	\
6010 	(((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
6011 
6012 #define	S_FW_PORT_TRACE_CMD_TRACEEN	15
6013 #define	M_FW_PORT_TRACE_CMD_TRACEEN	0x1
6014 #define	V_FW_PORT_TRACE_CMD_TRACEEN(x)	((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
6015 #define	G_FW_PORT_TRACE_CMD_TRACEEN(x)	\
6016 	(((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
6017 #define	F_FW_PORT_TRACE_CMD_TRACEEN	V_FW_PORT_TRACE_CMD_TRACEEN(1U)
6018 
6019 #define	S_FW_PORT_TRACE_CMD_FLTMODE	14
6020 #define	M_FW_PORT_TRACE_CMD_FLTMODE	0x1
6021 #define	V_FW_PORT_TRACE_CMD_FLTMODE(x)	((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
6022 #define	G_FW_PORT_TRACE_CMD_FLTMODE(x)	\
6023 	(((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
6024 #define	F_FW_PORT_TRACE_CMD_FLTMODE	V_FW_PORT_TRACE_CMD_FLTMODE(1U)
6025 
6026 #define	S_FW_PORT_TRACE_CMD_DUPLEN	13
6027 #define	M_FW_PORT_TRACE_CMD_DUPLEN	0x1
6028 #define	V_FW_PORT_TRACE_CMD_DUPLEN(x)	((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
6029 #define	G_FW_PORT_TRACE_CMD_DUPLEN(x)	\
6030 	(((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
6031 #define	F_FW_PORT_TRACE_CMD_DUPLEN	V_FW_PORT_TRACE_CMD_DUPLEN(1U)
6032 
6033 #define	S_FW_PORT_TRACE_CMD_RUNTFLTSIZE		8
6034 #define	M_FW_PORT_TRACE_CMD_RUNTFLTSIZE		0x1f
6035 #define	V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x)	\
6036 	((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
6037 #define	G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x)	\
6038 	(((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
6039 	M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
6040 
6041 #define	S_FW_PORT_TRACE_CMD_PCIECH	6
6042 #define	M_FW_PORT_TRACE_CMD_PCIECH	0x3
6043 #define	V_FW_PORT_TRACE_CMD_PCIECH(x)	((x) << S_FW_PORT_TRACE_CMD_PCIECH)
6044 #define	G_FW_PORT_TRACE_CMD_PCIECH(x)	\
6045 	(((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
6046 
6047 struct fw_port_trace_mmap_cmd {
6048 	__be32 op_to_portid;
6049 	__be32 retval_len16;
6050 	__be32 fid_to_skipoffset;
6051 	__be32 minpktsize_capturemax;
6052 	__u8   map[224];
6053 };
6054 
6055 #define	S_FW_PORT_TRACE_MMAP_CMD_PORTID		0
6056 #define	M_FW_PORT_TRACE_MMAP_CMD_PORTID		0xf
6057 #define	V_FW_PORT_TRACE_MMAP_CMD_PORTID(x)	\
6058 	((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
6059 #define	G_FW_PORT_TRACE_MMAP_CMD_PORTID(x)	\
6060 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
6061 	M_FW_PORT_TRACE_MMAP_CMD_PORTID)
6062 
6063 #define	S_FW_PORT_TRACE_MMAP_CMD_FID	30
6064 #define	M_FW_PORT_TRACE_MMAP_CMD_FID	0x3
6065 #define	V_FW_PORT_TRACE_MMAP_CMD_FID(x)	((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
6066 #define	G_FW_PORT_TRACE_MMAP_CMD_FID(x)	\
6067 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
6068 
6069 #define	S_FW_PORT_TRACE_MMAP_CMD_MMAPEN		29
6070 #define	M_FW_PORT_TRACE_MMAP_CMD_MMAPEN		0x1
6071 #define	V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x)	\
6072 	((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
6073 #define	G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x)	\
6074 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
6075 	M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
6076 #define	F_FW_PORT_TRACE_MMAP_CMD_MMAPEN	V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
6077 
6078 #define	S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN	28
6079 #define	M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN	0x1
6080 #define	V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x)	\
6081 	((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
6082 #define	G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x)	\
6083 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
6084 	M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
6085 #define	F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN	\
6086     V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
6087 
6088 #define	S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH	8
6089 #define	M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH	0x1f
6090 #define	V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x)	\
6091 	((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
6092 #define	G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x)	\
6093 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
6094 	M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
6095 
6096 #define	S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET	0
6097 #define	M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET	0x1f
6098 #define	V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x)	\
6099 	((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
6100 #define	G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x)	\
6101 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
6102 	M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
6103 
6104 #define	S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE	18
6105 #define	M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE	0x3fff
6106 #define	V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x)	\
6107 	((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
6108 #define	G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x)	\
6109 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
6110 	M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
6111 
6112 #define	S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX	0
6113 #define	M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX	0x3fff
6114 #define	V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x)	\
6115 	((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
6116 #define	G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x)	\
6117 	(((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
6118 	M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
6119 
6120 struct fw_rss_ind_tbl_cmd {
6121 	__be32 op_to_viid;
6122 	__be32 retval_len16;
6123 	__be16 niqid;
6124 	__be16 startidx;
6125 	__be32 r3;
6126 	__be32 iq0_to_iq2;
6127 	__be32 iq3_to_iq5;
6128 	__be32 iq6_to_iq8;
6129 	__be32 iq9_to_iq11;
6130 	__be32 iq12_to_iq14;
6131 	__be32 iq15_to_iq17;
6132 	__be32 iq18_to_iq20;
6133 	__be32 iq21_to_iq23;
6134 	__be32 iq24_to_iq26;
6135 	__be32 iq27_to_iq29;
6136 	__be32 iq30_iq31;
6137 	__be32 r15_lo;
6138 };
6139 
6140 #define	S_FW_RSS_IND_TBL_CMD_VIID	0
6141 #define	M_FW_RSS_IND_TBL_CMD_VIID	0xfff
6142 #define	V_FW_RSS_IND_TBL_CMD_VIID(x)	((x) << S_FW_RSS_IND_TBL_CMD_VIID)
6143 #define	G_FW_RSS_IND_TBL_CMD_VIID(x)	\
6144 	(((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
6145 
6146 #define	S_FW_RSS_IND_TBL_CMD_IQ0	20
6147 #define	M_FW_RSS_IND_TBL_CMD_IQ0	0x3ff
6148 #define	V_FW_RSS_IND_TBL_CMD_IQ0(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
6149 #define	G_FW_RSS_IND_TBL_CMD_IQ0(x)	\
6150 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
6151 
6152 #define	S_FW_RSS_IND_TBL_CMD_IQ1	10
6153 #define	M_FW_RSS_IND_TBL_CMD_IQ1	0x3ff
6154 #define	V_FW_RSS_IND_TBL_CMD_IQ1(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
6155 #define	G_FW_RSS_IND_TBL_CMD_IQ1(x)	\
6156 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
6157 
6158 #define	S_FW_RSS_IND_TBL_CMD_IQ2	0
6159 #define	M_FW_RSS_IND_TBL_CMD_IQ2	0x3ff
6160 #define	V_FW_RSS_IND_TBL_CMD_IQ2(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
6161 #define	G_FW_RSS_IND_TBL_CMD_IQ2(x)	\
6162 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
6163 
6164 #define	S_FW_RSS_IND_TBL_CMD_IQ3	20
6165 #define	M_FW_RSS_IND_TBL_CMD_IQ3	0x3ff
6166 #define	V_FW_RSS_IND_TBL_CMD_IQ3(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
6167 #define	G_FW_RSS_IND_TBL_CMD_IQ3(x)	\
6168 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
6169 
6170 #define	S_FW_RSS_IND_TBL_CMD_IQ4	10
6171 #define	M_FW_RSS_IND_TBL_CMD_IQ4	0x3ff
6172 #define	V_FW_RSS_IND_TBL_CMD_IQ4(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
6173 #define	G_FW_RSS_IND_TBL_CMD_IQ4(x)	\
6174 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
6175 
6176 #define	S_FW_RSS_IND_TBL_CMD_IQ5	0
6177 #define	M_FW_RSS_IND_TBL_CMD_IQ5	0x3ff
6178 #define	V_FW_RSS_IND_TBL_CMD_IQ5(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
6179 #define	G_FW_RSS_IND_TBL_CMD_IQ5(x)	\
6180 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
6181 
6182 #define	S_FW_RSS_IND_TBL_CMD_IQ6	20
6183 #define	M_FW_RSS_IND_TBL_CMD_IQ6	0x3ff
6184 #define	V_FW_RSS_IND_TBL_CMD_IQ6(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
6185 #define	G_FW_RSS_IND_TBL_CMD_IQ6(x)	\
6186 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
6187 
6188 #define	S_FW_RSS_IND_TBL_CMD_IQ7	10
6189 #define	M_FW_RSS_IND_TBL_CMD_IQ7	0x3ff
6190 #define	V_FW_RSS_IND_TBL_CMD_IQ7(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
6191 #define	G_FW_RSS_IND_TBL_CMD_IQ7(x)	\
6192 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
6193 
6194 #define	S_FW_RSS_IND_TBL_CMD_IQ8	0
6195 #define	M_FW_RSS_IND_TBL_CMD_IQ8	0x3ff
6196 #define	V_FW_RSS_IND_TBL_CMD_IQ8(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
6197 #define	G_FW_RSS_IND_TBL_CMD_IQ8(x)	\
6198 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
6199 
6200 #define	S_FW_RSS_IND_TBL_CMD_IQ9	20
6201 #define	M_FW_RSS_IND_TBL_CMD_IQ9	0x3ff
6202 #define	V_FW_RSS_IND_TBL_CMD_IQ9(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
6203 #define	G_FW_RSS_IND_TBL_CMD_IQ9(x)	\
6204 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
6205 
6206 #define	S_FW_RSS_IND_TBL_CMD_IQ10	10
6207 #define	M_FW_RSS_IND_TBL_CMD_IQ10	0x3ff
6208 #define	V_FW_RSS_IND_TBL_CMD_IQ10(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
6209 #define	G_FW_RSS_IND_TBL_CMD_IQ10(x)	\
6210 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
6211 
6212 #define	S_FW_RSS_IND_TBL_CMD_IQ11	0
6213 #define	M_FW_RSS_IND_TBL_CMD_IQ11	0x3ff
6214 #define	V_FW_RSS_IND_TBL_CMD_IQ11(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
6215 #define	G_FW_RSS_IND_TBL_CMD_IQ11(x)	\
6216 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
6217 
6218 #define	S_FW_RSS_IND_TBL_CMD_IQ12	20
6219 #define	M_FW_RSS_IND_TBL_CMD_IQ12	0x3ff
6220 #define	V_FW_RSS_IND_TBL_CMD_IQ12(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
6221 #define	G_FW_RSS_IND_TBL_CMD_IQ12(x)	\
6222 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
6223 
6224 #define	S_FW_RSS_IND_TBL_CMD_IQ13	10
6225 #define	M_FW_RSS_IND_TBL_CMD_IQ13	0x3ff
6226 #define	V_FW_RSS_IND_TBL_CMD_IQ13(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
6227 #define	G_FW_RSS_IND_TBL_CMD_IQ13(x)	\
6228 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
6229 
6230 #define	S_FW_RSS_IND_TBL_CMD_IQ14	0
6231 #define	M_FW_RSS_IND_TBL_CMD_IQ14	0x3ff
6232 #define	V_FW_RSS_IND_TBL_CMD_IQ14(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
6233 #define	G_FW_RSS_IND_TBL_CMD_IQ14(x)	\
6234 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
6235 
6236 #define	S_FW_RSS_IND_TBL_CMD_IQ15	20
6237 #define	M_FW_RSS_IND_TBL_CMD_IQ15	0x3ff
6238 #define	V_FW_RSS_IND_TBL_CMD_IQ15(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
6239 #define	G_FW_RSS_IND_TBL_CMD_IQ15(x)	\
6240 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
6241 
6242 #define	S_FW_RSS_IND_TBL_CMD_IQ16	10
6243 #define	M_FW_RSS_IND_TBL_CMD_IQ16	0x3ff
6244 #define	V_FW_RSS_IND_TBL_CMD_IQ16(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
6245 #define	G_FW_RSS_IND_TBL_CMD_IQ16(x)	\
6246 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
6247 
6248 #define	S_FW_RSS_IND_TBL_CMD_IQ17	0
6249 #define	M_FW_RSS_IND_TBL_CMD_IQ17	0x3ff
6250 #define	V_FW_RSS_IND_TBL_CMD_IQ17(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
6251 #define	G_FW_RSS_IND_TBL_CMD_IQ17(x)	\
6252 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
6253 
6254 #define	S_FW_RSS_IND_TBL_CMD_IQ18	20
6255 #define	M_FW_RSS_IND_TBL_CMD_IQ18	0x3ff
6256 #define	V_FW_RSS_IND_TBL_CMD_IQ18(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
6257 #define	G_FW_RSS_IND_TBL_CMD_IQ18(x)	\
6258 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
6259 
6260 #define	S_FW_RSS_IND_TBL_CMD_IQ19	10
6261 #define	M_FW_RSS_IND_TBL_CMD_IQ19	0x3ff
6262 #define	V_FW_RSS_IND_TBL_CMD_IQ19(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
6263 #define	G_FW_RSS_IND_TBL_CMD_IQ19(x)	\
6264 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
6265 
6266 #define	S_FW_RSS_IND_TBL_CMD_IQ20	0
6267 #define	M_FW_RSS_IND_TBL_CMD_IQ20	0x3ff
6268 #define	V_FW_RSS_IND_TBL_CMD_IQ20(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
6269 #define	G_FW_RSS_IND_TBL_CMD_IQ20(x)	\
6270 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
6271 
6272 #define	S_FW_RSS_IND_TBL_CMD_IQ21	20
6273 #define	M_FW_RSS_IND_TBL_CMD_IQ21	0x3ff
6274 #define	V_FW_RSS_IND_TBL_CMD_IQ21(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
6275 #define	G_FW_RSS_IND_TBL_CMD_IQ21(x)	\
6276 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
6277 
6278 #define	S_FW_RSS_IND_TBL_CMD_IQ22	10
6279 #define	M_FW_RSS_IND_TBL_CMD_IQ22	0x3ff
6280 #define	V_FW_RSS_IND_TBL_CMD_IQ22(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
6281 #define	G_FW_RSS_IND_TBL_CMD_IQ22(x)	\
6282 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
6283 
6284 #define	S_FW_RSS_IND_TBL_CMD_IQ23	0
6285 #define	M_FW_RSS_IND_TBL_CMD_IQ23	0x3ff
6286 #define	V_FW_RSS_IND_TBL_CMD_IQ23(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
6287 #define	G_FW_RSS_IND_TBL_CMD_IQ23(x)	\
6288 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
6289 
6290 #define	S_FW_RSS_IND_TBL_CMD_IQ24	20
6291 #define	M_FW_RSS_IND_TBL_CMD_IQ24	0x3ff
6292 #define	V_FW_RSS_IND_TBL_CMD_IQ24(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
6293 #define	G_FW_RSS_IND_TBL_CMD_IQ24(x)	\
6294 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
6295 
6296 #define	S_FW_RSS_IND_TBL_CMD_IQ25	10
6297 #define	M_FW_RSS_IND_TBL_CMD_IQ25	0x3ff
6298 #define	V_FW_RSS_IND_TBL_CMD_IQ25(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
6299 #define	G_FW_RSS_IND_TBL_CMD_IQ25(x)	\
6300 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
6301 
6302 #define	S_FW_RSS_IND_TBL_CMD_IQ26	0
6303 #define	M_FW_RSS_IND_TBL_CMD_IQ26	0x3ff
6304 #define	V_FW_RSS_IND_TBL_CMD_IQ26(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
6305 #define	G_FW_RSS_IND_TBL_CMD_IQ26(x)	\
6306 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
6307 
6308 #define	S_FW_RSS_IND_TBL_CMD_IQ27	20
6309 #define	M_FW_RSS_IND_TBL_CMD_IQ27	0x3ff
6310 #define	V_FW_RSS_IND_TBL_CMD_IQ27(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
6311 #define	G_FW_RSS_IND_TBL_CMD_IQ27(x)	\
6312 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
6313 
6314 #define	S_FW_RSS_IND_TBL_CMD_IQ28	10
6315 #define	M_FW_RSS_IND_TBL_CMD_IQ28	0x3ff
6316 #define	V_FW_RSS_IND_TBL_CMD_IQ28(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
6317 #define	G_FW_RSS_IND_TBL_CMD_IQ28(x)	\
6318 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
6319 
6320 #define	S_FW_RSS_IND_TBL_CMD_IQ29	0
6321 #define	M_FW_RSS_IND_TBL_CMD_IQ29	0x3ff
6322 #define	V_FW_RSS_IND_TBL_CMD_IQ29(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
6323 #define	G_FW_RSS_IND_TBL_CMD_IQ29(x)	\
6324 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
6325 
6326 #define	S_FW_RSS_IND_TBL_CMD_IQ30	20
6327 #define	M_FW_RSS_IND_TBL_CMD_IQ30	0x3ff
6328 #define	V_FW_RSS_IND_TBL_CMD_IQ30(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
6329 #define	G_FW_RSS_IND_TBL_CMD_IQ30(x)	\
6330 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
6331 
6332 #define	S_FW_RSS_IND_TBL_CMD_IQ31	10
6333 #define	M_FW_RSS_IND_TBL_CMD_IQ31	0x3ff
6334 #define	V_FW_RSS_IND_TBL_CMD_IQ31(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
6335 #define	G_FW_RSS_IND_TBL_CMD_IQ31(x)	\
6336 	(((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
6337 
6338 struct fw_rss_glb_config_cmd {
6339 	__be32 op_to_write;
6340 	__be32 retval_len16;
6341 	union fw_rss_glb_config {
6342 		struct fw_rss_glb_config_manual {
6343 			__be32 mode_pkd;
6344 			__be32 r3;
6345 			__be64 r4;
6346 			__be64 r5;
6347 		} manual;
6348 		struct fw_rss_glb_config_basicvirtual {
6349 			__be32 mode_pkd;
6350 			__be32 synmapen_to_hashtoeplitz;
6351 			__be64 r8;
6352 			__be64 r9;
6353 		} basicvirtual;
6354 	} u;
6355 };
6356 
6357 #define	S_FW_RSS_GLB_CONFIG_CMD_MODE	28
6358 #define	M_FW_RSS_GLB_CONFIG_CMD_MODE	0xf
6359 #define	V_FW_RSS_GLB_CONFIG_CMD_MODE(x)	((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
6360 #define	G_FW_RSS_GLB_CONFIG_CMD_MODE(x)	\
6361 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
6362 
6363 #define	FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
6364 #define	FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
6365 #define	FW_RSS_GLB_CONFIG_CMD_MODE_MAX		1
6366 
6367 #define	S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN	8
6368 #define	M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN	0x1
6369 #define	V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x)	\
6370 	((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
6371 #define	G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x)	\
6372 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
6373 	M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
6374 #define	F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN	\
6375     V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
6376 
6377 #define	S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6		7
6378 #define	M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6		0x1
6379 #define	V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x)	\
6380 	((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
6381 #define	G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x)	\
6382 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
6383 	M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
6384 #define	F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6	\
6385     V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
6386 
6387 #define	S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6		6
6388 #define	M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6		0x1
6389 #define	V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x)	\
6390 	((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
6391 #define	G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x)	\
6392 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
6393 	M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
6394 #define	F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6	\
6395     V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
6396 
6397 #define	S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4		5
6398 #define	M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4		0x1
6399 #define	V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x)	\
6400 	((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
6401 #define	G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x)	\
6402 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
6403 	M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
6404 #define	F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4	\
6405     V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
6406 
6407 #define	S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4		4
6408 #define	M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4		0x1
6409 #define	V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x)	\
6410 	((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
6411 #define	G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x)	\
6412 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
6413 	M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
6414 #define	F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4	\
6415     V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
6416 
6417 #define	S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN	3
6418 #define	M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN	0x1
6419 #define	V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x)	\
6420 	((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
6421 #define	G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x)	\
6422 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
6423 	M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
6424 #define	F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN	\
6425     V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
6426 
6427 #define	S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN	2
6428 #define	M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN	0x1
6429 #define	V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x)	\
6430 	((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
6431 #define	G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x)	\
6432 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
6433 	M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
6434 #define	F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN	\
6435     V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
6436 
6437 #define	S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP	1
6438 #define	M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP	0x1
6439 #define	V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x)	\
6440 	((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
6441 #define	G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x)	\
6442 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
6443 	M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
6444 #define	F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP	\
6445     V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
6446 
6447 #define	S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ	0
6448 #define	M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ	0x1
6449 #define	V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x)	\
6450 	((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
6451 #define	G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x)	\
6452 	(((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
6453 	M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
6454 #define	F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ	\
6455     V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
6456 
6457 struct fw_rss_vi_config_cmd {
6458 	__be32 op_to_viid;
6459 	__be32 retval_len16;
6460 	union fw_rss_vi_config {
6461 		struct fw_rss_vi_config_manual {
6462 			__be64 r3;
6463 			__be64 r4;
6464 			__be64 r5;
6465 		} manual;
6466 		struct fw_rss_vi_config_basicvirtual {
6467 			__be32 r6;
6468 			__be32 defaultq_to_udpen;
6469 			__be64 r9;
6470 			__be64 r10;
6471 		} basicvirtual;
6472 	} u;
6473 };
6474 
6475 #define	S_FW_RSS_VI_CONFIG_CMD_VIID	0
6476 #define	M_FW_RSS_VI_CONFIG_CMD_VIID	0xfff
6477 #define	V_FW_RSS_VI_CONFIG_CMD_VIID(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
6478 #define	G_FW_RSS_VI_CONFIG_CMD_VIID(x)	\
6479 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
6480 
6481 #define	S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ		16
6482 #define	M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ		0x3ff
6483 #define	V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)	\
6484 	((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
6485 #define	G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)	\
6486 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
6487 	M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
6488 
6489 #define	S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN	4
6490 #define	M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN	0x1
6491 #define	V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x)	\
6492 	((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6493 #define	G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x)	\
6494 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
6495 	M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6496 #define	F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN	\
6497     V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
6498 
6499 #define	S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN	3
6500 #define	M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN	0x1
6501 #define	V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x)	\
6502 	((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
6503 #define	G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x)	\
6504 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
6505 	M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
6506 #define	F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN	\
6507     V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
6508 
6509 #define	S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN	2
6510 #define	M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN	0x1
6511 #define	V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x)	\
6512 	((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6513 #define	G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x)	\
6514 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
6515 	M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6516 #define	F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN	\
6517     V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
6518 
6519 #define	S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	1
6520 #define	M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	0x1
6521 #define	V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x)	\
6522 	((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
6523 #define	G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x)	\
6524 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
6525 	M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
6526 #define	F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	\
6527     V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
6528 
6529 #define	S_FW_RSS_VI_CONFIG_CMD_UDPEN	0
6530 #define	M_FW_RSS_VI_CONFIG_CMD_UDPEN	0x1
6531 #define	V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
6532 #define	G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	\
6533 	(((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
6534 #define	F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
6535 
6536 enum fw_sched_sc {
6537 	FW_SCHED_SC_CONFIG		= 0,
6538 	FW_SCHED_SC_PARAMS		= 1,
6539 };
6540 
6541 enum fw_sched_type {
6542 	FW_SCHED_TYPE_PKTSCHED		= 0,
6543 	FW_SCHED_TYPE_STREAMSCHED	= 1,
6544 };
6545 
6546 enum fw_sched_params_level {
6547 	FW_SCHED_PARAMS_LEVEL_CL_RL	= 0,
6548 	FW_SCHED_PARAMS_LEVEL_CL_WRR	= 1,
6549 	FW_SCHED_PARAMS_LEVEL_CH_RL	= 2,
6550 	FW_SCHED_PARAMS_LEVEL_CH_WRR	= 3,
6551 };
6552 
6553 enum fw_sched_params_mode {
6554 	FW_SCHED_PARAMS_MODE_CLASS	= 0,
6555 	FW_SCHED_PARAMS_MODE_FLOW	= 1,
6556 };
6557 
6558 enum fw_sched_params_unit {
6559 	FW_SCHED_PARAMS_UNIT_BITRATE	= 0,
6560 	FW_SCHED_PARAMS_UNIT_PKTRATE	= 1,
6561 };
6562 
6563 enum fw_sched_params_rate {
6564 	FW_SCHED_PARAMS_RATE_REL	= 0,
6565 	FW_SCHED_PARAMS_RATE_ABS	= 1,
6566 };
6567 
6568 struct fw_sched_cmd {
6569 	__be32 op_to_write;
6570 	__be32 retval_len16;
6571 	union fw_sched {
6572 		struct fw_sched_config {
6573 			__u8   sc;
6574 			__u8   type;
6575 			__u8   minmaxen;
6576 			__u8   r3[5];
6577 		} config;
6578 		struct fw_sched_params {
6579 			__u8   sc;
6580 			__u8   type;
6581 			__u8   level;
6582 			__u8   mode;
6583 			__u8   unit;
6584 			__u8   rate;
6585 			__u8   ch;
6586 			__u8   cl;
6587 			__be32 min;
6588 			__be32 max;
6589 			__be16 weight;
6590 			__be16 pktsize;
6591 			__be32 r4;
6592 		} params;
6593 	} u;
6594 };
6595 
6596 /*
6597  *	length of the formatting string
6598  */
6599 #define	FW_DEVLOG_FMT_LEN	192
6600 
6601 /*
6602  *	maximum number of the formatting string parameters
6603  */
6604 #define	FW_DEVLOG_FMT_PARAMS_NUM 8
6605 
6606 /*
6607  *	priority levels
6608  */
6609 enum fw_devlog_level {
6610 	FW_DEVLOG_LEVEL_EMERG	= 0x0,
6611 	FW_DEVLOG_LEVEL_CRIT	= 0x1,
6612 	FW_DEVLOG_LEVEL_ERR	= 0x2,
6613 	FW_DEVLOG_LEVEL_NOTICE	= 0x3,
6614 	FW_DEVLOG_LEVEL_INFO	= 0x4,
6615 	FW_DEVLOG_LEVEL_DEBUG	= 0x5,
6616 	FW_DEVLOG_LEVEL_MAX	= 0x5,
6617 };
6618 
6619 /*
6620  *	facilities that may send a log message
6621  */
6622 enum fw_devlog_facility {
6623 	FW_DEVLOG_FACILITY_CORE		= 0x00,
6624 	FW_DEVLOG_FACILITY_SCHED	= 0x02,
6625 	FW_DEVLOG_FACILITY_TIMER	= 0x04,
6626 	FW_DEVLOG_FACILITY_RES		= 0x06,
6627 	FW_DEVLOG_FACILITY_HW		= 0x08,
6628 	FW_DEVLOG_FACILITY_FLR		= 0x10,
6629 	FW_DEVLOG_FACILITY_DMAQ		= 0x12,
6630 	FW_DEVLOG_FACILITY_PHY		= 0x14,
6631 	FW_DEVLOG_FACILITY_MAC		= 0x16,
6632 	FW_DEVLOG_FACILITY_PORT		= 0x18,
6633 	FW_DEVLOG_FACILITY_VI		= 0x1A,
6634 	FW_DEVLOG_FACILITY_FILTER	= 0x1C,
6635 	FW_DEVLOG_FACILITY_ACL		= 0x1E,
6636 	FW_DEVLOG_FACILITY_TM		= 0x20,
6637 	FW_DEVLOG_FACILITY_QFC		= 0x22,
6638 	FW_DEVLOG_FACILITY_DCB		= 0x24,
6639 	FW_DEVLOG_FACILITY_ETH		= 0x26,
6640 	FW_DEVLOG_FACILITY_OFLD		= 0x28,
6641 	FW_DEVLOG_FACILITY_RI		= 0x2A,
6642 	FW_DEVLOG_FACILITY_ISCSI	= 0x2C,
6643 	FW_DEVLOG_FACILITY_FCOE		= 0x2E,
6644 	FW_DEVLOG_FACILITY_FOISCSI	= 0x30,
6645 	FW_DEVLOG_FACILITY_FOFCOE	= 0x32,
6646 	FW_DEVLOG_FACILITY_MAX		= 0x32,
6647 };
6648 
6649 /*
6650  *	log message format
6651  */
6652 struct fw_devlog_e {
6653 	__be64	timestamp;
6654 	__be32	seqno;
6655 	__be16	reserved1;
6656 	__u8	level;
6657 	__u8	facility;
6658 	__u8	fmt[FW_DEVLOG_FMT_LEN];
6659 	__be32	params[FW_DEVLOG_FMT_PARAMS_NUM];
6660 	__be32	reserved3[4];
6661 };
6662 
6663 struct fw_devlog_cmd {
6664 	__be32 op_to_write;
6665 	__be32 retval_len16;
6666 	__u8   level;
6667 	__u8   r2[7];
6668 	__be32 memtype_devlog_memaddr16_devlog;
6669 	__be32 memsize_devlog;
6670 	__be32 r3[2];
6671 };
6672 
6673 #define	S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG		28
6674 #define	M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG		0xf
6675 #define	V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x)	\
6676 	((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
6677 #define	G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x)	\
6678 	(((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & \
6679 	M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
6680 
6681 #define	S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG	0
6682 #define	M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG	0xfffffff
6683 #define	V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x)	\
6684 	((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
6685 #define	G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x)	\
6686 	(((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
6687 	M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
6688 
6689 enum fw_watchdog_actions {
6690 	FW_WATCHDOG_ACTION_FLR = 0x1,
6691 	FW_WATCHDOG_ACTION_BYPASS = 0x2,
6692 };
6693 
6694 #define	FW_WATCHDOG_MAX_TIMEOUT_SECS	60
6695 
6696 struct fw_watchdog_cmd {
6697 	__be32 op_to_write;
6698 	__be32 retval_len16;
6699 	__be32 timeout;
6700 	__be32 actions;
6701 };
6702 
6703 struct fw_clip_cmd {
6704 	__be32 op_to_write;
6705 	__be32 alloc_to_len16;
6706 	__be64 ip_hi;
6707 	__be64 ip_lo;
6708 	__be32 r4[2];
6709 };
6710 
6711 #define	S_FW_CLIP_CMD_ALLOC	31
6712 #define	M_FW_CLIP_CMD_ALLOC	0x1
6713 #define	V_FW_CLIP_CMD_ALLOC(x)	((x) << S_FW_CLIP_CMD_ALLOC)
6714 #define	G_FW_CLIP_CMD_ALLOC(x)	\
6715 	(((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
6716 #define	F_FW_CLIP_CMD_ALLOC	V_FW_CLIP_CMD_ALLOC(1U)
6717 
6718 #define	S_FW_CLIP_CMD_FREE	30
6719 #define	M_FW_CLIP_CMD_FREE	0x1
6720 #define	V_FW_CLIP_CMD_FREE(x)	((x) << S_FW_CLIP_CMD_FREE)
6721 #define	G_FW_CLIP_CMD_FREE(x)	\
6722 	(((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
6723 #define	F_FW_CLIP_CMD_FREE	V_FW_CLIP_CMD_FREE(1U)
6724 
6725 /*
6726  *	************************************
6727  *	   F O i S C S I   C O M M A N D s
6728  *	************************************
6729  */
6730 
6731 #define	FW_CHNET_IFACE_ADDR_MAX	3
6732 
6733 enum fw_chnet_iface_cmd_subop {
6734 	FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
6735 
6736 	FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
6737 	FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
6738 
6739 	FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
6740 	FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
6741 
6742 	FW_CHNET_IFACE_CMD_SUBOP_MAX,
6743 };
6744 
6745 struct fw_chnet_iface_cmd {
6746 	__be32 op_to_portid;
6747 	__be32 retval_len16;
6748 	__u8   subop;
6749 	__u8   r2[3];
6750 	__be32 ifid_ifstate;
6751 	__be16 mtu;
6752 	__be16 vlanid;
6753 	__be32 r3;
6754 	__be16 r4;
6755 	__u8   mac[6];
6756 };
6757 
6758 #define	S_FW_CHNET_IFACE_CMD_PORTID	0
6759 #define	M_FW_CHNET_IFACE_CMD_PORTID	0xf
6760 #define	V_FW_CHNET_IFACE_CMD_PORTID(x)	((x) << S_FW_CHNET_IFACE_CMD_PORTID)
6761 #define	G_FW_CHNET_IFACE_CMD_PORTID(x)	\
6762 	(((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
6763 
6764 #define	S_FW_CHNET_IFACE_CMD_IFID	8
6765 #define	M_FW_CHNET_IFACE_CMD_IFID	0xffffff
6766 #define	V_FW_CHNET_IFACE_CMD_IFID(x)	((x) << S_FW_CHNET_IFACE_CMD_IFID)
6767 #define	G_FW_CHNET_IFACE_CMD_IFID(x)	\
6768 	(((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
6769 
6770 #define	S_FW_CHNET_IFACE_CMD_IFSTATE	0
6771 #define	M_FW_CHNET_IFACE_CMD_IFSTATE	0xff
6772 #define	V_FW_CHNET_IFACE_CMD_IFSTATE(x)	((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
6773 #define	G_FW_CHNET_IFACE_CMD_IFSTATE(x)	\
6774 	(((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
6775 
6776 /*
6777  *	**********************************
6778  *	   F O F C O E   C O M M A N D s
6779  *	**********************************
6780  */
6781 
6782 struct fw_fcoe_res_info_cmd {
6783 	__be32 op_to_read;
6784 	__be32 retval_len16;
6785 	__be16 e_d_tov;
6786 	__be16 r_a_tov_seq;
6787 	__be16 r_a_tov_els;
6788 	__be16 r_r_tov;
6789 	__be32 max_xchgs;
6790 	__be32 max_ssns;
6791 	__be32 used_xchgs;
6792 	__be32 used_ssns;
6793 	__be32 max_fcfs;
6794 	__be32 max_vnps;
6795 	__be32 used_fcfs;
6796 	__be32 used_vnps;
6797 };
6798 
6799 struct fw_fcoe_link_cmd {
6800 	__be32 op_to_portid;
6801 	__be32 retval_len16;
6802 	__be32 sub_opcode_fcfi;
6803 	__u8   r3;
6804 	__u8   lstatus;
6805 	__be16 flags;
6806 	__u8   r4;
6807 	__u8   set_vlan;
6808 	__be16 vlan_id;
6809 	__be32 vnpi_pkd;
6810 	__be16 r6;
6811 	__u8   phy_mac[6];
6812 	__u8   vnport_wwnn[8];
6813 	__u8   vnport_wwpn[8];
6814 };
6815 
6816 #define	S_FW_FCOE_LINK_CMD_PORTID	0
6817 #define	M_FW_FCOE_LINK_CMD_PORTID	0xf
6818 #define	V_FW_FCOE_LINK_CMD_PORTID(x)	((x) << S_FW_FCOE_LINK_CMD_PORTID)
6819 #define	G_FW_FCOE_LINK_CMD_PORTID(x)	\
6820 	(((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
6821 
6822 #define	S_FW_FCOE_LINK_CMD_SUB_OPCODE		24
6823 #define	M_FW_FCOE_LINK_CMD_SUB_OPCODE		0xff
6824 #define	V_FW_FCOE_LINK_CMD_SUB_OPCODE(x)	\
6825 	((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
6826 #define	G_FW_FCOE_LINK_CMD_SUB_OPCODE(x)	\
6827 	(((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
6828 
6829 #define	S_FW_FCOE_LINK_CMD_FCFI		0
6830 #define	M_FW_FCOE_LINK_CMD_FCFI		0xffffff
6831 #define	V_FW_FCOE_LINK_CMD_FCFI(x)	((x) << S_FW_FCOE_LINK_CMD_FCFI)
6832 #define	G_FW_FCOE_LINK_CMD_FCFI(x)	\
6833 	(((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
6834 
6835 #define	S_FW_FCOE_LINK_CMD_VNPI		0
6836 #define	M_FW_FCOE_LINK_CMD_VNPI		0xfffff
6837 #define	V_FW_FCOE_LINK_CMD_VNPI(x)	((x) << S_FW_FCOE_LINK_CMD_VNPI)
6838 #define	G_FW_FCOE_LINK_CMD_VNPI(x)	\
6839 	(((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
6840 
6841 struct fw_fcoe_vnp_cmd {
6842 	__be32 op_to_fcfi;
6843 	__be32 alloc_to_len16;
6844 	__be32 gen_wwn_to_vnpi;
6845 	__be32 vf_id;
6846 	__be16 iqid;
6847 	__u8   vnport_mac[6];
6848 	__u8   vnport_wwnn[8];
6849 	__u8   vnport_wwpn[8];
6850 	__u8   cmn_srv_parms[16];
6851 	__u8   clsp_word_0_1[8];
6852 };
6853 
6854 #define	S_FW_FCOE_VNP_CMD_FCFI		0
6855 #define	M_FW_FCOE_VNP_CMD_FCFI		0xfffff
6856 #define	V_FW_FCOE_VNP_CMD_FCFI(x)	((x) << S_FW_FCOE_VNP_CMD_FCFI)
6857 #define	G_FW_FCOE_VNP_CMD_FCFI(x)	\
6858 	(((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
6859 
6860 #define	S_FW_FCOE_VNP_CMD_ALLOC		31
6861 #define	M_FW_FCOE_VNP_CMD_ALLOC		0x1
6862 #define	V_FW_FCOE_VNP_CMD_ALLOC(x)	((x) << S_FW_FCOE_VNP_CMD_ALLOC)
6863 #define	G_FW_FCOE_VNP_CMD_ALLOC(x)	\
6864 	(((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
6865 #define	F_FW_FCOE_VNP_CMD_ALLOC	V_FW_FCOE_VNP_CMD_ALLOC(1U)
6866 
6867 #define	S_FW_FCOE_VNP_CMD_FREE		30
6868 #define	M_FW_FCOE_VNP_CMD_FREE		0x1
6869 #define	V_FW_FCOE_VNP_CMD_FREE(x)	((x) << S_FW_FCOE_VNP_CMD_FREE)
6870 #define	G_FW_FCOE_VNP_CMD_FREE(x)	\
6871 	(((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
6872 #define	F_FW_FCOE_VNP_CMD_FREE	V_FW_FCOE_VNP_CMD_FREE(1U)
6873 
6874 #define	S_FW_FCOE_VNP_CMD_MODIFY	29
6875 #define	M_FW_FCOE_VNP_CMD_MODIFY	0x1
6876 #define	V_FW_FCOE_VNP_CMD_MODIFY(x)	((x) << S_FW_FCOE_VNP_CMD_MODIFY)
6877 #define	G_FW_FCOE_VNP_CMD_MODIFY(x)	\
6878 	(((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
6879 #define	F_FW_FCOE_VNP_CMD_MODIFY	V_FW_FCOE_VNP_CMD_MODIFY(1U)
6880 
6881 #define	S_FW_FCOE_VNP_CMD_GEN_WWN	22
6882 #define	M_FW_FCOE_VNP_CMD_GEN_WWN	0x1
6883 #define	V_FW_FCOE_VNP_CMD_GEN_WWN(x)	((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
6884 #define	G_FW_FCOE_VNP_CMD_GEN_WWN(x)	\
6885 	(((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
6886 #define	F_FW_FCOE_VNP_CMD_GEN_WWN	V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
6887 
6888 #define	S_FW_FCOE_VNP_CMD_PERSIST	21
6889 #define	M_FW_FCOE_VNP_CMD_PERSIST	0x1
6890 #define	V_FW_FCOE_VNP_CMD_PERSIST(x)	((x) << S_FW_FCOE_VNP_CMD_PERSIST)
6891 #define	G_FW_FCOE_VNP_CMD_PERSIST(x)	\
6892 	(((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
6893 #define	F_FW_FCOE_VNP_CMD_PERSIST	V_FW_FCOE_VNP_CMD_PERSIST(1U)
6894 
6895 #define	S_FW_FCOE_VNP_CMD_VFID_EN	20
6896 #define	M_FW_FCOE_VNP_CMD_VFID_EN	0x1
6897 #define	V_FW_FCOE_VNP_CMD_VFID_EN(x)	((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
6898 #define	G_FW_FCOE_VNP_CMD_VFID_EN(x)	\
6899 	(((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
6900 #define	F_FW_FCOE_VNP_CMD_VFID_EN	V_FW_FCOE_VNP_CMD_VFID_EN(1U)
6901 
6902 #define	S_FW_FCOE_VNP_CMD_VNPI		0
6903 #define	M_FW_FCOE_VNP_CMD_VNPI		0xfffff
6904 #define	V_FW_FCOE_VNP_CMD_VNPI(x)	((x) << S_FW_FCOE_VNP_CMD_VNPI)
6905 #define	G_FW_FCOE_VNP_CMD_VNPI(x)	\
6906 	(((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
6907 
6908 struct fw_fcoe_sparams_cmd {
6909 	__be32 op_to_portid;
6910 	__be32 retval_len16;
6911 	__u8   r3[7];
6912 	__u8   cos;
6913 	__u8   lport_wwnn[8];
6914 	__u8   lport_wwpn[8];
6915 	__u8   cmn_srv_parms[16];
6916 	__u8   cls_srv_parms[16];
6917 };
6918 
6919 #define	S_FW_FCOE_SPARAMS_CMD_PORTID	0
6920 #define	M_FW_FCOE_SPARAMS_CMD_PORTID	0xf
6921 #define	V_FW_FCOE_SPARAMS_CMD_PORTID(x)	((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
6922 #define	G_FW_FCOE_SPARAMS_CMD_PORTID(x)	\
6923 	(((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
6924 
6925 struct fw_fcoe_stats_cmd {
6926 	__be32 op_to_flowid;
6927 	__be32 free_to_len16;
6928 	union fw_fcoe_stats {
6929 		struct fw_fcoe_stats_ctl {
6930 			__u8   nstats_port;
6931 			__u8   port_valid_ix;
6932 			__be16 r6;
6933 			__be32 r7;
6934 			__be64 stat0;
6935 			__be64 stat1;
6936 			__be64 stat2;
6937 			__be64 stat3;
6938 			__be64 stat4;
6939 			__be64 stat5;
6940 		} ctl;
6941 		struct fw_fcoe_port_stats {
6942 			__be64 tx_bcast_bytes;
6943 			__be64 tx_bcast_frames;
6944 			__be64 tx_mcast_bytes;
6945 			__be64 tx_mcast_frames;
6946 			__be64 tx_ucast_bytes;
6947 			__be64 tx_ucast_frames;
6948 			__be64 tx_drop_frames;
6949 			__be64 tx_offload_bytes;
6950 			__be64 tx_offload_frames;
6951 			__be64 rx_bcast_bytes;
6952 			__be64 rx_bcast_frames;
6953 			__be64 rx_mcast_bytes;
6954 			__be64 rx_mcast_frames;
6955 			__be64 rx_ucast_bytes;
6956 			__be64 rx_ucast_frames;
6957 			__be64 rx_err_frames;
6958 		} port_stats;
6959 		struct fw_fcoe_fcf_stats {
6960 			__be32 fip_tx_bytes;
6961 			__be32 fip_tx_fr;
6962 			__be64 fcf_ka;
6963 			__be64 mcast_adv_rcvd;
6964 			__be16 ucast_adv_rcvd;
6965 			__be16 sol_sent;
6966 			__be16 vlan_req;
6967 			__be16 vlan_rpl;
6968 			__be16 clr_vlink;
6969 			__be16 link_down;
6970 			__be16 link_up;
6971 			__be16 logo;
6972 			__be16 flogi_req;
6973 			__be16 flogi_rpl;
6974 			__be16 fdisc_req;
6975 			__be16 fdisc_rpl;
6976 			__be16 fka_prd_chg;
6977 			__be16 fc_map_chg;
6978 			__be16 vfid_chg;
6979 			__u8   no_fka_req;
6980 			__u8   no_vnp;
6981 		} fcf_stats;
6982 		struct fw_fcoe_pcb_stats {
6983 			__be64 tx_bytes;
6984 			__be64 tx_frames;
6985 			__be64 rx_bytes;
6986 			__be64 rx_frames;
6987 			__be32 vnp_ka;
6988 			__be32 unsol_els_rcvd;
6989 			__be64 unsol_cmd_rcvd;
6990 			__be16 implicit_logo;
6991 			__be16 flogi_inv_sparm;
6992 			__be16 fdisc_inv_sparm;
6993 			__be16 flogi_rjt;
6994 			__be16 fdisc_rjt;
6995 			__be16 no_ssn;
6996 			__be16 mac_flt_fail;
6997 			__be16 inv_fr_rcvd;
6998 		} pcb_stats;
6999 		struct fw_fcoe_scb_stats {
7000 			__be64 tx_bytes;
7001 			__be64 tx_frames;
7002 			__be64 rx_bytes;
7003 			__be64 rx_frames;
7004 			__be32 host_abrt_req;
7005 			__be32 adap_auto_abrt;
7006 			__be32 adap_abrt_rsp;
7007 			__be32 host_ios_req;
7008 			__be16 ssn_offl_ios;
7009 			__be16 ssn_not_rdy_ios;
7010 			__u8   rx_data_ddp_err;
7011 			__u8   ddp_flt_set_err;
7012 			__be16 rx_data_fr_err;
7013 			__u8   bad_st_abrt_req;
7014 			__u8   no_io_abrt_req;
7015 			__u8   abort_tmo;
7016 			__u8   abort_tmo_2;
7017 			__be32 abort_req;
7018 			__u8   no_ppod_res_tmo;
7019 			__u8   bp_tmo;
7020 			__u8   adap_auto_cls;
7021 			__u8   no_io_cls_req;
7022 			__be32 host_cls_req;
7023 			__be64 unsol_cmd_rcvd;
7024 			__be32 plogi_req_rcvd;
7025 			__be32 prli_req_rcvd;
7026 			__be16 logo_req_rcvd;
7027 			__be16 prlo_req_rcvd;
7028 			__be16 plogi_rjt_rcvd;
7029 			__be16 prli_rjt_rcvd;
7030 			__be32 adisc_req_rcvd;
7031 			__be32 rscn_rcvd;
7032 			__be32 rrq_req_rcvd;
7033 			__be32 unsol_els_rcvd;
7034 			__u8   adisc_rjt_rcvd;
7035 			__u8   scr_rjt;
7036 			__u8   ct_rjt;
7037 			__u8   inval_bls_rcvd;
7038 			__be32 ba_rjt_rcvd;
7039 		} scb_stats;
7040 	} u;
7041 };
7042 
7043 #define	S_FW_FCOE_STATS_CMD_FLOWID	0
7044 #define	M_FW_FCOE_STATS_CMD_FLOWID	0xfffff
7045 #define	V_FW_FCOE_STATS_CMD_FLOWID(x)	((x) << S_FW_FCOE_STATS_CMD_FLOWID)
7046 #define	G_FW_FCOE_STATS_CMD_FLOWID(x)	\
7047 	(((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
7048 
7049 #define	S_FW_FCOE_STATS_CMD_FREE	30
7050 #define	M_FW_FCOE_STATS_CMD_FREE	0x1
7051 #define	V_FW_FCOE_STATS_CMD_FREE(x)	((x) << S_FW_FCOE_STATS_CMD_FREE)
7052 #define	G_FW_FCOE_STATS_CMD_FREE(x)	\
7053 	(((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
7054 #define	F_FW_FCOE_STATS_CMD_FREE	V_FW_FCOE_STATS_CMD_FREE(1U)
7055 
7056 #define	S_FW_FCOE_STATS_CMD_NSTATS	4
7057 #define	M_FW_FCOE_STATS_CMD_NSTATS	0x7
7058 #define	V_FW_FCOE_STATS_CMD_NSTATS(x)	((x) << S_FW_FCOE_STATS_CMD_NSTATS)
7059 #define	G_FW_FCOE_STATS_CMD_NSTATS(x)	\
7060 	(((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
7061 
7062 #define	S_FW_FCOE_STATS_CMD_PORT	0
7063 #define	M_FW_FCOE_STATS_CMD_PORT	0x3
7064 #define	V_FW_FCOE_STATS_CMD_PORT(x)	((x) << S_FW_FCOE_STATS_CMD_PORT)
7065 #define	G_FW_FCOE_STATS_CMD_PORT(x)	\
7066 	(((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
7067 
7068 #define	S_FW_FCOE_STATS_CMD_PORT_VALID		7
7069 #define	M_FW_FCOE_STATS_CMD_PORT_VALID		0x1
7070 #define	V_FW_FCOE_STATS_CMD_PORT_VALID(x)	\
7071 	((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
7072 #define	G_FW_FCOE_STATS_CMD_PORT_VALID(x)	\
7073 	(((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & \
7074 	M_FW_FCOE_STATS_CMD_PORT_VALID)
7075 #define	F_FW_FCOE_STATS_CMD_PORT_VALID	V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
7076 
7077 #define	S_FW_FCOE_STATS_CMD_IX		0
7078 #define	M_FW_FCOE_STATS_CMD_IX		0x3f
7079 #define	V_FW_FCOE_STATS_CMD_IX(x)	((x) << S_FW_FCOE_STATS_CMD_IX)
7080 #define	G_FW_FCOE_STATS_CMD_IX(x)	\
7081 	(((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
7082 
7083 struct fw_fcoe_fcf_cmd {
7084 	__be32 op_to_fcfi;
7085 	__be32 retval_len16;
7086 	__be16 priority_pkd;
7087 	__u8   mac[6];
7088 	__u8   name_id[8];
7089 	__u8   fabric[8];
7090 	__be16 vf_id;
7091 	__be16 max_fcoe_size;
7092 	__u8   vlan_id;
7093 	__u8   fc_map[3];
7094 	__be32 fka_adv;
7095 	__be32 r6;
7096 	__u8   r7_hi;
7097 	__u8   fpma_to_portid;
7098 	__u8   spma_mac[6];
7099 	__be64 r8;
7100 };
7101 
7102 #define	S_FW_FCOE_FCF_CMD_FCFI		0
7103 #define	M_FW_FCOE_FCF_CMD_FCFI		0xfffff
7104 #define	V_FW_FCOE_FCF_CMD_FCFI(x)	((x) << S_FW_FCOE_FCF_CMD_FCFI)
7105 #define	G_FW_FCOE_FCF_CMD_FCFI(x)	\
7106 	(((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
7107 
7108 #define	S_FW_FCOE_FCF_CMD_PRIORITY	0
7109 #define	M_FW_FCOE_FCF_CMD_PRIORITY	0xff
7110 #define	V_FW_FCOE_FCF_CMD_PRIORITY(x)	((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
7111 #define	G_FW_FCOE_FCF_CMD_PRIORITY(x)	\
7112 	(((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
7113 
7114 #define	S_FW_FCOE_FCF_CMD_FPMA		6
7115 #define	M_FW_FCOE_FCF_CMD_FPMA		0x1
7116 #define	V_FW_FCOE_FCF_CMD_FPMA(x)	((x) << S_FW_FCOE_FCF_CMD_FPMA)
7117 #define	G_FW_FCOE_FCF_CMD_FPMA(x)	\
7118 	(((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
7119 #define	F_FW_FCOE_FCF_CMD_FPMA	V_FW_FCOE_FCF_CMD_FPMA(1U)
7120 
7121 #define	S_FW_FCOE_FCF_CMD_SPMA		5
7122 #define	M_FW_FCOE_FCF_CMD_SPMA		0x1
7123 #define	V_FW_FCOE_FCF_CMD_SPMA(x)	((x) << S_FW_FCOE_FCF_CMD_SPMA)
7124 #define	G_FW_FCOE_FCF_CMD_SPMA(x)	\
7125 	(((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
7126 #define	F_FW_FCOE_FCF_CMD_SPMA	V_FW_FCOE_FCF_CMD_SPMA(1U)
7127 
7128 #define	S_FW_FCOE_FCF_CMD_LOGIN		4
7129 #define	M_FW_FCOE_FCF_CMD_LOGIN		0x1
7130 #define	V_FW_FCOE_FCF_CMD_LOGIN(x)	((x) << S_FW_FCOE_FCF_CMD_LOGIN)
7131 #define	G_FW_FCOE_FCF_CMD_LOGIN(x)	\
7132 	(((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
7133 #define	F_FW_FCOE_FCF_CMD_LOGIN	V_FW_FCOE_FCF_CMD_LOGIN(1U)
7134 
7135 #define	S_FW_FCOE_FCF_CMD_PORTID	0
7136 #define	M_FW_FCOE_FCF_CMD_PORTID	0xf
7137 #define	V_FW_FCOE_FCF_CMD_PORTID(x)	((x) << S_FW_FCOE_FCF_CMD_PORTID)
7138 #define	G_FW_FCOE_FCF_CMD_PORTID(x)	\
7139 	(((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
7140 
7141 /*
7142  *	****************************************************
7143  *	   E R R O R   a n d   D E B U G   C O M M A N D s
7144  *	****************************************************
7145  */
7146 
7147 enum fw_error_type {
7148 	FW_ERROR_TYPE_EXCEPTION	= 0x0,
7149 	FW_ERROR_TYPE_HWMODULE	= 0x1,
7150 	FW_ERROR_TYPE_WR	= 0x2,
7151 	FW_ERROR_TYPE_ACL	= 0x3,
7152 };
7153 
7154 struct fw_error_cmd {
7155 	__be32 op_to_type;
7156 	__be32 len16_pkd;
7157 	union fw_error {
7158 		struct fw_error_exception {
7159 			__be32 info[6];
7160 		} exception;
7161 		struct fw_error_hwmodule {
7162 			__be32 regaddr;
7163 			__be32 regval;
7164 		} hwmodule;
7165 		struct fw_error_wr {
7166 			__be16 cidx;
7167 			__be16 pfn_vfn;
7168 			__be32 eqid;
7169 			__u8   wrhdr[16];
7170 		} wr;
7171 		struct fw_error_acl {
7172 			__be16 cidx;
7173 			__be16 pfn_vfn;
7174 			__be32 eqid;
7175 			__be16 mv_pkd;
7176 			__u8   val[6];
7177 			__be64 r4;
7178 		} acl;
7179 	} u;
7180 };
7181 
7182 #define	S_FW_ERROR_CMD_FATAL	4
7183 #define	M_FW_ERROR_CMD_FATAL	0x1
7184 #define	V_FW_ERROR_CMD_FATAL(x)	((x) << S_FW_ERROR_CMD_FATAL)
7185 #define	G_FW_ERROR_CMD_FATAL(x)	\
7186 	(((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
7187 #define	F_FW_ERROR_CMD_FATAL	V_FW_ERROR_CMD_FATAL(1U)
7188 
7189 #define	S_FW_ERROR_CMD_TYPE	0
7190 #define	M_FW_ERROR_CMD_TYPE	0xf
7191 #define	V_FW_ERROR_CMD_TYPE(x)	((x) << S_FW_ERROR_CMD_TYPE)
7192 #define	G_FW_ERROR_CMD_TYPE(x)	\
7193 	(((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
7194 
7195 #define	S_FW_ERROR_CMD_PFN	8
7196 #define	M_FW_ERROR_CMD_PFN	0x7
7197 #define	V_FW_ERROR_CMD_PFN(x)	((x) << S_FW_ERROR_CMD_PFN)
7198 #define	G_FW_ERROR_CMD_PFN(x)	\
7199 	(((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
7200 
7201 #define	S_FW_ERROR_CMD_VFN	0
7202 #define	M_FW_ERROR_CMD_VFN	0xff
7203 #define	V_FW_ERROR_CMD_VFN(x)	((x) << S_FW_ERROR_CMD_VFN)
7204 #define	G_FW_ERROR_CMD_VFN(x)	\
7205 	(((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
7206 
7207 #define	S_FW_ERROR_CMD_PFN	8
7208 #define	M_FW_ERROR_CMD_PFN	0x7
7209 #define	V_FW_ERROR_CMD_PFN(x)	((x) << S_FW_ERROR_CMD_PFN)
7210 #define	G_FW_ERROR_CMD_PFN(x)	\
7211 	(((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
7212 
7213 #define	S_FW_ERROR_CMD_VFN	0
7214 #define	M_FW_ERROR_CMD_VFN	0xff
7215 #define	V_FW_ERROR_CMD_VFN(x)	((x) << S_FW_ERROR_CMD_VFN)
7216 #define	G_FW_ERROR_CMD_VFN(x)	\
7217 	(((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
7218 
7219 #define	S_FW_ERROR_CMD_MV	15
7220 #define	M_FW_ERROR_CMD_MV	0x1
7221 #define	V_FW_ERROR_CMD_MV(x)	((x) << S_FW_ERROR_CMD_MV)
7222 #define	G_FW_ERROR_CMD_MV(x)	\
7223 	(((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
7224 #define	F_FW_ERROR_CMD_MV	V_FW_ERROR_CMD_MV(1U)
7225 
7226 struct fw_debug_cmd {
7227 	__be32 op_type;
7228 	__be32 len16_pkd;
7229 	union fw_debug {
7230 		struct fw_debug_assert {
7231 			__be32 fcid;
7232 			__be32 line;
7233 			__be32 x;
7234 			__be32 y;
7235 			__u8   filename_0_7[8];
7236 			__u8   filename_8_15[8];
7237 			__be64 r3;
7238 		} assert;
7239 		struct fw_debug_prt {
7240 			__be16 dprtstridx;
7241 			__be16 r3[3];
7242 			__be32 dprtstrparam0;
7243 			__be32 dprtstrparam1;
7244 			__be32 dprtstrparam2;
7245 			__be32 dprtstrparam3;
7246 		} prt;
7247 	} u;
7248 };
7249 
7250 #define	S_FW_DEBUG_CMD_TYPE	0
7251 #define	M_FW_DEBUG_CMD_TYPE	0xff
7252 #define	V_FW_DEBUG_CMD_TYPE(x)	((x) << S_FW_DEBUG_CMD_TYPE)
7253 #define	G_FW_DEBUG_CMD_TYPE(x)	\
7254 	(((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
7255 
7256 /*
7257  *	************************************
7258  *	  P C I E   F W   R E G I S T E R
7259  *	************************************
7260  */
7261 
7262 /*
7263  *	Register definitions for the PCIE_FW register which the firmware uses
7264  *	to restain status across RESETs.  This register should be considered
7265  *	as a READ-ONLY register for Host Software and only to be used to
7266  *	track firmware initialization/error state, etc.
7267  */
7268 #define	S_PCIE_FW_ERR		31
7269 #define	M_PCIE_FW_ERR		0x1
7270 #define	V_PCIE_FW_ERR(x)	((x) << S_PCIE_FW_ERR)
7271 #define	G_PCIE_FW_ERR(x)	(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
7272 #define	F_PCIE_FW_ERR		V_PCIE_FW_ERR(1U)
7273 
7274 #define	S_PCIE_FW_INIT		30
7275 #define	M_PCIE_FW_INIT		0x1
7276 #define	V_PCIE_FW_INIT(x)	((x) << S_PCIE_FW_INIT)
7277 #define	G_PCIE_FW_INIT(x)	(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
7278 #define	F_PCIE_FW_INIT		V_PCIE_FW_INIT(1U)
7279 
7280 #define	S_PCIE_FW_HALT		29
7281 #define	M_PCIE_FW_HALT		0x1
7282 #define	V_PCIE_FW_HALT(x)	((x) << S_PCIE_FW_HALT)
7283 #define	G_PCIE_FW_HALT(x)	(((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
7284 #define	F_PCIE_FW_HALT		V_PCIE_FW_HALT(1U)
7285 
7286 #define	S_PCIE_FW_STAGE		21
7287 #define	M_PCIE_FW_STAGE		0x7
7288 #define	V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
7289 #define	G_PCIE_FW_STAGE(x)	(((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
7290 
7291 #define	S_PCIE_FW_ASYNCNOT_VLD	20
7292 #define	M_PCIE_FW_ASYNCNOT_VLD	0x1
7293 #define	V_PCIE_FW_ASYNCNOT_VLD(x) \
7294 	((x) << S_PCIE_FW_ASYNCNOT_VLD)
7295 #define	G_PCIE_FW_ASYNCNOT_VLD(x) \
7296 	(((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
7297 #define	F_PCIE_FW_ASYNCNOT_VLD	V_PCIE_FW_ASYNCNOT_VLD(1U)
7298 
7299 #define	S_PCIE_FW_ASYNCNOTINT	19
7300 #define	M_PCIE_FW_ASYNCNOTINT	0x1
7301 #define	V_PCIE_FW_ASYNCNOTINT(x) \
7302 	((x) << S_PCIE_FW_ASYNCNOTINT)
7303 #define	G_PCIE_FW_ASYNCNOTINT(x) \
7304 	(((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
7305 #define	F_PCIE_FW_ASYNCNOTINT	V_PCIE_FW_ASYNCNOTINT(1U)
7306 
7307 #define	S_PCIE_FW_ASYNCNOT	16
7308 #define	M_PCIE_FW_ASYNCNOT	0x7
7309 #define	V_PCIE_FW_ASYNCNOT(x)	((x) << S_PCIE_FW_ASYNCNOT)
7310 #define	G_PCIE_FW_ASYNCNOT(x)	\
7311 	(((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
7312 
7313 #define	S_PCIE_FW_MASTER_VLD	15
7314 #define	M_PCIE_FW_MASTER_VLD	0x1
7315 #define	V_PCIE_FW_MASTER_VLD(x)	((x) << S_PCIE_FW_MASTER_VLD)
7316 #define	G_PCIE_FW_MASTER_VLD(x)	\
7317 	(((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
7318 #define	F_PCIE_FW_MASTER_VLD	V_PCIE_FW_MASTER_VLD(1U)
7319 
7320 #define	S_PCIE_FW_MASTER	12
7321 #define	M_PCIE_FW_MASTER	0x7
7322 #define	V_PCIE_FW_MASTER(x)	((x) << S_PCIE_FW_MASTER)
7323 #define	G_PCIE_FW_MASTER(x)	(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
7324 
7325 #define	S_PCIE_FW_RESET_VLD		11
7326 #define	M_PCIE_FW_RESET_VLD		0x1
7327 #define	V_PCIE_FW_RESET_VLD(x)	((x) << S_PCIE_FW_RESET_VLD)
7328 #define	G_PCIE_FW_RESET_VLD(x)	\
7329 	(((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
7330 #define	F_PCIE_FW_RESET_VLD	V_PCIE_FW_RESET_VLD(1U)
7331 
7332 #define	S_PCIE_FW_RESET		8
7333 #define	M_PCIE_FW_RESET		0x7
7334 #define	V_PCIE_FW_RESET(x)	((x) << S_PCIE_FW_RESET)
7335 #define	G_PCIE_FW_RESET(x)	\
7336 	(((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
7337 
7338 #define	S_PCIE_FW_REGISTERED	0
7339 #define	M_PCIE_FW_REGISTERED	0xff
7340 #define	V_PCIE_FW_REGISTERED(x)	((x) << S_PCIE_FW_REGISTERED)
7341 #define	G_PCIE_FW_REGISTERED(x)	\
7342 	(((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
7343 
7344 /*
7345  *	********************************************
7346  *	   B I N A R Y   H E A D E R   F O R M A T
7347  *	********************************************
7348  */
7349 
7350 /*
7351  *	firmware binary header format
7352  */
7353 struct fw_hdr {
7354 	__u8	ver;
7355 	__u8	chip;			/* terminator chip family */
7356 	__be16	len512;			/* bin length in units of 512-bytes */
7357 	__be32	fw_ver;			/* firmware version */
7358 	__be32	tp_microcode_ver;	/* tcp processor microcode version */
7359 	__u8	intfver_nic;
7360 	__u8	intfver_vnic;
7361 	__u8	intfver_ofld;
7362 	__u8	intfver_ri;
7363 	__u8	intfver_iscsipdu;
7364 	__u8	intfver_iscsi;
7365 	__u8	intfver_fcoe;
7366 	__u8	reserved2;
7367 	__u32	reserved3;
7368 	__u32	reserved4;
7369 	__u32	reserved5;
7370 	__be32	flags;
7371 	__be32	reserved6[23];
7372 };
7373 
7374 enum fw_hdr_chip {
7375 	FW_HDR_CHIP_T4,
7376 	FW_HDR_CHIP_T5
7377 };
7378 
7379 #define	S_FW_HDR_FW_VER_MAJOR	24
7380 #define	M_FW_HDR_FW_VER_MAJOR	0xff
7381 #define	V_FW_HDR_FW_VER_MAJOR(x) \
7382 	((x) << S_FW_HDR_FW_VER_MAJOR)
7383 #define	G_FW_HDR_FW_VER_MAJOR(x) \
7384 	(((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
7385 
7386 #define	S_FW_HDR_FW_VER_MINOR	16
7387 #define	M_FW_HDR_FW_VER_MINOR	0xff
7388 #define	V_FW_HDR_FW_VER_MINOR(x) \
7389 	((x) << S_FW_HDR_FW_VER_MINOR)
7390 #define	G_FW_HDR_FW_VER_MINOR(x) \
7391 	(((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
7392 
7393 #define	S_FW_HDR_FW_VER_MICRO	8
7394 #define	M_FW_HDR_FW_VER_MICRO	0xff
7395 #define	V_FW_HDR_FW_VER_MICRO(x) \
7396 	((x) << S_FW_HDR_FW_VER_MICRO)
7397 #define	G_FW_HDR_FW_VER_MICRO(x) \
7398 	(((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
7399 
7400 #define	S_FW_HDR_FW_VER_BUILD	0
7401 #define	M_FW_HDR_FW_VER_BUILD	0xff
7402 #define	V_FW_HDR_FW_VER_BUILD(x) \
7403 	((x) << S_FW_HDR_FW_VER_BUILD)
7404 #define	G_FW_HDR_FW_VER_BUILD(x) \
7405 	(((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
7406 
7407 enum fw_hdr_intfver {
7408 	FW_HDR_INTFVER_NIC	= 0x00,
7409 	FW_HDR_INTFVER_VNIC	= 0x00,
7410 	FW_HDR_INTFVER_OFLD	= 0x00,
7411 	FW_HDR_INTFVER_RI	= 0x00,
7412 	FW_HDR_INTFVER_ISCSIPDU	= 0x00,
7413 	FW_HDR_INTFVER_ISCSI	= 0x00,
7414 	FW_HDR_INTFVER_FCOE	= 0x00,
7415 };
7416 
7417 enum fw_hdr_flags {
7418 	FW_HDR_FLAGS_RESET_HALT	= 0x00000001,
7419 };
7420 
7421 #endif /* _T4FW_INTERFACE_H_ */
7422