1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2000, 2001
6 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60 /*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
78 * alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
91 #ifdef HAVE_KERNEL_OPTION_HEADERS
92 #include "opt_device_polling.h"
93 #endif
94
95 #include <sys/param.h>
96 #include <sys/systm.h>
97 #include <sys/bus.h>
98 #include <sys/endian.h>
99 #include <sys/kernel.h>
100 #include <sys/lock.h>
101 #include <sys/malloc.h>
102 #include <sys/mbuf.h>
103 #include <sys/module.h>
104 #include <sys/mutex.h>
105 #include <sys/rman.h>
106 #include <sys/socket.h>
107 #include <sys/sockio.h>
108 #include <sys/sysctl.h>
109
110 #include <net/bpf.h>
111 #include <net/if.h>
112 #include <net/if_var.h>
113 #include <net/if_arp.h>
114 #include <net/ethernet.h>
115 #include <net/if_dl.h>
116 #include <net/if_media.h>
117 #include <net/if_types.h>
118 #include <net/if_vlan_var.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/mii_bitbang.h>
122 #include <dev/mii/miivar.h>
123
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
126
127 #include <machine/bus.h>
128
129 #include <dev/nge/if_ngereg.h>
130
131 /* "device miibus" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
133
134 MODULE_DEPEND(nge, pci, 1, 1, 1);
135 MODULE_DEPEND(nge, ether, 1, 1, 1);
136 MODULE_DEPEND(nge, miibus, 1, 1, 1);
137
138 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
139
140 /*
141 * Various supported device vendors/types and their names.
142 */
143 static const struct nge_type nge_devs[] = {
144 { NGE_VENDORID, NGE_DEVICEID,
145 "National Semiconductor Gigabit Ethernet" },
146 { 0, 0, NULL }
147 };
148
149 static int nge_probe(device_t);
150 static int nge_attach(device_t);
151 static int nge_detach(device_t);
152 static int nge_shutdown(device_t);
153 static int nge_suspend(device_t);
154 static int nge_resume(device_t);
155
156 static __inline void nge_discard_rxbuf(struct nge_softc *, int);
157 static int nge_newbuf(struct nge_softc *, int);
158 static int nge_encap(struct nge_softc *, struct mbuf **);
159 #ifndef __NO_STRICT_ALIGNMENT
160 static __inline void nge_fixup_rx(struct mbuf *);
161 #endif
162 static int nge_rxeof(struct nge_softc *);
163 static void nge_txeof(struct nge_softc *);
164 static void nge_intr(void *);
165 static void nge_tick(void *);
166 static void nge_stats_update(struct nge_softc *);
167 static void nge_start(if_t);
168 static void nge_start_locked(if_t);
169 static int nge_ioctl(if_t, u_long, caddr_t);
170 static void nge_init(void *);
171 static void nge_init_locked(struct nge_softc *);
172 static int nge_stop_mac(struct nge_softc *);
173 static void nge_stop(struct nge_softc *);
174 static void nge_wol(struct nge_softc *);
175 static void nge_watchdog(struct nge_softc *);
176 static int nge_mediachange(if_t);
177 static void nge_mediastatus(if_t, struct ifmediareq *);
178
179 static void nge_delay(struct nge_softc *);
180 static void nge_eeprom_idle(struct nge_softc *);
181 static void nge_eeprom_putbyte(struct nge_softc *, int);
182 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
183 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int);
184
185 static int nge_miibus_readreg(device_t, int, int);
186 static int nge_miibus_writereg(device_t, int, int, int);
187 static void nge_miibus_statchg(device_t);
188
189 static void nge_rxfilter(struct nge_softc *);
190 static void nge_reset(struct nge_softc *);
191 static void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
192 static int nge_dma_alloc(struct nge_softc *);
193 static void nge_dma_free(struct nge_softc *);
194 static int nge_list_rx_init(struct nge_softc *);
195 static int nge_list_tx_init(struct nge_softc *);
196 static void nge_sysctl_node(struct nge_softc *);
197 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
198 static int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS);
199
200 /*
201 * MII bit-bang glue
202 */
203 static uint32_t nge_mii_bitbang_read(device_t);
204 static void nge_mii_bitbang_write(device_t, uint32_t);
205
206 static const struct mii_bitbang_ops nge_mii_bitbang_ops = {
207 nge_mii_bitbang_read,
208 nge_mii_bitbang_write,
209 {
210 NGE_MEAR_MII_DATA, /* MII_BIT_MDO */
211 NGE_MEAR_MII_DATA, /* MII_BIT_MDI */
212 NGE_MEAR_MII_CLK, /* MII_BIT_MDC */
213 NGE_MEAR_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
214 0, /* MII_BIT_DIR_PHY_HOST */
215 }
216 };
217
218 static device_method_t nge_methods[] = {
219 /* Device interface */
220 DEVMETHOD(device_probe, nge_probe),
221 DEVMETHOD(device_attach, nge_attach),
222 DEVMETHOD(device_detach, nge_detach),
223 DEVMETHOD(device_shutdown, nge_shutdown),
224 DEVMETHOD(device_suspend, nge_suspend),
225 DEVMETHOD(device_resume, nge_resume),
226
227 /* MII interface */
228 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
229 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
230 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
231
232 DEVMETHOD_END
233 };
234
235 static driver_t nge_driver = {
236 "nge",
237 nge_methods,
238 sizeof(struct nge_softc)
239 };
240
241 DRIVER_MODULE(nge, pci, nge_driver, 0, 0);
242 DRIVER_MODULE(miibus, nge, miibus_driver, 0, 0);
243
244 #define NGE_SETBIT(sc, reg, x) \
245 CSR_WRITE_4(sc, reg, \
246 CSR_READ_4(sc, reg) | (x))
247
248 #define NGE_CLRBIT(sc, reg, x) \
249 CSR_WRITE_4(sc, reg, \
250 CSR_READ_4(sc, reg) & ~(x))
251
252 #define SIO_SET(x) \
253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
254
255 #define SIO_CLR(x) \
256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
257
258 static void
nge_delay(struct nge_softc * sc)259 nge_delay(struct nge_softc *sc)
260 {
261 int idx;
262
263 for (idx = (300 / 33) + 1; idx > 0; idx--)
264 CSR_READ_4(sc, NGE_CSR);
265 }
266
267 static void
nge_eeprom_idle(struct nge_softc * sc)268 nge_eeprom_idle(struct nge_softc *sc)
269 {
270 int i;
271
272 SIO_SET(NGE_MEAR_EE_CSEL);
273 nge_delay(sc);
274 SIO_SET(NGE_MEAR_EE_CLK);
275 nge_delay(sc);
276
277 for (i = 0; i < 25; i++) {
278 SIO_CLR(NGE_MEAR_EE_CLK);
279 nge_delay(sc);
280 SIO_SET(NGE_MEAR_EE_CLK);
281 nge_delay(sc);
282 }
283
284 SIO_CLR(NGE_MEAR_EE_CLK);
285 nge_delay(sc);
286 SIO_CLR(NGE_MEAR_EE_CSEL);
287 nge_delay(sc);
288 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
289 }
290
291 /*
292 * Send a read command and address to the EEPROM, check for ACK.
293 */
294 static void
nge_eeprom_putbyte(struct nge_softc * sc,int addr)295 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
296 {
297 int d, i;
298
299 d = addr | NGE_EECMD_READ;
300
301 /*
302 * Feed in each bit and stobe the clock.
303 */
304 for (i = 0x400; i; i >>= 1) {
305 if (d & i) {
306 SIO_SET(NGE_MEAR_EE_DIN);
307 } else {
308 SIO_CLR(NGE_MEAR_EE_DIN);
309 }
310 nge_delay(sc);
311 SIO_SET(NGE_MEAR_EE_CLK);
312 nge_delay(sc);
313 SIO_CLR(NGE_MEAR_EE_CLK);
314 nge_delay(sc);
315 }
316 }
317
318 /*
319 * Read a word of data stored in the EEPROM at address 'addr.'
320 */
321 static void
nge_eeprom_getword(struct nge_softc * sc,int addr,uint16_t * dest)322 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
323 {
324 int i;
325 uint16_t word = 0;
326
327 /* Force EEPROM to idle state. */
328 nge_eeprom_idle(sc);
329
330 /* Enter EEPROM access mode. */
331 nge_delay(sc);
332 SIO_CLR(NGE_MEAR_EE_CLK);
333 nge_delay(sc);
334 SIO_SET(NGE_MEAR_EE_CSEL);
335 nge_delay(sc);
336
337 /*
338 * Send address of word we want to read.
339 */
340 nge_eeprom_putbyte(sc, addr);
341
342 /*
343 * Start reading bits from EEPROM.
344 */
345 for (i = 0x8000; i; i >>= 1) {
346 SIO_SET(NGE_MEAR_EE_CLK);
347 nge_delay(sc);
348 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
349 word |= i;
350 nge_delay(sc);
351 SIO_CLR(NGE_MEAR_EE_CLK);
352 nge_delay(sc);
353 }
354
355 /* Turn off EEPROM access mode. */
356 nge_eeprom_idle(sc);
357
358 *dest = word;
359 }
360
361 /*
362 * Read a sequence of words from the EEPROM.
363 */
364 static void
nge_read_eeprom(struct nge_softc * sc,caddr_t dest,int off,int cnt)365 nge_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt)
366 {
367 int i;
368 uint16_t word = 0, *ptr;
369
370 for (i = 0; i < cnt; i++) {
371 nge_eeprom_getword(sc, off + i, &word);
372 ptr = (uint16_t *)(dest + (i * 2));
373 *ptr = word;
374 }
375 }
376
377 /*
378 * Read the MII serial port for the MII bit-bang module.
379 */
380 static uint32_t
nge_mii_bitbang_read(device_t dev)381 nge_mii_bitbang_read(device_t dev)
382 {
383 struct nge_softc *sc;
384 uint32_t val;
385
386 sc = device_get_softc(dev);
387
388 val = CSR_READ_4(sc, NGE_MEAR);
389 CSR_BARRIER_4(sc, NGE_MEAR,
390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
391
392 return (val);
393 }
394
395 /*
396 * Write the MII serial port for the MII bit-bang module.
397 */
398 static void
nge_mii_bitbang_write(device_t dev,uint32_t val)399 nge_mii_bitbang_write(device_t dev, uint32_t val)
400 {
401 struct nge_softc *sc;
402
403 sc = device_get_softc(dev);
404
405 CSR_WRITE_4(sc, NGE_MEAR, val);
406 CSR_BARRIER_4(sc, NGE_MEAR,
407 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
408 }
409
410 static int
nge_miibus_readreg(device_t dev,int phy,int reg)411 nge_miibus_readreg(device_t dev, int phy, int reg)
412 {
413 struct nge_softc *sc;
414 int rv;
415
416 sc = device_get_softc(dev);
417 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) {
418 /* Pretend PHY is at address 0. */
419 if (phy != 0)
420 return (0);
421 switch (reg) {
422 case MII_BMCR:
423 reg = NGE_TBI_BMCR;
424 break;
425 case MII_BMSR:
426 /* 83820/83821 has different bit layout for BMSR. */
427 rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT;
428 reg = CSR_READ_4(sc, NGE_TBI_BMSR);
429 if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0)
430 rv |= BMSR_ACOMP;
431 if ((reg & NGE_TBIBMSR_LINKSTAT) != 0)
432 rv |= BMSR_LINK;
433 return (rv);
434 case MII_ANAR:
435 reg = NGE_TBI_ANAR;
436 break;
437 case MII_ANLPAR:
438 reg = NGE_TBI_ANLPAR;
439 break;
440 case MII_ANER:
441 reg = NGE_TBI_ANER;
442 break;
443 case MII_EXTSR:
444 reg = NGE_TBI_ESR;
445 break;
446 case MII_PHYIDR1:
447 case MII_PHYIDR2:
448 return (0);
449 default:
450 device_printf(sc->nge_dev,
451 "bad phy register read : %d\n", reg);
452 return (0);
453 }
454 return (CSR_READ_4(sc, reg));
455 }
456
457 return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg));
458 }
459
460 static int
nge_miibus_writereg(device_t dev,int phy,int reg,int data)461 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
462 {
463 struct nge_softc *sc;
464
465 sc = device_get_softc(dev);
466 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) {
467 /* Pretend PHY is at address 0. */
468 if (phy != 0)
469 return (0);
470 switch (reg) {
471 case MII_BMCR:
472 reg = NGE_TBI_BMCR;
473 break;
474 case MII_BMSR:
475 return (0);
476 case MII_ANAR:
477 reg = NGE_TBI_ANAR;
478 break;
479 case MII_ANLPAR:
480 reg = NGE_TBI_ANLPAR;
481 break;
482 case MII_ANER:
483 reg = NGE_TBI_ANER;
484 break;
485 case MII_EXTSR:
486 reg = NGE_TBI_ESR;
487 break;
488 case MII_PHYIDR1:
489 case MII_PHYIDR2:
490 return (0);
491 default:
492 device_printf(sc->nge_dev,
493 "bad phy register write : %d\n", reg);
494 return (0);
495 }
496 CSR_WRITE_4(sc, reg, data);
497 return (0);
498 }
499
500 mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data);
501
502 return (0);
503 }
504
505 /*
506 * media status/link state change handler.
507 */
508 static void
nge_miibus_statchg(device_t dev)509 nge_miibus_statchg(device_t dev)
510 {
511 struct nge_softc *sc;
512 struct mii_data *mii;
513 if_t ifp;
514 struct nge_txdesc *txd;
515 uint32_t done, reg, status;
516 int i;
517
518 sc = device_get_softc(dev);
519 NGE_LOCK_ASSERT(sc);
520
521 mii = device_get_softc(sc->nge_miibus);
522 ifp = sc->nge_ifp;
523 if (mii == NULL || ifp == NULL ||
524 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
525 return;
526
527 sc->nge_flags &= ~NGE_FLAG_LINK;
528 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
529 (IFM_AVALID | IFM_ACTIVE)) {
530 switch (IFM_SUBTYPE(mii->mii_media_active)) {
531 case IFM_10_T:
532 case IFM_100_TX:
533 case IFM_1000_T:
534 case IFM_1000_SX:
535 case IFM_1000_LX:
536 case IFM_1000_CX:
537 sc->nge_flags |= NGE_FLAG_LINK;
538 break;
539 default:
540 break;
541 }
542 }
543
544 /* Stop Tx/Rx MACs. */
545 if (nge_stop_mac(sc) == ETIMEDOUT)
546 device_printf(sc->nge_dev,
547 "%s: unable to stop Tx/Rx MAC\n", __func__);
548 nge_txeof(sc);
549 nge_rxeof(sc);
550 if (sc->nge_head != NULL) {
551 m_freem(sc->nge_head);
552 sc->nge_head = sc->nge_tail = NULL;
553 }
554
555 /* Release queued frames. */
556 for (i = 0; i < NGE_TX_RING_CNT; i++) {
557 txd = &sc->nge_cdata.nge_txdesc[i];
558 if (txd->tx_m != NULL) {
559 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag,
560 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
561 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag,
562 txd->tx_dmamap);
563 m_freem(txd->tx_m);
564 txd->tx_m = NULL;
565 }
566 }
567
568 /* Program MAC with resolved speed/duplex. */
569 if ((sc->nge_flags & NGE_FLAG_LINK) != 0) {
570 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
571 NGE_SETBIT(sc, NGE_TX_CFG,
572 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
573 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
574 #ifdef notyet
575 /* Enable flow-control. */
576 if ((IFM_OPTIONS(mii->mii_media_active) &
577 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0)
578 NGE_SETBIT(sc, NGE_PAUSECSR,
579 NGE_PAUSECSR_PAUSE_ENB);
580 #endif
581 } else {
582 NGE_CLRBIT(sc, NGE_TX_CFG,
583 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
584 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
585 NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB);
586 }
587 /* If we have a 1000Mbps link, set the mode_1000 bit. */
588 reg = CSR_READ_4(sc, NGE_CFG);
589 switch (IFM_SUBTYPE(mii->mii_media_active)) {
590 case IFM_1000_SX:
591 case IFM_1000_LX:
592 case IFM_1000_CX:
593 case IFM_1000_T:
594 reg |= NGE_CFG_MODE_1000;
595 break;
596 default:
597 reg &= ~NGE_CFG_MODE_1000;
598 break;
599 }
600 CSR_WRITE_4(sc, NGE_CFG, reg);
601
602 /* Reset Tx/Rx MAC. */
603 reg = CSR_READ_4(sc, NGE_CSR);
604 reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET;
605 CSR_WRITE_4(sc, NGE_CSR, reg);
606 /* Check the completion of reset. */
607 done = 0;
608 for (i = 0; i < NGE_TIMEOUT; i++) {
609 DELAY(1);
610 status = CSR_READ_4(sc, NGE_ISR);
611 if ((status & NGE_ISR_RX_RESET_DONE) != 0)
612 done |= NGE_ISR_RX_RESET_DONE;
613 if ((status & NGE_ISR_TX_RESET_DONE) != 0)
614 done |= NGE_ISR_TX_RESET_DONE;
615 if (done ==
616 (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE))
617 break;
618 }
619 if (i == NGE_TIMEOUT)
620 device_printf(sc->nge_dev,
621 "%s: unable to reset Tx/Rx MAC\n", __func__);
622 /* Reuse Rx buffer and reset consumer pointer. */
623 sc->nge_cdata.nge_rx_cons = 0;
624 /*
625 * It seems that resetting Rx/Tx MAC results in
626 * resetting Tx/Rx descriptor pointer registers such
627 * that reloading Tx/Rx lists address are needed.
628 */
629 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI,
630 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr));
631 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO,
632 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr));
633 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI,
634 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr));
635 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO,
636 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr));
637 /* Reinitialize Tx buffers. */
638 nge_list_tx_init(sc);
639
640 /* Restart Rx MAC. */
641 reg = CSR_READ_4(sc, NGE_CSR);
642 reg |= NGE_CSR_RX_ENABLE;
643 CSR_WRITE_4(sc, NGE_CSR, reg);
644 for (i = 0; i < NGE_TIMEOUT; i++) {
645 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0)
646 break;
647 DELAY(1);
648 }
649 if (i == NGE_TIMEOUT)
650 device_printf(sc->nge_dev,
651 "%s: unable to restart Rx MAC\n", __func__);
652 }
653
654 /* Data LED off for TBI mode */
655 if ((sc->nge_flags & NGE_FLAG_TBI) != 0)
656 CSR_WRITE_4(sc, NGE_GPIO,
657 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);
658 }
659
660 static u_int
nge_write_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)661 nge_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
662 {
663 struct nge_softc *sc = arg;
664 uint32_t h;
665 int bit, index;
666
667 /*
668 * From the 11 bits returned by the crc routine, the top 7
669 * bits represent the 16-bit word in the mcast hash table
670 * that needs to be updated, and the lower 4 bits represent
671 * which bit within that byte needs to be set.
672 */
673 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 21;
674 index = (h >> 4) & 0x7F;
675 bit = h & 0xF;
676 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + (index * 2));
677 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
678
679 return (1);
680 }
681
682 static void
nge_rxfilter(struct nge_softc * sc)683 nge_rxfilter(struct nge_softc *sc)
684 {
685 if_t ifp;
686 uint32_t i, rxfilt;
687
688 NGE_LOCK_ASSERT(sc);
689 ifp = sc->nge_ifp;
690
691 /* Make sure to stop Rx filtering. */
692 rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL);
693 rxfilt &= ~NGE_RXFILTCTL_ENABLE;
694 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt);
695 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE);
696
697 rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS);
698 rxfilt &= ~NGE_RXFILTCTL_BROAD;
699 /*
700 * We don't want to use the hash table for matching unicast
701 * addresses.
702 */
703 rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
704
705 /*
706 * For the NatSemi chip, we have to explicitly enable the
707 * reception of ARP frames, as well as turn on the 'perfect
708 * match' filter where we store the station address, otherwise
709 * we won't receive unicasts meant for this host.
710 */
711 rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT;
712
713 /*
714 * Set the capture broadcast bit to capture broadcast frames.
715 */
716 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
717 rxfilt |= NGE_RXFILTCTL_BROAD;
718
719 if ((if_getflags(ifp) & IFF_PROMISC) != 0 ||
720 (if_getflags(ifp) & IFF_ALLMULTI) != 0) {
721 rxfilt |= NGE_RXFILTCTL_ALLMULTI;
722 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
723 rxfilt |= NGE_RXFILTCTL_ALLPHYS;
724 goto done;
725 }
726
727 /*
728 * We have to explicitly enable the multicast hash table
729 * on the NatSemi chip if we want to use it, which we do.
730 */
731 rxfilt |= NGE_RXFILTCTL_MCHASH;
732
733 /* first, zot all the existing hash bits */
734 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
735 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
736 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
737 }
738
739 if_foreach_llmaddr(ifp, nge_write_maddr, sc);
740 done:
741 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt);
742 /* Turn the receive filter on. */
743 rxfilt |= NGE_RXFILTCTL_ENABLE;
744 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt);
745 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE);
746 }
747
748 static void
nge_reset(struct nge_softc * sc)749 nge_reset(struct nge_softc *sc)
750 {
751 uint32_t v;
752 int i;
753
754 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
755
756 for (i = 0; i < NGE_TIMEOUT; i++) {
757 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
758 break;
759 DELAY(1);
760 }
761
762 if (i == NGE_TIMEOUT)
763 device_printf(sc->nge_dev, "reset never completed\n");
764
765 /* Wait a little while for the chip to get its brains in order. */
766 DELAY(1000);
767
768 /*
769 * If this is a NetSemi chip, make sure to clear
770 * PME mode.
771 */
772 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
773 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
774
775 /* Clear WOL events which may interfere normal Rx filter opertaion. */
776 CSR_WRITE_4(sc, NGE_WOLCSR, 0);
777
778 /*
779 * Only DP83820 supports 64bits addressing/data transfers and
780 * 64bit addressing requires different descriptor structures.
781 * To make it simple, disable 64bit addressing/data transfers.
782 */
783 v = CSR_READ_4(sc, NGE_CFG);
784 v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB);
785 CSR_WRITE_4(sc, NGE_CFG, v);
786 }
787
788 /*
789 * Probe for a NatSemi chip. Check the PCI vendor and device
790 * IDs against our list and return a device name if we find a match.
791 */
792 static int
nge_probe(device_t dev)793 nge_probe(device_t dev)
794 {
795 const struct nge_type *t;
796
797 t = nge_devs;
798
799 while (t->nge_name != NULL) {
800 if ((pci_get_vendor(dev) == t->nge_vid) &&
801 (pci_get_device(dev) == t->nge_did)) {
802 device_set_desc(dev, t->nge_name);
803 return (BUS_PROBE_DEFAULT);
804 }
805 t++;
806 }
807
808 return (ENXIO);
809 }
810
811 /*
812 * Attach the interface. Allocate softc structures, do ifmedia
813 * setup and ethernet/BPF attach.
814 */
815 static int
nge_attach(device_t dev)816 nge_attach(device_t dev)
817 {
818 uint8_t eaddr[ETHER_ADDR_LEN];
819 uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg;
820 struct nge_softc *sc;
821 if_t ifp;
822 int error, i, rid;
823
824 error = 0;
825 sc = device_get_softc(dev);
826 sc->nge_dev = dev;
827
828 NGE_LOCK_INIT(sc, device_get_nameunit(dev));
829 callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0);
830
831 /*
832 * Map control/status registers.
833 */
834 pci_enable_busmaster(dev);
835
836 #ifdef NGE_USEIOSPACE
837 sc->nge_res_type = SYS_RES_IOPORT;
838 sc->nge_res_id = PCIR_BAR(0);
839 #else
840 sc->nge_res_type = SYS_RES_MEMORY;
841 sc->nge_res_id = PCIR_BAR(1);
842 #endif
843 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type,
844 &sc->nge_res_id, RF_ACTIVE);
845
846 if (sc->nge_res == NULL) {
847 if (sc->nge_res_type == SYS_RES_MEMORY) {
848 sc->nge_res_type = SYS_RES_IOPORT;
849 sc->nge_res_id = PCIR_BAR(0);
850 } else {
851 sc->nge_res_type = SYS_RES_MEMORY;
852 sc->nge_res_id = PCIR_BAR(1);
853 }
854 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type,
855 &sc->nge_res_id, RF_ACTIVE);
856 if (sc->nge_res == NULL) {
857 device_printf(dev, "couldn't allocate %s resources\n",
858 sc->nge_res_type == SYS_RES_MEMORY ? "memory" :
859 "I/O");
860 NGE_LOCK_DESTROY(sc);
861 return (ENXIO);
862 }
863 }
864
865 /* Allocate interrupt */
866 rid = 0;
867 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
868 RF_SHAREABLE | RF_ACTIVE);
869
870 if (sc->nge_irq == NULL) {
871 device_printf(dev, "couldn't map interrupt\n");
872 error = ENXIO;
873 goto fail;
874 }
875
876 /* Enable MWI. */
877 reg = pci_read_config(dev, PCIR_COMMAND, 2);
878 reg |= PCIM_CMD_MWRICEN;
879 pci_write_config(dev, PCIR_COMMAND, reg, 2);
880
881 /* Reset the adapter. */
882 nge_reset(sc);
883
884 /*
885 * Get station address from the EEPROM.
886 */
887 nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3);
888 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
889 ea[i] = le16toh(ea[i]);
890 ea_temp = ea[0];
891 ea[0] = ea[2];
892 ea[2] = ea_temp;
893 bcopy(ea, eaddr, sizeof(eaddr));
894
895 if (nge_dma_alloc(sc) != 0) {
896 error = ENXIO;
897 goto fail;
898 }
899
900 nge_sysctl_node(sc);
901
902 ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
903 if_setsoftc(ifp, sc);
904 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
905 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
906 if_setioctlfn(ifp, nge_ioctl);
907 if_setstartfn(ifp, nge_start);
908 if_setinitfn(ifp, nge_init);
909 if_setsendqlen(ifp, NGE_TX_RING_CNT - 1);
910 if_setsendqready(ifp);
911 if_sethwassist(ifp, NGE_CSUM_FEATURES);
912 if_setcapabilities(ifp, IFCAP_HWCSUM);
913 /*
914 * It seems that some hardwares doesn't provide 3.3V auxiliary
915 * supply(3VAUX) to drive PME such that checking PCI power
916 * management capability is necessary.
917 */
918 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0)
919 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0);
920 if_setcapenable(ifp, if_getcapabilities(ifp));
921
922 if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) {
923 sc->nge_flags |= NGE_FLAG_TBI;
924 device_printf(dev, "Using TBI\n");
925 /* Configure GPIO. */
926 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
927 | NGE_GPIO_GP4_OUT
928 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
929 | NGE_GPIO_GP3_OUTENB
930 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
931 }
932
933 /*
934 * Do MII setup.
935 */
936 error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange,
937 nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
938 if (error != 0) {
939 device_printf(dev, "attaching PHYs failed\n");
940 goto fail;
941 }
942
943 /*
944 * Call MI attach routine.
945 */
946 ether_ifattach(ifp, eaddr);
947
948 /* VLAN capability setup. */
949 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0);
950 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
951 if_setcapenable(ifp, if_getcapabilities(ifp));
952 #ifdef DEVICE_POLLING
953 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
954 #endif
955 /*
956 * Tell the upper layer(s) we support long frames.
957 * Must appear after the call to ether_ifattach() because
958 * ether_ifattach() sets ifi_hdrlen to the default value.
959 */
960 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
961
962 /*
963 * Hookup IRQ last.
964 */
965 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
966 NULL, nge_intr, sc, &sc->nge_intrhand);
967 if (error) {
968 device_printf(dev, "couldn't set up irq\n");
969 goto fail;
970 }
971
972 fail:
973 if (error != 0)
974 nge_detach(dev);
975 return (error);
976 }
977
978 static int
nge_detach(device_t dev)979 nge_detach(device_t dev)
980 {
981 struct nge_softc *sc;
982 if_t ifp;
983
984 sc = device_get_softc(dev);
985 ifp = sc->nge_ifp;
986
987 #ifdef DEVICE_POLLING
988 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING)
989 ether_poll_deregister(ifp);
990 #endif
991
992 if (device_is_attached(dev)) {
993 NGE_LOCK(sc);
994 sc->nge_flags |= NGE_FLAG_DETACH;
995 nge_stop(sc);
996 NGE_UNLOCK(sc);
997 callout_drain(&sc->nge_stat_ch);
998 if (ifp != NULL)
999 ether_ifdetach(ifp);
1000 }
1001
1002 if (sc->nge_miibus != NULL) {
1003 device_delete_child(dev, sc->nge_miibus);
1004 sc->nge_miibus = NULL;
1005 }
1006 bus_generic_detach(dev);
1007 if (sc->nge_intrhand != NULL)
1008 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
1009 if (sc->nge_irq != NULL)
1010 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
1011 if (sc->nge_res != NULL)
1012 bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id,
1013 sc->nge_res);
1014
1015 nge_dma_free(sc);
1016 if (ifp != NULL)
1017 if_free(ifp);
1018
1019 NGE_LOCK_DESTROY(sc);
1020
1021 return (0);
1022 }
1023
1024 struct nge_dmamap_arg {
1025 bus_addr_t nge_busaddr;
1026 };
1027
1028 static void
nge_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)1029 nge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1030 {
1031 struct nge_dmamap_arg *ctx;
1032
1033 if (error != 0)
1034 return;
1035 ctx = arg;
1036 ctx->nge_busaddr = segs[0].ds_addr;
1037 }
1038
1039 static int
nge_dma_alloc(struct nge_softc * sc)1040 nge_dma_alloc(struct nge_softc *sc)
1041 {
1042 struct nge_dmamap_arg ctx;
1043 struct nge_txdesc *txd;
1044 struct nge_rxdesc *rxd;
1045 int error, i;
1046
1047 /* Create parent DMA tag. */
1048 error = bus_dma_tag_create(
1049 bus_get_dma_tag(sc->nge_dev), /* parent */
1050 1, 0, /* alignment, boundary */
1051 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1052 BUS_SPACE_MAXADDR, /* highaddr */
1053 NULL, NULL, /* filter, filterarg */
1054 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1055 0, /* nsegments */
1056 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1057 0, /* flags */
1058 NULL, NULL, /* lockfunc, lockarg */
1059 &sc->nge_cdata.nge_parent_tag);
1060 if (error != 0) {
1061 device_printf(sc->nge_dev, "failed to create parent DMA tag\n");
1062 goto fail;
1063 }
1064 /* Create tag for Tx ring. */
1065 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1066 NGE_RING_ALIGN, 0, /* alignment, boundary */
1067 BUS_SPACE_MAXADDR, /* lowaddr */
1068 BUS_SPACE_MAXADDR, /* highaddr */
1069 NULL, NULL, /* filter, filterarg */
1070 NGE_TX_RING_SIZE, /* maxsize */
1071 1, /* nsegments */
1072 NGE_TX_RING_SIZE, /* maxsegsize */
1073 0, /* flags */
1074 NULL, NULL, /* lockfunc, lockarg */
1075 &sc->nge_cdata.nge_tx_ring_tag);
1076 if (error != 0) {
1077 device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n");
1078 goto fail;
1079 }
1080
1081 /* Create tag for Rx ring. */
1082 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1083 NGE_RING_ALIGN, 0, /* alignment, boundary */
1084 BUS_SPACE_MAXADDR, /* lowaddr */
1085 BUS_SPACE_MAXADDR, /* highaddr */
1086 NULL, NULL, /* filter, filterarg */
1087 NGE_RX_RING_SIZE, /* maxsize */
1088 1, /* nsegments */
1089 NGE_RX_RING_SIZE, /* maxsegsize */
1090 0, /* flags */
1091 NULL, NULL, /* lockfunc, lockarg */
1092 &sc->nge_cdata.nge_rx_ring_tag);
1093 if (error != 0) {
1094 device_printf(sc->nge_dev,
1095 "failed to create Rx ring DMA tag\n");
1096 goto fail;
1097 }
1098
1099 /* Create tag for Tx buffers. */
1100 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1101 1, 0, /* alignment, boundary */
1102 BUS_SPACE_MAXADDR, /* lowaddr */
1103 BUS_SPACE_MAXADDR, /* highaddr */
1104 NULL, NULL, /* filter, filterarg */
1105 MCLBYTES * NGE_MAXTXSEGS, /* maxsize */
1106 NGE_MAXTXSEGS, /* nsegments */
1107 MCLBYTES, /* maxsegsize */
1108 0, /* flags */
1109 NULL, NULL, /* lockfunc, lockarg */
1110 &sc->nge_cdata.nge_tx_tag);
1111 if (error != 0) {
1112 device_printf(sc->nge_dev, "failed to create Tx DMA tag\n");
1113 goto fail;
1114 }
1115
1116 /* Create tag for Rx buffers. */
1117 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1118 NGE_RX_ALIGN, 0, /* alignment, boundary */
1119 BUS_SPACE_MAXADDR, /* lowaddr */
1120 BUS_SPACE_MAXADDR, /* highaddr */
1121 NULL, NULL, /* filter, filterarg */
1122 MCLBYTES, /* maxsize */
1123 1, /* nsegments */
1124 MCLBYTES, /* maxsegsize */
1125 0, /* flags */
1126 NULL, NULL, /* lockfunc, lockarg */
1127 &sc->nge_cdata.nge_rx_tag);
1128 if (error != 0) {
1129 device_printf(sc->nge_dev, "failed to create Rx DMA tag\n");
1130 goto fail;
1131 }
1132
1133 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1134 error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag,
1135 (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK |
1136 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map);
1137 if (error != 0) {
1138 device_printf(sc->nge_dev,
1139 "failed to allocate DMA'able memory for Tx ring\n");
1140 goto fail;
1141 }
1142
1143 ctx.nge_busaddr = 0;
1144 error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag,
1145 sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring,
1146 NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0);
1147 if (error != 0 || ctx.nge_busaddr == 0) {
1148 device_printf(sc->nge_dev,
1149 "failed to load DMA'able memory for Tx ring\n");
1150 goto fail;
1151 }
1152 sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr;
1153
1154 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1155 error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag,
1156 (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK |
1157 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map);
1158 if (error != 0) {
1159 device_printf(sc->nge_dev,
1160 "failed to allocate DMA'able memory for Rx ring\n");
1161 goto fail;
1162 }
1163
1164 ctx.nge_busaddr = 0;
1165 error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag,
1166 sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring,
1167 NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0);
1168 if (error != 0 || ctx.nge_busaddr == 0) {
1169 device_printf(sc->nge_dev,
1170 "failed to load DMA'able memory for Rx ring\n");
1171 goto fail;
1172 }
1173 sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr;
1174
1175 /* Create DMA maps for Tx buffers. */
1176 for (i = 0; i < NGE_TX_RING_CNT; i++) {
1177 txd = &sc->nge_cdata.nge_txdesc[i];
1178 txd->tx_m = NULL;
1179 txd->tx_dmamap = NULL;
1180 error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0,
1181 &txd->tx_dmamap);
1182 if (error != 0) {
1183 device_printf(sc->nge_dev,
1184 "failed to create Tx dmamap\n");
1185 goto fail;
1186 }
1187 }
1188 /* Create DMA maps for Rx buffers. */
1189 if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0,
1190 &sc->nge_cdata.nge_rx_sparemap)) != 0) {
1191 device_printf(sc->nge_dev,
1192 "failed to create spare Rx dmamap\n");
1193 goto fail;
1194 }
1195 for (i = 0; i < NGE_RX_RING_CNT; i++) {
1196 rxd = &sc->nge_cdata.nge_rxdesc[i];
1197 rxd->rx_m = NULL;
1198 rxd->rx_dmamap = NULL;
1199 error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0,
1200 &rxd->rx_dmamap);
1201 if (error != 0) {
1202 device_printf(sc->nge_dev,
1203 "failed to create Rx dmamap\n");
1204 goto fail;
1205 }
1206 }
1207
1208 fail:
1209 return (error);
1210 }
1211
1212 static void
nge_dma_free(struct nge_softc * sc)1213 nge_dma_free(struct nge_softc *sc)
1214 {
1215 struct nge_txdesc *txd;
1216 struct nge_rxdesc *rxd;
1217 int i;
1218
1219 /* Tx ring. */
1220 if (sc->nge_cdata.nge_tx_ring_tag) {
1221 if (sc->nge_rdata.nge_tx_ring_paddr)
1222 bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag,
1223 sc->nge_cdata.nge_tx_ring_map);
1224 if (sc->nge_rdata.nge_tx_ring)
1225 bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag,
1226 sc->nge_rdata.nge_tx_ring,
1227 sc->nge_cdata.nge_tx_ring_map);
1228 sc->nge_rdata.nge_tx_ring = NULL;
1229 sc->nge_rdata.nge_tx_ring_paddr = 0;
1230 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag);
1231 sc->nge_cdata.nge_tx_ring_tag = NULL;
1232 }
1233 /* Rx ring. */
1234 if (sc->nge_cdata.nge_rx_ring_tag) {
1235 if (sc->nge_rdata.nge_rx_ring_paddr)
1236 bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag,
1237 sc->nge_cdata.nge_rx_ring_map);
1238 if (sc->nge_rdata.nge_rx_ring)
1239 bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag,
1240 sc->nge_rdata.nge_rx_ring,
1241 sc->nge_cdata.nge_rx_ring_map);
1242 sc->nge_rdata.nge_rx_ring = NULL;
1243 sc->nge_rdata.nge_rx_ring_paddr = 0;
1244 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag);
1245 sc->nge_cdata.nge_rx_ring_tag = NULL;
1246 }
1247 /* Tx buffers. */
1248 if (sc->nge_cdata.nge_tx_tag) {
1249 for (i = 0; i < NGE_TX_RING_CNT; i++) {
1250 txd = &sc->nge_cdata.nge_txdesc[i];
1251 if (txd->tx_dmamap) {
1252 bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag,
1253 txd->tx_dmamap);
1254 txd->tx_dmamap = NULL;
1255 }
1256 }
1257 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag);
1258 sc->nge_cdata.nge_tx_tag = NULL;
1259 }
1260 /* Rx buffers. */
1261 if (sc->nge_cdata.nge_rx_tag) {
1262 for (i = 0; i < NGE_RX_RING_CNT; i++) {
1263 rxd = &sc->nge_cdata.nge_rxdesc[i];
1264 if (rxd->rx_dmamap) {
1265 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag,
1266 rxd->rx_dmamap);
1267 rxd->rx_dmamap = NULL;
1268 }
1269 }
1270 if (sc->nge_cdata.nge_rx_sparemap) {
1271 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag,
1272 sc->nge_cdata.nge_rx_sparemap);
1273 sc->nge_cdata.nge_rx_sparemap = 0;
1274 }
1275 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag);
1276 sc->nge_cdata.nge_rx_tag = NULL;
1277 }
1278
1279 if (sc->nge_cdata.nge_parent_tag) {
1280 bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag);
1281 sc->nge_cdata.nge_parent_tag = NULL;
1282 }
1283 }
1284
1285 /*
1286 * Initialize the transmit descriptors.
1287 */
1288 static int
nge_list_tx_init(struct nge_softc * sc)1289 nge_list_tx_init(struct nge_softc *sc)
1290 {
1291 struct nge_ring_data *rd;
1292 struct nge_txdesc *txd;
1293 bus_addr_t addr;
1294 int i;
1295
1296 sc->nge_cdata.nge_tx_prod = 0;
1297 sc->nge_cdata.nge_tx_cons = 0;
1298 sc->nge_cdata.nge_tx_cnt = 0;
1299
1300 rd = &sc->nge_rdata;
1301 bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT);
1302 for (i = 0; i < NGE_TX_RING_CNT; i++) {
1303 if (i == NGE_TX_RING_CNT - 1)
1304 addr = NGE_TX_RING_ADDR(sc, 0);
1305 else
1306 addr = NGE_TX_RING_ADDR(sc, i + 1);
1307 rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr));
1308 txd = &sc->nge_cdata.nge_txdesc[i];
1309 txd->tx_m = NULL;
1310 }
1311
1312 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag,
1313 sc->nge_cdata.nge_tx_ring_map,
1314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1315
1316 return (0);
1317 }
1318
1319 /*
1320 * Initialize the RX descriptors and allocate mbufs for them. Note that
1321 * we arrange the descriptors in a closed ring, so that the last descriptor
1322 * points back to the first.
1323 */
1324 static int
nge_list_rx_init(struct nge_softc * sc)1325 nge_list_rx_init(struct nge_softc *sc)
1326 {
1327 struct nge_ring_data *rd;
1328 bus_addr_t addr;
1329 int i;
1330
1331 sc->nge_cdata.nge_rx_cons = 0;
1332 sc->nge_head = sc->nge_tail = NULL;
1333
1334 rd = &sc->nge_rdata;
1335 bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT);
1336 for (i = 0; i < NGE_RX_RING_CNT; i++) {
1337 if (nge_newbuf(sc, i) != 0)
1338 return (ENOBUFS);
1339 if (i == NGE_RX_RING_CNT - 1)
1340 addr = NGE_RX_RING_ADDR(sc, 0);
1341 else
1342 addr = NGE_RX_RING_ADDR(sc, i + 1);
1343 rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr));
1344 }
1345
1346 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag,
1347 sc->nge_cdata.nge_rx_ring_map,
1348 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1349
1350 return (0);
1351 }
1352
1353 static __inline void
nge_discard_rxbuf(struct nge_softc * sc,int idx)1354 nge_discard_rxbuf(struct nge_softc *sc, int idx)
1355 {
1356 struct nge_desc *desc;
1357
1358 desc = &sc->nge_rdata.nge_rx_ring[idx];
1359 desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t));
1360 desc->nge_extsts = 0;
1361 }
1362
1363 /*
1364 * Initialize an RX descriptor and attach an MBUF cluster.
1365 */
1366 static int
nge_newbuf(struct nge_softc * sc,int idx)1367 nge_newbuf(struct nge_softc *sc, int idx)
1368 {
1369 struct nge_desc *desc;
1370 struct nge_rxdesc *rxd;
1371 struct mbuf *m;
1372 bus_dma_segment_t segs[1];
1373 bus_dmamap_t map;
1374 int nsegs;
1375
1376 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1377 if (m == NULL)
1378 return (ENOBUFS);
1379 m->m_len = m->m_pkthdr.len = MCLBYTES;
1380 m_adj(m, sizeof(uint64_t));
1381
1382 if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag,
1383 sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1384 m_freem(m);
1385 return (ENOBUFS);
1386 }
1387 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1388
1389 rxd = &sc->nge_cdata.nge_rxdesc[idx];
1390 if (rxd->rx_m != NULL) {
1391 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap,
1392 BUS_DMASYNC_POSTREAD);
1393 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap);
1394 }
1395 map = rxd->rx_dmamap;
1396 rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap;
1397 sc->nge_cdata.nge_rx_sparemap = map;
1398 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap,
1399 BUS_DMASYNC_PREREAD);
1400 rxd->rx_m = m;
1401 desc = &sc->nge_rdata.nge_rx_ring[idx];
1402 desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr));
1403 desc->nge_cmdsts = htole32(segs[0].ds_len);
1404 desc->nge_extsts = 0;
1405
1406 return (0);
1407 }
1408
1409 #ifndef __NO_STRICT_ALIGNMENT
1410 static __inline void
nge_fixup_rx(struct mbuf * m)1411 nge_fixup_rx(struct mbuf *m)
1412 {
1413 int i;
1414 uint16_t *src, *dst;
1415
1416 src = mtod(m, uint16_t *);
1417 dst = src - 1;
1418
1419 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1420 *dst++ = *src++;
1421
1422 m->m_data -= ETHER_ALIGN;
1423 }
1424 #endif
1425
1426 /*
1427 * A frame has been uploaded: pass the resulting mbuf chain up to
1428 * the higher level protocols.
1429 */
1430 static int
nge_rxeof(struct nge_softc * sc)1431 nge_rxeof(struct nge_softc *sc)
1432 {
1433 struct mbuf *m;
1434 if_t ifp;
1435 struct nge_desc *cur_rx;
1436 struct nge_rxdesc *rxd;
1437 int cons, prog, rx_npkts, total_len;
1438 uint32_t cmdsts, extsts;
1439
1440 NGE_LOCK_ASSERT(sc);
1441
1442 ifp = sc->nge_ifp;
1443 cons = sc->nge_cdata.nge_rx_cons;
1444 rx_npkts = 0;
1445
1446 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag,
1447 sc->nge_cdata.nge_rx_ring_map,
1448 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1449
1450 for (prog = 0; prog < NGE_RX_RING_CNT &&
1451 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;
1452 NGE_INC(cons, NGE_RX_RING_CNT)) {
1453 #ifdef DEVICE_POLLING
1454 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1455 if (sc->rxcycles <= 0)
1456 break;
1457 sc->rxcycles--;
1458 }
1459 #endif
1460 cur_rx = &sc->nge_rdata.nge_rx_ring[cons];
1461 cmdsts = le32toh(cur_rx->nge_cmdsts);
1462 extsts = le32toh(cur_rx->nge_extsts);
1463 if ((cmdsts & NGE_CMDSTS_OWN) == 0)
1464 break;
1465 prog++;
1466 rxd = &sc->nge_cdata.nge_rxdesc[cons];
1467 m = rxd->rx_m;
1468 total_len = cmdsts & NGE_CMDSTS_BUFLEN;
1469
1470 if ((cmdsts & NGE_CMDSTS_MORE) != 0) {
1471 if (nge_newbuf(sc, cons) != 0) {
1472 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1473 if (sc->nge_head != NULL) {
1474 m_freem(sc->nge_head);
1475 sc->nge_head = sc->nge_tail = NULL;
1476 }
1477 nge_discard_rxbuf(sc, cons);
1478 continue;
1479 }
1480 m->m_len = total_len;
1481 if (sc->nge_head == NULL) {
1482 m->m_pkthdr.len = total_len;
1483 sc->nge_head = sc->nge_tail = m;
1484 } else {
1485 m->m_flags &= ~M_PKTHDR;
1486 sc->nge_head->m_pkthdr.len += total_len;
1487 sc->nge_tail->m_next = m;
1488 sc->nge_tail = m;
1489 }
1490 continue;
1491 }
1492
1493 /*
1494 * If an error occurs, update stats, clear the
1495 * status word and leave the mbuf cluster in place:
1496 * it should simply get re-used next time this descriptor
1497 * comes up in the ring.
1498 */
1499 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) {
1500 if ((cmdsts & NGE_RXSTAT_RUNT) &&
1501 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) {
1502 /*
1503 * Work-around hardware bug, accept runt frames
1504 * if its length is larger than or equal to 56.
1505 */
1506 } else {
1507 /*
1508 * Input error counters are updated by hardware.
1509 */
1510 if (sc->nge_head != NULL) {
1511 m_freem(sc->nge_head);
1512 sc->nge_head = sc->nge_tail = NULL;
1513 }
1514 nge_discard_rxbuf(sc, cons);
1515 continue;
1516 }
1517 }
1518
1519 /* Try conjure up a replacement mbuf. */
1520
1521 if (nge_newbuf(sc, cons) != 0) {
1522 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1523 if (sc->nge_head != NULL) {
1524 m_freem(sc->nge_head);
1525 sc->nge_head = sc->nge_tail = NULL;
1526 }
1527 nge_discard_rxbuf(sc, cons);
1528 continue;
1529 }
1530
1531 /* Chain received mbufs. */
1532 if (sc->nge_head != NULL) {
1533 m->m_len = total_len;
1534 m->m_flags &= ~M_PKTHDR;
1535 sc->nge_tail->m_next = m;
1536 m = sc->nge_head;
1537 m->m_pkthdr.len += total_len;
1538 sc->nge_head = sc->nge_tail = NULL;
1539 } else
1540 m->m_pkthdr.len = m->m_len = total_len;
1541
1542 /*
1543 * Ok. NatSemi really screwed up here. This is the
1544 * only gigE chip I know of with alignment constraints
1545 * on receive buffers. RX buffers must be 64-bit aligned.
1546 */
1547 /*
1548 * By popular demand, ignore the alignment problems
1549 * on the non-strict alignment platform. The performance hit
1550 * incurred due to unaligned accesses is much smaller
1551 * than the hit produced by forcing buffer copies all
1552 * the time, especially with jumbo frames. We still
1553 * need to fix up the alignment everywhere else though.
1554 */
1555 #ifndef __NO_STRICT_ALIGNMENT
1556 nge_fixup_rx(m);
1557 #endif
1558 m->m_pkthdr.rcvif = ifp;
1559 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1560
1561 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1562 /* Do IP checksum checking. */
1563 if ((extsts & NGE_RXEXTSTS_IPPKT) != 0)
1564 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1565 if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0)
1566 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1567 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1568 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1569 (extsts & NGE_RXEXTSTS_UDPPKT &&
1570 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1571 m->m_pkthdr.csum_flags |=
1572 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1573 m->m_pkthdr.csum_data = 0xffff;
1574 }
1575 }
1576
1577 /*
1578 * If we received a packet with a vlan tag, pass it
1579 * to vlan_input() instead of ether_input().
1580 */
1581 if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 &&
1582 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1583 m->m_pkthdr.ether_vtag =
1584 bswap16(extsts & NGE_RXEXTSTS_VTCI);
1585 m->m_flags |= M_VLANTAG;
1586 }
1587 NGE_UNLOCK(sc);
1588 if_input(ifp, m);
1589 NGE_LOCK(sc);
1590 rx_npkts++;
1591 }
1592
1593 if (prog > 0) {
1594 sc->nge_cdata.nge_rx_cons = cons;
1595 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag,
1596 sc->nge_cdata.nge_rx_ring_map,
1597 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1598 }
1599 return (rx_npkts);
1600 }
1601
1602 /*
1603 * A frame was downloaded to the chip. It's safe for us to clean up
1604 * the list buffers.
1605 */
1606 static void
nge_txeof(struct nge_softc * sc)1607 nge_txeof(struct nge_softc *sc)
1608 {
1609 struct nge_desc *cur_tx;
1610 struct nge_txdesc *txd;
1611 if_t ifp;
1612 uint32_t cmdsts;
1613 int cons, prod;
1614
1615 NGE_LOCK_ASSERT(sc);
1616 ifp = sc->nge_ifp;
1617
1618 cons = sc->nge_cdata.nge_tx_cons;
1619 prod = sc->nge_cdata.nge_tx_prod;
1620 if (cons == prod)
1621 return;
1622
1623 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag,
1624 sc->nge_cdata.nge_tx_ring_map,
1625 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1626
1627 /*
1628 * Go through our tx list and free mbufs for those
1629 * frames that have been transmitted.
1630 */
1631 for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) {
1632 cur_tx = &sc->nge_rdata.nge_tx_ring[cons];
1633 cmdsts = le32toh(cur_tx->nge_cmdsts);
1634 if ((cmdsts & NGE_CMDSTS_OWN) != 0)
1635 break;
1636 sc->nge_cdata.nge_tx_cnt--;
1637 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1638 if ((cmdsts & NGE_CMDSTS_MORE) != 0)
1639 continue;
1640
1641 txd = &sc->nge_cdata.nge_txdesc[cons];
1642 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap,
1643 BUS_DMASYNC_POSTWRITE);
1644 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap);
1645 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) {
1646 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1647 if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0)
1648 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1649 if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0)
1650 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1651 } else
1652 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1653
1654 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (cmdsts & NGE_TXSTAT_COLLCNT) >> 16);
1655 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n",
1656 __func__));
1657 m_freem(txd->tx_m);
1658 txd->tx_m = NULL;
1659 }
1660
1661 sc->nge_cdata.nge_tx_cons = cons;
1662 if (sc->nge_cdata.nge_tx_cnt == 0)
1663 sc->nge_watchdog_timer = 0;
1664 }
1665
1666 static void
nge_tick(void * xsc)1667 nge_tick(void *xsc)
1668 {
1669 struct nge_softc *sc;
1670 struct mii_data *mii;
1671
1672 sc = xsc;
1673 NGE_LOCK_ASSERT(sc);
1674 mii = device_get_softc(sc->nge_miibus);
1675 mii_tick(mii);
1676 /*
1677 * For PHYs that does not reset established link, it is
1678 * necessary to check whether driver still have a valid
1679 * link(e.g link state change callback is not called).
1680 * Otherwise, driver think it lost link because driver
1681 * initialization routine clears link state flag.
1682 */
1683 if ((sc->nge_flags & NGE_FLAG_LINK) == 0)
1684 nge_miibus_statchg(sc->nge_dev);
1685 nge_stats_update(sc);
1686 nge_watchdog(sc);
1687 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
1688 }
1689
1690 static void
nge_stats_update(struct nge_softc * sc)1691 nge_stats_update(struct nge_softc *sc)
1692 {
1693 if_t ifp;
1694 struct nge_stats now, *stats, *nstats;
1695
1696 NGE_LOCK_ASSERT(sc);
1697
1698 ifp = sc->nge_ifp;
1699 stats = &now;
1700 stats->rx_pkts_errs =
1701 CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF;
1702 stats->rx_crc_errs =
1703 CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF;
1704 stats->rx_fifo_oflows =
1705 CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF;
1706 stats->rx_align_errs =
1707 CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF;
1708 stats->rx_sym_errs =
1709 CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF;
1710 stats->rx_pkts_jumbos =
1711 CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF;
1712 stats->rx_len_errs =
1713 CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF;
1714 stats->rx_unctl_frames =
1715 CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF;
1716 stats->rx_pause =
1717 CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF;
1718 stats->tx_pause =
1719 CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF;
1720 stats->tx_seq_errs =
1721 CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF;
1722
1723 /*
1724 * Since we've accept errored frames exclude Rx length errors.
1725 */
1726 if_inc_counter(ifp, IFCOUNTER_IERRORS,
1727 stats->rx_pkts_errs + stats->rx_crc_errs +
1728 stats->rx_fifo_oflows + stats->rx_sym_errs);
1729
1730 nstats = &sc->nge_stats;
1731 nstats->rx_pkts_errs += stats->rx_pkts_errs;
1732 nstats->rx_crc_errs += stats->rx_crc_errs;
1733 nstats->rx_fifo_oflows += stats->rx_fifo_oflows;
1734 nstats->rx_align_errs += stats->rx_align_errs;
1735 nstats->rx_sym_errs += stats->rx_sym_errs;
1736 nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos;
1737 nstats->rx_len_errs += stats->rx_len_errs;
1738 nstats->rx_unctl_frames += stats->rx_unctl_frames;
1739 nstats->rx_pause += stats->rx_pause;
1740 nstats->tx_pause += stats->tx_pause;
1741 nstats->tx_seq_errs += stats->tx_seq_errs;
1742 }
1743
1744 #ifdef DEVICE_POLLING
1745 static poll_handler_t nge_poll;
1746
1747 static int
nge_poll(if_t ifp,enum poll_cmd cmd,int count)1748 nge_poll(if_t ifp, enum poll_cmd cmd, int count)
1749 {
1750 struct nge_softc *sc;
1751 int rx_npkts = 0;
1752
1753 sc = if_getsoftc(ifp);
1754
1755 NGE_LOCK(sc);
1756 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1757 NGE_UNLOCK(sc);
1758 return (rx_npkts);
1759 }
1760
1761 /*
1762 * On the nge, reading the status register also clears it.
1763 * So before returning to intr mode we must make sure that all
1764 * possible pending sources of interrupts have been served.
1765 * In practice this means run to completion the *eof routines,
1766 * and then call the interrupt routine.
1767 */
1768 sc->rxcycles = count;
1769 rx_npkts = nge_rxeof(sc);
1770 nge_txeof(sc);
1771 if (!if_sendq_empty(ifp))
1772 nge_start_locked(ifp);
1773
1774 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1775 uint32_t status;
1776
1777 /* Reading the ISR register clears all interrupts. */
1778 status = CSR_READ_4(sc, NGE_ISR);
1779
1780 if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0)
1781 rx_npkts += nge_rxeof(sc);
1782
1783 if ((status & NGE_ISR_RX_IDLE) != 0)
1784 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1785
1786 if ((status & NGE_ISR_SYSERR) != 0) {
1787 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1788 nge_init_locked(sc);
1789 }
1790 }
1791 NGE_UNLOCK(sc);
1792 return (rx_npkts);
1793 }
1794 #endif /* DEVICE_POLLING */
1795
1796 static void
nge_intr(void * arg)1797 nge_intr(void *arg)
1798 {
1799 struct nge_softc *sc;
1800 if_t ifp;
1801 uint32_t status;
1802
1803 sc = (struct nge_softc *)arg;
1804 ifp = sc->nge_ifp;
1805
1806 NGE_LOCK(sc);
1807
1808 if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0)
1809 goto done_locked;
1810
1811 /* Reading the ISR register clears all interrupts. */
1812 status = CSR_READ_4(sc, NGE_ISR);
1813 if (status == 0xffffffff || (status & NGE_INTRS) == 0)
1814 goto done_locked;
1815 #ifdef DEVICE_POLLING
1816 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0)
1817 goto done_locked;
1818 #endif
1819 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1820 goto done_locked;
1821
1822 /* Disable interrupts. */
1823 CSR_WRITE_4(sc, NGE_IER, 0);
1824
1825 /* Data LED on for TBI mode */
1826 if ((sc->nge_flags & NGE_FLAG_TBI) != 0)
1827 CSR_WRITE_4(sc, NGE_GPIO,
1828 CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT);
1829
1830 for (; (status & NGE_INTRS) != 0;) {
1831 if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR |
1832 NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0)
1833 nge_txeof(sc);
1834
1835 if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR |
1836 NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW |
1837 NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0)
1838 nge_rxeof(sc);
1839
1840 if ((status & NGE_ISR_RX_IDLE) != 0)
1841 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1842
1843 if ((status & NGE_ISR_SYSERR) != 0) {
1844 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1845 nge_init_locked(sc);
1846 }
1847 /* Reading the ISR register clears all interrupts. */
1848 status = CSR_READ_4(sc, NGE_ISR);
1849 }
1850
1851 /* Re-enable interrupts. */
1852 CSR_WRITE_4(sc, NGE_IER, 1);
1853
1854 if (!if_sendq_empty(ifp))
1855 nge_start_locked(ifp);
1856
1857 /* Data LED off for TBI mode */
1858 if ((sc->nge_flags & NGE_FLAG_TBI) != 0)
1859 CSR_WRITE_4(sc, NGE_GPIO,
1860 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);
1861
1862 done_locked:
1863 NGE_UNLOCK(sc);
1864 }
1865
1866 /*
1867 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1868 * pointers to the fragment pointers.
1869 */
1870 static int
nge_encap(struct nge_softc * sc,struct mbuf ** m_head)1871 nge_encap(struct nge_softc *sc, struct mbuf **m_head)
1872 {
1873 struct nge_txdesc *txd, *txd_last;
1874 struct nge_desc *desc;
1875 struct mbuf *m;
1876 bus_dmamap_t map;
1877 bus_dma_segment_t txsegs[NGE_MAXTXSEGS];
1878 int error, i, nsegs, prod, si;
1879
1880 NGE_LOCK_ASSERT(sc);
1881
1882 m = *m_head;
1883 prod = sc->nge_cdata.nge_tx_prod;
1884 txd = &sc->nge_cdata.nge_txdesc[prod];
1885 txd_last = txd;
1886 map = txd->tx_dmamap;
1887 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map,
1888 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1889 if (error == EFBIG) {
1890 m = m_collapse(*m_head, M_NOWAIT, NGE_MAXTXSEGS);
1891 if (m == NULL) {
1892 m_freem(*m_head);
1893 *m_head = NULL;
1894 return (ENOBUFS);
1895 }
1896 *m_head = m;
1897 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag,
1898 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1899 if (error != 0) {
1900 m_freem(*m_head);
1901 *m_head = NULL;
1902 return (error);
1903 }
1904 } else if (error != 0)
1905 return (error);
1906 if (nsegs == 0) {
1907 m_freem(*m_head);
1908 *m_head = NULL;
1909 return (EIO);
1910 }
1911
1912 /* Check number of available descriptors. */
1913 if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) {
1914 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map);
1915 return (ENOBUFS);
1916 }
1917
1918 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE);
1919
1920 si = prod;
1921 for (i = 0; i < nsegs; i++) {
1922 desc = &sc->nge_rdata.nge_tx_ring[prod];
1923 desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr));
1924 if (i == 0)
1925 desc->nge_cmdsts = htole32(txsegs[i].ds_len |
1926 NGE_CMDSTS_MORE);
1927 else
1928 desc->nge_cmdsts = htole32(txsegs[i].ds_len |
1929 NGE_CMDSTS_MORE | NGE_CMDSTS_OWN);
1930 desc->nge_extsts = 0;
1931 sc->nge_cdata.nge_tx_cnt++;
1932 NGE_INC(prod, NGE_TX_RING_CNT);
1933 }
1934 /* Update producer index. */
1935 sc->nge_cdata.nge_tx_prod = prod;
1936
1937 prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT;
1938 desc = &sc->nge_rdata.nge_tx_ring[prod];
1939 /* Check if we have a VLAN tag to insert. */
1940 if ((m->m_flags & M_VLANTAG) != 0)
1941 desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT |
1942 bswap16(m->m_pkthdr.ether_vtag));
1943 /* Set EOP on the last descriptor. */
1944 desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE);
1945
1946 /* Set checksum offload in the first descriptor. */
1947 desc = &sc->nge_rdata.nge_tx_ring[si];
1948 if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) {
1949 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1950 desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM);
1951 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1952 desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM);
1953 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1954 desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM);
1955 }
1956 /* Lastly, turn the first descriptor ownership to hardware. */
1957 desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN);
1958
1959 txd = &sc->nge_cdata.nge_txdesc[prod];
1960 map = txd_last->tx_dmamap;
1961 txd_last->tx_dmamap = txd->tx_dmamap;
1962 txd->tx_dmamap = map;
1963 txd->tx_m = m;
1964
1965 return (0);
1966 }
1967
1968 /*
1969 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1970 * to the mbuf data regions directly in the transmit lists. We also save a
1971 * copy of the pointers since the transmit list fragment pointers are
1972 * physical addresses.
1973 */
1974
1975 static void
nge_start(if_t ifp)1976 nge_start(if_t ifp)
1977 {
1978 struct nge_softc *sc;
1979
1980 sc = if_getsoftc(ifp);
1981 NGE_LOCK(sc);
1982 nge_start_locked(ifp);
1983 NGE_UNLOCK(sc);
1984 }
1985
1986 static void
nge_start_locked(if_t ifp)1987 nge_start_locked(if_t ifp)
1988 {
1989 struct nge_softc *sc;
1990 struct mbuf *m_head;
1991 int enq;
1992
1993 sc = if_getsoftc(ifp);
1994
1995 NGE_LOCK_ASSERT(sc);
1996
1997 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1998 IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0)
1999 return;
2000
2001 for (enq = 0; !if_sendq_empty(ifp) &&
2002 sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) {
2003 m_head = if_dequeue(ifp);
2004 if (m_head == NULL)
2005 break;
2006 /*
2007 * Pack the data into the transmit ring. If we
2008 * don't have room, set the OACTIVE flag and wait
2009 * for the NIC to drain the ring.
2010 */
2011 if (nge_encap(sc, &m_head)) {
2012 if (m_head == NULL)
2013 break;
2014 if_sendq_prepend(ifp, m_head);
2015 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2016 break;
2017 }
2018
2019 enq++;
2020 /*
2021 * If there's a BPF listener, bounce a copy of this frame
2022 * to him.
2023 */
2024 ETHER_BPF_MTAP(ifp, m_head);
2025 }
2026
2027 if (enq > 0) {
2028 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag,
2029 sc->nge_cdata.nge_tx_ring_map,
2030 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2031 /* Transmit */
2032 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
2033
2034 /* Set a timeout in case the chip goes out to lunch. */
2035 sc->nge_watchdog_timer = 5;
2036 }
2037 }
2038
2039 static void
nge_init(void * xsc)2040 nge_init(void *xsc)
2041 {
2042 struct nge_softc *sc = xsc;
2043
2044 NGE_LOCK(sc);
2045 nge_init_locked(sc);
2046 NGE_UNLOCK(sc);
2047 }
2048
2049 static void
nge_init_locked(struct nge_softc * sc)2050 nge_init_locked(struct nge_softc *sc)
2051 {
2052 if_t ifp = sc->nge_ifp;
2053 struct mii_data *mii;
2054 uint8_t *eaddr;
2055 uint32_t reg;
2056
2057 NGE_LOCK_ASSERT(sc);
2058
2059 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2060 return;
2061
2062 /*
2063 * Cancel pending I/O and free all RX/TX buffers.
2064 */
2065 nge_stop(sc);
2066
2067 /* Reset the adapter. */
2068 nge_reset(sc);
2069
2070 /* Disable Rx filter prior to programming Rx filter. */
2071 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0);
2072 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE);
2073
2074 mii = device_get_softc(sc->nge_miibus);
2075
2076 /* Set MAC address. */
2077 eaddr = if_getlladdr(sc->nge_ifp);
2078 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
2079 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]);
2080 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
2081 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]);
2082 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
2083 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]);
2084
2085 /* Init circular RX list. */
2086 if (nge_list_rx_init(sc) == ENOBUFS) {
2087 device_printf(sc->nge_dev, "initialization failed: no "
2088 "memory for rx buffers\n");
2089 nge_stop(sc);
2090 return;
2091 }
2092
2093 /*
2094 * Init tx descriptors.
2095 */
2096 nge_list_tx_init(sc);
2097
2098 /* Set Rx filter. */
2099 nge_rxfilter(sc);
2100
2101 /* Disable PRIQ ctl. */
2102 CSR_WRITE_4(sc, NGE_PRIOQCTL, 0);
2103
2104 /*
2105 * Set pause frames parameters.
2106 * Rx stat FIFO hi-threshold : 2 or more packets
2107 * Rx stat FIFO lo-threshold : less than 2 packets
2108 * Rx data FIFO hi-threshold : 2K or more bytes
2109 * Rx data FIFO lo-threshold : less than 2K bytes
2110 * pause time : (512ns * 0xffff) -> 33.55ms
2111 */
2112 CSR_WRITE_4(sc, NGE_PAUSECSR,
2113 NGE_PAUSECSR_PAUSE_ON_MCAST |
2114 NGE_PAUSECSR_PAUSE_ON_DA |
2115 ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) |
2116 ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) |
2117 ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) |
2118 ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) |
2119 NGE_PAUSECSR_CNT);
2120
2121 /*
2122 * Load the address of the RX and TX lists.
2123 */
2124 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI,
2125 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr));
2126 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO,
2127 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr));
2128 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI,
2129 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr));
2130 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO,
2131 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr));
2132
2133 /* Set RX configuration. */
2134 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
2135
2136 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0);
2137 /*
2138 * Enable hardware checksum validation for all IPv4
2139 * packets, do not reject packets with bad checksums.
2140 */
2141 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2142 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
2143
2144 /*
2145 * Tell the chip to detect and strip VLAN tag info from
2146 * received frames. The tag will be provided in the extsts
2147 * field in the RX descriptors.
2148 */
2149 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB);
2150 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2151 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB);
2152
2153 /* Set TX configuration. */
2154 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
2155
2156 /*
2157 * Enable TX IPv4 checksumming on a per-packet basis.
2158 */
2159 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
2160
2161 /*
2162 * Tell the chip to insert VLAN tags on a per-packet basis as
2163 * dictated by the code in the frame encapsulation routine.
2164 */
2165 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
2166
2167 /*
2168 * Enable the delivery of PHY interrupts based on
2169 * link/speed/duplex status changes. Also enable the
2170 * extsts field in the DMA descriptors (needed for
2171 * TCP/IP checksum offload on transmit).
2172 */
2173 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
2174 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
2175
2176 /*
2177 * Configure interrupt holdoff (moderation). We can
2178 * have the chip delay interrupt delivery for a certain
2179 * period. Units are in 100us, and the max setting
2180 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
2181 */
2182 CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff);
2183
2184 /*
2185 * Enable MAC statistics counters and clear.
2186 */
2187 reg = CSR_READ_4(sc, NGE_MIBCTL);
2188 reg &= ~NGE_MIBCTL_FREEZE_CNT;
2189 reg |= NGE_MIBCTL_CLEAR_CNT;
2190 CSR_WRITE_4(sc, NGE_MIBCTL, reg);
2191
2192 /*
2193 * Enable interrupts.
2194 */
2195 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
2196 #ifdef DEVICE_POLLING
2197 /*
2198 * ... only enable interrupts if we are not polling, make sure
2199 * they are off otherwise.
2200 */
2201 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0)
2202 CSR_WRITE_4(sc, NGE_IER, 0);
2203 else
2204 #endif
2205 CSR_WRITE_4(sc, NGE_IER, 1);
2206
2207 sc->nge_flags &= ~NGE_FLAG_LINK;
2208 mii_mediachg(mii);
2209
2210 sc->nge_watchdog_timer = 0;
2211 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
2212
2213 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2214 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2215 }
2216
2217 /*
2218 * Set media options.
2219 */
2220 static int
nge_mediachange(if_t ifp)2221 nge_mediachange(if_t ifp)
2222 {
2223 struct nge_softc *sc;
2224 struct mii_data *mii;
2225 struct mii_softc *miisc;
2226 int error;
2227
2228 sc = if_getsoftc(ifp);
2229 NGE_LOCK(sc);
2230 mii = device_get_softc(sc->nge_miibus);
2231 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2232 PHY_RESET(miisc);
2233 error = mii_mediachg(mii);
2234 NGE_UNLOCK(sc);
2235
2236 return (error);
2237 }
2238
2239 /*
2240 * Report current media status.
2241 */
2242 static void
nge_mediastatus(if_t ifp,struct ifmediareq * ifmr)2243 nge_mediastatus(if_t ifp, struct ifmediareq *ifmr)
2244 {
2245 struct nge_softc *sc;
2246 struct mii_data *mii;
2247
2248 sc = if_getsoftc(ifp);
2249 NGE_LOCK(sc);
2250 mii = device_get_softc(sc->nge_miibus);
2251 mii_pollstat(mii);
2252 ifmr->ifm_active = mii->mii_media_active;
2253 ifmr->ifm_status = mii->mii_media_status;
2254 NGE_UNLOCK(sc);
2255 }
2256
2257 static int
nge_ioctl(if_t ifp,u_long command,caddr_t data)2258 nge_ioctl(if_t ifp, u_long command, caddr_t data)
2259 {
2260 struct nge_softc *sc = if_getsoftc(ifp);
2261 struct ifreq *ifr = (struct ifreq *) data;
2262 struct mii_data *mii;
2263 int error = 0, mask;
2264
2265 switch (command) {
2266 case SIOCSIFMTU:
2267 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU)
2268 error = EINVAL;
2269 else {
2270 NGE_LOCK(sc);
2271 if_setmtu(ifp, ifr->ifr_mtu);
2272 /*
2273 * Workaround: if the MTU is larger than
2274 * 8152 (TX FIFO size minus 64 minus 18), turn off
2275 * TX checksum offloading.
2276 */
2277 if (ifr->ifr_mtu >= 8152) {
2278 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
2279 if_sethwassistbits(ifp, 0, NGE_CSUM_FEATURES);
2280 } else {
2281 if_setcapenablebit(ifp, IFCAP_TXCSUM, 0);
2282 if_sethwassistbits(ifp, NGE_CSUM_FEATURES, 0);
2283 }
2284 NGE_UNLOCK(sc);
2285 VLAN_CAPABILITIES(ifp);
2286 }
2287 break;
2288 case SIOCSIFFLAGS:
2289 NGE_LOCK(sc);
2290 if ((if_getflags(ifp) & IFF_UP) != 0) {
2291 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2292 if ((if_getflags(ifp) ^ sc->nge_if_flags) &
2293 (IFF_PROMISC | IFF_ALLMULTI))
2294 nge_rxfilter(sc);
2295 } else {
2296 if ((sc->nge_flags & NGE_FLAG_DETACH) == 0)
2297 nge_init_locked(sc);
2298 }
2299 } else {
2300 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2301 nge_stop(sc);
2302 }
2303 sc->nge_if_flags = if_getflags(ifp);
2304 NGE_UNLOCK(sc);
2305 error = 0;
2306 break;
2307 case SIOCADDMULTI:
2308 case SIOCDELMULTI:
2309 NGE_LOCK(sc);
2310 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2311 nge_rxfilter(sc);
2312 NGE_UNLOCK(sc);
2313 break;
2314 case SIOCGIFMEDIA:
2315 case SIOCSIFMEDIA:
2316 mii = device_get_softc(sc->nge_miibus);
2317 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2318 break;
2319 case SIOCSIFCAP:
2320 NGE_LOCK(sc);
2321 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2322 #ifdef DEVICE_POLLING
2323 if ((mask & IFCAP_POLLING) != 0 &&
2324 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) {
2325 if_togglecapenable(ifp, IFCAP_POLLING);
2326 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) {
2327 error = ether_poll_register(nge_poll, ifp);
2328 if (error != 0) {
2329 NGE_UNLOCK(sc);
2330 break;
2331 }
2332 /* Disable interrupts. */
2333 CSR_WRITE_4(sc, NGE_IER, 0);
2334 } else {
2335 error = ether_poll_deregister(ifp);
2336 /* Enable interrupts. */
2337 CSR_WRITE_4(sc, NGE_IER, 1);
2338 }
2339 }
2340 #endif /* DEVICE_POLLING */
2341 if ((mask & IFCAP_TXCSUM) != 0 &&
2342 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
2343 if_togglecapenable(ifp, IFCAP_TXCSUM);
2344 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0)
2345 if_sethwassistbits(ifp, NGE_CSUM_FEATURES, 0);
2346 else
2347 if_sethwassistbits(ifp, 0, NGE_CSUM_FEATURES);
2348 }
2349 if ((mask & IFCAP_RXCSUM) != 0 &&
2350 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0)
2351 if_togglecapenable(ifp, IFCAP_RXCSUM);
2352
2353 if ((mask & IFCAP_WOL) != 0 &&
2354 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) {
2355 if ((mask & IFCAP_WOL_UCAST) != 0)
2356 if_togglecapenable(ifp, IFCAP_WOL_UCAST);
2357 if ((mask & IFCAP_WOL_MCAST) != 0)
2358 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
2359 if ((mask & IFCAP_WOL_MAGIC) != 0)
2360 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2361 }
2362
2363 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2364 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2365 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2366 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2367 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2368 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2369 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2370 if ((if_getcapenable(ifp) &
2371 IFCAP_VLAN_HWTAGGING) != 0)
2372 NGE_SETBIT(sc,
2373 NGE_VLAN_IP_RXCTL,
2374 NGE_VIPRXCTL_TAG_STRIP_ENB);
2375 else
2376 NGE_CLRBIT(sc,
2377 NGE_VLAN_IP_RXCTL,
2378 NGE_VIPRXCTL_TAG_STRIP_ENB);
2379 }
2380 }
2381 /*
2382 * Both VLAN hardware tagging and checksum offload is
2383 * required to do checksum offload on VLAN interface.
2384 */
2385 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) == 0)
2386 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM);
2387 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2388 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM);
2389 NGE_UNLOCK(sc);
2390 VLAN_CAPABILITIES(ifp);
2391 break;
2392 default:
2393 error = ether_ioctl(ifp, command, data);
2394 break;
2395 }
2396
2397 return (error);
2398 }
2399
2400 static void
nge_watchdog(struct nge_softc * sc)2401 nge_watchdog(struct nge_softc *sc)
2402 {
2403 if_t ifp;
2404
2405 NGE_LOCK_ASSERT(sc);
2406
2407 if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer)
2408 return;
2409
2410 ifp = sc->nge_ifp;
2411 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2412 if_printf(ifp, "watchdog timeout\n");
2413
2414 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2415 nge_init_locked(sc);
2416
2417 if (!if_sendq_empty(ifp))
2418 nge_start_locked(ifp);
2419 }
2420
2421 static int
nge_stop_mac(struct nge_softc * sc)2422 nge_stop_mac(struct nge_softc *sc)
2423 {
2424 uint32_t reg;
2425 int i;
2426
2427 NGE_LOCK_ASSERT(sc);
2428
2429 reg = CSR_READ_4(sc, NGE_CSR);
2430 if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) {
2431 reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE);
2432 reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE;
2433 CSR_WRITE_4(sc, NGE_CSR, reg);
2434 for (i = 0; i < NGE_TIMEOUT; i++) {
2435 DELAY(1);
2436 if ((CSR_READ_4(sc, NGE_CSR) &
2437 (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0)
2438 break;
2439 }
2440 if (i == NGE_TIMEOUT)
2441 return (ETIMEDOUT);
2442 }
2443
2444 return (0);
2445 }
2446
2447 /*
2448 * Stop the adapter and free any mbufs allocated to the
2449 * RX and TX lists.
2450 */
2451 static void
nge_stop(struct nge_softc * sc)2452 nge_stop(struct nge_softc *sc)
2453 {
2454 struct nge_txdesc *txd;
2455 struct nge_rxdesc *rxd;
2456 int i;
2457 if_t ifp;
2458
2459 NGE_LOCK_ASSERT(sc);
2460 ifp = sc->nge_ifp;
2461
2462 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2463 sc->nge_flags &= ~NGE_FLAG_LINK;
2464 callout_stop(&sc->nge_stat_ch);
2465 sc->nge_watchdog_timer = 0;
2466
2467 CSR_WRITE_4(sc, NGE_IER, 0);
2468 CSR_WRITE_4(sc, NGE_IMR, 0);
2469 if (nge_stop_mac(sc) == ETIMEDOUT)
2470 device_printf(sc->nge_dev,
2471 "%s: unable to stop Tx/Rx MAC\n", __func__);
2472 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0);
2473 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0);
2474 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0);
2475 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0);
2476 nge_stats_update(sc);
2477 if (sc->nge_head != NULL) {
2478 m_freem(sc->nge_head);
2479 sc->nge_head = sc->nge_tail = NULL;
2480 }
2481
2482 /*
2483 * Free RX and TX mbufs still in the queues.
2484 */
2485 for (i = 0; i < NGE_RX_RING_CNT; i++) {
2486 rxd = &sc->nge_cdata.nge_rxdesc[i];
2487 if (rxd->rx_m != NULL) {
2488 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag,
2489 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2490 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag,
2491 rxd->rx_dmamap);
2492 m_freem(rxd->rx_m);
2493 rxd->rx_m = NULL;
2494 }
2495 }
2496 for (i = 0; i < NGE_TX_RING_CNT; i++) {
2497 txd = &sc->nge_cdata.nge_txdesc[i];
2498 if (txd->tx_m != NULL) {
2499 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag,
2500 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2501 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag,
2502 txd->tx_dmamap);
2503 m_freem(txd->tx_m);
2504 txd->tx_m = NULL;
2505 }
2506 }
2507 }
2508
2509 /*
2510 * Before setting WOL bits, caller should have stopped Receiver.
2511 */
2512 static void
nge_wol(struct nge_softc * sc)2513 nge_wol(struct nge_softc *sc)
2514 {
2515 if_t ifp;
2516 uint32_t reg;
2517 uint16_t pmstat;
2518 int pmc;
2519
2520 NGE_LOCK_ASSERT(sc);
2521
2522 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0)
2523 return;
2524
2525 ifp = sc->nge_ifp;
2526 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
2527 /* Disable WOL & disconnect CLKRUN to save power. */
2528 CSR_WRITE_4(sc, NGE_WOLCSR, 0);
2529 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
2530 } else {
2531 if (nge_stop_mac(sc) == ETIMEDOUT)
2532 device_printf(sc->nge_dev,
2533 "%s: unable to stop Tx/Rx MAC\n", __func__);
2534 /*
2535 * Make sure wake frames will be buffered in the Rx FIFO.
2536 * (i.e. Silent Rx mode.)
2537 */
2538 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0);
2539 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_HI, BUS_SPACE_BARRIER_WRITE);
2540 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0);
2541 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_LO, BUS_SPACE_BARRIER_WRITE);
2542 /* Enable Rx again. */
2543 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
2544 CSR_BARRIER_4(sc, NGE_CSR, BUS_SPACE_BARRIER_WRITE);
2545
2546 /* Configure WOL events. */
2547 reg = 0;
2548 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0)
2549 reg |= NGE_WOLCSR_WAKE_ON_UNICAST;
2550 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2551 reg |= NGE_WOLCSR_WAKE_ON_MULTICAST;
2552 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2553 reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT;
2554 CSR_WRITE_4(sc, NGE_WOLCSR, reg);
2555
2556 /* Activate CLKRUN. */
2557 reg = CSR_READ_4(sc, NGE_CLKRUN);
2558 reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB;
2559 CSR_WRITE_4(sc, NGE_CLKRUN, reg);
2560 }
2561
2562 /* Request PME. */
2563 pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2);
2564 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2565 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2566 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2567 pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2568 }
2569
2570 /*
2571 * Stop all chip I/O so that the kernel's probe routines don't
2572 * get confused by errant DMAs when rebooting.
2573 */
2574 static int
nge_shutdown(device_t dev)2575 nge_shutdown(device_t dev)
2576 {
2577
2578 return (nge_suspend(dev));
2579 }
2580
2581 static int
nge_suspend(device_t dev)2582 nge_suspend(device_t dev)
2583 {
2584 struct nge_softc *sc;
2585
2586 sc = device_get_softc(dev);
2587
2588 NGE_LOCK(sc);
2589 nge_stop(sc);
2590 nge_wol(sc);
2591 sc->nge_flags |= NGE_FLAG_SUSPENDED;
2592 NGE_UNLOCK(sc);
2593
2594 return (0);
2595 }
2596
2597 static int
nge_resume(device_t dev)2598 nge_resume(device_t dev)
2599 {
2600 struct nge_softc *sc;
2601 if_t ifp;
2602 uint16_t pmstat;
2603 int pmc;
2604
2605 sc = device_get_softc(dev);
2606
2607 NGE_LOCK(sc);
2608 ifp = sc->nge_ifp;
2609 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) {
2610 /* Disable PME and clear PME status. */
2611 pmstat = pci_read_config(sc->nge_dev,
2612 pmc + PCIR_POWER_STATUS, 2);
2613 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2614 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2615 pci_write_config(sc->nge_dev,
2616 pmc + PCIR_POWER_STATUS, pmstat, 2);
2617 }
2618 }
2619 if (if_getflags(ifp) & IFF_UP) {
2620 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2621 nge_init_locked(sc);
2622 }
2623
2624 sc->nge_flags &= ~NGE_FLAG_SUSPENDED;
2625 NGE_UNLOCK(sc);
2626
2627 return (0);
2628 }
2629
2630 #define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2631 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2632
2633 static void
nge_sysctl_node(struct nge_softc * sc)2634 nge_sysctl_node(struct nge_softc *sc)
2635 {
2636 struct sysctl_ctx_list *ctx;
2637 struct sysctl_oid_list *child, *parent;
2638 struct sysctl_oid *tree;
2639 struct nge_stats *stats;
2640 int error;
2641
2642 ctx = device_get_sysctl_ctx(sc->nge_dev);
2643 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev));
2644 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff",
2645 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->nge_int_holdoff,
2646 0, sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation");
2647 /* Pull in device tunables. */
2648 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT;
2649 error = resource_int_value(device_get_name(sc->nge_dev),
2650 device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff);
2651 if (error == 0) {
2652 if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN ||
2653 sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) {
2654 device_printf(sc->nge_dev,
2655 "int_holdoff value out of range; "
2656 "using default: %d(%d us)\n",
2657 NGE_INT_HOLDOFF_DEFAULT,
2658 NGE_INT_HOLDOFF_DEFAULT * 100);
2659 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT;
2660 }
2661 }
2662
2663 stats = &sc->nge_stats;
2664 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
2665 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NGE statistics");
2666 parent = SYSCTL_CHILDREN(tree);
2667
2668 /* Rx statistics. */
2669 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
2670 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
2671 child = SYSCTL_CHILDREN(tree);
2672 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs",
2673 &stats->rx_pkts_errs,
2674 "Packet errors including both wire errors and FIFO overruns");
2675 NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
2676 &stats->rx_crc_errs, "CRC errors");
2677 NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
2678 &stats->rx_fifo_oflows, "FIFO overflows");
2679 NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
2680 &stats->rx_align_errs, "Frame alignment errors");
2681 NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs",
2682 &stats->rx_sym_errs, "One or more symbol errors");
2683 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos",
2684 &stats->rx_pkts_jumbos,
2685 "Packets received with length greater than 1518 bytes");
2686 NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
2687 &stats->rx_len_errs, "In Range Length errors");
2688 NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames",
2689 &stats->rx_unctl_frames, "Control frames with unsupported opcode");
2690 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause",
2691 &stats->rx_pause, "Pause frames");
2692
2693 /* Tx statistics. */
2694 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
2695 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
2696 child = SYSCTL_CHILDREN(tree);
2697 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause",
2698 &stats->tx_pause, "Pause frames");
2699 NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs",
2700 &stats->tx_seq_errs,
2701 "Loss of collision heartbeat during transmission");
2702 }
2703
2704 #undef NGE_SYSCTL_STAT_ADD32
2705
2706 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)2707 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2708 {
2709 int error, value;
2710
2711 if (arg1 == NULL)
2712 return (EINVAL);
2713 value = *(int *)arg1;
2714 error = sysctl_handle_int(oidp, &value, 0, req);
2715 if (error != 0 || req->newptr == NULL)
2716 return (error);
2717 if (value < low || value > high)
2718 return (EINVAL);
2719 *(int *)arg1 = value;
2720
2721 return (0);
2722 }
2723
2724 static int
sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS)2725 sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS)
2726 {
2727
2728 return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN,
2729 NGE_INT_HOLDOFF_MAX));
2730 }
2731