xref: /titanic_41/usr/src/uts/common/io/i40e/core/i40e_adminq.h (revision f8cad4941c772dbfb48b3a9446f336b524ea3b3d)
1 /******************************************************************************
2 
3   Copyright (c) 2013-2015, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
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10       this list of conditions and the following disclaimer.
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12    2. Redistributions in binary form must reproduce the above copyright
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14       documentation and/or other materials provided with the distribution.
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16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _I40E_ADMINQ_H_
36 #define _I40E_ADMINQ_H_
37 
38 #include "i40e_osdep.h"
39 #include "i40e_status.h"
40 #include "i40e_adminq_cmd.h"
41 
42 #define I40E_ADMINQ_DESC(R, i)   \
43 	(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
44 
45 #define I40E_ADMINQ_DESC_ALIGNMENT 4096
46 
47 struct i40e_adminq_ring {
48 	struct i40e_virt_mem dma_head;	/* space for dma structures */
49 	struct i40e_dma_mem desc_buf;	/* descriptor ring memory */
50 	struct i40e_virt_mem cmd_buf;	/* command buffer memory */
51 
52 	union {
53 		struct i40e_dma_mem *asq_bi;
54 		struct i40e_dma_mem *arq_bi;
55 	} r;
56 
57 	u16 count;		/* Number of descriptors */
58 	u16 rx_buf_len;		/* Admin Receive Queue buffer length */
59 
60 	/* used for interrupt processing */
61 	u16 next_to_use;
62 	u16 next_to_clean;
63 
64 	/* used for queue tracking */
65 	u32 head;
66 	u32 tail;
67 	u32 len;
68 	u32 bah;
69 	u32 bal;
70 };
71 
72 /* ASQ transaction details */
73 struct i40e_asq_cmd_details {
74 	void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
75 	u64 cookie;
76 	u16 flags_ena;
77 	u16 flags_dis;
78 	bool async;
79 	bool postpone;
80 	struct i40e_aq_desc *wb_desc;
81 };
82 
83 #define I40E_ADMINQ_DETAILS(R, i)   \
84 	(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
85 
86 /* ARQ event information */
87 struct i40e_arq_event_info {
88 	struct i40e_aq_desc desc;
89 	u16 msg_len;
90 	u16 buf_len;
91 	u8 *msg_buf;
92 };
93 
94 /* Admin Queue information */
95 struct i40e_adminq_info {
96 	struct i40e_adminq_ring arq;    /* receive queue */
97 	struct i40e_adminq_ring asq;    /* send queue */
98 	u32 asq_cmd_timeout;            /* send queue cmd write back timeout*/
99 	u16 num_arq_entries;            /* receive queue depth */
100 	u16 num_asq_entries;            /* send queue depth */
101 	u16 arq_buf_size;               /* receive queue buffer size */
102 	u16 asq_buf_size;               /* send queue buffer size */
103 	u16 fw_maj_ver;                 /* firmware major version */
104 	u16 fw_min_ver;                 /* firmware minor version */
105 	u32 fw_build;                   /* firmware build number */
106 	u16 api_maj_ver;                /* api major version */
107 	u16 api_min_ver;                /* api minor version */
108 
109 	struct i40e_spinlock asq_spinlock; /* Send queue spinlock */
110 	struct i40e_spinlock arq_spinlock; /* Receive queue spinlock */
111 
112 	/* last status values on send and receive queues */
113 	enum i40e_admin_queue_err asq_last_status;
114 	enum i40e_admin_queue_err arq_last_status;
115 };
116 
117 /**
118  * i40e_aq_rc_to_posix - convert errors to user-land codes
119  * aq_ret: AdminQ handler error code can override aq_rc
120  * aq_rc: AdminQ firmware error code to convert
121  **/
i40e_aq_rc_to_posix(int aq_ret,int aq_rc)122 static INLINE int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)
123 {
124 	int aq_to_posix[] = {
125 		0,           /* I40E_AQ_RC_OK */
126 		-EPERM,      /* I40E_AQ_RC_EPERM */
127 		-ENOENT,     /* I40E_AQ_RC_ENOENT */
128 		-ESRCH,      /* I40E_AQ_RC_ESRCH */
129 		-EINTR,      /* I40E_AQ_RC_EINTR */
130 		-EIO,        /* I40E_AQ_RC_EIO */
131 		-ENXIO,      /* I40E_AQ_RC_ENXIO */
132 		-E2BIG,      /* I40E_AQ_RC_E2BIG */
133 		-EAGAIN,     /* I40E_AQ_RC_EAGAIN */
134 		-ENOMEM,     /* I40E_AQ_RC_ENOMEM */
135 		-EACCES,     /* I40E_AQ_RC_EACCES */
136 		-EFAULT,     /* I40E_AQ_RC_EFAULT */
137 		-EBUSY,      /* I40E_AQ_RC_EBUSY */
138 		-EEXIST,     /* I40E_AQ_RC_EEXIST */
139 		-EINVAL,     /* I40E_AQ_RC_EINVAL */
140 		-ENOTTY,     /* I40E_AQ_RC_ENOTTY */
141 		-ENOSPC,     /* I40E_AQ_RC_ENOSPC */
142 		-ENOSYS,     /* I40E_AQ_RC_ENOSYS */
143 		-ERANGE,     /* I40E_AQ_RC_ERANGE */
144 		-EPIPE,      /* I40E_AQ_RC_EFLUSHED */
145 		-ESPIPE,     /* I40E_AQ_RC_BAD_ADDR */
146 		-EROFS,      /* I40E_AQ_RC_EMODE */
147 		-EFBIG,      /* I40E_AQ_RC_EFBIG */
148 	};
149 
150 	/* aq_rc is invalid if AQ timed out */
151 	if (aq_ret == I40E_ERR_ADMIN_QUEUE_TIMEOUT)
152 		return -EAGAIN;
153 
154 	if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0]))))
155 		return -ERANGE;
156 
157 	return aq_to_posix[aq_rc];
158 }
159 
160 /* general information */
161 #define I40E_AQ_LARGE_BUF	512
162 #define I40E_ASQ_CMD_TIMEOUT	250  /* msecs */
163 
164 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
165 				       u16 opcode);
166 
167 #endif /* _I40E_ADMINQ_H_ */
168