xref: /linux/drivers/net/ethernet/freescale/enetc/enetc.h (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
3 
4 #include <linux/timer.h>
5 #include <linux/pci.h>
6 #include <linux/netdevice.h>
7 #include <linux/etherdevice.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/skbuff.h>
10 #include <linux/ethtool.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <linux/dim.h>
14 #include <net/xdp.h>
15 
16 #include "enetc_hw.h"
17 #include "enetc4_hw.h"
18 
19 #define ENETC_MAC_MAXFRM_SIZE	9600
20 #define ENETC_MAX_MTU		(ENETC_MAC_MAXFRM_SIZE - \
21 				(ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN))
22 
23 #define ENETC_CBD_DATA_MEM_ALIGN 64
24 
25 struct enetc_tx_swbd {
26 	union {
27 		struct sk_buff *skb;
28 		struct xdp_frame *xdp_frame;
29 	};
30 	dma_addr_t dma;
31 	struct page *page;	/* valid only if is_xdp_tx */
32 	u16 page_offset;	/* valid only if is_xdp_tx */
33 	u16 len;
34 	enum dma_data_direction dir;
35 	u8 is_dma_page:1;
36 	u8 check_wb:1;
37 	u8 do_twostep_tstamp:1;
38 	u8 is_eof:1;
39 	u8 is_xdp_tx:1;
40 	u8 is_xdp_redirect:1;
41 	u8 qbv_en:1;
42 };
43 
44 #define ENETC_RX_MAXFRM_SIZE	ENETC_MAC_MAXFRM_SIZE
45 #define ENETC_RXB_TRUESIZE	2048 /* PAGE_SIZE >> 1 */
46 #define ENETC_RXB_PAD		NET_SKB_PAD /* add extra space if needed */
47 #define ENETC_RXB_DMA_SIZE	\
48 	(SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD)
49 #define ENETC_RXB_DMA_SIZE_XDP	\
50 	(SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - XDP_PACKET_HEADROOM)
51 
52 struct enetc_rx_swbd {
53 	dma_addr_t dma;
54 	struct page *page;
55 	u16 page_offset;
56 	enum dma_data_direction dir;
57 	u16 len;
58 };
59 
60 /* ENETC overhead: optional extension BD + 1 BD gap */
61 #define ENETC_TXBDS_NEEDED(val)	((val) + 2)
62 /* max # of chained Tx BDs is 15, including head and extension BD */
63 #define ENETC_MAX_SKB_FRAGS	13
64 #define ENETC_TXBDS_MAX_NEEDED	ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1)
65 
66 struct enetc_ring_stats {
67 	unsigned int packets;
68 	unsigned int bytes;
69 	unsigned int rx_alloc_errs;
70 	unsigned int xdp_drops;
71 	unsigned int xdp_tx;
72 	unsigned int xdp_tx_drops;
73 	unsigned int xdp_redirect;
74 	unsigned int xdp_redirect_failures;
75 	unsigned int recycles;
76 	unsigned int recycle_failures;
77 	unsigned int win_drop;
78 };
79 
80 struct enetc_xdp_data {
81 	struct xdp_rxq_info rxq;
82 	struct bpf_prog *prog;
83 	int xdp_tx_in_flight;
84 };
85 
86 #define ENETC_RX_RING_DEFAULT_SIZE	2048
87 #define ENETC_TX_RING_DEFAULT_SIZE	2048
88 #define ENETC_DEFAULT_TX_WORK		(ENETC_TX_RING_DEFAULT_SIZE / 2)
89 
90 struct enetc_bdr_resource {
91 	/* Input arguments saved for teardown */
92 	struct device *dev; /* for DMA mapping */
93 	size_t bd_count;
94 	size_t bd_size;
95 
96 	/* Resource proper */
97 	void *bd_base; /* points to Rx or Tx BD ring */
98 	dma_addr_t bd_dma_base;
99 	union {
100 		struct enetc_tx_swbd *tx_swbd;
101 		struct enetc_rx_swbd *rx_swbd;
102 	};
103 	char *tso_headers;
104 	dma_addr_t tso_headers_dma;
105 };
106 
107 struct enetc_bdr {
108 	struct device *dev; /* for DMA mapping */
109 	struct net_device *ndev;
110 	void *bd_base; /* points to Rx or Tx BD ring */
111 	union {
112 		void __iomem *tpir;
113 		void __iomem *rcir;
114 	};
115 	u16 index;
116 	u16 prio;
117 	int bd_count; /* # of BDs */
118 	int next_to_use;
119 	int next_to_clean;
120 	union {
121 		struct enetc_tx_swbd *tx_swbd;
122 		struct enetc_rx_swbd *rx_swbd;
123 	};
124 	union {
125 		void __iomem *tcir; /* Tx */
126 		int next_to_alloc; /* Rx */
127 	};
128 	void __iomem *idr; /* Interrupt Detect Register pointer */
129 
130 	int buffer_offset;
131 	struct enetc_xdp_data xdp;
132 
133 	struct enetc_ring_stats stats;
134 
135 	dma_addr_t bd_dma_base;
136 	u8 tsd_enable; /* Time specific departure */
137 	bool ext_en; /* enable h/w descriptor extensions */
138 
139 	/* DMA buffer for TSO headers */
140 	char *tso_headers;
141 	dma_addr_t tso_headers_dma;
142 } ____cacheline_aligned_in_smp;
143 
enetc_bdr_idx_inc(struct enetc_bdr * bdr,int * i)144 static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i)
145 {
146 	if (unlikely(++*i == bdr->bd_count))
147 		*i = 0;
148 }
149 
enetc_bd_unused(struct enetc_bdr * bdr)150 static inline int enetc_bd_unused(struct enetc_bdr *bdr)
151 {
152 	if (bdr->next_to_clean > bdr->next_to_use)
153 		return bdr->next_to_clean - bdr->next_to_use - 1;
154 
155 	return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;
156 }
157 
enetc_swbd_unused(struct enetc_bdr * bdr)158 static inline int enetc_swbd_unused(struct enetc_bdr *bdr)
159 {
160 	if (bdr->next_to_clean > bdr->next_to_alloc)
161 		return bdr->next_to_clean - bdr->next_to_alloc - 1;
162 
163 	return bdr->bd_count + bdr->next_to_clean - bdr->next_to_alloc - 1;
164 }
165 
166 /* Control BD ring */
167 #define ENETC_CBDR_DEFAULT_SIZE	64
168 struct enetc_cbdr {
169 	void *bd_base; /* points to Rx or Tx BD ring */
170 	void __iomem *pir;
171 	void __iomem *cir;
172 	void __iomem *mr; /* mode register */
173 
174 	int bd_count; /* # of BDs */
175 	int next_to_use;
176 	int next_to_clean;
177 
178 	dma_addr_t bd_dma_base;
179 	struct device *dma_dev;
180 };
181 
182 #define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i]))
183 
enetc_rxbd(struct enetc_bdr * rx_ring,int i)184 static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i)
185 {
186 	int hw_idx = i;
187 
188 	if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) && rx_ring->ext_en)
189 		hw_idx = 2 * i;
190 
191 	return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]);
192 }
193 
enetc_rxbd_next(struct enetc_bdr * rx_ring,union enetc_rx_bd ** old_rxbd,int * old_index)194 static inline void enetc_rxbd_next(struct enetc_bdr *rx_ring,
195 				   union enetc_rx_bd **old_rxbd, int *old_index)
196 {
197 	union enetc_rx_bd *new_rxbd = *old_rxbd;
198 	int new_index = *old_index;
199 
200 	new_rxbd++;
201 
202 	if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) && rx_ring->ext_en)
203 		new_rxbd++;
204 
205 	if (unlikely(++new_index == rx_ring->bd_count)) {
206 		new_rxbd = rx_ring->bd_base;
207 		new_index = 0;
208 	}
209 
210 	*old_rxbd = new_rxbd;
211 	*old_index = new_index;
212 }
213 
enetc_rxbd_ext(union enetc_rx_bd * rxbd)214 static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd)
215 {
216 	return ++rxbd;
217 }
218 
219 struct enetc_msg_swbd {
220 	void *vaddr;
221 	dma_addr_t dma;
222 	int size;
223 };
224 
225 #define ENETC_REV1	0x1
226 enum enetc_errata {
227 	ENETC_ERR_VLAN_ISOL	= BIT(0),
228 	ENETC_ERR_UCMCSWP	= BIT(1),
229 };
230 
231 #define ENETC_SI_F_PSFP BIT(0)
232 #define ENETC_SI_F_QBV  BIT(1)
233 #define ENETC_SI_F_QBU  BIT(2)
234 
235 struct enetc_drvdata {
236 	u32 pmac_offset; /* Only valid for PSI which supports 802.1Qbu */
237 	u64 sysclk_freq;
238 	const struct ethtool_ops *eth_ops;
239 };
240 
241 struct enetc_platform_info {
242 	u16 revision;
243 	u16 dev_id;
244 	const struct enetc_drvdata *data;
245 };
246 
247 /* PCI IEP device data */
248 struct enetc_si {
249 	struct pci_dev *pdev;
250 	struct enetc_hw hw;
251 	enum enetc_errata errata;
252 
253 	struct net_device *ndev; /* back ref. */
254 
255 	struct enetc_cbdr cbd_ring;
256 
257 	int num_rx_rings; /* how many rings are available in the SI */
258 	int num_tx_rings;
259 	int num_fs_entries;
260 	int num_rss; /* number of RSS buckets */
261 	unsigned short pad;
262 	u16 revision;
263 	int hw_features;
264 	const struct enetc_drvdata *drvdata;
265 };
266 
267 #define ENETC_SI_ALIGN	32
268 
is_enetc_rev1(struct enetc_si * si)269 static inline bool is_enetc_rev1(struct enetc_si *si)
270 {
271 	return si->pdev->revision == ENETC_REV1;
272 }
273 
enetc_si_priv(const struct enetc_si * si)274 static inline void *enetc_si_priv(const struct enetc_si *si)
275 {
276 	return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN);
277 }
278 
enetc_si_is_pf(struct enetc_si * si)279 static inline bool enetc_si_is_pf(struct enetc_si *si)
280 {
281 	return !!(si->hw.port);
282 }
283 
enetc_pf_to_port(struct pci_dev * pf_pdev)284 static inline int enetc_pf_to_port(struct pci_dev *pf_pdev)
285 {
286 	switch (pf_pdev->devfn) {
287 	case 0:
288 		return 0;
289 	case 1:
290 		return 1;
291 	case 2:
292 		return 2;
293 	case 6:
294 		return 3;
295 	default:
296 		return -1;
297 	}
298 }
299 
300 #define ENETC_MAX_NUM_TXQS	8
301 #define ENETC_INT_NAME_MAX	(IFNAMSIZ + 8)
302 
303 struct enetc_int_vector {
304 	void __iomem *rbier;
305 	void __iomem *tbier_base;
306 	void __iomem *ricr1;
307 	unsigned long tx_rings_map;
308 	int count_tx_rings;
309 	u32 rx_ictt;
310 	u16 comp_cnt;
311 	bool rx_dim_en, rx_napi_work;
312 	struct napi_struct napi ____cacheline_aligned_in_smp;
313 	struct dim rx_dim ____cacheline_aligned_in_smp;
314 	char name[ENETC_INT_NAME_MAX];
315 
316 	struct enetc_bdr rx_ring;
317 	struct enetc_bdr tx_ring[] __counted_by(count_tx_rings);
318 } ____cacheline_aligned_in_smp;
319 
320 struct enetc_cls_rule {
321 	struct ethtool_rx_flow_spec fs;
322 	int used;
323 };
324 
325 #define ENETC_MAX_BDR_INT	6 /* fixed to max # of available cpus */
326 struct psfp_cap {
327 	u32 max_streamid;
328 	u32 max_psfp_filter;
329 	u32 max_psfp_gate;
330 	u32 max_psfp_gatelist;
331 	u32 max_psfp_meter;
332 };
333 
334 #define ENETC_F_TX_TSTAMP_MASK	0xff
335 enum enetc_active_offloads {
336 	/* 8 bits reserved for TX timestamp types (hwtstamp_tx_types) */
337 	ENETC_F_TX_TSTAMP		= BIT(0),
338 	ENETC_F_TX_ONESTEP_SYNC_TSTAMP	= BIT(1),
339 
340 	ENETC_F_RX_TSTAMP		= BIT(8),
341 	ENETC_F_QBV			= BIT(9),
342 	ENETC_F_QCI			= BIT(10),
343 	ENETC_F_QBU			= BIT(11),
344 };
345 
346 enum enetc_flags_bit {
347 	ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS = 0,
348 	ENETC_TX_DOWN,
349 };
350 
351 /* interrupt coalescing modes */
352 enum enetc_ic_mode {
353 	/* one interrupt per frame */
354 	ENETC_IC_NONE = 0,
355 	/* activated when int coalescing time is set to a non-0 value */
356 	ENETC_IC_RX_MANUAL = BIT(0),
357 	ENETC_IC_TX_MANUAL = BIT(1),
358 	/* use dynamic interrupt moderation */
359 	ENETC_IC_RX_ADAPTIVE = BIT(2),
360 };
361 
362 #define ENETC_RXIC_PKTTHR	min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2)
363 #define ENETC_TXIC_PKTTHR	min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2)
364 
365 struct enetc_ndev_priv {
366 	struct net_device *ndev;
367 	struct device *dev; /* dma-mapping device */
368 	struct enetc_si *si;
369 
370 	int bdr_int_num; /* number of Rx/Tx ring interrupts */
371 	struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT];
372 	u16 num_rx_rings, num_tx_rings;
373 	u16 rx_bd_count, tx_bd_count;
374 
375 	u16 msg_enable;
376 
377 	u8 preemptible_tcs;
378 
379 	enum enetc_active_offloads active_offloads;
380 
381 	u32 speed; /* store speed for compare update pspeed */
382 
383 	struct enetc_bdr **xdp_tx_ring;
384 	struct enetc_bdr *tx_ring[16];
385 	struct enetc_bdr *rx_ring[16];
386 	const struct enetc_bdr_resource *tx_res;
387 	const struct enetc_bdr_resource *rx_res;
388 
389 	struct enetc_cls_rule *cls_rules;
390 
391 	struct psfp_cap psfp_cap;
392 
393 	/* Minimum number of TX queues required by the network stack */
394 	unsigned int min_num_stack_tx_queues;
395 
396 	struct phylink *phylink;
397 	int ic_mode;
398 	u32 tx_ictt;
399 
400 	struct bpf_prog *xdp_prog;
401 
402 	unsigned long flags;
403 
404 	struct work_struct	tx_onestep_tstamp;
405 	struct sk_buff_head	tx_skbs;
406 
407 	/* Serialize access to MAC Merge state between ethtool requests
408 	 * and link state updates
409 	 */
410 	struct mutex		mm_lock;
411 
412 	struct clk *ref_clk; /* RGMII/RMII reference clock */
413 	u64 sysclk_freq; /* NETC system clock frequency */
414 };
415 
416 /* Messaging */
417 
418 /* VF-PF set primary MAC address message format */
419 struct enetc_msg_cmd_set_primary_mac {
420 	struct enetc_msg_cmd_header header;
421 	struct sockaddr mac;
422 };
423 
424 #define ENETC_CBD(R, i)	(&(((struct enetc_cbd *)((R).bd_base))[i]))
425 
426 #define ENETC_CBDR_TIMEOUT	1000 /* usecs */
427 
428 /* PTP driver exports */
429 extern int enetc_phc_index;
430 
431 /* SI common */
432 u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg);
433 void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val);
434 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
435 void enetc_pci_remove(struct pci_dev *pdev);
436 int enetc_alloc_msix(struct enetc_ndev_priv *priv);
437 void enetc_free_msix(struct enetc_ndev_priv *priv);
438 void enetc_get_si_caps(struct enetc_si *si);
439 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv);
440 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv);
441 void enetc_free_si_resources(struct enetc_ndev_priv *priv);
442 int enetc_configure_si(struct enetc_ndev_priv *priv);
443 int enetc_get_driver_data(struct enetc_si *si);
444 
445 int enetc_open(struct net_device *ndev);
446 int enetc_close(struct net_device *ndev);
447 void enetc_start(struct net_device *ndev);
448 void enetc_stop(struct net_device *ndev);
449 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev);
450 struct net_device_stats *enetc_get_stats(struct net_device *ndev);
451 void enetc_set_features(struct net_device *ndev, netdev_features_t features);
452 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd);
453 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data);
454 void enetc_reset_tc_mqprio(struct net_device *ndev);
455 int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
456 int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
457 		   struct xdp_frame **frames, u32 flags);
458 
459 /* ethtool */
460 extern const struct ethtool_ops enetc_pf_ethtool_ops;
461 extern const struct ethtool_ops enetc4_pf_ethtool_ops;
462 extern const struct ethtool_ops enetc_vf_ethtool_ops;
463 void enetc_set_ethtool_ops(struct net_device *ndev);
464 void enetc_mm_link_state_update(struct enetc_ndev_priv *priv, bool link);
465 void enetc_mm_commit_preemptible_tcs(struct enetc_ndev_priv *priv);
466 
467 /* control buffer descriptor ring (CBDR) */
468 int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count,
469 		     struct enetc_cbdr *cbdr);
470 void enetc_teardown_cbdr(struct enetc_cbdr *cbdr);
471 int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
472 			    char *mac_addr, int si_map);
473 int enetc_clear_mac_flt_entry(struct enetc_si *si, int index);
474 int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
475 		       int index);
476 void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes);
477 int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count);
478 int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count);
479 int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd);
480 
enetc_cbd_alloc_data_mem(struct enetc_si * si,struct enetc_cbd * cbd,int size,dma_addr_t * dma,void ** data_align)481 static inline void *enetc_cbd_alloc_data_mem(struct enetc_si *si,
482 					     struct enetc_cbd *cbd,
483 					     int size, dma_addr_t *dma,
484 					     void **data_align)
485 {
486 	struct enetc_cbdr *ring = &si->cbd_ring;
487 	dma_addr_t dma_align;
488 	void *data;
489 
490 	data = dma_alloc_coherent(ring->dma_dev,
491 				  size + ENETC_CBD_DATA_MEM_ALIGN,
492 				  dma, GFP_KERNEL);
493 	if (!data) {
494 		dev_err(ring->dma_dev, "CBD alloc data memory failed!\n");
495 		return NULL;
496 	}
497 
498 	dma_align = ALIGN(*dma, ENETC_CBD_DATA_MEM_ALIGN);
499 	*data_align = PTR_ALIGN(data, ENETC_CBD_DATA_MEM_ALIGN);
500 
501 	cbd->addr[0] = cpu_to_le32(lower_32_bits(dma_align));
502 	cbd->addr[1] = cpu_to_le32(upper_32_bits(dma_align));
503 	cbd->length = cpu_to_le16(size);
504 
505 	return data;
506 }
507 
enetc_cbd_free_data_mem(struct enetc_si * si,int size,void * data,dma_addr_t * dma)508 static inline void enetc_cbd_free_data_mem(struct enetc_si *si, int size,
509 					   void *data, dma_addr_t *dma)
510 {
511 	struct enetc_cbdr *ring = &si->cbd_ring;
512 
513 	dma_free_coherent(ring->dma_dev, size + ENETC_CBD_DATA_MEM_ALIGN,
514 			  data, *dma);
515 }
516 
517 void enetc_reset_ptcmsdur(struct enetc_hw *hw);
518 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *queue_max_sdu);
519 
520 #ifdef CONFIG_FSL_ENETC_QOS
521 int enetc_qos_query_caps(struct net_device *ndev, void *type_data);
522 int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data);
523 void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed);
524 int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data);
525 int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data);
526 int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
527 			    void *cb_priv);
528 int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data);
529 int enetc_psfp_init(struct enetc_ndev_priv *priv);
530 int enetc_psfp_clean(struct enetc_ndev_priv *priv);
531 int enetc_set_psfp(struct net_device *ndev, bool en);
532 
enetc_get_max_cap(struct enetc_ndev_priv * priv)533 static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv)
534 {
535 	struct enetc_hw *hw = &priv->si->hw;
536 	u32 reg;
537 
538 	reg = enetc_port_rd(hw, ENETC_PSIDCAPR);
539 	priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK;
540 	/* Port stream filter capability */
541 	reg = enetc_port_rd(hw, ENETC_PSFCAPR);
542 	priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK;
543 	/* Port stream gate capability */
544 	reg = enetc_port_rd(hw, ENETC_PSGCAPR);
545 	priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK);
546 	priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16;
547 	/* Port flow meter capability */
548 	reg = enetc_port_rd(hw, ENETC_PFMCAPR);
549 	priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK;
550 }
551 
enetc_psfp_enable(struct enetc_ndev_priv * priv)552 static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
553 {
554 	struct enetc_hw *hw = &priv->si->hw;
555 	int err;
556 
557 	enetc_get_max_cap(priv);
558 
559 	err = enetc_psfp_init(priv);
560 	if (err)
561 		return err;
562 
563 	enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) |
564 		 ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS |
565 		 ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC);
566 
567 	return 0;
568 }
569 
enetc_psfp_disable(struct enetc_ndev_priv * priv)570 static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
571 {
572 	struct enetc_hw *hw = &priv->si->hw;
573 	int err;
574 
575 	err = enetc_psfp_clean(priv);
576 	if (err)
577 		return err;
578 
579 	enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) &
580 		 ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS &
581 		 ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC);
582 
583 	memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap));
584 
585 	return 0;
586 }
587 
588 #else
589 #define enetc_qos_query_caps(ndev, type_data) -EOPNOTSUPP
590 #define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP
591 #define enetc_sched_speed_set(priv, speed) (void)0
592 #define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP
593 #define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP
594 #define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP
595 #define enetc_setup_tc_block_cb NULL
596 
597 #define enetc_get_max_cap(p)		\
598 	memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap))
599 
enetc_psfp_enable(struct enetc_ndev_priv * priv)600 static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
601 {
602 	return 0;
603 }
604 
enetc_psfp_disable(struct enetc_ndev_priv * priv)605 static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
606 {
607 	return 0;
608 }
609 
enetc_set_psfp(struct net_device * ndev,bool en)610 static inline int enetc_set_psfp(struct net_device *ndev, bool en)
611 {
612 	return 0;
613 }
614 #endif
615