1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_tunnel.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_damage_helper.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_fourcc.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_rect.h> 45 46 #include "gem/i915_gem_lmem.h" 47 #include "gem/i915_gem_object.h" 48 49 #include "g4x_dp.h" 50 #include "g4x_hdmi.h" 51 #include "hsw_ips.h" 52 #include "i915_config.h" 53 #include "i915_drv.h" 54 #include "i915_reg.h" 55 #include "i915_utils.h" 56 #include "i9xx_plane.h" 57 #include "i9xx_plane_regs.h" 58 #include "i9xx_wm.h" 59 #include "intel_atomic.h" 60 #include "intel_atomic_plane.h" 61 #include "intel_audio.h" 62 #include "intel_bw.h" 63 #include "intel_cdclk.h" 64 #include "intel_clock_gating.h" 65 #include "intel_color.h" 66 #include "intel_crt.h" 67 #include "intel_crtc.h" 68 #include "intel_crtc_state_dump.h" 69 #include "intel_cursor_regs.h" 70 #include "intel_cx0_phy.h" 71 #include "intel_cursor.h" 72 #include "intel_ddi.h" 73 #include "intel_de.h" 74 #include "intel_display_driver.h" 75 #include "intel_display_power.h" 76 #include "intel_display_types.h" 77 #include "intel_dmc.h" 78 #include "intel_dp.h" 79 #include "intel_dp_link_training.h" 80 #include "intel_dp_mst.h" 81 #include "intel_dp_tunnel.h" 82 #include "intel_dpll.h" 83 #include "intel_dpll_mgr.h" 84 #include "intel_dpt.h" 85 #include "intel_dpt_common.h" 86 #include "intel_drrs.h" 87 #include "intel_dsb.h" 88 #include "intel_dsi.h" 89 #include "intel_dvo.h" 90 #include "intel_fb.h" 91 #include "intel_fbc.h" 92 #include "intel_fdi.h" 93 #include "intel_fifo_underrun.h" 94 #include "intel_frontbuffer.h" 95 #include "intel_hdmi.h" 96 #include "intel_hotplug.h" 97 #include "intel_link_bw.h" 98 #include "intel_lvds.h" 99 #include "intel_lvds_regs.h" 100 #include "intel_modeset_setup.h" 101 #include "intel_modeset_verify.h" 102 #include "intel_overlay.h" 103 #include "intel_panel.h" 104 #include "intel_pch_display.h" 105 #include "intel_pch_refclk.h" 106 #include "intel_pcode.h" 107 #include "intel_pipe_crc.h" 108 #include "intel_plane_initial.h" 109 #include "intel_pmdemand.h" 110 #include "intel_pps.h" 111 #include "intel_psr.h" 112 #include "intel_psr_regs.h" 113 #include "intel_sdvo.h" 114 #include "intel_snps_phy.h" 115 #include "intel_tc.h" 116 #include "intel_tdf.h" 117 #include "intel_tv.h" 118 #include "intel_vblank.h" 119 #include "intel_vdsc.h" 120 #include "intel_vdsc_regs.h" 121 #include "intel_vga.h" 122 #include "intel_vrr.h" 123 #include "intel_wm.h" 124 #include "skl_scaler.h" 125 #include "skl_universal_plane.h" 126 #include "skl_universal_plane_regs.h" 127 #include "skl_watermark.h" 128 #include "vlv_dpio_phy_regs.h" 129 #include "vlv_dsi.h" 130 #include "vlv_dsi_pll.h" 131 #include "vlv_dsi_regs.h" 132 #include "vlv_sideband.h" 133 134 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 135 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 136 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 137 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 138 139 /* returns HPLL frequency in kHz */ 140 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 141 { 142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 143 144 /* Obtain SKU information */ 145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 146 CCK_FUSE_HPLL_FREQ_MASK; 147 148 return vco_freq[hpll_freq] * 1000; 149 } 150 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 152 const char *name, u32 reg, int ref_freq) 153 { 154 u32 val; 155 int divider; 156 157 val = vlv_cck_read(dev_priv, reg); 158 divider = val & CCK_FREQUENCY_VALUES; 159 160 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 161 (divider << CCK_FREQUENCY_STATUS_SHIFT), 162 "%s change in progress\n", name); 163 164 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 165 } 166 167 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 168 const char *name, u32 reg) 169 { 170 int hpll; 171 172 vlv_cck_get(dev_priv); 173 174 if (dev_priv->hpll_freq == 0) 175 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 176 177 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 178 179 vlv_cck_put(dev_priv); 180 181 return hpll; 182 } 183 184 void intel_update_czclk(struct drm_i915_private *dev_priv) 185 { 186 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 187 return; 188 189 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 190 CCK_CZ_CLOCK_CONTROL); 191 192 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 193 dev_priv->czclk_freq); 194 } 195 196 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 197 { 198 return (crtc_state->active_planes & 199 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 200 } 201 202 /* WA Display #0827: Gen9:all */ 203 static void 204 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 205 { 206 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 207 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 208 enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0); 209 } 210 211 /* Wa_2006604312:icl,ehl */ 212 static void 213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 214 bool enable) 215 { 216 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 217 DPFR_GATING_DIS, 218 enable ? DPFR_GATING_DIS : 0); 219 } 220 221 /* Wa_1604331009:icl,jsl,ehl */ 222 static void 223 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 224 bool enable) 225 { 226 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 227 CURSOR_GATING_DIS, 228 enable ? CURSOR_GATING_DIS : 0); 229 } 230 231 static bool 232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 233 { 234 return crtc_state->master_transcoder != INVALID_TRANSCODER; 235 } 236 237 bool 238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 239 { 240 return crtc_state->sync_mode_slaves_mask != 0; 241 } 242 243 bool 244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 245 { 246 return is_trans_port_sync_master(crtc_state) || 247 is_trans_port_sync_slave(crtc_state); 248 } 249 250 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) 251 { 252 return ffs(crtc_state->joiner_pipes) - 1; 253 } 254 255 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 256 { 257 if (crtc_state->joiner_pipes) 258 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); 259 else 260 return 0; 261 } 262 263 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) 264 { 265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 266 267 return crtc_state->joiner_pipes && 268 crtc->pipe != joiner_primary_pipe(crtc_state); 269 } 270 271 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) 272 { 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 275 return crtc_state->joiner_pipes && 276 crtc->pipe == joiner_primary_pipe(crtc_state); 277 } 278 279 static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) 280 { 281 return hweight8(crtc_state->joiner_pipes); 282 } 283 284 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) 285 { 286 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 287 288 return BIT(crtc->pipe) | crtc_state->joiner_pipes; 289 } 290 291 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) 292 { 293 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 294 295 if (intel_crtc_is_joiner_secondary(crtc_state)) 296 return intel_crtc_for_pipe(i915, joiner_primary_pipe(crtc_state)); 297 else 298 return to_intel_crtc(crtc_state->uapi.crtc); 299 } 300 301 static void 302 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 303 { 304 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 305 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 306 307 if (DISPLAY_VER(dev_priv) >= 4) { 308 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 309 310 /* Wait for the Pipe State to go off */ 311 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), 312 TRANSCONF_STATE_ENABLE, 100)) 313 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 314 } else { 315 intel_wait_for_pipe_scanline_stopped(crtc); 316 } 317 } 318 319 void assert_transcoder(struct drm_i915_private *dev_priv, 320 enum transcoder cpu_transcoder, bool state) 321 { 322 bool cur_state; 323 enum intel_display_power_domain power_domain; 324 intel_wakeref_t wakeref; 325 326 /* we keep both pipes enabled on 830 */ 327 if (IS_I830(dev_priv)) 328 state = true; 329 330 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 331 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 332 if (wakeref) { 333 u32 val = intel_de_read(dev_priv, 334 TRANSCONF(dev_priv, cpu_transcoder)); 335 cur_state = !!(val & TRANSCONF_ENABLE); 336 337 intel_display_power_put(dev_priv, power_domain, wakeref); 338 } else { 339 cur_state = false; 340 } 341 342 I915_STATE_WARN(dev_priv, cur_state != state, 343 "transcoder %s assertion failure (expected %s, current %s)\n", 344 transcoder_name(cpu_transcoder), str_on_off(state), 345 str_on_off(cur_state)); 346 } 347 348 static void assert_plane(struct intel_plane *plane, bool state) 349 { 350 struct drm_i915_private *i915 = to_i915(plane->base.dev); 351 enum pipe pipe; 352 bool cur_state; 353 354 cur_state = plane->get_hw_state(plane, &pipe); 355 356 I915_STATE_WARN(i915, cur_state != state, 357 "%s assertion failure (expected %s, current %s)\n", 358 plane->base.name, str_on_off(state), 359 str_on_off(cur_state)); 360 } 361 362 #define assert_plane_enabled(p) assert_plane(p, true) 363 #define assert_plane_disabled(p) assert_plane(p, false) 364 365 static void assert_planes_disabled(struct intel_crtc *crtc) 366 { 367 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 368 struct intel_plane *plane; 369 370 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 371 assert_plane_disabled(plane); 372 } 373 374 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 375 struct intel_digital_port *dig_port, 376 unsigned int expected_mask) 377 { 378 u32 port_mask; 379 i915_reg_t dpll_reg; 380 381 switch (dig_port->base.port) { 382 default: 383 MISSING_CASE(dig_port->base.port); 384 fallthrough; 385 case PORT_B: 386 port_mask = DPLL_PORTB_READY_MASK; 387 dpll_reg = DPLL(dev_priv, 0); 388 break; 389 case PORT_C: 390 port_mask = DPLL_PORTC_READY_MASK; 391 dpll_reg = DPLL(dev_priv, 0); 392 expected_mask <<= 4; 393 break; 394 case PORT_D: 395 port_mask = DPLL_PORTD_READY_MASK; 396 dpll_reg = DPIO_PHY_STATUS; 397 break; 398 } 399 400 if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000)) 401 drm_WARN(&dev_priv->drm, 1, 402 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 403 dig_port->base.base.base.id, dig_port->base.base.name, 404 intel_de_read(dev_priv, dpll_reg) & port_mask, 405 expected_mask); 406 } 407 408 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 409 { 410 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 412 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 413 enum pipe pipe = crtc->pipe; 414 u32 val; 415 416 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 417 418 assert_planes_disabled(crtc); 419 420 /* 421 * A pipe without a PLL won't actually be able to drive bits from 422 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 423 * need the check. 424 */ 425 if (HAS_GMCH(dev_priv)) { 426 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 427 assert_dsi_pll_enabled(dev_priv); 428 else 429 assert_pll_enabled(dev_priv, pipe); 430 } else { 431 if (new_crtc_state->has_pch_encoder) { 432 /* if driving the PCH, we need FDI enabled */ 433 assert_fdi_rx_pll_enabled(dev_priv, 434 intel_crtc_pch_transcoder(crtc)); 435 assert_fdi_tx_pll_enabled(dev_priv, 436 (enum pipe) cpu_transcoder); 437 } 438 /* FIXME: assert CPU port conditions for SNB+ */ 439 } 440 441 /* Wa_22012358565:adl-p */ 442 if (DISPLAY_VER(dev_priv) == 13) 443 intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe), 444 0, PIPE_ARB_USE_PROG_SLOTS); 445 446 if (DISPLAY_VER(dev_priv) >= 14) { 447 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; 448 u32 set = 0; 449 450 if (DISPLAY_VER(dev_priv) == 14) 451 set |= DP_FEC_BS_JITTER_WA; 452 453 intel_de_rmw(dev_priv, 454 hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 455 clear, set); 456 } 457 458 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); 459 if (val & TRANSCONF_ENABLE) { 460 /* we keep both pipes enabled on 830 */ 461 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 462 return; 463 } 464 465 /* Wa_1409098942:adlp+ */ 466 if (DISPLAY_VER(dev_priv) >= 13 && 467 new_crtc_state->dsc.compression_enable) { 468 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 469 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, 470 TRANSCONF_PIXEL_COUNT_SCALING_X4); 471 } 472 473 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), 474 val | TRANSCONF_ENABLE); 475 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); 476 477 /* 478 * Until the pipe starts PIPEDSL reads will return a stale value, 479 * which causes an apparent vblank timestamp jump when PIPEDSL 480 * resets to its proper value. That also messes up the frame count 481 * when it's derived from the timestamps. So let's wait for the 482 * pipe to start properly before we call drm_crtc_vblank_on() 483 */ 484 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 485 intel_wait_for_pipe_scanline_moving(crtc); 486 } 487 488 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 489 { 490 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 492 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 493 enum pipe pipe = crtc->pipe; 494 u32 val; 495 496 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 497 498 /* 499 * Make sure planes won't keep trying to pump pixels to us, 500 * or we might hang the display. 501 */ 502 assert_planes_disabled(crtc); 503 504 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); 505 if ((val & TRANSCONF_ENABLE) == 0) 506 return; 507 508 /* 509 * Double wide has implications for planes 510 * so best keep it disabled when not needed. 511 */ 512 if (old_crtc_state->double_wide) 513 val &= ~TRANSCONF_DOUBLE_WIDE; 514 515 /* Don't disable pipe or pipe PLLs if needed */ 516 if (!IS_I830(dev_priv)) 517 val &= ~TRANSCONF_ENABLE; 518 519 /* Wa_1409098942:adlp+ */ 520 if (DISPLAY_VER(dev_priv) >= 13 && 521 old_crtc_state->dsc.compression_enable) 522 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 523 524 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); 525 526 if (DISPLAY_VER(dev_priv) >= 12) 527 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 528 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 529 530 if ((val & TRANSCONF_ENABLE) == 0) 531 intel_wait_for_pipe_off(old_crtc_state); 532 } 533 534 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 535 { 536 unsigned int size = 0; 537 int i; 538 539 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 540 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 541 542 return size; 543 } 544 545 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 546 { 547 unsigned int size = 0; 548 int i; 549 550 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 551 unsigned int plane_size; 552 553 if (rem_info->plane[i].linear) 554 plane_size = rem_info->plane[i].size; 555 else 556 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 557 558 if (plane_size == 0) 559 continue; 560 561 if (rem_info->plane_alignment) 562 size = ALIGN(size, rem_info->plane_alignment); 563 564 size += plane_size; 565 } 566 567 return size; 568 } 569 570 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 571 { 572 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 573 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 574 575 return DISPLAY_VER(dev_priv) < 4 || 576 (plane->fbc && !plane_state->no_fbc_reason && 577 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 578 } 579 580 /* 581 * Convert the x/y offsets into a linear offset. 582 * Only valid with 0/180 degree rotation, which is fine since linear 583 * offset is only used with linear buffers on pre-hsw and tiled buffers 584 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 585 */ 586 u32 intel_fb_xy_to_linear(int x, int y, 587 const struct intel_plane_state *state, 588 int color_plane) 589 { 590 const struct drm_framebuffer *fb = state->hw.fb; 591 unsigned int cpp = fb->format->cpp[color_plane]; 592 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 593 594 return y * pitch + x * cpp; 595 } 596 597 /* 598 * Add the x/y offsets derived from fb->offsets[] to the user 599 * specified plane src x/y offsets. The resulting x/y offsets 600 * specify the start of scanout from the beginning of the gtt mapping. 601 */ 602 void intel_add_fb_offsets(int *x, int *y, 603 const struct intel_plane_state *state, 604 int color_plane) 605 606 { 607 *x += state->view.color_plane[color_plane].x; 608 *y += state->view.color_plane[color_plane].y; 609 } 610 611 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 612 u32 pixel_format, u64 modifier) 613 { 614 struct intel_crtc *crtc; 615 struct intel_plane *plane; 616 617 if (!HAS_DISPLAY(dev_priv)) 618 return 0; 619 620 /* 621 * We assume the primary plane for pipe A has 622 * the highest stride limits of them all, 623 * if in case pipe A is disabled, use the first pipe from pipe_mask. 624 */ 625 crtc = intel_first_crtc(dev_priv); 626 if (!crtc) 627 return 0; 628 629 plane = to_intel_plane(crtc->base.primary); 630 631 return plane->max_stride(plane, pixel_format, modifier, 632 DRM_MODE_ROTATE_0); 633 } 634 635 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 636 struct intel_plane_state *plane_state, 637 bool visible) 638 { 639 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 640 641 plane_state->uapi.visible = visible; 642 643 if (visible) 644 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 645 else 646 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 647 } 648 649 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 650 { 651 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 652 struct drm_plane *plane; 653 654 /* 655 * Active_planes aliases if multiple "primary" or cursor planes 656 * have been used on the same (or wrong) pipe. plane_mask uses 657 * unique ids, hence we can use that to reconstruct active_planes. 658 */ 659 crtc_state->enabled_planes = 0; 660 crtc_state->active_planes = 0; 661 662 drm_for_each_plane_mask(plane, &dev_priv->drm, 663 crtc_state->uapi.plane_mask) { 664 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 665 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 666 } 667 } 668 669 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 670 struct intel_plane *plane) 671 { 672 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 673 struct intel_crtc_state *crtc_state = 674 to_intel_crtc_state(crtc->base.state); 675 struct intel_plane_state *plane_state = 676 to_intel_plane_state(plane->base.state); 677 678 drm_dbg_kms(&dev_priv->drm, 679 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 680 plane->base.base.id, plane->base.name, 681 crtc->base.base.id, crtc->base.name); 682 683 intel_set_plane_visible(crtc_state, plane_state, false); 684 intel_plane_fixup_bitmasks(crtc_state); 685 crtc_state->data_rate[plane->id] = 0; 686 crtc_state->data_rate_y[plane->id] = 0; 687 crtc_state->rel_data_rate[plane->id] = 0; 688 crtc_state->rel_data_rate_y[plane->id] = 0; 689 crtc_state->min_cdclk[plane->id] = 0; 690 691 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 692 hsw_ips_disable(crtc_state)) { 693 crtc_state->ips_enabled = false; 694 intel_crtc_wait_for_next_vblank(crtc); 695 } 696 697 /* 698 * Vblank time updates from the shadow to live plane control register 699 * are blocked if the memory self-refresh mode is active at that 700 * moment. So to make sure the plane gets truly disabled, disable 701 * first the self-refresh mode. The self-refresh enable bit in turn 702 * will be checked/applied by the HW only at the next frame start 703 * event which is after the vblank start event, so we need to have a 704 * wait-for-vblank between disabling the plane and the pipe. 705 */ 706 if (HAS_GMCH(dev_priv) && 707 intel_set_memory_cxsr(dev_priv, false)) 708 intel_crtc_wait_for_next_vblank(crtc); 709 710 /* 711 * Gen2 reports pipe underruns whenever all planes are disabled. 712 * So disable underrun reporting before all the planes get disabled. 713 */ 714 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 715 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 716 717 intel_plane_disable_arm(plane, crtc_state); 718 intel_crtc_wait_for_next_vblank(crtc); 719 } 720 721 unsigned int 722 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 723 { 724 int x = 0, y = 0; 725 726 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 727 plane_state->view.color_plane[0].offset, 0); 728 729 return y; 730 } 731 732 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 733 { 734 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 735 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 736 enum pipe pipe = crtc->pipe; 737 u32 tmp; 738 739 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 740 741 /* 742 * Display WA #1153: icl 743 * enable hardware to bypass the alpha math 744 * and rounding for per-pixel values 00 and 0xff 745 */ 746 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 747 /* 748 * Display WA # 1605353570: icl 749 * Set the pixel rounding bit to 1 for allowing 750 * passthrough of Frame buffer pixels unmodified 751 * across pipe 752 */ 753 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 754 755 /* 756 * Underrun recovery must always be disabled on display 13+. 757 * DG2 chicken bit meaning is inverted compared to other platforms. 758 */ 759 if (IS_DG2(dev_priv)) 760 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 761 else if (DISPLAY_VER(dev_priv) >= 13) 762 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 763 764 /* Wa_14010547955:dg2 */ 765 if (IS_DG2(dev_priv)) 766 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 767 768 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 769 } 770 771 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 772 { 773 struct drm_crtc *crtc; 774 bool cleanup_done; 775 776 drm_for_each_crtc(crtc, &dev_priv->drm) { 777 struct drm_crtc_commit *commit; 778 spin_lock(&crtc->commit_lock); 779 commit = list_first_entry_or_null(&crtc->commit_list, 780 struct drm_crtc_commit, commit_entry); 781 cleanup_done = commit ? 782 try_wait_for_completion(&commit->cleanup_done) : true; 783 spin_unlock(&crtc->commit_lock); 784 785 if (cleanup_done) 786 continue; 787 788 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 789 790 return true; 791 } 792 793 return false; 794 } 795 796 /* 797 * Finds the encoder associated with the given CRTC. This can only be 798 * used when we know that the CRTC isn't feeding multiple encoders! 799 */ 800 struct intel_encoder * 801 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 802 const struct intel_crtc_state *crtc_state) 803 { 804 const struct drm_connector_state *connector_state; 805 const struct drm_connector *connector; 806 struct intel_encoder *encoder = NULL; 807 struct intel_crtc *primary_crtc; 808 int num_encoders = 0; 809 int i; 810 811 primary_crtc = intel_primary_crtc(crtc_state); 812 813 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 814 if (connector_state->crtc != &primary_crtc->base) 815 continue; 816 817 encoder = to_intel_encoder(connector_state->best_encoder); 818 num_encoders++; 819 } 820 821 drm_WARN(state->base.dev, num_encoders != 1, 822 "%d encoders for pipe %c\n", 823 num_encoders, pipe_name(primary_crtc->pipe)); 824 825 return encoder; 826 } 827 828 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 829 { 830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 832 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 833 enum pipe pipe = crtc->pipe; 834 int width = drm_rect_width(dst); 835 int height = drm_rect_height(dst); 836 int x = dst->x1; 837 int y = dst->y1; 838 839 if (!crtc_state->pch_pfit.enabled) 840 return; 841 842 /* Force use of hard-coded filter coefficients 843 * as some pre-programmed values are broken, 844 * e.g. x201. 845 */ 846 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 847 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 848 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 849 else 850 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 851 PF_FILTER_MED_3x3); 852 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 853 PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); 854 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 855 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); 856 } 857 858 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 859 { 860 if (crtc->overlay) 861 (void) intel_overlay_switch_off(crtc->overlay); 862 863 /* Let userspace switch the overlay on again. In most cases userspace 864 * has to recompute where to put it anyway. 865 */ 866 } 867 868 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 869 { 870 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 871 872 if (!crtc_state->nv12_planes) 873 return false; 874 875 /* WA Display #0827: Gen9:all */ 876 if (DISPLAY_VER(dev_priv) == 9) 877 return true; 878 879 return false; 880 } 881 882 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 883 { 884 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 885 886 /* Wa_2006604312:icl,ehl */ 887 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 888 return true; 889 890 return false; 891 } 892 893 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 894 { 895 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 896 897 /* Wa_1604331009:icl,jsl,ehl */ 898 if (is_hdr_mode(crtc_state) && 899 crtc_state->active_planes & BIT(PLANE_CURSOR) && 900 DISPLAY_VER(dev_priv) == 11) 901 return true; 902 903 return false; 904 } 905 906 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 907 enum pipe pipe, bool enable) 908 { 909 if (DISPLAY_VER(i915) == 9) { 910 /* 911 * "Plane N strech max must be programmed to 11b (x1) 912 * when Async flips are enabled on that plane." 913 */ 914 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 915 SKL_PLANE1_STRETCH_MAX_MASK, 916 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 917 } else { 918 /* Also needed on HSW/BDW albeit undocumented */ 919 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 920 HSW_PRI_STRETCH_MAX_MASK, 921 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 922 } 923 } 924 925 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 926 { 927 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 928 929 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 930 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 931 } 932 933 static void intel_encoders_audio_enable(struct intel_atomic_state *state, 934 struct intel_crtc *crtc) 935 { 936 const struct intel_crtc_state *crtc_state = 937 intel_atomic_get_new_crtc_state(state, crtc); 938 const struct drm_connector_state *conn_state; 939 struct drm_connector *conn; 940 int i; 941 942 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 943 struct intel_encoder *encoder = 944 to_intel_encoder(conn_state->best_encoder); 945 946 if (conn_state->crtc != &crtc->base) 947 continue; 948 949 if (encoder->audio_enable) 950 encoder->audio_enable(encoder, crtc_state, conn_state); 951 } 952 } 953 954 static void intel_encoders_audio_disable(struct intel_atomic_state *state, 955 struct intel_crtc *crtc) 956 { 957 const struct intel_crtc_state *old_crtc_state = 958 intel_atomic_get_old_crtc_state(state, crtc); 959 const struct drm_connector_state *old_conn_state; 960 struct drm_connector *conn; 961 int i; 962 963 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 964 struct intel_encoder *encoder = 965 to_intel_encoder(old_conn_state->best_encoder); 966 967 if (old_conn_state->crtc != &crtc->base) 968 continue; 969 970 if (encoder->audio_disable) 971 encoder->audio_disable(encoder, old_crtc_state, old_conn_state); 972 } 973 } 974 975 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 976 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 977 (new_crtc_state)->feature) 978 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 979 ((old_crtc_state)->feature && \ 980 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 981 982 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 983 const struct intel_crtc_state *new_crtc_state) 984 { 985 if (!new_crtc_state->hw.active) 986 return false; 987 988 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 989 } 990 991 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 992 const struct intel_crtc_state *new_crtc_state) 993 { 994 if (!old_crtc_state->hw.active) 995 return false; 996 997 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 998 } 999 1000 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, 1001 const struct intel_crtc_state *new_crtc_state) 1002 { 1003 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline || 1004 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || 1005 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || 1006 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || 1007 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; 1008 } 1009 1010 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, 1011 const struct intel_crtc_state *new_crtc_state) 1012 { 1013 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || 1014 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; 1015 } 1016 1017 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 1018 const struct intel_crtc_state *new_crtc_state) 1019 { 1020 if (!new_crtc_state->hw.active) 1021 return false; 1022 1023 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) || 1024 (new_crtc_state->vrr.enable && 1025 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 1026 vrr_params_changed(old_crtc_state, new_crtc_state))); 1027 } 1028 1029 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 1030 const struct intel_crtc_state *new_crtc_state) 1031 { 1032 if (!old_crtc_state->hw.active) 1033 return false; 1034 1035 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) || 1036 (old_crtc_state->vrr.enable && 1037 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 1038 vrr_params_changed(old_crtc_state, new_crtc_state))); 1039 } 1040 1041 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, 1042 const struct intel_crtc_state *new_crtc_state) 1043 { 1044 if (!new_crtc_state->hw.active) 1045 return false; 1046 1047 return is_enabling(has_audio, old_crtc_state, new_crtc_state) || 1048 (new_crtc_state->has_audio && 1049 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 1050 } 1051 1052 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, 1053 const struct intel_crtc_state *new_crtc_state) 1054 { 1055 if (!old_crtc_state->hw.active) 1056 return false; 1057 1058 return is_disabling(has_audio, old_crtc_state, new_crtc_state) || 1059 (old_crtc_state->has_audio && 1060 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 1061 } 1062 1063 #undef is_disabling 1064 #undef is_enabling 1065 1066 static void intel_post_plane_update(struct intel_atomic_state *state, 1067 struct intel_crtc *crtc) 1068 { 1069 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1070 const struct intel_crtc_state *old_crtc_state = 1071 intel_atomic_get_old_crtc_state(state, crtc); 1072 const struct intel_crtc_state *new_crtc_state = 1073 intel_atomic_get_new_crtc_state(state, crtc); 1074 enum pipe pipe = crtc->pipe; 1075 1076 intel_psr_post_plane_update(state, crtc); 1077 1078 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1079 1080 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1081 intel_update_watermarks(dev_priv); 1082 1083 intel_fbc_post_update(state, crtc); 1084 1085 if (needs_async_flip_vtd_wa(old_crtc_state) && 1086 !needs_async_flip_vtd_wa(new_crtc_state)) 1087 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1088 1089 if (needs_nv12_wa(old_crtc_state) && 1090 !needs_nv12_wa(new_crtc_state)) 1091 skl_wa_827(dev_priv, pipe, false); 1092 1093 if (needs_scalerclk_wa(old_crtc_state) && 1094 !needs_scalerclk_wa(new_crtc_state)) 1095 icl_wa_scalerclkgating(dev_priv, pipe, false); 1096 1097 if (needs_cursorclk_wa(old_crtc_state) && 1098 !needs_cursorclk_wa(new_crtc_state)) 1099 icl_wa_cursorclkgating(dev_priv, pipe, false); 1100 1101 if (intel_crtc_needs_color_update(new_crtc_state)) 1102 intel_color_post_update(new_crtc_state); 1103 1104 if (audio_enabling(old_crtc_state, new_crtc_state)) 1105 intel_encoders_audio_enable(state, crtc); 1106 } 1107 1108 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1109 struct intel_crtc *crtc) 1110 { 1111 const struct intel_crtc_state *crtc_state = 1112 intel_atomic_get_new_crtc_state(state, crtc); 1113 u8 update_planes = crtc_state->update_planes; 1114 const struct intel_plane_state __maybe_unused *plane_state; 1115 struct intel_plane *plane; 1116 int i; 1117 1118 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1119 if (plane->pipe == crtc->pipe && 1120 update_planes & BIT(plane->id)) 1121 plane->enable_flip_done(plane); 1122 } 1123 } 1124 1125 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1126 struct intel_crtc *crtc) 1127 { 1128 const struct intel_crtc_state *crtc_state = 1129 intel_atomic_get_new_crtc_state(state, crtc); 1130 u8 update_planes = crtc_state->update_planes; 1131 const struct intel_plane_state __maybe_unused *plane_state; 1132 struct intel_plane *plane; 1133 int i; 1134 1135 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1136 if (plane->pipe == crtc->pipe && 1137 update_planes & BIT(plane->id)) 1138 plane->disable_flip_done(plane); 1139 } 1140 } 1141 1142 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1143 struct intel_crtc *crtc) 1144 { 1145 const struct intel_crtc_state *old_crtc_state = 1146 intel_atomic_get_old_crtc_state(state, crtc); 1147 const struct intel_crtc_state *new_crtc_state = 1148 intel_atomic_get_new_crtc_state(state, crtc); 1149 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1150 ~new_crtc_state->async_flip_planes; 1151 const struct intel_plane_state *old_plane_state; 1152 struct intel_plane *plane; 1153 bool need_vbl_wait = false; 1154 int i; 1155 1156 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1157 if (plane->need_async_flip_toggle_wa && 1158 plane->pipe == crtc->pipe && 1159 disable_async_flip_planes & BIT(plane->id)) { 1160 /* 1161 * Apart from the async flip bit we want to 1162 * preserve the old state for the plane. 1163 */ 1164 intel_plane_async_flip(plane, old_crtc_state, 1165 old_plane_state, false); 1166 need_vbl_wait = true; 1167 } 1168 } 1169 1170 if (need_vbl_wait) 1171 intel_crtc_wait_for_next_vblank(crtc); 1172 } 1173 1174 static void intel_pre_plane_update(struct intel_atomic_state *state, 1175 struct intel_crtc *crtc) 1176 { 1177 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1178 const struct intel_crtc_state *old_crtc_state = 1179 intel_atomic_get_old_crtc_state(state, crtc); 1180 const struct intel_crtc_state *new_crtc_state = 1181 intel_atomic_get_new_crtc_state(state, crtc); 1182 enum pipe pipe = crtc->pipe; 1183 1184 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1185 intel_vrr_disable(old_crtc_state); 1186 intel_crtc_update_active_timings(old_crtc_state, false); 1187 } 1188 1189 if (audio_disabling(old_crtc_state, new_crtc_state)) 1190 intel_encoders_audio_disable(state, crtc); 1191 1192 intel_drrs_deactivate(old_crtc_state); 1193 1194 intel_psr_pre_plane_update(state, crtc); 1195 1196 if (hsw_ips_pre_update(state, crtc)) 1197 intel_crtc_wait_for_next_vblank(crtc); 1198 1199 if (intel_fbc_pre_update(state, crtc)) 1200 intel_crtc_wait_for_next_vblank(crtc); 1201 1202 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1203 needs_async_flip_vtd_wa(new_crtc_state)) 1204 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1205 1206 /* Display WA 827 */ 1207 if (!needs_nv12_wa(old_crtc_state) && 1208 needs_nv12_wa(new_crtc_state)) 1209 skl_wa_827(dev_priv, pipe, true); 1210 1211 /* Wa_2006604312:icl,ehl */ 1212 if (!needs_scalerclk_wa(old_crtc_state) && 1213 needs_scalerclk_wa(new_crtc_state)) 1214 icl_wa_scalerclkgating(dev_priv, pipe, true); 1215 1216 /* Wa_1604331009:icl,jsl,ehl */ 1217 if (!needs_cursorclk_wa(old_crtc_state) && 1218 needs_cursorclk_wa(new_crtc_state)) 1219 icl_wa_cursorclkgating(dev_priv, pipe, true); 1220 1221 /* 1222 * Vblank time updates from the shadow to live plane control register 1223 * are blocked if the memory self-refresh mode is active at that 1224 * moment. So to make sure the plane gets truly disabled, disable 1225 * first the self-refresh mode. The self-refresh enable bit in turn 1226 * will be checked/applied by the HW only at the next frame start 1227 * event which is after the vblank start event, so we need to have a 1228 * wait-for-vblank between disabling the plane and the pipe. 1229 */ 1230 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1231 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1232 intel_crtc_wait_for_next_vblank(crtc); 1233 1234 /* 1235 * IVB workaround: must disable low power watermarks for at least 1236 * one frame before enabling scaling. LP watermarks can be re-enabled 1237 * when scaling is disabled. 1238 * 1239 * WaCxSRDisabledForSpriteScaling:ivb 1240 */ 1241 if (old_crtc_state->hw.active && 1242 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1243 intel_crtc_wait_for_next_vblank(crtc); 1244 1245 /* 1246 * If we're doing a modeset we don't need to do any 1247 * pre-vblank watermark programming here. 1248 */ 1249 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1250 /* 1251 * For platforms that support atomic watermarks, program the 1252 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1253 * will be the intermediate values that are safe for both pre- and 1254 * post- vblank; when vblank happens, the 'active' values will be set 1255 * to the final 'target' values and we'll do this again to get the 1256 * optimal watermarks. For gen9+ platforms, the values we program here 1257 * will be the final target values which will get automatically latched 1258 * at vblank time; no further programming will be necessary. 1259 * 1260 * If a platform hasn't been transitioned to atomic watermarks yet, 1261 * we'll continue to update watermarks the old way, if flags tell 1262 * us to. 1263 */ 1264 if (!intel_initial_watermarks(state, crtc)) 1265 if (new_crtc_state->update_wm_pre) 1266 intel_update_watermarks(dev_priv); 1267 } 1268 1269 /* 1270 * Gen2 reports pipe underruns whenever all planes are disabled. 1271 * So disable underrun reporting before all the planes get disabled. 1272 * 1273 * We do this after .initial_watermarks() so that we have a 1274 * chance of catching underruns with the intermediate watermarks 1275 * vs. the old plane configuration. 1276 */ 1277 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1278 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1279 1280 /* 1281 * WA for platforms where async address update enable bit 1282 * is double buffered and only latched at start of vblank. 1283 */ 1284 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1285 intel_crtc_async_flip_disable_wa(state, crtc); 1286 } 1287 1288 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1289 struct intel_crtc *crtc) 1290 { 1291 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1292 const struct intel_crtc_state *new_crtc_state = 1293 intel_atomic_get_new_crtc_state(state, crtc); 1294 unsigned int update_mask = new_crtc_state->update_planes; 1295 const struct intel_plane_state *old_plane_state; 1296 struct intel_plane *plane; 1297 unsigned fb_bits = 0; 1298 int i; 1299 1300 intel_crtc_dpms_overlay_disable(crtc); 1301 1302 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1303 if (crtc->pipe != plane->pipe || 1304 !(update_mask & BIT(plane->id))) 1305 continue; 1306 1307 intel_plane_disable_arm(plane, new_crtc_state); 1308 1309 if (old_plane_state->uapi.visible) 1310 fb_bits |= plane->frontbuffer_bit; 1311 } 1312 1313 intel_frontbuffer_flip(dev_priv, fb_bits); 1314 } 1315 1316 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1317 { 1318 struct drm_i915_private *i915 = to_i915(state->base.dev); 1319 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1320 struct intel_crtc *crtc; 1321 int i; 1322 1323 /* 1324 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1325 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1326 */ 1327 if (i915->display.dpll.mgr) { 1328 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1329 if (intel_crtc_needs_modeset(new_crtc_state)) 1330 continue; 1331 1332 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1333 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1334 } 1335 } 1336 } 1337 1338 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1339 struct intel_crtc *crtc) 1340 { 1341 const struct intel_crtc_state *crtc_state = 1342 intel_atomic_get_new_crtc_state(state, crtc); 1343 const struct drm_connector_state *conn_state; 1344 struct drm_connector *conn; 1345 int i; 1346 1347 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1348 struct intel_encoder *encoder = 1349 to_intel_encoder(conn_state->best_encoder); 1350 1351 if (conn_state->crtc != &crtc->base) 1352 continue; 1353 1354 if (encoder->pre_pll_enable) 1355 encoder->pre_pll_enable(state, encoder, 1356 crtc_state, conn_state); 1357 } 1358 } 1359 1360 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1361 struct intel_crtc *crtc) 1362 { 1363 const struct intel_crtc_state *crtc_state = 1364 intel_atomic_get_new_crtc_state(state, crtc); 1365 const struct drm_connector_state *conn_state; 1366 struct drm_connector *conn; 1367 int i; 1368 1369 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1370 struct intel_encoder *encoder = 1371 to_intel_encoder(conn_state->best_encoder); 1372 1373 if (conn_state->crtc != &crtc->base) 1374 continue; 1375 1376 if (encoder->pre_enable) 1377 encoder->pre_enable(state, encoder, 1378 crtc_state, conn_state); 1379 } 1380 } 1381 1382 static void intel_encoders_enable(struct intel_atomic_state *state, 1383 struct intel_crtc *crtc) 1384 { 1385 const struct intel_crtc_state *crtc_state = 1386 intel_atomic_get_new_crtc_state(state, crtc); 1387 const struct drm_connector_state *conn_state; 1388 struct drm_connector *conn; 1389 int i; 1390 1391 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1392 struct intel_encoder *encoder = 1393 to_intel_encoder(conn_state->best_encoder); 1394 1395 if (conn_state->crtc != &crtc->base) 1396 continue; 1397 1398 if (encoder->enable) 1399 encoder->enable(state, encoder, 1400 crtc_state, conn_state); 1401 intel_opregion_notify_encoder(encoder, true); 1402 } 1403 } 1404 1405 static void intel_encoders_disable(struct intel_atomic_state *state, 1406 struct intel_crtc *crtc) 1407 { 1408 const struct intel_crtc_state *old_crtc_state = 1409 intel_atomic_get_old_crtc_state(state, crtc); 1410 const struct drm_connector_state *old_conn_state; 1411 struct drm_connector *conn; 1412 int i; 1413 1414 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1415 struct intel_encoder *encoder = 1416 to_intel_encoder(old_conn_state->best_encoder); 1417 1418 if (old_conn_state->crtc != &crtc->base) 1419 continue; 1420 1421 intel_opregion_notify_encoder(encoder, false); 1422 if (encoder->disable) 1423 encoder->disable(state, encoder, 1424 old_crtc_state, old_conn_state); 1425 } 1426 } 1427 1428 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1429 struct intel_crtc *crtc) 1430 { 1431 const struct intel_crtc_state *old_crtc_state = 1432 intel_atomic_get_old_crtc_state(state, crtc); 1433 const struct drm_connector_state *old_conn_state; 1434 struct drm_connector *conn; 1435 int i; 1436 1437 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1438 struct intel_encoder *encoder = 1439 to_intel_encoder(old_conn_state->best_encoder); 1440 1441 if (old_conn_state->crtc != &crtc->base) 1442 continue; 1443 1444 if (encoder->post_disable) 1445 encoder->post_disable(state, encoder, 1446 old_crtc_state, old_conn_state); 1447 } 1448 } 1449 1450 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1451 struct intel_crtc *crtc) 1452 { 1453 const struct intel_crtc_state *old_crtc_state = 1454 intel_atomic_get_old_crtc_state(state, crtc); 1455 const struct drm_connector_state *old_conn_state; 1456 struct drm_connector *conn; 1457 int i; 1458 1459 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1460 struct intel_encoder *encoder = 1461 to_intel_encoder(old_conn_state->best_encoder); 1462 1463 if (old_conn_state->crtc != &crtc->base) 1464 continue; 1465 1466 if (encoder->post_pll_disable) 1467 encoder->post_pll_disable(state, encoder, 1468 old_crtc_state, old_conn_state); 1469 } 1470 } 1471 1472 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1473 struct intel_crtc *crtc) 1474 { 1475 const struct intel_crtc_state *crtc_state = 1476 intel_atomic_get_new_crtc_state(state, crtc); 1477 const struct drm_connector_state *conn_state; 1478 struct drm_connector *conn; 1479 int i; 1480 1481 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1482 struct intel_encoder *encoder = 1483 to_intel_encoder(conn_state->best_encoder); 1484 1485 if (conn_state->crtc != &crtc->base) 1486 continue; 1487 1488 if (encoder->update_pipe) 1489 encoder->update_pipe(state, encoder, 1490 crtc_state, conn_state); 1491 } 1492 } 1493 1494 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1495 { 1496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1497 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1498 1499 plane->disable_arm(plane, crtc_state); 1500 } 1501 1502 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1503 { 1504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1505 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1506 1507 if (crtc_state->has_pch_encoder) { 1508 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1509 &crtc_state->fdi_m_n); 1510 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1511 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1512 &crtc_state->dp_m_n); 1513 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1514 &crtc_state->dp_m2_n2); 1515 } 1516 1517 intel_set_transcoder_timings(crtc_state); 1518 1519 ilk_set_pipeconf(crtc_state); 1520 } 1521 1522 static void ilk_crtc_enable(struct intel_atomic_state *state, 1523 struct intel_crtc *crtc) 1524 { 1525 const struct intel_crtc_state *new_crtc_state = 1526 intel_atomic_get_new_crtc_state(state, crtc); 1527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1528 enum pipe pipe = crtc->pipe; 1529 1530 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1531 return; 1532 1533 /* 1534 * Sometimes spurious CPU pipe underruns happen during FDI 1535 * training, at least with VGA+HDMI cloning. Suppress them. 1536 * 1537 * On ILK we get an occasional spurious CPU pipe underruns 1538 * between eDP port A enable and vdd enable. Also PCH port 1539 * enable seems to result in the occasional CPU pipe underrun. 1540 * 1541 * Spurious PCH underruns also occur during PCH enabling. 1542 */ 1543 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1544 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1545 1546 ilk_configure_cpu_transcoder(new_crtc_state); 1547 1548 intel_set_pipe_src_size(new_crtc_state); 1549 1550 crtc->active = true; 1551 1552 intel_encoders_pre_enable(state, crtc); 1553 1554 if (new_crtc_state->has_pch_encoder) { 1555 ilk_pch_pre_enable(state, crtc); 1556 } else { 1557 assert_fdi_tx_disabled(dev_priv, pipe); 1558 assert_fdi_rx_disabled(dev_priv, pipe); 1559 } 1560 1561 ilk_pfit_enable(new_crtc_state); 1562 1563 /* 1564 * On ILK+ LUT must be loaded before the pipe is running but with 1565 * clocks enabled 1566 */ 1567 intel_color_load_luts(new_crtc_state); 1568 intel_color_commit_noarm(new_crtc_state); 1569 intel_color_commit_arm(new_crtc_state); 1570 /* update DSPCNTR to configure gamma for pipe bottom color */ 1571 intel_disable_primary_plane(new_crtc_state); 1572 1573 intel_initial_watermarks(state, crtc); 1574 intel_enable_transcoder(new_crtc_state); 1575 1576 if (new_crtc_state->has_pch_encoder) 1577 ilk_pch_enable(state, crtc); 1578 1579 intel_crtc_vblank_on(new_crtc_state); 1580 1581 intel_encoders_enable(state, crtc); 1582 1583 if (HAS_PCH_CPT(dev_priv)) 1584 intel_wait_for_pipe_scanline_moving(crtc); 1585 1586 /* 1587 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1588 * And a second vblank wait is needed at least on ILK with 1589 * some interlaced HDMI modes. Let's do the double wait always 1590 * in case there are more corner cases we don't know about. 1591 */ 1592 if (new_crtc_state->has_pch_encoder) { 1593 intel_crtc_wait_for_next_vblank(crtc); 1594 intel_crtc_wait_for_next_vblank(crtc); 1595 } 1596 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1597 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1598 } 1599 1600 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1601 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) 1602 { 1603 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1604 1605 return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled; 1606 } 1607 1608 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) 1609 { 1610 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1611 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1612 1613 intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe), 1614 mask, enable ? mask : 0); 1615 } 1616 1617 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1618 { 1619 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1621 1622 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1623 HSW_LINETIME(crtc_state->linetime) | 1624 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1625 } 1626 1627 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1628 { 1629 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1630 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1631 1632 intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder), 1633 HSW_FRAME_START_DELAY_MASK, 1634 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1635 } 1636 1637 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1638 { 1639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1641 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1642 1643 if (crtc_state->has_pch_encoder) { 1644 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1645 &crtc_state->fdi_m_n); 1646 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1647 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1648 &crtc_state->dp_m_n); 1649 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1650 &crtc_state->dp_m2_n2); 1651 } 1652 1653 intel_set_transcoder_timings(crtc_state); 1654 if (HAS_VRR(dev_priv)) 1655 intel_vrr_set_transcoder_timings(crtc_state); 1656 1657 if (cpu_transcoder != TRANSCODER_EDP) 1658 intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder), 1659 crtc_state->pixel_multiplier - 1); 1660 1661 hsw_set_frame_start_delay(crtc_state); 1662 1663 hsw_set_transconf(crtc_state); 1664 } 1665 1666 static void hsw_crtc_enable(struct intel_atomic_state *state, 1667 struct intel_crtc *crtc) 1668 { 1669 const struct intel_crtc_state *new_crtc_state = 1670 intel_atomic_get_new_crtc_state(state, crtc); 1671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1672 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1673 struct intel_crtc *pipe_crtc; 1674 1675 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1676 return; 1677 1678 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, 1679 intel_crtc_joined_pipe_mask(new_crtc_state)) 1680 intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe); 1681 1682 intel_encoders_pre_pll_enable(state, crtc); 1683 1684 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, 1685 intel_crtc_joined_pipe_mask(new_crtc_state)) { 1686 const struct intel_crtc_state *pipe_crtc_state = 1687 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1688 1689 if (pipe_crtc_state->shared_dpll) 1690 intel_enable_shared_dpll(pipe_crtc_state); 1691 } 1692 1693 intel_encoders_pre_enable(state, crtc); 1694 1695 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, 1696 intel_crtc_joined_pipe_mask(new_crtc_state)) { 1697 const struct intel_crtc_state *pipe_crtc_state = 1698 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1699 1700 intel_dsc_enable(pipe_crtc_state); 1701 1702 if (DISPLAY_VER(dev_priv) >= 13) 1703 intel_uncompressed_joiner_enable(pipe_crtc_state); 1704 1705 intel_set_pipe_src_size(pipe_crtc_state); 1706 1707 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1708 bdw_set_pipe_misc(pipe_crtc_state); 1709 } 1710 1711 if (!transcoder_is_dsi(cpu_transcoder)) 1712 hsw_configure_cpu_transcoder(new_crtc_state); 1713 1714 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, 1715 intel_crtc_joined_pipe_mask(new_crtc_state)) { 1716 const struct intel_crtc_state *pipe_crtc_state = 1717 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1718 1719 pipe_crtc->active = true; 1720 1721 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) 1722 glk_pipe_scaler_clock_gating_wa(pipe_crtc, true); 1723 1724 if (DISPLAY_VER(dev_priv) >= 9) 1725 skl_pfit_enable(pipe_crtc_state); 1726 else 1727 ilk_pfit_enable(pipe_crtc_state); 1728 1729 /* 1730 * On ILK+ LUT must be loaded before the pipe is running but with 1731 * clocks enabled 1732 */ 1733 intel_color_load_luts(pipe_crtc_state); 1734 intel_color_commit_noarm(pipe_crtc_state); 1735 intel_color_commit_arm(pipe_crtc_state); 1736 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1737 if (DISPLAY_VER(dev_priv) < 9) 1738 intel_disable_primary_plane(pipe_crtc_state); 1739 1740 hsw_set_linetime_wm(pipe_crtc_state); 1741 1742 if (DISPLAY_VER(dev_priv) >= 11) 1743 icl_set_pipe_chicken(pipe_crtc_state); 1744 1745 intel_initial_watermarks(state, pipe_crtc); 1746 } 1747 1748 intel_encoders_enable(state, crtc); 1749 1750 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, 1751 intel_crtc_joined_pipe_mask(new_crtc_state)) { 1752 const struct intel_crtc_state *pipe_crtc_state = 1753 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1754 enum pipe hsw_workaround_pipe; 1755 1756 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) { 1757 intel_crtc_wait_for_next_vblank(pipe_crtc); 1758 glk_pipe_scaler_clock_gating_wa(pipe_crtc, false); 1759 } 1760 1761 /* 1762 * If we change the relative order between pipe/planes 1763 * enabling, we need to change the workaround. 1764 */ 1765 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe; 1766 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1767 struct intel_crtc *wa_crtc = 1768 intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1769 1770 intel_crtc_wait_for_next_vblank(wa_crtc); 1771 intel_crtc_wait_for_next_vblank(wa_crtc); 1772 } 1773 } 1774 } 1775 1776 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1777 { 1778 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1779 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1780 enum pipe pipe = crtc->pipe; 1781 1782 /* To avoid upsetting the power well on haswell only disable the pfit if 1783 * it's in use. The hw state code will make sure we get this right. */ 1784 if (!old_crtc_state->pch_pfit.enabled) 1785 return; 1786 1787 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1788 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1789 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1790 } 1791 1792 static void ilk_crtc_disable(struct intel_atomic_state *state, 1793 struct intel_crtc *crtc) 1794 { 1795 const struct intel_crtc_state *old_crtc_state = 1796 intel_atomic_get_old_crtc_state(state, crtc); 1797 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1798 enum pipe pipe = crtc->pipe; 1799 1800 /* 1801 * Sometimes spurious CPU pipe underruns happen when the 1802 * pipe is already disabled, but FDI RX/TX is still enabled. 1803 * Happens at least with VGA+HDMI cloning. Suppress them. 1804 */ 1805 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1806 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1807 1808 intel_encoders_disable(state, crtc); 1809 1810 intel_crtc_vblank_off(old_crtc_state); 1811 1812 intel_disable_transcoder(old_crtc_state); 1813 1814 ilk_pfit_disable(old_crtc_state); 1815 1816 if (old_crtc_state->has_pch_encoder) 1817 ilk_pch_disable(state, crtc); 1818 1819 intel_encoders_post_disable(state, crtc); 1820 1821 if (old_crtc_state->has_pch_encoder) 1822 ilk_pch_post_disable(state, crtc); 1823 1824 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1825 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1826 1827 intel_disable_shared_dpll(old_crtc_state); 1828 } 1829 1830 static void hsw_crtc_disable(struct intel_atomic_state *state, 1831 struct intel_crtc *crtc) 1832 { 1833 const struct intel_crtc_state *old_crtc_state = 1834 intel_atomic_get_old_crtc_state(state, crtc); 1835 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1836 struct intel_crtc *pipe_crtc; 1837 1838 /* 1839 * FIXME collapse everything to one hook. 1840 * Need care with mst->ddi interactions. 1841 */ 1842 intel_encoders_disable(state, crtc); 1843 intel_encoders_post_disable(state, crtc); 1844 1845 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 1846 intel_crtc_joined_pipe_mask(old_crtc_state)) { 1847 const struct intel_crtc_state *old_pipe_crtc_state = 1848 intel_atomic_get_old_crtc_state(state, pipe_crtc); 1849 1850 intel_disable_shared_dpll(old_pipe_crtc_state); 1851 } 1852 1853 intel_encoders_post_pll_disable(state, crtc); 1854 1855 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 1856 intel_crtc_joined_pipe_mask(old_crtc_state)) 1857 intel_dmc_disable_pipe(i915, pipe_crtc->pipe); 1858 } 1859 1860 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1861 { 1862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1863 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1864 1865 if (!crtc_state->gmch_pfit.control) 1866 return; 1867 1868 /* 1869 * The panel fitter should only be adjusted whilst the pipe is disabled, 1870 * according to register description and PRM. 1871 */ 1872 drm_WARN_ON(&dev_priv->drm, 1873 intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE); 1874 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1875 1876 intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv), 1877 crtc_state->gmch_pfit.pgm_ratios); 1878 intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 1879 crtc_state->gmch_pfit.control); 1880 1881 /* Border color in case we don't scale up to the full screen. Black by 1882 * default, change to something else for debugging. */ 1883 intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); 1884 } 1885 1886 /* Prefer intel_encoder_is_combo() */ 1887 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1888 { 1889 if (phy == PHY_NONE) 1890 return false; 1891 else if (IS_ALDERLAKE_S(dev_priv)) 1892 return phy <= PHY_E; 1893 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1894 return phy <= PHY_D; 1895 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 1896 return phy <= PHY_C; 1897 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1898 return phy <= PHY_B; 1899 else 1900 /* 1901 * DG2 outputs labelled as "combo PHY" in the bspec use 1902 * SNPS PHYs with completely different programming, 1903 * hence we always return false here. 1904 */ 1905 return false; 1906 } 1907 1908 /* Prefer intel_encoder_is_tc() */ 1909 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1910 { 1911 /* 1912 * Discrete GPU phy's are not attached to FIA's to support TC 1913 * subsystem Legacy or non-legacy, and only support native DP/HDMI 1914 */ 1915 if (IS_DGFX(dev_priv)) 1916 return false; 1917 1918 if (DISPLAY_VER(dev_priv) >= 13) 1919 return phy >= PHY_F && phy <= PHY_I; 1920 else if (IS_TIGERLAKE(dev_priv)) 1921 return phy >= PHY_D && phy <= PHY_I; 1922 else if (IS_ICELAKE(dev_priv)) 1923 return phy >= PHY_C && phy <= PHY_F; 1924 1925 return false; 1926 } 1927 1928 /* Prefer intel_encoder_is_snps() */ 1929 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1930 { 1931 /* 1932 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port 1933 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc(). 1934 */ 1935 return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E; 1936 } 1937 1938 /* Prefer intel_encoder_to_phy() */ 1939 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1940 { 1941 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1942 return PHY_D + port - PORT_D_XELPD; 1943 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1944 return PHY_F + port - PORT_TC1; 1945 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1946 return PHY_B + port - PORT_TC1; 1947 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1948 return PHY_C + port - PORT_TC1; 1949 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && 1950 port == PORT_D) 1951 return PHY_A; 1952 1953 return PHY_A + port - PORT_A; 1954 } 1955 1956 /* Prefer intel_encoder_to_tc() */ 1957 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1958 { 1959 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1960 return TC_PORT_NONE; 1961 1962 if (DISPLAY_VER(dev_priv) >= 12) 1963 return TC_PORT_1 + port - PORT_TC1; 1964 else 1965 return TC_PORT_1 + port - PORT_C; 1966 } 1967 1968 enum phy intel_encoder_to_phy(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 1972 return intel_port_to_phy(i915, encoder->port); 1973 } 1974 1975 bool intel_encoder_is_combo(struct intel_encoder *encoder) 1976 { 1977 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1978 1979 return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder)); 1980 } 1981 1982 bool intel_encoder_is_snps(struct intel_encoder *encoder) 1983 { 1984 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1985 1986 return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder)); 1987 } 1988 1989 bool intel_encoder_is_tc(struct intel_encoder *encoder) 1990 { 1991 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1992 1993 return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder)); 1994 } 1995 1996 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) 1997 { 1998 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1999 2000 return intel_port_to_tc(i915, encoder->port); 2001 } 2002 2003 enum intel_display_power_domain 2004 intel_aux_power_domain(struct intel_digital_port *dig_port) 2005 { 2006 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2007 2008 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2009 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2010 2011 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2012 } 2013 2014 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2015 struct intel_power_domain_mask *mask) 2016 { 2017 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2018 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2019 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2020 struct drm_encoder *encoder; 2021 enum pipe pipe = crtc->pipe; 2022 2023 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2024 2025 if (!crtc_state->hw.active) 2026 return; 2027 2028 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2029 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2030 if (crtc_state->pch_pfit.enabled || 2031 crtc_state->pch_pfit.force_thru) 2032 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2033 2034 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2035 crtc_state->uapi.encoder_mask) { 2036 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2037 2038 set_bit(intel_encoder->power_domain, mask->bits); 2039 } 2040 2041 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2042 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2043 2044 if (crtc_state->shared_dpll) 2045 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2046 2047 if (crtc_state->dsc.compression_enable) 2048 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2049 } 2050 2051 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2052 struct intel_power_domain_mask *old_domains) 2053 { 2054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2055 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2056 enum intel_display_power_domain domain; 2057 struct intel_power_domain_mask domains, new_domains; 2058 2059 get_crtc_power_domains(crtc_state, &domains); 2060 2061 bitmap_andnot(new_domains.bits, 2062 domains.bits, 2063 crtc->enabled_power_domains.mask.bits, 2064 POWER_DOMAIN_NUM); 2065 bitmap_andnot(old_domains->bits, 2066 crtc->enabled_power_domains.mask.bits, 2067 domains.bits, 2068 POWER_DOMAIN_NUM); 2069 2070 for_each_power_domain(domain, &new_domains) 2071 intel_display_power_get_in_set(dev_priv, 2072 &crtc->enabled_power_domains, 2073 domain); 2074 } 2075 2076 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2077 struct intel_power_domain_mask *domains) 2078 { 2079 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2080 &crtc->enabled_power_domains, 2081 domains); 2082 } 2083 2084 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2085 { 2086 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2087 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2088 2089 if (intel_crtc_has_dp_encoder(crtc_state)) { 2090 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2091 &crtc_state->dp_m_n); 2092 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2093 &crtc_state->dp_m2_n2); 2094 } 2095 2096 intel_set_transcoder_timings(crtc_state); 2097 2098 i9xx_set_pipeconf(crtc_state); 2099 } 2100 2101 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2102 struct intel_crtc *crtc) 2103 { 2104 const struct intel_crtc_state *new_crtc_state = 2105 intel_atomic_get_new_crtc_state(state, crtc); 2106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2107 enum pipe pipe = crtc->pipe; 2108 2109 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2110 return; 2111 2112 i9xx_configure_cpu_transcoder(new_crtc_state); 2113 2114 intel_set_pipe_src_size(new_crtc_state); 2115 2116 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 2117 2118 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2119 intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe), 2120 CHV_BLEND_LEGACY); 2121 intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0); 2122 } 2123 2124 crtc->active = true; 2125 2126 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2127 2128 intel_encoders_pre_pll_enable(state, crtc); 2129 2130 if (IS_CHERRYVIEW(dev_priv)) 2131 chv_enable_pll(new_crtc_state); 2132 else 2133 vlv_enable_pll(new_crtc_state); 2134 2135 intel_encoders_pre_enable(state, crtc); 2136 2137 i9xx_pfit_enable(new_crtc_state); 2138 2139 intel_color_load_luts(new_crtc_state); 2140 intel_color_commit_noarm(new_crtc_state); 2141 intel_color_commit_arm(new_crtc_state); 2142 /* update DSPCNTR to configure gamma for pipe bottom color */ 2143 intel_disable_primary_plane(new_crtc_state); 2144 2145 intel_initial_watermarks(state, crtc); 2146 intel_enable_transcoder(new_crtc_state); 2147 2148 intel_crtc_vblank_on(new_crtc_state); 2149 2150 intel_encoders_enable(state, crtc); 2151 } 2152 2153 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2154 struct intel_crtc *crtc) 2155 { 2156 const struct intel_crtc_state *new_crtc_state = 2157 intel_atomic_get_new_crtc_state(state, crtc); 2158 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2159 enum pipe pipe = crtc->pipe; 2160 2161 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2162 return; 2163 2164 i9xx_configure_cpu_transcoder(new_crtc_state); 2165 2166 intel_set_pipe_src_size(new_crtc_state); 2167 2168 crtc->active = true; 2169 2170 if (DISPLAY_VER(dev_priv) != 2) 2171 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2172 2173 intel_encoders_pre_enable(state, crtc); 2174 2175 i9xx_enable_pll(new_crtc_state); 2176 2177 i9xx_pfit_enable(new_crtc_state); 2178 2179 intel_color_load_luts(new_crtc_state); 2180 intel_color_commit_noarm(new_crtc_state); 2181 intel_color_commit_arm(new_crtc_state); 2182 /* update DSPCNTR to configure gamma for pipe bottom color */ 2183 intel_disable_primary_plane(new_crtc_state); 2184 2185 if (!intel_initial_watermarks(state, crtc)) 2186 intel_update_watermarks(dev_priv); 2187 intel_enable_transcoder(new_crtc_state); 2188 2189 intel_crtc_vblank_on(new_crtc_state); 2190 2191 intel_encoders_enable(state, crtc); 2192 2193 /* prevents spurious underruns */ 2194 if (DISPLAY_VER(dev_priv) == 2) 2195 intel_crtc_wait_for_next_vblank(crtc); 2196 } 2197 2198 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2199 { 2200 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2201 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2202 2203 if (!old_crtc_state->gmch_pfit.control) 2204 return; 2205 2206 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2207 2208 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2209 intel_de_read(dev_priv, PFIT_CONTROL(dev_priv))); 2210 intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0); 2211 } 2212 2213 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2214 struct intel_crtc *crtc) 2215 { 2216 struct intel_crtc_state *old_crtc_state = 2217 intel_atomic_get_old_crtc_state(state, crtc); 2218 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2219 enum pipe pipe = crtc->pipe; 2220 2221 /* 2222 * On gen2 planes are double buffered but the pipe isn't, so we must 2223 * wait for planes to fully turn off before disabling the pipe. 2224 */ 2225 if (DISPLAY_VER(dev_priv) == 2) 2226 intel_crtc_wait_for_next_vblank(crtc); 2227 2228 intel_encoders_disable(state, crtc); 2229 2230 intel_crtc_vblank_off(old_crtc_state); 2231 2232 intel_disable_transcoder(old_crtc_state); 2233 2234 i9xx_pfit_disable(old_crtc_state); 2235 2236 intel_encoders_post_disable(state, crtc); 2237 2238 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2239 if (IS_CHERRYVIEW(dev_priv)) 2240 chv_disable_pll(dev_priv, pipe); 2241 else if (IS_VALLEYVIEW(dev_priv)) 2242 vlv_disable_pll(dev_priv, pipe); 2243 else 2244 i9xx_disable_pll(old_crtc_state); 2245 } 2246 2247 intel_encoders_post_pll_disable(state, crtc); 2248 2249 if (DISPLAY_VER(dev_priv) != 2) 2250 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2251 2252 if (!dev_priv->display.funcs.wm->initial_watermarks) 2253 intel_update_watermarks(dev_priv); 2254 2255 /* clock the pipe down to 640x480@60 to potentially save power */ 2256 if (IS_I830(dev_priv)) 2257 i830_enable_pipe(dev_priv, pipe); 2258 } 2259 2260 void intel_encoder_destroy(struct drm_encoder *encoder) 2261 { 2262 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2263 2264 drm_encoder_cleanup(encoder); 2265 kfree(intel_encoder); 2266 } 2267 2268 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2269 { 2270 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2271 2272 /* GDG double wide on either pipe, otherwise pipe A only */ 2273 return DISPLAY_VER(dev_priv) < 4 && 2274 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2275 } 2276 2277 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2278 { 2279 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2280 struct drm_rect src; 2281 2282 /* 2283 * We only use IF-ID interlacing. If we ever use 2284 * PF-ID we'll need to adjust the pixel_rate here. 2285 */ 2286 2287 if (!crtc_state->pch_pfit.enabled) 2288 return pixel_rate; 2289 2290 drm_rect_init(&src, 0, 0, 2291 drm_rect_width(&crtc_state->pipe_src) << 16, 2292 drm_rect_height(&crtc_state->pipe_src) << 16); 2293 2294 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2295 pixel_rate); 2296 } 2297 2298 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2299 const struct drm_display_mode *timings) 2300 { 2301 mode->hdisplay = timings->crtc_hdisplay; 2302 mode->htotal = timings->crtc_htotal; 2303 mode->hsync_start = timings->crtc_hsync_start; 2304 mode->hsync_end = timings->crtc_hsync_end; 2305 2306 mode->vdisplay = timings->crtc_vdisplay; 2307 mode->vtotal = timings->crtc_vtotal; 2308 mode->vsync_start = timings->crtc_vsync_start; 2309 mode->vsync_end = timings->crtc_vsync_end; 2310 2311 mode->flags = timings->flags; 2312 mode->type = DRM_MODE_TYPE_DRIVER; 2313 2314 mode->clock = timings->crtc_clock; 2315 2316 drm_mode_set_name(mode); 2317 } 2318 2319 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2320 { 2321 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2322 2323 if (HAS_GMCH(dev_priv)) 2324 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2325 crtc_state->pixel_rate = 2326 crtc_state->hw.pipe_mode.crtc_clock; 2327 else 2328 crtc_state->pixel_rate = 2329 ilk_pipe_pixel_rate(crtc_state); 2330 } 2331 2332 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2333 struct drm_display_mode *mode) 2334 { 2335 int num_pipes = intel_joiner_num_pipes(crtc_state); 2336 2337 if (num_pipes < 2) 2338 return; 2339 2340 mode->crtc_clock /= num_pipes; 2341 mode->crtc_hdisplay /= num_pipes; 2342 mode->crtc_hblank_start /= num_pipes; 2343 mode->crtc_hblank_end /= num_pipes; 2344 mode->crtc_hsync_start /= num_pipes; 2345 mode->crtc_hsync_end /= num_pipes; 2346 mode->crtc_htotal /= num_pipes; 2347 } 2348 2349 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2350 struct drm_display_mode *mode) 2351 { 2352 int overlap = crtc_state->splitter.pixel_overlap; 2353 int n = crtc_state->splitter.link_count; 2354 2355 if (!crtc_state->splitter.enable) 2356 return; 2357 2358 /* 2359 * eDP MSO uses segment timings from EDID for transcoder 2360 * timings, but full mode for everything else. 2361 * 2362 * h_full = (h_segment - pixel_overlap) * link_count 2363 */ 2364 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2365 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2366 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2367 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2368 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2369 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2370 mode->crtc_clock *= n; 2371 } 2372 2373 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2374 { 2375 struct drm_display_mode *mode = &crtc_state->hw.mode; 2376 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2377 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2378 2379 /* 2380 * Start with the adjusted_mode crtc timings, which 2381 * have been filled with the transcoder timings. 2382 */ 2383 drm_mode_copy(pipe_mode, adjusted_mode); 2384 2385 /* Expand MSO per-segment transcoder timings to full */ 2386 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2387 2388 /* 2389 * We want the full numbers in adjusted_mode normal timings, 2390 * adjusted_mode crtc timings are left with the raw transcoder 2391 * timings. 2392 */ 2393 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2394 2395 /* Populate the "user" mode with full numbers */ 2396 drm_mode_copy(mode, pipe_mode); 2397 intel_mode_from_crtc_timings(mode, mode); 2398 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2399 (intel_joiner_num_pipes(crtc_state) ?: 1); 2400 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2401 2402 /* Derive per-pipe timings in case joiner is used */ 2403 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2404 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2405 2406 intel_crtc_compute_pixel_rate(crtc_state); 2407 } 2408 2409 void intel_encoder_get_config(struct intel_encoder *encoder, 2410 struct intel_crtc_state *crtc_state) 2411 { 2412 encoder->get_config(encoder, crtc_state); 2413 2414 intel_crtc_readout_derived_state(crtc_state); 2415 } 2416 2417 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2418 { 2419 int num_pipes = intel_joiner_num_pipes(crtc_state); 2420 int width, height; 2421 2422 if (num_pipes < 2) 2423 return; 2424 2425 width = drm_rect_width(&crtc_state->pipe_src); 2426 height = drm_rect_height(&crtc_state->pipe_src); 2427 2428 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2429 width / num_pipes, height); 2430 } 2431 2432 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2433 { 2434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2435 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2436 2437 intel_joiner_compute_pipe_src(crtc_state); 2438 2439 /* 2440 * Pipe horizontal size must be even in: 2441 * - DVO ganged mode 2442 * - LVDS dual channel mode 2443 * - Double wide pipe 2444 */ 2445 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2446 if (crtc_state->double_wide) { 2447 drm_dbg_kms(&i915->drm, 2448 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2449 crtc->base.base.id, crtc->base.name); 2450 return -EINVAL; 2451 } 2452 2453 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2454 intel_is_dual_link_lvds(i915)) { 2455 drm_dbg_kms(&i915->drm, 2456 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2457 crtc->base.base.id, crtc->base.name); 2458 return -EINVAL; 2459 } 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2466 { 2467 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2468 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2469 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2470 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2471 int clock_limit = i915->display.cdclk.max_dotclk_freq; 2472 2473 /* 2474 * Start with the adjusted_mode crtc timings, which 2475 * have been filled with the transcoder timings. 2476 */ 2477 drm_mode_copy(pipe_mode, adjusted_mode); 2478 2479 /* Expand MSO per-segment transcoder timings to full */ 2480 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2481 2482 /* Derive per-pipe timings in case joiner is used */ 2483 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2484 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2485 2486 if (DISPLAY_VER(i915) < 4) { 2487 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2488 2489 /* 2490 * Enable double wide mode when the dot clock 2491 * is > 90% of the (display) core speed. 2492 */ 2493 if (intel_crtc_supports_double_wide(crtc) && 2494 pipe_mode->crtc_clock > clock_limit) { 2495 clock_limit = i915->display.cdclk.max_dotclk_freq; 2496 crtc_state->double_wide = true; 2497 } 2498 } 2499 2500 if (pipe_mode->crtc_clock > clock_limit) { 2501 drm_dbg_kms(&i915->drm, 2502 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2503 crtc->base.base.id, crtc->base.name, 2504 pipe_mode->crtc_clock, clock_limit, 2505 str_yes_no(crtc_state->double_wide)); 2506 return -EINVAL; 2507 } 2508 2509 return 0; 2510 } 2511 2512 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2513 struct intel_crtc *crtc) 2514 { 2515 struct intel_crtc_state *crtc_state = 2516 intel_atomic_get_new_crtc_state(state, crtc); 2517 int ret; 2518 2519 ret = intel_dpll_crtc_compute_clock(state, crtc); 2520 if (ret) 2521 return ret; 2522 2523 ret = intel_crtc_compute_pipe_src(crtc_state); 2524 if (ret) 2525 return ret; 2526 2527 ret = intel_crtc_compute_pipe_mode(crtc_state); 2528 if (ret) 2529 return ret; 2530 2531 intel_crtc_compute_pixel_rate(crtc_state); 2532 2533 if (crtc_state->has_pch_encoder) 2534 return ilk_fdi_compute_config(crtc, crtc_state); 2535 2536 return 0; 2537 } 2538 2539 static void 2540 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2541 { 2542 while (*num > DATA_LINK_M_N_MASK || 2543 *den > DATA_LINK_M_N_MASK) { 2544 *num >>= 1; 2545 *den >>= 1; 2546 } 2547 } 2548 2549 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2550 u32 m, u32 n, u32 constant_n) 2551 { 2552 if (constant_n) 2553 *ret_n = constant_n; 2554 else 2555 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2556 2557 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2558 intel_reduce_m_n_ratio(ret_m, ret_n); 2559 } 2560 2561 void 2562 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 2563 int pixel_clock, int link_clock, 2564 int bw_overhead, 2565 struct intel_link_m_n *m_n) 2566 { 2567 u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); 2568 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, 2569 bw_overhead); 2570 u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); 2571 2572 /* 2573 * Windows/BIOS uses fixed M/N values always. Follow suit. 2574 * 2575 * Also several DP dongles in particular seem to be fussy 2576 * about too large link M/N values. Presumably the 20bit 2577 * value used by Windows/BIOS is acceptable to everyone. 2578 */ 2579 m_n->tu = 64; 2580 compute_m_n(&m_n->data_m, &m_n->data_n, 2581 data_m, data_n, 2582 0x8000000); 2583 2584 compute_m_n(&m_n->link_m, &m_n->link_n, 2585 pixel_clock, link_symbol_clock, 2586 0x80000); 2587 } 2588 2589 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2590 { 2591 /* 2592 * There may be no VBT; and if the BIOS enabled SSC we can 2593 * just keep using it to avoid unnecessary flicker. Whereas if the 2594 * BIOS isn't using it, don't assume it will work even if the VBT 2595 * indicates as much. 2596 */ 2597 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2598 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2599 PCH_DREF_CONTROL) & 2600 DREF_SSC1_ENABLE; 2601 2602 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2603 drm_dbg_kms(&dev_priv->drm, 2604 "SSC %s by BIOS, overriding VBT which says %s\n", 2605 str_enabled_disabled(bios_lvds_use_ssc), 2606 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2607 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2608 } 2609 } 2610 } 2611 2612 void intel_zero_m_n(struct intel_link_m_n *m_n) 2613 { 2614 /* corresponds to 0 register value */ 2615 memset(m_n, 0, sizeof(*m_n)); 2616 m_n->tu = 1; 2617 } 2618 2619 void intel_set_m_n(struct drm_i915_private *i915, 2620 const struct intel_link_m_n *m_n, 2621 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2622 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2623 { 2624 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2625 intel_de_write(i915, data_n_reg, m_n->data_n); 2626 intel_de_write(i915, link_m_reg, m_n->link_m); 2627 /* 2628 * On BDW+ writing LINK_N arms the double buffered update 2629 * of all the M/N registers, so it must be written last. 2630 */ 2631 intel_de_write(i915, link_n_reg, m_n->link_n); 2632 } 2633 2634 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2635 enum transcoder transcoder) 2636 { 2637 if (IS_HASWELL(dev_priv)) 2638 return transcoder == TRANSCODER_EDP; 2639 2640 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2641 } 2642 2643 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2644 enum transcoder transcoder, 2645 const struct intel_link_m_n *m_n) 2646 { 2647 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2648 enum pipe pipe = crtc->pipe; 2649 2650 if (DISPLAY_VER(dev_priv) >= 5) 2651 intel_set_m_n(dev_priv, m_n, 2652 PIPE_DATA_M1(dev_priv, transcoder), 2653 PIPE_DATA_N1(dev_priv, transcoder), 2654 PIPE_LINK_M1(dev_priv, transcoder), 2655 PIPE_LINK_N1(dev_priv, transcoder)); 2656 else 2657 intel_set_m_n(dev_priv, m_n, 2658 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2659 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2660 } 2661 2662 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2663 enum transcoder transcoder, 2664 const struct intel_link_m_n *m_n) 2665 { 2666 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2667 2668 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2669 return; 2670 2671 intel_set_m_n(dev_priv, m_n, 2672 PIPE_DATA_M2(dev_priv, transcoder), 2673 PIPE_DATA_N2(dev_priv, transcoder), 2674 PIPE_LINK_M2(dev_priv, transcoder), 2675 PIPE_LINK_N2(dev_priv, transcoder)); 2676 } 2677 2678 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2679 { 2680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2682 enum pipe pipe = crtc->pipe; 2683 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2684 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2685 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2686 int vsyncshift = 0; 2687 2688 /* We need to be careful not to changed the adjusted mode, for otherwise 2689 * the hw state checker will get angry at the mismatch. */ 2690 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2691 crtc_vtotal = adjusted_mode->crtc_vtotal; 2692 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2693 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2694 2695 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2696 /* the chip adds 2 halflines automatically */ 2697 crtc_vtotal -= 1; 2698 crtc_vblank_end -= 1; 2699 2700 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2701 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2702 else 2703 vsyncshift = adjusted_mode->crtc_hsync_start - 2704 adjusted_mode->crtc_htotal / 2; 2705 if (vsyncshift < 0) 2706 vsyncshift += adjusted_mode->crtc_htotal; 2707 } 2708 2709 /* 2710 * VBLANK_START no longer works on ADL+, instead we must use 2711 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2712 */ 2713 if (DISPLAY_VER(dev_priv) >= 13) { 2714 intel_de_write(dev_priv, 2715 TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder), 2716 crtc_vblank_start - crtc_vdisplay); 2717 2718 /* 2719 * VBLANK_START not used by hw, just clear it 2720 * to make it stand out in register dumps. 2721 */ 2722 crtc_vblank_start = 1; 2723 } 2724 2725 if (DISPLAY_VER(dev_priv) >= 4) 2726 intel_de_write(dev_priv, 2727 TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder), 2728 vsyncshift); 2729 2730 intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), 2731 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2732 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2733 intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), 2734 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2735 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2736 intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), 2737 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2738 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2739 2740 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), 2741 VACTIVE(crtc_vdisplay - 1) | 2742 VTOTAL(crtc_vtotal - 1)); 2743 intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), 2744 VBLANK_START(crtc_vblank_start - 1) | 2745 VBLANK_END(crtc_vblank_end - 1)); 2746 intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), 2747 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2748 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2749 2750 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2751 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2752 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2753 * bits. */ 2754 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2755 (pipe == PIPE_B || pipe == PIPE_C)) 2756 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe), 2757 VACTIVE(crtc_vdisplay - 1) | 2758 VTOTAL(crtc_vtotal - 1)); 2759 } 2760 2761 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) 2762 { 2763 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2764 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2765 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2766 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2767 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2768 2769 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2770 crtc_vtotal = adjusted_mode->crtc_vtotal; 2771 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2772 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2773 2774 drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE); 2775 2776 /* 2777 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. 2778 * But let's write it anyway to keep the state checker happy. 2779 */ 2780 intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), 2781 VBLANK_START(crtc_vblank_start - 1) | 2782 VBLANK_END(crtc_vblank_end - 1)); 2783 /* 2784 * The double buffer latch point for TRANS_VTOTAL 2785 * is the transcoder's undelayed vblank. 2786 */ 2787 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), 2788 VACTIVE(crtc_vdisplay - 1) | 2789 VTOTAL(crtc_vtotal - 1)); 2790 } 2791 2792 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2793 { 2794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2795 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2796 int width = drm_rect_width(&crtc_state->pipe_src); 2797 int height = drm_rect_height(&crtc_state->pipe_src); 2798 enum pipe pipe = crtc->pipe; 2799 2800 /* pipesrc controls the size that is scaled from, which should 2801 * always be the user's requested size. 2802 */ 2803 intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), 2804 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2805 } 2806 2807 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2808 { 2809 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2810 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2811 2812 if (DISPLAY_VER(dev_priv) == 2) 2813 return false; 2814 2815 if (DISPLAY_VER(dev_priv) >= 9 || 2816 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2817 return intel_de_read(dev_priv, 2818 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2819 else 2820 return intel_de_read(dev_priv, 2821 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2822 } 2823 2824 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2825 struct intel_crtc_state *pipe_config) 2826 { 2827 struct drm_device *dev = crtc->base.dev; 2828 struct drm_i915_private *dev_priv = to_i915(dev); 2829 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2830 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2831 u32 tmp; 2832 2833 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)); 2834 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2835 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2836 2837 if (!transcoder_is_dsi(cpu_transcoder)) { 2838 tmp = intel_de_read(dev_priv, 2839 TRANS_HBLANK(dev_priv, cpu_transcoder)); 2840 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2841 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2842 } 2843 2844 tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)); 2845 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2846 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2847 2848 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); 2849 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2850 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2851 2852 /* FIXME TGL+ DSI transcoders have this! */ 2853 if (!transcoder_is_dsi(cpu_transcoder)) { 2854 tmp = intel_de_read(dev_priv, 2855 TRANS_VBLANK(dev_priv, cpu_transcoder)); 2856 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2857 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2858 } 2859 tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)); 2860 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2861 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2862 2863 if (intel_pipe_is_interlaced(pipe_config)) { 2864 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2865 adjusted_mode->crtc_vtotal += 1; 2866 adjusted_mode->crtc_vblank_end += 1; 2867 } 2868 2869 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2870 adjusted_mode->crtc_vblank_start = 2871 adjusted_mode->crtc_vdisplay + 2872 intel_de_read(dev_priv, 2873 TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder)); 2874 } 2875 2876 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2877 { 2878 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2879 int num_pipes = intel_joiner_num_pipes(crtc_state); 2880 enum pipe primary_pipe, pipe = crtc->pipe; 2881 int width; 2882 2883 if (num_pipes < 2) 2884 return; 2885 2886 primary_pipe = joiner_primary_pipe(crtc_state); 2887 width = drm_rect_width(&crtc_state->pipe_src); 2888 2889 drm_rect_translate_to(&crtc_state->pipe_src, 2890 (pipe - primary_pipe) * width, 0); 2891 } 2892 2893 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2894 struct intel_crtc_state *pipe_config) 2895 { 2896 struct drm_device *dev = crtc->base.dev; 2897 struct drm_i915_private *dev_priv = to_i915(dev); 2898 u32 tmp; 2899 2900 tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe)); 2901 2902 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2903 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2904 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2905 2906 intel_joiner_adjust_pipe_src(pipe_config); 2907 } 2908 2909 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2910 { 2911 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2913 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2914 u32 val = 0; 2915 2916 /* 2917 * - We keep both pipes enabled on 830 2918 * - During modeset the pipe is still disabled and must remain so 2919 * - During fastset the pipe is already enabled and must remain so 2920 */ 2921 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2922 val |= TRANSCONF_ENABLE; 2923 2924 if (crtc_state->double_wide) 2925 val |= TRANSCONF_DOUBLE_WIDE; 2926 2927 /* only g4x and later have fancy bpc/dither controls */ 2928 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2929 IS_CHERRYVIEW(dev_priv)) { 2930 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2931 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2932 val |= TRANSCONF_DITHER_EN | 2933 TRANSCONF_DITHER_TYPE_SP; 2934 2935 switch (crtc_state->pipe_bpp) { 2936 default: 2937 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2938 MISSING_CASE(crtc_state->pipe_bpp); 2939 fallthrough; 2940 case 18: 2941 val |= TRANSCONF_BPC_6; 2942 break; 2943 case 24: 2944 val |= TRANSCONF_BPC_8; 2945 break; 2946 case 30: 2947 val |= TRANSCONF_BPC_10; 2948 break; 2949 } 2950 } 2951 2952 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2953 if (DISPLAY_VER(dev_priv) < 4 || 2954 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2955 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2956 else 2957 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2958 } else { 2959 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2960 } 2961 2962 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2963 crtc_state->limited_color_range) 2964 val |= TRANSCONF_COLOR_RANGE_SELECT; 2965 2966 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2967 2968 if (crtc_state->wgc_enable) 2969 val |= TRANSCONF_WGC_ENABLE; 2970 2971 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2972 2973 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); 2974 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); 2975 } 2976 2977 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2978 { 2979 if (IS_I830(dev_priv)) 2980 return false; 2981 2982 return DISPLAY_VER(dev_priv) >= 4 || 2983 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2984 } 2985 2986 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2987 { 2988 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2989 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2990 enum pipe pipe; 2991 u32 tmp; 2992 2993 if (!i9xx_has_pfit(dev_priv)) 2994 return; 2995 2996 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); 2997 if (!(tmp & PFIT_ENABLE)) 2998 return; 2999 3000 /* Check whether the pfit is attached to our pipe. */ 3001 if (DISPLAY_VER(dev_priv) >= 4) 3002 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 3003 else 3004 pipe = PIPE_B; 3005 3006 if (pipe != crtc->pipe) 3007 return; 3008 3009 crtc_state->gmch_pfit.control = tmp; 3010 crtc_state->gmch_pfit.pgm_ratios = 3011 intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); 3012 } 3013 3014 static enum intel_output_format 3015 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 3016 { 3017 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3018 u32 tmp; 3019 3020 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3021 3022 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3023 /* We support 4:2:0 in full blend mode only */ 3024 drm_WARN_ON(&dev_priv->drm, 3025 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3026 3027 return INTEL_OUTPUT_FORMAT_YCBCR420; 3028 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 3029 return INTEL_OUTPUT_FORMAT_YCBCR444; 3030 } else { 3031 return INTEL_OUTPUT_FORMAT_RGB; 3032 } 3033 } 3034 3035 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3036 struct intel_crtc_state *pipe_config) 3037 { 3038 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3039 enum intel_display_power_domain power_domain; 3040 intel_wakeref_t wakeref; 3041 u32 tmp; 3042 bool ret; 3043 3044 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3045 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3046 if (!wakeref) 3047 return false; 3048 3049 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3050 pipe_config->sink_format = pipe_config->output_format; 3051 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3052 pipe_config->shared_dpll = NULL; 3053 3054 ret = false; 3055 3056 tmp = intel_de_read(dev_priv, 3057 TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); 3058 if (!(tmp & TRANSCONF_ENABLE)) 3059 goto out; 3060 3061 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3062 IS_CHERRYVIEW(dev_priv)) { 3063 switch (tmp & TRANSCONF_BPC_MASK) { 3064 case TRANSCONF_BPC_6: 3065 pipe_config->pipe_bpp = 18; 3066 break; 3067 case TRANSCONF_BPC_8: 3068 pipe_config->pipe_bpp = 24; 3069 break; 3070 case TRANSCONF_BPC_10: 3071 pipe_config->pipe_bpp = 30; 3072 break; 3073 default: 3074 MISSING_CASE(tmp); 3075 break; 3076 } 3077 } 3078 3079 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3080 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3081 pipe_config->limited_color_range = true; 3082 3083 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3084 3085 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3086 3087 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3088 (tmp & TRANSCONF_WGC_ENABLE)) 3089 pipe_config->wgc_enable = true; 3090 3091 intel_color_get_config(pipe_config); 3092 3093 if (DISPLAY_VER(dev_priv) < 4) 3094 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3095 3096 intel_get_transcoder_timings(crtc, pipe_config); 3097 intel_get_pipe_src_size(crtc, pipe_config); 3098 3099 i9xx_get_pfit_config(pipe_config); 3100 3101 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); 3102 3103 if (DISPLAY_VER(dev_priv) >= 4) { 3104 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; 3105 pipe_config->pixel_multiplier = 3106 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3107 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3108 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3109 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3110 tmp = pipe_config->dpll_hw_state.i9xx.dpll; 3111 pipe_config->pixel_multiplier = 3112 ((tmp & SDVO_MULTIPLIER_MASK) 3113 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3114 } else { 3115 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3116 * port and will be fixed up in the encoder->get_config 3117 * function. */ 3118 pipe_config->pixel_multiplier = 1; 3119 } 3120 3121 if (IS_CHERRYVIEW(dev_priv)) 3122 chv_crtc_clock_get(pipe_config); 3123 else if (IS_VALLEYVIEW(dev_priv)) 3124 vlv_crtc_clock_get(pipe_config); 3125 else 3126 i9xx_crtc_clock_get(pipe_config); 3127 3128 /* 3129 * Normally the dotclock is filled in by the encoder .get_config() 3130 * but in case the pipe is enabled w/o any ports we need a sane 3131 * default. 3132 */ 3133 pipe_config->hw.adjusted_mode.crtc_clock = 3134 pipe_config->port_clock / pipe_config->pixel_multiplier; 3135 3136 ret = true; 3137 3138 out: 3139 intel_display_power_put(dev_priv, power_domain, wakeref); 3140 3141 return ret; 3142 } 3143 3144 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3145 { 3146 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3147 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3148 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3149 u32 val = 0; 3150 3151 /* 3152 * - During modeset the pipe is still disabled and must remain so 3153 * - During fastset the pipe is already enabled and must remain so 3154 */ 3155 if (!intel_crtc_needs_modeset(crtc_state)) 3156 val |= TRANSCONF_ENABLE; 3157 3158 switch (crtc_state->pipe_bpp) { 3159 default: 3160 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3161 MISSING_CASE(crtc_state->pipe_bpp); 3162 fallthrough; 3163 case 18: 3164 val |= TRANSCONF_BPC_6; 3165 break; 3166 case 24: 3167 val |= TRANSCONF_BPC_8; 3168 break; 3169 case 30: 3170 val |= TRANSCONF_BPC_10; 3171 break; 3172 case 36: 3173 val |= TRANSCONF_BPC_12; 3174 break; 3175 } 3176 3177 if (crtc_state->dither) 3178 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3179 3180 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3181 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3182 else 3183 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3184 3185 /* 3186 * This would end up with an odd purple hue over 3187 * the entire display. Make sure we don't do it. 3188 */ 3189 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3190 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3191 3192 if (crtc_state->limited_color_range && 3193 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3194 val |= TRANSCONF_COLOR_RANGE_SELECT; 3195 3196 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3197 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3198 3199 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3200 3201 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3202 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3203 3204 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); 3205 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); 3206 } 3207 3208 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3209 { 3210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3212 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3213 u32 val = 0; 3214 3215 /* 3216 * - During modeset the pipe is still disabled and must remain so 3217 * - During fastset the pipe is already enabled and must remain so 3218 */ 3219 if (!intel_crtc_needs_modeset(crtc_state)) 3220 val |= TRANSCONF_ENABLE; 3221 3222 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3223 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3224 3225 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3226 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3227 else 3228 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3229 3230 if (IS_HASWELL(dev_priv) && 3231 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3232 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3233 3234 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); 3235 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); 3236 } 3237 3238 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3239 { 3240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3242 u32 val = 0; 3243 3244 switch (crtc_state->pipe_bpp) { 3245 case 18: 3246 val |= PIPE_MISC_BPC_6; 3247 break; 3248 case 24: 3249 val |= PIPE_MISC_BPC_8; 3250 break; 3251 case 30: 3252 val |= PIPE_MISC_BPC_10; 3253 break; 3254 case 36: 3255 /* Port output 12BPC defined for ADLP+ */ 3256 if (DISPLAY_VER(dev_priv) >= 13) 3257 val |= PIPE_MISC_BPC_12_ADLP; 3258 break; 3259 default: 3260 MISSING_CASE(crtc_state->pipe_bpp); 3261 break; 3262 } 3263 3264 if (crtc_state->dither) 3265 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3266 3267 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3268 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3269 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3270 3271 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3272 val |= PIPE_MISC_YUV420_ENABLE | 3273 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3274 3275 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3276 val |= PIPE_MISC_HDR_MODE_PRECISION; 3277 3278 if (DISPLAY_VER(dev_priv) >= 12) 3279 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3280 3281 /* allow PSR with sprite enabled */ 3282 if (IS_BROADWELL(dev_priv)) 3283 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3284 3285 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3286 } 3287 3288 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3289 { 3290 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3291 u32 tmp; 3292 3293 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3294 3295 switch (tmp & PIPE_MISC_BPC_MASK) { 3296 case PIPE_MISC_BPC_6: 3297 return 18; 3298 case PIPE_MISC_BPC_8: 3299 return 24; 3300 case PIPE_MISC_BPC_10: 3301 return 30; 3302 /* 3303 * PORT OUTPUT 12 BPC defined for ADLP+. 3304 * 3305 * TODO: 3306 * For previous platforms with DSI interface, bits 5:7 3307 * are used for storing pipe_bpp irrespective of dithering. 3308 * Since the value of 12 BPC is not defined for these bits 3309 * on older platforms, need to find a workaround for 12 BPC 3310 * MIPI DSI HW readout. 3311 */ 3312 case PIPE_MISC_BPC_12_ADLP: 3313 if (DISPLAY_VER(dev_priv) >= 13) 3314 return 36; 3315 fallthrough; 3316 default: 3317 MISSING_CASE(tmp); 3318 return 0; 3319 } 3320 } 3321 3322 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3323 { 3324 /* 3325 * Account for spread spectrum to avoid 3326 * oversubscribing the link. Max center spread 3327 * is 2.5%; use 5% for safety's sake. 3328 */ 3329 u32 bps = target_clock * bpp * 21 / 20; 3330 return DIV_ROUND_UP(bps, link_bw * 8); 3331 } 3332 3333 void intel_get_m_n(struct drm_i915_private *i915, 3334 struct intel_link_m_n *m_n, 3335 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3336 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3337 { 3338 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3339 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3340 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3341 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3342 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3343 } 3344 3345 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3346 enum transcoder transcoder, 3347 struct intel_link_m_n *m_n) 3348 { 3349 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3350 enum pipe pipe = crtc->pipe; 3351 3352 if (DISPLAY_VER(dev_priv) >= 5) 3353 intel_get_m_n(dev_priv, m_n, 3354 PIPE_DATA_M1(dev_priv, transcoder), 3355 PIPE_DATA_N1(dev_priv, transcoder), 3356 PIPE_LINK_M1(dev_priv, transcoder), 3357 PIPE_LINK_N1(dev_priv, transcoder)); 3358 else 3359 intel_get_m_n(dev_priv, m_n, 3360 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3361 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3362 } 3363 3364 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3365 enum transcoder transcoder, 3366 struct intel_link_m_n *m_n) 3367 { 3368 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3369 3370 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3371 return; 3372 3373 intel_get_m_n(dev_priv, m_n, 3374 PIPE_DATA_M2(dev_priv, transcoder), 3375 PIPE_DATA_N2(dev_priv, transcoder), 3376 PIPE_LINK_M2(dev_priv, transcoder), 3377 PIPE_LINK_N2(dev_priv, transcoder)); 3378 } 3379 3380 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3381 { 3382 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3384 u32 ctl, pos, size; 3385 enum pipe pipe; 3386 3387 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3388 if ((ctl & PF_ENABLE) == 0) 3389 return; 3390 3391 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3392 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3393 else 3394 pipe = crtc->pipe; 3395 3396 crtc_state->pch_pfit.enabled = true; 3397 3398 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3399 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3400 3401 drm_rect_init(&crtc_state->pch_pfit.dst, 3402 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), 3403 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), 3404 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), 3405 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); 3406 3407 /* 3408 * We currently do not free assignements of panel fitters on 3409 * ivb/hsw (since we don't use the higher upscaling modes which 3410 * differentiates them) so just WARN about this case for now. 3411 */ 3412 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3413 } 3414 3415 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3416 struct intel_crtc_state *pipe_config) 3417 { 3418 struct drm_device *dev = crtc->base.dev; 3419 struct drm_i915_private *dev_priv = to_i915(dev); 3420 enum intel_display_power_domain power_domain; 3421 intel_wakeref_t wakeref; 3422 u32 tmp; 3423 bool ret; 3424 3425 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3426 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3427 if (!wakeref) 3428 return false; 3429 3430 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3431 pipe_config->shared_dpll = NULL; 3432 3433 ret = false; 3434 tmp = intel_de_read(dev_priv, 3435 TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); 3436 if (!(tmp & TRANSCONF_ENABLE)) 3437 goto out; 3438 3439 switch (tmp & TRANSCONF_BPC_MASK) { 3440 case TRANSCONF_BPC_6: 3441 pipe_config->pipe_bpp = 18; 3442 break; 3443 case TRANSCONF_BPC_8: 3444 pipe_config->pipe_bpp = 24; 3445 break; 3446 case TRANSCONF_BPC_10: 3447 pipe_config->pipe_bpp = 30; 3448 break; 3449 case TRANSCONF_BPC_12: 3450 pipe_config->pipe_bpp = 36; 3451 break; 3452 default: 3453 break; 3454 } 3455 3456 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3457 pipe_config->limited_color_range = true; 3458 3459 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3460 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3461 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3462 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3463 break; 3464 default: 3465 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3466 break; 3467 } 3468 3469 pipe_config->sink_format = pipe_config->output_format; 3470 3471 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3472 3473 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3474 3475 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3476 3477 intel_color_get_config(pipe_config); 3478 3479 pipe_config->pixel_multiplier = 1; 3480 3481 ilk_pch_get_config(pipe_config); 3482 3483 intel_get_transcoder_timings(crtc, pipe_config); 3484 intel_get_pipe_src_size(crtc, pipe_config); 3485 3486 ilk_get_pfit_config(pipe_config); 3487 3488 ret = true; 3489 3490 out: 3491 intel_display_power_put(dev_priv, power_domain, wakeref); 3492 3493 return ret; 3494 } 3495 3496 static u8 joiner_pipes(struct drm_i915_private *i915) 3497 { 3498 u8 pipes; 3499 3500 if (DISPLAY_VER(i915) >= 12) 3501 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3502 else if (DISPLAY_VER(i915) >= 11) 3503 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3504 else 3505 pipes = 0; 3506 3507 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; 3508 } 3509 3510 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3511 enum transcoder cpu_transcoder) 3512 { 3513 enum intel_display_power_domain power_domain; 3514 intel_wakeref_t wakeref; 3515 u32 tmp = 0; 3516 3517 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3518 3519 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3520 tmp = intel_de_read(dev_priv, 3521 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3522 3523 return tmp & TRANS_DDI_FUNC_ENABLE; 3524 } 3525 3526 static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, 3527 u8 *primary_pipes, u8 *secondary_pipes) 3528 { 3529 struct intel_crtc *crtc; 3530 3531 *primary_pipes = 0; 3532 *secondary_pipes = 0; 3533 3534 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3535 joiner_pipes(dev_priv)) { 3536 enum intel_display_power_domain power_domain; 3537 enum pipe pipe = crtc->pipe; 3538 intel_wakeref_t wakeref; 3539 3540 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3541 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3542 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3543 3544 if (!(tmp & BIG_JOINER_ENABLE)) 3545 continue; 3546 3547 if (tmp & PRIMARY_BIG_JOINER_ENABLE) 3548 *primary_pipes |= BIT(pipe); 3549 else 3550 *secondary_pipes |= BIT(pipe); 3551 } 3552 3553 if (DISPLAY_VER(dev_priv) < 13) 3554 continue; 3555 3556 power_domain = POWER_DOMAIN_PIPE(pipe); 3557 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3558 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3559 3560 if (tmp & UNCOMPRESSED_JOINER_PRIMARY) 3561 *primary_pipes |= BIT(pipe); 3562 if (tmp & UNCOMPRESSED_JOINER_SECONDARY) 3563 *secondary_pipes |= BIT(pipe); 3564 } 3565 } 3566 3567 /* Joiner pipes should always be consecutive primary and secondary */ 3568 drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1, 3569 "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n", 3570 *primary_pipes, *secondary_pipes); 3571 } 3572 3573 static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) 3574 { 3575 if ((secondary_pipes & BIT(pipe)) == 0) 3576 return pipe; 3577 3578 /* ignore everything above our pipe */ 3579 primary_pipes &= ~GENMASK(7, pipe); 3580 3581 /* highest remaining bit should be our primary pipe */ 3582 return fls(primary_pipes) - 1; 3583 } 3584 3585 static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) 3586 { 3587 enum pipe primary_pipe, next_primary_pipe; 3588 3589 primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes); 3590 3591 if ((primary_pipes & BIT(primary_pipe)) == 0) 3592 return 0; 3593 3594 /* ignore our primary pipe and everything below it */ 3595 primary_pipes &= ~GENMASK(primary_pipe, 0); 3596 /* make sure a high bit is set for the ffs() */ 3597 primary_pipes |= BIT(7); 3598 /* lowest remaining bit should be the next primary pipe */ 3599 next_primary_pipe = ffs(primary_pipes) - 1; 3600 3601 return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe); 3602 } 3603 3604 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3605 { 3606 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3607 3608 if (DISPLAY_VER(i915) >= 11) 3609 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3610 3611 return panel_transcoder_mask; 3612 } 3613 3614 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3615 { 3616 struct drm_device *dev = crtc->base.dev; 3617 struct drm_i915_private *dev_priv = to_i915(dev); 3618 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3619 enum transcoder cpu_transcoder; 3620 u8 primary_pipes, secondary_pipes; 3621 u8 enabled_transcoders = 0; 3622 3623 /* 3624 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3625 * consistency and less surprising code; it's in always on power). 3626 */ 3627 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3628 panel_transcoder_mask) { 3629 enum intel_display_power_domain power_domain; 3630 intel_wakeref_t wakeref; 3631 enum pipe trans_pipe; 3632 u32 tmp = 0; 3633 3634 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3635 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3636 tmp = intel_de_read(dev_priv, 3637 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3638 3639 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3640 continue; 3641 3642 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3643 default: 3644 drm_WARN(dev, 1, 3645 "unknown pipe linked to transcoder %s\n", 3646 transcoder_name(cpu_transcoder)); 3647 fallthrough; 3648 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3649 case TRANS_DDI_EDP_INPUT_A_ON: 3650 trans_pipe = PIPE_A; 3651 break; 3652 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3653 trans_pipe = PIPE_B; 3654 break; 3655 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3656 trans_pipe = PIPE_C; 3657 break; 3658 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3659 trans_pipe = PIPE_D; 3660 break; 3661 } 3662 3663 if (trans_pipe == crtc->pipe) 3664 enabled_transcoders |= BIT(cpu_transcoder); 3665 } 3666 3667 /* single pipe or joiner primary */ 3668 cpu_transcoder = (enum transcoder) crtc->pipe; 3669 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3670 enabled_transcoders |= BIT(cpu_transcoder); 3671 3672 /* joiner secondary -> consider the primary pipe's transcoder as well */ 3673 enabled_joiner_pipes(dev_priv, &primary_pipes, &secondary_pipes); 3674 if (secondary_pipes & BIT(crtc->pipe)) { 3675 cpu_transcoder = (enum transcoder) 3676 get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes); 3677 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3678 enabled_transcoders |= BIT(cpu_transcoder); 3679 } 3680 3681 return enabled_transcoders; 3682 } 3683 3684 static bool has_edp_transcoders(u8 enabled_transcoders) 3685 { 3686 return enabled_transcoders & BIT(TRANSCODER_EDP); 3687 } 3688 3689 static bool has_dsi_transcoders(u8 enabled_transcoders) 3690 { 3691 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3692 BIT(TRANSCODER_DSI_1)); 3693 } 3694 3695 static bool has_pipe_transcoders(u8 enabled_transcoders) 3696 { 3697 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3698 BIT(TRANSCODER_DSI_0) | 3699 BIT(TRANSCODER_DSI_1)); 3700 } 3701 3702 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3703 u8 enabled_transcoders) 3704 { 3705 /* Only one type of transcoder please */ 3706 drm_WARN_ON(&i915->drm, 3707 has_edp_transcoders(enabled_transcoders) + 3708 has_dsi_transcoders(enabled_transcoders) + 3709 has_pipe_transcoders(enabled_transcoders) > 1); 3710 3711 /* Only DSI transcoders can be ganged */ 3712 drm_WARN_ON(&i915->drm, 3713 !has_dsi_transcoders(enabled_transcoders) && 3714 !is_power_of_2(enabled_transcoders)); 3715 } 3716 3717 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3718 struct intel_crtc_state *pipe_config, 3719 struct intel_display_power_domain_set *power_domain_set) 3720 { 3721 struct drm_device *dev = crtc->base.dev; 3722 struct drm_i915_private *dev_priv = to_i915(dev); 3723 unsigned long enabled_transcoders; 3724 u32 tmp; 3725 3726 enabled_transcoders = hsw_enabled_transcoders(crtc); 3727 if (!enabled_transcoders) 3728 return false; 3729 3730 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3731 3732 /* 3733 * With the exception of DSI we should only ever have 3734 * a single enabled transcoder. With DSI let's just 3735 * pick the first one. 3736 */ 3737 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3738 3739 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3740 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3741 return false; 3742 3743 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3744 tmp = intel_de_read(dev_priv, 3745 TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder)); 3746 3747 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3748 pipe_config->pch_pfit.force_thru = true; 3749 } 3750 3751 tmp = intel_de_read(dev_priv, 3752 TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); 3753 3754 return tmp & TRANSCONF_ENABLE; 3755 } 3756 3757 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3758 struct intel_crtc_state *pipe_config, 3759 struct intel_display_power_domain_set *power_domain_set) 3760 { 3761 struct intel_display *display = to_intel_display(crtc); 3762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3763 enum transcoder cpu_transcoder; 3764 enum port port; 3765 u32 tmp; 3766 3767 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3768 if (port == PORT_A) 3769 cpu_transcoder = TRANSCODER_DSI_A; 3770 else 3771 cpu_transcoder = TRANSCODER_DSI_C; 3772 3773 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3774 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3775 continue; 3776 3777 /* 3778 * The PLL needs to be enabled with a valid divider 3779 * configuration, otherwise accessing DSI registers will hang 3780 * the machine. See BSpec North Display Engine 3781 * registers/MIPI[BXT]. We can break out here early, since we 3782 * need the same DSI PLL to be enabled for both DSI ports. 3783 */ 3784 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3785 break; 3786 3787 /* XXX: this works for video mode only */ 3788 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); 3789 if (!(tmp & DPI_ENABLE)) 3790 continue; 3791 3792 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 3793 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3794 continue; 3795 3796 pipe_config->cpu_transcoder = cpu_transcoder; 3797 break; 3798 } 3799 3800 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3801 } 3802 3803 static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) 3804 { 3805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3806 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3807 u8 primary_pipes, secondary_pipes; 3808 enum pipe pipe = crtc->pipe; 3809 3810 enabled_joiner_pipes(i915, &primary_pipes, &secondary_pipes); 3811 3812 if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0) 3813 return; 3814 3815 crtc_state->joiner_pipes = 3816 BIT(get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes)) | 3817 get_joiner_secondary_pipes(pipe, primary_pipes, secondary_pipes); 3818 } 3819 3820 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3821 struct intel_crtc_state *pipe_config) 3822 { 3823 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3824 bool active; 3825 u32 tmp; 3826 3827 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3828 POWER_DOMAIN_PIPE(crtc->pipe))) 3829 return false; 3830 3831 pipe_config->shared_dpll = NULL; 3832 3833 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3834 3835 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3836 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3837 drm_WARN_ON(&dev_priv->drm, active); 3838 active = true; 3839 } 3840 3841 if (!active) 3842 goto out; 3843 3844 intel_joiner_get_config(pipe_config); 3845 intel_dsc_get_config(pipe_config); 3846 3847 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3848 DISPLAY_VER(dev_priv) >= 11) 3849 intel_get_transcoder_timings(crtc, pipe_config); 3850 3851 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3852 intel_vrr_get_config(pipe_config); 3853 3854 intel_get_pipe_src_size(crtc, pipe_config); 3855 3856 if (IS_HASWELL(dev_priv)) { 3857 u32 tmp = intel_de_read(dev_priv, 3858 TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); 3859 3860 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3861 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3862 else 3863 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3864 } else { 3865 pipe_config->output_format = 3866 bdw_get_pipe_misc_output_format(crtc); 3867 } 3868 3869 pipe_config->sink_format = pipe_config->output_format; 3870 3871 intel_color_get_config(pipe_config); 3872 3873 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3874 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3875 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3876 pipe_config->ips_linetime = 3877 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3878 3879 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3880 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3881 if (DISPLAY_VER(dev_priv) >= 9) 3882 skl_scaler_get_config(pipe_config); 3883 else 3884 ilk_get_pfit_config(pipe_config); 3885 } 3886 3887 hsw_ips_get_config(pipe_config); 3888 3889 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3890 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3891 pipe_config->pixel_multiplier = 3892 intel_de_read(dev_priv, 3893 TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1; 3894 } else { 3895 pipe_config->pixel_multiplier = 1; 3896 } 3897 3898 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3899 tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder)); 3900 3901 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3902 } else { 3903 /* no idea if this is correct */ 3904 pipe_config->framestart_delay = 1; 3905 } 3906 3907 out: 3908 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3909 3910 return active; 3911 } 3912 3913 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3914 { 3915 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3916 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3917 3918 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3919 return false; 3920 3921 crtc_state->hw.active = true; 3922 3923 intel_crtc_readout_derived_state(crtc_state); 3924 3925 return true; 3926 } 3927 3928 int intel_dotclock_calculate(int link_freq, 3929 const struct intel_link_m_n *m_n) 3930 { 3931 /* 3932 * The calculation for the data clock -> pixel clock is: 3933 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3934 * But we want to avoid losing precison if possible, so: 3935 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3936 * 3937 * and for link freq (10kbs units) -> pixel clock it is: 3938 * link_symbol_clock = link_freq * 10 / link_symbol_size 3939 * pixel_clock = (m * link_symbol_clock) / n 3940 * or for more precision: 3941 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) 3942 */ 3943 3944 if (!m_n->link_n) 3945 return 0; 3946 3947 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), 3948 m_n->link_n * intel_dp_link_symbol_size(link_freq)); 3949 } 3950 3951 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3952 { 3953 int dotclock; 3954 3955 if (intel_crtc_has_dp_encoder(pipe_config)) 3956 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3957 &pipe_config->dp_m_n); 3958 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3959 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3960 pipe_config->pipe_bpp); 3961 else 3962 dotclock = pipe_config->port_clock; 3963 3964 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3965 !intel_crtc_has_dp_encoder(pipe_config)) 3966 dotclock *= 2; 3967 3968 if (pipe_config->pixel_multiplier) 3969 dotclock /= pipe_config->pixel_multiplier; 3970 3971 return dotclock; 3972 } 3973 3974 /* Returns the currently programmed mode of the given encoder. */ 3975 struct drm_display_mode * 3976 intel_encoder_current_mode(struct intel_encoder *encoder) 3977 { 3978 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3979 struct intel_crtc_state *crtc_state; 3980 struct drm_display_mode *mode; 3981 struct intel_crtc *crtc; 3982 enum pipe pipe; 3983 3984 if (!encoder->get_hw_state(encoder, &pipe)) 3985 return NULL; 3986 3987 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3988 3989 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3990 if (!mode) 3991 return NULL; 3992 3993 crtc_state = intel_crtc_state_alloc(crtc); 3994 if (!crtc_state) { 3995 kfree(mode); 3996 return NULL; 3997 } 3998 3999 if (!intel_crtc_get_pipe_config(crtc_state)) { 4000 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4001 kfree(mode); 4002 return NULL; 4003 } 4004 4005 intel_encoder_get_config(encoder, crtc_state); 4006 4007 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4008 4009 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4010 4011 return mode; 4012 } 4013 4014 static bool encoders_cloneable(const struct intel_encoder *a, 4015 const struct intel_encoder *b) 4016 { 4017 /* masks could be asymmetric, so check both ways */ 4018 return a == b || (a->cloneable & BIT(b->type) && 4019 b->cloneable & BIT(a->type)); 4020 } 4021 4022 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4023 struct intel_crtc *crtc, 4024 struct intel_encoder *encoder) 4025 { 4026 struct intel_encoder *source_encoder; 4027 struct drm_connector *connector; 4028 struct drm_connector_state *connector_state; 4029 int i; 4030 4031 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4032 if (connector_state->crtc != &crtc->base) 4033 continue; 4034 4035 source_encoder = 4036 to_intel_encoder(connector_state->best_encoder); 4037 if (!encoders_cloneable(encoder, source_encoder)) 4038 return false; 4039 } 4040 4041 return true; 4042 } 4043 4044 static int icl_add_linked_planes(struct intel_atomic_state *state) 4045 { 4046 struct intel_plane *plane, *linked; 4047 struct intel_plane_state *plane_state, *linked_plane_state; 4048 int i; 4049 4050 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4051 linked = plane_state->planar_linked_plane; 4052 4053 if (!linked) 4054 continue; 4055 4056 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4057 if (IS_ERR(linked_plane_state)) 4058 return PTR_ERR(linked_plane_state); 4059 4060 drm_WARN_ON(state->base.dev, 4061 linked_plane_state->planar_linked_plane != plane); 4062 drm_WARN_ON(state->base.dev, 4063 linked_plane_state->planar_slave == plane_state->planar_slave); 4064 } 4065 4066 return 0; 4067 } 4068 4069 static int icl_check_nv12_planes(struct intel_atomic_state *state, 4070 struct intel_crtc *crtc) 4071 { 4072 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4073 struct intel_crtc_state *crtc_state = 4074 intel_atomic_get_new_crtc_state(state, crtc); 4075 struct intel_plane *plane, *linked; 4076 struct intel_plane_state *plane_state; 4077 int i; 4078 4079 if (DISPLAY_VER(dev_priv) < 11) 4080 return 0; 4081 4082 /* 4083 * Destroy all old plane links and make the slave plane invisible 4084 * in the crtc_state->active_planes mask. 4085 */ 4086 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4087 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4088 continue; 4089 4090 plane_state->planar_linked_plane = NULL; 4091 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4092 crtc_state->enabled_planes &= ~BIT(plane->id); 4093 crtc_state->active_planes &= ~BIT(plane->id); 4094 crtc_state->update_planes |= BIT(plane->id); 4095 crtc_state->data_rate[plane->id] = 0; 4096 crtc_state->rel_data_rate[plane->id] = 0; 4097 } 4098 4099 plane_state->planar_slave = false; 4100 } 4101 4102 if (!crtc_state->nv12_planes) 4103 return 0; 4104 4105 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4106 struct intel_plane_state *linked_state = NULL; 4107 4108 if (plane->pipe != crtc->pipe || 4109 !(crtc_state->nv12_planes & BIT(plane->id))) 4110 continue; 4111 4112 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4113 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4114 continue; 4115 4116 if (crtc_state->active_planes & BIT(linked->id)) 4117 continue; 4118 4119 linked_state = intel_atomic_get_plane_state(state, linked); 4120 if (IS_ERR(linked_state)) 4121 return PTR_ERR(linked_state); 4122 4123 break; 4124 } 4125 4126 if (!linked_state) { 4127 drm_dbg_kms(&dev_priv->drm, 4128 "Need %d free Y planes for planar YUV\n", 4129 hweight8(crtc_state->nv12_planes)); 4130 4131 return -EINVAL; 4132 } 4133 4134 plane_state->planar_linked_plane = linked; 4135 4136 linked_state->planar_slave = true; 4137 linked_state->planar_linked_plane = plane; 4138 crtc_state->enabled_planes |= BIT(linked->id); 4139 crtc_state->active_planes |= BIT(linked->id); 4140 crtc_state->update_planes |= BIT(linked->id); 4141 crtc_state->data_rate[linked->id] = 4142 crtc_state->data_rate_y[plane->id]; 4143 crtc_state->rel_data_rate[linked->id] = 4144 crtc_state->rel_data_rate_y[plane->id]; 4145 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4146 linked->base.name, plane->base.name); 4147 4148 /* Copy parameters to slave plane */ 4149 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4150 linked_state->color_ctl = plane_state->color_ctl; 4151 linked_state->view = plane_state->view; 4152 linked_state->decrypt = plane_state->decrypt; 4153 4154 intel_plane_copy_hw_state(linked_state, plane_state); 4155 linked_state->uapi.src = plane_state->uapi.src; 4156 linked_state->uapi.dst = plane_state->uapi.dst; 4157 4158 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4159 if (linked->id == PLANE_7) 4160 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4161 else if (linked->id == PLANE_6) 4162 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4163 else if (linked->id == PLANE_5) 4164 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4165 else if (linked->id == PLANE_4) 4166 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4167 else 4168 MISSING_CASE(linked->id); 4169 } 4170 } 4171 4172 return 0; 4173 } 4174 4175 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4176 { 4177 const struct drm_display_mode *pipe_mode = 4178 &crtc_state->hw.pipe_mode; 4179 int linetime_wm; 4180 4181 if (!crtc_state->hw.enable) 4182 return 0; 4183 4184 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4185 pipe_mode->crtc_clock); 4186 4187 return min(linetime_wm, 0x1ff); 4188 } 4189 4190 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4191 const struct intel_cdclk_state *cdclk_state) 4192 { 4193 const struct drm_display_mode *pipe_mode = 4194 &crtc_state->hw.pipe_mode; 4195 int linetime_wm; 4196 4197 if (!crtc_state->hw.enable) 4198 return 0; 4199 4200 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4201 cdclk_state->logical.cdclk); 4202 4203 return min(linetime_wm, 0x1ff); 4204 } 4205 4206 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4207 { 4208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4210 const struct drm_display_mode *pipe_mode = 4211 &crtc_state->hw.pipe_mode; 4212 int linetime_wm; 4213 4214 if (!crtc_state->hw.enable) 4215 return 0; 4216 4217 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4218 crtc_state->pixel_rate); 4219 4220 /* Display WA #1135: BXT:ALL GLK:ALL */ 4221 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4222 skl_watermark_ipc_enabled(dev_priv)) 4223 linetime_wm /= 2; 4224 4225 return min(linetime_wm, 0x1ff); 4226 } 4227 4228 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4229 struct intel_crtc *crtc) 4230 { 4231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4232 struct intel_crtc_state *crtc_state = 4233 intel_atomic_get_new_crtc_state(state, crtc); 4234 const struct intel_cdclk_state *cdclk_state; 4235 4236 if (DISPLAY_VER(dev_priv) >= 9) 4237 crtc_state->linetime = skl_linetime_wm(crtc_state); 4238 else 4239 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4240 4241 if (!hsw_crtc_supports_ips(crtc)) 4242 return 0; 4243 4244 cdclk_state = intel_atomic_get_cdclk_state(state); 4245 if (IS_ERR(cdclk_state)) 4246 return PTR_ERR(cdclk_state); 4247 4248 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4249 cdclk_state); 4250 4251 return 0; 4252 } 4253 4254 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4255 struct intel_crtc *crtc) 4256 { 4257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4258 struct intel_crtc_state *crtc_state = 4259 intel_atomic_get_new_crtc_state(state, crtc); 4260 int ret; 4261 4262 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4263 intel_crtc_needs_modeset(crtc_state) && 4264 !crtc_state->hw.active) 4265 crtc_state->update_wm_post = true; 4266 4267 if (intel_crtc_needs_modeset(crtc_state)) { 4268 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4269 if (ret) 4270 return ret; 4271 } 4272 4273 ret = intel_color_check(state, crtc); 4274 if (ret) 4275 return ret; 4276 4277 ret = intel_compute_pipe_wm(state, crtc); 4278 if (ret) { 4279 drm_dbg_kms(&dev_priv->drm, 4280 "Target pipe watermarks are invalid\n"); 4281 return ret; 4282 } 4283 4284 /* 4285 * Calculate 'intermediate' watermarks that satisfy both the 4286 * old state and the new state. We can program these 4287 * immediately. 4288 */ 4289 ret = intel_compute_intermediate_wm(state, crtc); 4290 if (ret) { 4291 drm_dbg_kms(&dev_priv->drm, 4292 "No valid intermediate pipe watermarks are possible\n"); 4293 return ret; 4294 } 4295 4296 if (DISPLAY_VER(dev_priv) >= 9) { 4297 if (intel_crtc_needs_modeset(crtc_state) || 4298 intel_crtc_needs_fastset(crtc_state)) { 4299 ret = skl_update_scaler_crtc(crtc_state); 4300 if (ret) 4301 return ret; 4302 } 4303 4304 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4305 if (ret) 4306 return ret; 4307 } 4308 4309 if (HAS_IPS(dev_priv)) { 4310 ret = hsw_ips_compute_config(state, crtc); 4311 if (ret) 4312 return ret; 4313 } 4314 4315 if (DISPLAY_VER(dev_priv) >= 9 || 4316 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4317 ret = hsw_compute_linetime_wm(state, crtc); 4318 if (ret) 4319 return ret; 4320 4321 } 4322 4323 ret = intel_psr2_sel_fetch_update(state, crtc); 4324 if (ret) 4325 return ret; 4326 4327 return 0; 4328 } 4329 4330 static int 4331 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4332 struct intel_crtc_state *crtc_state) 4333 { 4334 struct drm_connector *connector = conn_state->connector; 4335 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4336 const struct drm_display_info *info = &connector->display_info; 4337 int bpp; 4338 4339 switch (conn_state->max_bpc) { 4340 case 6 ... 7: 4341 bpp = 6 * 3; 4342 break; 4343 case 8 ... 9: 4344 bpp = 8 * 3; 4345 break; 4346 case 10 ... 11: 4347 bpp = 10 * 3; 4348 break; 4349 case 12 ... 16: 4350 bpp = 12 * 3; 4351 break; 4352 default: 4353 MISSING_CASE(conn_state->max_bpc); 4354 return -EINVAL; 4355 } 4356 4357 if (bpp < crtc_state->pipe_bpp) { 4358 drm_dbg_kms(&i915->drm, 4359 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4360 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4361 connector->base.id, connector->name, 4362 bpp, 3 * info->bpc, 4363 3 * conn_state->max_requested_bpc, 4364 crtc_state->pipe_bpp); 4365 4366 crtc_state->pipe_bpp = bpp; 4367 } 4368 4369 return 0; 4370 } 4371 4372 static int 4373 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4374 struct intel_crtc *crtc) 4375 { 4376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4377 struct intel_crtc_state *crtc_state = 4378 intel_atomic_get_new_crtc_state(state, crtc); 4379 struct drm_connector *connector; 4380 struct drm_connector_state *connector_state; 4381 int bpp, i; 4382 4383 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4384 IS_CHERRYVIEW(dev_priv))) 4385 bpp = 10*3; 4386 else if (DISPLAY_VER(dev_priv) >= 5) 4387 bpp = 12*3; 4388 else 4389 bpp = 8*3; 4390 4391 crtc_state->pipe_bpp = bpp; 4392 4393 /* Clamp display bpp to connector max bpp */ 4394 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4395 int ret; 4396 4397 if (connector_state->crtc != &crtc->base) 4398 continue; 4399 4400 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4401 if (ret) 4402 return ret; 4403 } 4404 4405 return 0; 4406 } 4407 4408 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4409 { 4410 struct drm_device *dev = state->base.dev; 4411 struct drm_connector *connector; 4412 struct drm_connector_list_iter conn_iter; 4413 unsigned int used_ports = 0; 4414 unsigned int used_mst_ports = 0; 4415 bool ret = true; 4416 4417 /* 4418 * We're going to peek into connector->state, 4419 * hence connection_mutex must be held. 4420 */ 4421 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4422 4423 /* 4424 * Walk the connector list instead of the encoder 4425 * list to detect the problem on ddi platforms 4426 * where there's just one encoder per digital port. 4427 */ 4428 drm_connector_list_iter_begin(dev, &conn_iter); 4429 drm_for_each_connector_iter(connector, &conn_iter) { 4430 struct drm_connector_state *connector_state; 4431 struct intel_encoder *encoder; 4432 4433 connector_state = 4434 drm_atomic_get_new_connector_state(&state->base, 4435 connector); 4436 if (!connector_state) 4437 connector_state = connector->state; 4438 4439 if (!connector_state->best_encoder) 4440 continue; 4441 4442 encoder = to_intel_encoder(connector_state->best_encoder); 4443 4444 drm_WARN_ON(dev, !connector_state->crtc); 4445 4446 switch (encoder->type) { 4447 case INTEL_OUTPUT_DDI: 4448 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4449 break; 4450 fallthrough; 4451 case INTEL_OUTPUT_DP: 4452 case INTEL_OUTPUT_HDMI: 4453 case INTEL_OUTPUT_EDP: 4454 /* the same port mustn't appear more than once */ 4455 if (used_ports & BIT(encoder->port)) 4456 ret = false; 4457 4458 used_ports |= BIT(encoder->port); 4459 break; 4460 case INTEL_OUTPUT_DP_MST: 4461 used_mst_ports |= 4462 1 << encoder->port; 4463 break; 4464 default: 4465 break; 4466 } 4467 } 4468 drm_connector_list_iter_end(&conn_iter); 4469 4470 /* can't mix MST and SST/HDMI on the same port */ 4471 if (used_ports & used_mst_ports) 4472 return false; 4473 4474 return ret; 4475 } 4476 4477 static void 4478 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4479 struct intel_crtc *crtc) 4480 { 4481 struct intel_crtc_state *crtc_state = 4482 intel_atomic_get_new_crtc_state(state, crtc); 4483 4484 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4485 4486 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4487 crtc_state->uapi.degamma_lut); 4488 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4489 crtc_state->uapi.gamma_lut); 4490 drm_property_replace_blob(&crtc_state->hw.ctm, 4491 crtc_state->uapi.ctm); 4492 } 4493 4494 static void 4495 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4496 struct intel_crtc *crtc) 4497 { 4498 struct intel_crtc_state *crtc_state = 4499 intel_atomic_get_new_crtc_state(state, crtc); 4500 4501 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4502 4503 crtc_state->hw.enable = crtc_state->uapi.enable; 4504 crtc_state->hw.active = crtc_state->uapi.active; 4505 drm_mode_copy(&crtc_state->hw.mode, 4506 &crtc_state->uapi.mode); 4507 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4508 &crtc_state->uapi.adjusted_mode); 4509 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4510 4511 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4512 } 4513 4514 static void 4515 copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4516 struct intel_crtc *secondary_crtc) 4517 { 4518 struct intel_crtc_state *secondary_crtc_state = 4519 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4520 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4521 const struct intel_crtc_state *primary_crtc_state = 4522 intel_atomic_get_new_crtc_state(state, primary_crtc); 4523 4524 drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut, 4525 primary_crtc_state->hw.degamma_lut); 4526 drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut, 4527 primary_crtc_state->hw.gamma_lut); 4528 drm_property_replace_blob(&secondary_crtc_state->hw.ctm, 4529 primary_crtc_state->hw.ctm); 4530 4531 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed; 4532 } 4533 4534 static int 4535 copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, 4536 struct intel_crtc *secondary_crtc) 4537 { 4538 struct intel_crtc_state *secondary_crtc_state = 4539 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4540 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4541 const struct intel_crtc_state *primary_crtc_state = 4542 intel_atomic_get_new_crtc_state(state, primary_crtc); 4543 struct intel_crtc_state *saved_state; 4544 4545 WARN_ON(primary_crtc_state->joiner_pipes != 4546 secondary_crtc_state->joiner_pipes); 4547 4548 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4549 if (!saved_state) 4550 return -ENOMEM; 4551 4552 /* preserve some things from the slave's original crtc state */ 4553 saved_state->uapi = secondary_crtc_state->uapi; 4554 saved_state->scaler_state = secondary_crtc_state->scaler_state; 4555 saved_state->shared_dpll = secondary_crtc_state->shared_dpll; 4556 saved_state->crc_enabled = secondary_crtc_state->crc_enabled; 4557 4558 intel_crtc_free_hw_state(secondary_crtc_state); 4559 if (secondary_crtc_state->dp_tunnel_ref.tunnel) 4560 drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref); 4561 memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state)); 4562 kfree(saved_state); 4563 4564 /* Re-init hw state */ 4565 memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw)); 4566 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable; 4567 secondary_crtc_state->hw.active = primary_crtc_state->hw.active; 4568 drm_mode_copy(&secondary_crtc_state->hw.mode, 4569 &primary_crtc_state->hw.mode); 4570 drm_mode_copy(&secondary_crtc_state->hw.pipe_mode, 4571 &primary_crtc_state->hw.pipe_mode); 4572 drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, 4573 &primary_crtc_state->hw.adjusted_mode); 4574 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; 4575 4576 if (primary_crtc_state->dp_tunnel_ref.tunnel) 4577 drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, 4578 &secondary_crtc_state->dp_tunnel_ref); 4579 4580 copy_joiner_crtc_state_nomodeset(state, secondary_crtc); 4581 4582 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed; 4583 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed; 4584 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed; 4585 4586 WARN_ON(primary_crtc_state->joiner_pipes != 4587 secondary_crtc_state->joiner_pipes); 4588 4589 return 0; 4590 } 4591 4592 static int 4593 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4594 struct intel_crtc *crtc) 4595 { 4596 struct intel_crtc_state *crtc_state = 4597 intel_atomic_get_new_crtc_state(state, crtc); 4598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4599 struct intel_crtc_state *saved_state; 4600 4601 saved_state = intel_crtc_state_alloc(crtc); 4602 if (!saved_state) 4603 return -ENOMEM; 4604 4605 /* free the old crtc_state->hw members */ 4606 intel_crtc_free_hw_state(crtc_state); 4607 4608 intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4609 4610 /* FIXME: before the switch to atomic started, a new pipe_config was 4611 * kzalloc'd. Code that depends on any field being zero should be 4612 * fixed, so that the crtc_state can be safely duplicated. For now, 4613 * only fields that are know to not cause problems are preserved. */ 4614 4615 saved_state->uapi = crtc_state->uapi; 4616 saved_state->inherited = crtc_state->inherited; 4617 saved_state->scaler_state = crtc_state->scaler_state; 4618 saved_state->shared_dpll = crtc_state->shared_dpll; 4619 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4620 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4621 sizeof(saved_state->icl_port_dplls)); 4622 saved_state->crc_enabled = crtc_state->crc_enabled; 4623 if (IS_G4X(dev_priv) || 4624 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4625 saved_state->wm = crtc_state->wm; 4626 4627 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4628 kfree(saved_state); 4629 4630 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4631 4632 return 0; 4633 } 4634 4635 static int 4636 intel_modeset_pipe_config(struct intel_atomic_state *state, 4637 struct intel_crtc *crtc, 4638 const struct intel_link_bw_limits *limits) 4639 { 4640 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4641 struct intel_crtc_state *crtc_state = 4642 intel_atomic_get_new_crtc_state(state, crtc); 4643 struct drm_connector *connector; 4644 struct drm_connector_state *connector_state; 4645 int pipe_src_w, pipe_src_h; 4646 int base_bpp, ret, i; 4647 4648 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4649 4650 crtc_state->framestart_delay = 1; 4651 4652 /* 4653 * Sanitize sync polarity flags based on requested ones. If neither 4654 * positive or negative polarity is requested, treat this as meaning 4655 * negative polarity. 4656 */ 4657 if (!(crtc_state->hw.adjusted_mode.flags & 4658 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4659 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4660 4661 if (!(crtc_state->hw.adjusted_mode.flags & 4662 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4663 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4664 4665 ret = compute_baseline_pipe_bpp(state, crtc); 4666 if (ret) 4667 return ret; 4668 4669 crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe); 4670 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; 4671 4672 if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) { 4673 drm_dbg_kms(&i915->drm, 4674 "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n", 4675 crtc->base.base.id, crtc->base.name, 4676 BPP_X16_ARGS(crtc_state->max_link_bpp_x16)); 4677 crtc_state->bw_constrained = true; 4678 } 4679 4680 base_bpp = crtc_state->pipe_bpp; 4681 4682 /* 4683 * Determine the real pipe dimensions. Note that stereo modes can 4684 * increase the actual pipe size due to the frame doubling and 4685 * insertion of additional space for blanks between the frame. This 4686 * is stored in the crtc timings. We use the requested mode to do this 4687 * computation to clearly distinguish it from the adjusted mode, which 4688 * can be changed by the connectors in the below retry loop. 4689 */ 4690 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4691 &pipe_src_w, &pipe_src_h); 4692 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4693 pipe_src_w, pipe_src_h); 4694 4695 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4696 struct intel_encoder *encoder = 4697 to_intel_encoder(connector_state->best_encoder); 4698 4699 if (connector_state->crtc != &crtc->base) 4700 continue; 4701 4702 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4703 drm_dbg_kms(&i915->drm, 4704 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4705 encoder->base.base.id, encoder->base.name); 4706 return -EINVAL; 4707 } 4708 4709 /* 4710 * Determine output_types before calling the .compute_config() 4711 * hooks so that the hooks can use this information safely. 4712 */ 4713 if (encoder->compute_output_type) 4714 crtc_state->output_types |= 4715 BIT(encoder->compute_output_type(encoder, crtc_state, 4716 connector_state)); 4717 else 4718 crtc_state->output_types |= BIT(encoder->type); 4719 } 4720 4721 /* Ensure the port clock defaults are reset when retrying. */ 4722 crtc_state->port_clock = 0; 4723 crtc_state->pixel_multiplier = 1; 4724 4725 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4726 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4727 CRTC_STEREO_DOUBLE); 4728 4729 /* Pass our mode to the connectors and the CRTC to give them a chance to 4730 * adjust it according to limitations or connector properties, and also 4731 * a chance to reject the mode entirely. 4732 */ 4733 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4734 struct intel_encoder *encoder = 4735 to_intel_encoder(connector_state->best_encoder); 4736 4737 if (connector_state->crtc != &crtc->base) 4738 continue; 4739 4740 ret = encoder->compute_config(encoder, crtc_state, 4741 connector_state); 4742 if (ret == -EDEADLK) 4743 return ret; 4744 if (ret < 0) { 4745 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4746 encoder->base.base.id, encoder->base.name, ret); 4747 return ret; 4748 } 4749 } 4750 4751 /* Set default port clock if not overwritten by the encoder. Needs to be 4752 * done afterwards in case the encoder adjusts the mode. */ 4753 if (!crtc_state->port_clock) 4754 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4755 * crtc_state->pixel_multiplier; 4756 4757 ret = intel_crtc_compute_config(state, crtc); 4758 if (ret == -EDEADLK) 4759 return ret; 4760 if (ret < 0) { 4761 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4762 crtc->base.base.id, crtc->base.name, ret); 4763 return ret; 4764 } 4765 4766 /* Dithering seems to not pass-through bits correctly when it should, so 4767 * only enable it on 6bpc panels and when its not a compliance 4768 * test requesting 6bpc video pattern. 4769 */ 4770 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4771 !crtc_state->dither_force_disable; 4772 drm_dbg_kms(&i915->drm, 4773 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4774 crtc->base.base.id, crtc->base.name, 4775 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4776 4777 return 0; 4778 } 4779 4780 static int 4781 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4782 struct intel_crtc *crtc) 4783 { 4784 struct intel_crtc_state *crtc_state = 4785 intel_atomic_get_new_crtc_state(state, crtc); 4786 struct drm_connector_state *conn_state; 4787 struct drm_connector *connector; 4788 int i; 4789 4790 for_each_new_connector_in_state(&state->base, connector, 4791 conn_state, i) { 4792 struct intel_encoder *encoder = 4793 to_intel_encoder(conn_state->best_encoder); 4794 int ret; 4795 4796 if (conn_state->crtc != &crtc->base || 4797 !encoder->compute_config_late) 4798 continue; 4799 4800 ret = encoder->compute_config_late(encoder, crtc_state, 4801 conn_state); 4802 if (ret) 4803 return ret; 4804 } 4805 4806 return 0; 4807 } 4808 4809 bool intel_fuzzy_clock_check(int clock1, int clock2) 4810 { 4811 int diff; 4812 4813 if (clock1 == clock2) 4814 return true; 4815 4816 if (!clock1 || !clock2) 4817 return false; 4818 4819 diff = abs(clock1 - clock2); 4820 4821 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4822 return true; 4823 4824 return false; 4825 } 4826 4827 static bool 4828 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4829 const struct intel_link_m_n *m2_n2) 4830 { 4831 return m_n->tu == m2_n2->tu && 4832 m_n->data_m == m2_n2->data_m && 4833 m_n->data_n == m2_n2->data_n && 4834 m_n->link_m == m2_n2->link_m && 4835 m_n->link_n == m2_n2->link_n; 4836 } 4837 4838 static bool 4839 intel_compare_infoframe(const union hdmi_infoframe *a, 4840 const union hdmi_infoframe *b) 4841 { 4842 return memcmp(a, b, sizeof(*a)) == 0; 4843 } 4844 4845 static bool 4846 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4847 const struct drm_dp_vsc_sdp *b) 4848 { 4849 return a->pixelformat == b->pixelformat && 4850 a->colorimetry == b->colorimetry && 4851 a->bpc == b->bpc && 4852 a->dynamic_range == b->dynamic_range && 4853 a->content_type == b->content_type; 4854 } 4855 4856 static bool 4857 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, 4858 const struct drm_dp_as_sdp *b) 4859 { 4860 return a->vtotal == b->vtotal && 4861 a->target_rr == b->target_rr && 4862 a->duration_incr_ms == b->duration_incr_ms && 4863 a->duration_decr_ms == b->duration_decr_ms && 4864 a->mode == b->mode; 4865 } 4866 4867 static bool 4868 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4869 { 4870 return memcmp(a, b, len) == 0; 4871 } 4872 4873 static void __printf(5, 6) 4874 pipe_config_mismatch(struct drm_printer *p, bool fastset, 4875 const struct intel_crtc *crtc, 4876 const char *name, const char *format, ...) 4877 { 4878 struct va_format vaf; 4879 va_list args; 4880 4881 va_start(args, format); 4882 vaf.fmt = format; 4883 vaf.va = &args; 4884 4885 if (fastset) 4886 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4887 crtc->base.base.id, crtc->base.name, name, &vaf); 4888 else 4889 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n", 4890 crtc->base.base.id, crtc->base.name, name, &vaf); 4891 4892 va_end(args); 4893 } 4894 4895 static void 4896 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, 4897 const struct intel_crtc *crtc, 4898 const char *name, 4899 const union hdmi_infoframe *a, 4900 const union hdmi_infoframe *b) 4901 { 4902 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4903 const char *loglevel; 4904 4905 if (fastset) { 4906 if (!drm_debug_enabled(DRM_UT_KMS)) 4907 return; 4908 4909 loglevel = KERN_DEBUG; 4910 } else { 4911 loglevel = KERN_ERR; 4912 } 4913 4914 pipe_config_mismatch(p, fastset, crtc, name, "infoframe"); 4915 4916 drm_printf(p, "expected:\n"); 4917 hdmi_infoframe_log(loglevel, i915->drm.dev, a); 4918 drm_printf(p, "found:\n"); 4919 hdmi_infoframe_log(loglevel, i915->drm.dev, b); 4920 } 4921 4922 static void 4923 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset, 4924 const struct intel_crtc *crtc, 4925 const char *name, 4926 const struct drm_dp_vsc_sdp *a, 4927 const struct drm_dp_vsc_sdp *b) 4928 { 4929 pipe_config_mismatch(p, fastset, crtc, name, "dp sdp"); 4930 4931 drm_printf(p, "expected:\n"); 4932 drm_dp_vsc_sdp_log(p, a); 4933 drm_printf(p, "found:\n"); 4934 drm_dp_vsc_sdp_log(p, b); 4935 } 4936 4937 static void 4938 pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915, 4939 bool fastset, const char *name, 4940 const struct drm_dp_as_sdp *a, 4941 const struct drm_dp_as_sdp *b) 4942 { 4943 struct drm_printer p; 4944 4945 if (fastset) { 4946 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL); 4947 4948 drm_printf(&p, "fastset requirement not met in %s dp sdp\n", name); 4949 } else { 4950 p = drm_err_printer(&i915->drm, NULL); 4951 4952 drm_printf(&p, "mismatch in %s dp sdp\n", name); 4953 } 4954 4955 drm_printf(&p, "expected:\n"); 4956 drm_dp_as_sdp_log(&p, a); 4957 drm_printf(&p, "found:\n"); 4958 drm_dp_as_sdp_log(&p, b); 4959 } 4960 4961 /* Returns the length up to and including the last differing byte */ 4962 static size_t 4963 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4964 { 4965 int i; 4966 4967 for (i = len - 1; i >= 0; i--) { 4968 if (a[i] != b[i]) 4969 return i + 1; 4970 } 4971 4972 return 0; 4973 } 4974 4975 static void 4976 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset, 4977 const struct intel_crtc *crtc, 4978 const char *name, 4979 const u8 *a, const u8 *b, size_t len) 4980 { 4981 const char *loglevel; 4982 4983 if (fastset) { 4984 if (!drm_debug_enabled(DRM_UT_KMS)) 4985 return; 4986 4987 loglevel = KERN_DEBUG; 4988 } else { 4989 loglevel = KERN_ERR; 4990 } 4991 4992 pipe_config_mismatch(p, fastset, crtc, name, "buffer"); 4993 4994 /* only dump up to the last difference */ 4995 len = memcmp_diff_len(a, b, len); 4996 4997 print_hex_dump(loglevel, "expected: ", DUMP_PREFIX_NONE, 4998 16, 0, a, len, false); 4999 print_hex_dump(loglevel, "found: ", DUMP_PREFIX_NONE, 5000 16, 0, b, len, false); 5001 } 5002 5003 static void 5004 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, 5005 const struct intel_crtc *crtc, 5006 const char *name, 5007 const struct intel_dpll_hw_state *a, 5008 const struct intel_dpll_hw_state *b) 5009 { 5010 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5011 5012 pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */ 5013 5014 drm_printf(p, "expected:\n"); 5015 intel_dpll_dump_hw_state(i915, p, a); 5016 drm_printf(p, "found:\n"); 5017 intel_dpll_dump_hw_state(i915, p, b); 5018 } 5019 5020 static void 5021 pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, 5022 const struct intel_crtc *crtc, 5023 const char *name, 5024 const struct intel_cx0pll_state *a, 5025 const struct intel_cx0pll_state *b) 5026 { 5027 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5028 char *chipname = a->use_c10 ? "C10" : "C20"; 5029 5030 pipe_config_mismatch(p, fastset, crtc, name, chipname); 5031 5032 drm_printf(p, "expected:\n"); 5033 intel_cx0pll_dump_hw_state(i915, a); 5034 drm_printf(p, "found:\n"); 5035 intel_cx0pll_dump_hw_state(i915, b); 5036 } 5037 5038 bool 5039 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5040 const struct intel_crtc_state *pipe_config, 5041 bool fastset) 5042 { 5043 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5044 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5045 struct drm_printer p; 5046 bool ret = true; 5047 5048 if (fastset) 5049 p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL); 5050 else 5051 p = drm_err_printer(&dev_priv->drm, NULL); 5052 5053 #define PIPE_CONF_CHECK_X(name) do { \ 5054 if (current_config->name != pipe_config->name) { \ 5055 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5056 __stringify(name) " is bool"); \ 5057 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5058 "(expected 0x%08x, found 0x%08x)", \ 5059 current_config->name, \ 5060 pipe_config->name); \ 5061 ret = false; \ 5062 } \ 5063 } while (0) 5064 5065 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5066 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5067 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5068 __stringify(name) " is bool"); \ 5069 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5070 "(expected 0x%08x, found 0x%08x)", \ 5071 current_config->name & (mask), \ 5072 pipe_config->name & (mask)); \ 5073 ret = false; \ 5074 } \ 5075 } while (0) 5076 5077 #define PIPE_CONF_CHECK_I(name) do { \ 5078 if (current_config->name != pipe_config->name) { \ 5079 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5080 __stringify(name) " is bool"); \ 5081 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5082 "(expected %i, found %i)", \ 5083 current_config->name, \ 5084 pipe_config->name); \ 5085 ret = false; \ 5086 } \ 5087 } while (0) 5088 5089 #define PIPE_CONF_CHECK_LLI(name) do { \ 5090 if (current_config->name != pipe_config->name) { \ 5091 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5092 "(expected %lli, found %lli)", \ 5093 current_config->name, \ 5094 pipe_config->name); \ 5095 ret = false; \ 5096 } \ 5097 } while (0) 5098 5099 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5100 if (current_config->name != pipe_config->name) { \ 5101 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ 5102 __stringify(name) " is not bool"); \ 5103 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5104 "(expected %s, found %s)", \ 5105 str_yes_no(current_config->name), \ 5106 str_yes_no(pipe_config->name)); \ 5107 ret = false; \ 5108 } \ 5109 } while (0) 5110 5111 #define PIPE_CONF_CHECK_P(name) do { \ 5112 if (current_config->name != pipe_config->name) { \ 5113 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5114 "(expected %p, found %p)", \ 5115 current_config->name, \ 5116 pipe_config->name); \ 5117 ret = false; \ 5118 } \ 5119 } while (0) 5120 5121 #define PIPE_CONF_CHECK_M_N(name) do { \ 5122 if (!intel_compare_link_m_n(¤t_config->name, \ 5123 &pipe_config->name)) { \ 5124 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5125 "(expected tu %i data %i/%i link %i/%i, " \ 5126 "found tu %i, data %i/%i link %i/%i)", \ 5127 current_config->name.tu, \ 5128 current_config->name.data_m, \ 5129 current_config->name.data_n, \ 5130 current_config->name.link_m, \ 5131 current_config->name.link_n, \ 5132 pipe_config->name.tu, \ 5133 pipe_config->name.data_m, \ 5134 pipe_config->name.data_n, \ 5135 pipe_config->name.link_m, \ 5136 pipe_config->name.link_n); \ 5137 ret = false; \ 5138 } \ 5139 } while (0) 5140 5141 #define PIPE_CONF_CHECK_PLL(name) do { \ 5142 if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \ 5143 &pipe_config->name)) { \ 5144 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5145 ¤t_config->name, \ 5146 &pipe_config->name); \ 5147 ret = false; \ 5148 } \ 5149 } while (0) 5150 5151 #define PIPE_CONF_CHECK_PLL_CX0(name) do { \ 5152 if (!intel_cx0pll_compare_hw_state(¤t_config->name, \ 5153 &pipe_config->name)) { \ 5154 pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5155 ¤t_config->name, \ 5156 &pipe_config->name); \ 5157 ret = false; \ 5158 } \ 5159 } while (0) 5160 5161 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5162 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5163 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5164 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5165 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5166 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5167 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5168 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5169 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5170 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5171 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5172 if (!fastset || !pipe_config->update_lrr) { \ 5173 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5174 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5175 } \ 5176 } while (0) 5177 5178 #define PIPE_CONF_CHECK_RECT(name) do { \ 5179 PIPE_CONF_CHECK_I(name.x1); \ 5180 PIPE_CONF_CHECK_I(name.x2); \ 5181 PIPE_CONF_CHECK_I(name.y1); \ 5182 PIPE_CONF_CHECK_I(name.y2); \ 5183 } while (0) 5184 5185 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5186 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5187 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5188 "(%x) (expected %i, found %i)", \ 5189 (mask), \ 5190 current_config->name & (mask), \ 5191 pipe_config->name & (mask)); \ 5192 ret = false; \ 5193 } \ 5194 } while (0) 5195 5196 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5197 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5198 &pipe_config->infoframes.name)) { \ 5199 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \ 5200 ¤t_config->infoframes.name, \ 5201 &pipe_config->infoframes.name); \ 5202 ret = false; \ 5203 } \ 5204 } while (0) 5205 5206 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5207 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5208 &pipe_config->infoframes.name)) { \ 5209 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5210 ¤t_config->infoframes.name, \ 5211 &pipe_config->infoframes.name); \ 5212 ret = false; \ 5213 } \ 5214 } while (0) 5215 5216 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ 5217 if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \ 5218 &pipe_config->infoframes.name)) { \ 5219 pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5220 ¤t_config->infoframes.name, \ 5221 &pipe_config->infoframes.name); \ 5222 ret = false; \ 5223 } \ 5224 } while (0) 5225 5226 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5227 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5228 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5229 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5230 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \ 5231 current_config->name, \ 5232 pipe_config->name, \ 5233 (len)); \ 5234 ret = false; \ 5235 } \ 5236 } while (0) 5237 5238 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5239 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5240 !intel_color_lut_equal(current_config, \ 5241 current_config->lut, pipe_config->lut, \ 5242 is_pre_csc_lut)) { \ 5243 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \ 5244 "hw_state doesn't match sw_state"); \ 5245 ret = false; \ 5246 } \ 5247 } while (0) 5248 5249 #define PIPE_CONF_CHECK_CSC(name) do { \ 5250 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5251 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5252 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5253 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5254 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5255 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5256 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5257 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5258 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5259 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5260 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5261 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5262 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5263 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5264 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5265 } while (0) 5266 5267 #define PIPE_CONF_QUIRK(quirk) \ 5268 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5269 5270 PIPE_CONF_CHECK_BOOL(hw.enable); 5271 PIPE_CONF_CHECK_BOOL(hw.active); 5272 5273 PIPE_CONF_CHECK_I(cpu_transcoder); 5274 PIPE_CONF_CHECK_I(mst_master_transcoder); 5275 5276 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5277 PIPE_CONF_CHECK_I(fdi_lanes); 5278 PIPE_CONF_CHECK_M_N(fdi_m_n); 5279 5280 PIPE_CONF_CHECK_I(lane_count); 5281 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5282 5283 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5284 if (!fastset || !pipe_config->update_m_n) 5285 PIPE_CONF_CHECK_M_N(dp_m_n); 5286 } else { 5287 PIPE_CONF_CHECK_M_N(dp_m_n); 5288 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5289 } 5290 5291 PIPE_CONF_CHECK_X(output_types); 5292 5293 PIPE_CONF_CHECK_I(framestart_delay); 5294 PIPE_CONF_CHECK_I(msa_timing_delay); 5295 5296 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5297 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5298 5299 PIPE_CONF_CHECK_I(pixel_multiplier); 5300 5301 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5302 DRM_MODE_FLAG_INTERLACE); 5303 5304 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5305 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5306 DRM_MODE_FLAG_PHSYNC); 5307 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5308 DRM_MODE_FLAG_NHSYNC); 5309 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5310 DRM_MODE_FLAG_PVSYNC); 5311 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5312 DRM_MODE_FLAG_NVSYNC); 5313 } 5314 5315 PIPE_CONF_CHECK_I(output_format); 5316 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5317 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5318 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5319 PIPE_CONF_CHECK_BOOL(limited_color_range); 5320 5321 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5322 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5323 PIPE_CONF_CHECK_BOOL(has_infoframe); 5324 PIPE_CONF_CHECK_BOOL(enhanced_framing); 5325 PIPE_CONF_CHECK_BOOL(fec_enable); 5326 5327 if (!fastset) { 5328 PIPE_CONF_CHECK_BOOL(has_audio); 5329 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5330 } 5331 5332 PIPE_CONF_CHECK_X(gmch_pfit.control); 5333 /* pfit ratios are autocomputed by the hw on gen4+ */ 5334 if (DISPLAY_VER(dev_priv) < 4) 5335 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5336 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5337 5338 /* 5339 * Changing the EDP transcoder input mux 5340 * (A_ONOFF vs. A_ON) requires a full modeset. 5341 */ 5342 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5343 5344 if (!fastset) { 5345 PIPE_CONF_CHECK_RECT(pipe_src); 5346 5347 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5348 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5349 5350 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5351 PIPE_CONF_CHECK_I(pixel_rate); 5352 5353 PIPE_CONF_CHECK_X(gamma_mode); 5354 if (IS_CHERRYVIEW(dev_priv)) 5355 PIPE_CONF_CHECK_X(cgm_mode); 5356 else 5357 PIPE_CONF_CHECK_X(csc_mode); 5358 PIPE_CONF_CHECK_BOOL(gamma_enable); 5359 PIPE_CONF_CHECK_BOOL(csc_enable); 5360 PIPE_CONF_CHECK_BOOL(wgc_enable); 5361 5362 PIPE_CONF_CHECK_I(linetime); 5363 PIPE_CONF_CHECK_I(ips_linetime); 5364 5365 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5366 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5367 5368 PIPE_CONF_CHECK_CSC(csc); 5369 PIPE_CONF_CHECK_CSC(output_csc); 5370 } 5371 5372 /* 5373 * Panel replay has to be enabled before link training. PSR doesn't have 5374 * this requirement -> check these only if using panel replay 5375 */ 5376 if (current_config->active_planes && 5377 (current_config->has_panel_replay || 5378 pipe_config->has_panel_replay)) { 5379 PIPE_CONF_CHECK_BOOL(has_psr); 5380 PIPE_CONF_CHECK_BOOL(has_sel_update); 5381 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5382 PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); 5383 PIPE_CONF_CHECK_BOOL(has_panel_replay); 5384 } 5385 5386 PIPE_CONF_CHECK_BOOL(double_wide); 5387 5388 if (dev_priv->display.dpll.mgr) 5389 PIPE_CONF_CHECK_P(shared_dpll); 5390 5391 /* FIXME convert everything over the dpll_mgr */ 5392 if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv)) 5393 PIPE_CONF_CHECK_PLL(dpll_hw_state); 5394 5395 /* FIXME convert MTL+ platforms over to dpll_mgr */ 5396 if (DISPLAY_VER(dev_priv) >= 14) 5397 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); 5398 5399 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5400 PIPE_CONF_CHECK_X(dsi_pll.div); 5401 5402 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5403 PIPE_CONF_CHECK_I(pipe_bpp); 5404 5405 if (!fastset || !pipe_config->update_m_n) { 5406 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5407 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5408 } 5409 PIPE_CONF_CHECK_I(port_clock); 5410 5411 PIPE_CONF_CHECK_I(min_voltage_level); 5412 5413 if (current_config->has_psr || pipe_config->has_psr) 5414 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5415 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5416 else 5417 PIPE_CONF_CHECK_X(infoframes.enable); 5418 5419 PIPE_CONF_CHECK_X(infoframes.gcp); 5420 PIPE_CONF_CHECK_INFOFRAME(avi); 5421 PIPE_CONF_CHECK_INFOFRAME(spd); 5422 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5423 PIPE_CONF_CHECK_INFOFRAME(drm); 5424 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5425 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); 5426 5427 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5428 PIPE_CONF_CHECK_I(master_transcoder); 5429 PIPE_CONF_CHECK_X(joiner_pipes); 5430 5431 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); 5432 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); 5433 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422); 5434 PIPE_CONF_CHECK_BOOL(dsc.config.native_422); 5435 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); 5436 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable); 5437 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth); 5438 PIPE_CONF_CHECK_I(dsc.config.bits_per_component); 5439 PIPE_CONF_CHECK_I(dsc.config.pic_width); 5440 PIPE_CONF_CHECK_I(dsc.config.pic_height); 5441 PIPE_CONF_CHECK_I(dsc.config.slice_width); 5442 PIPE_CONF_CHECK_I(dsc.config.slice_height); 5443 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay); 5444 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay); 5445 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval); 5446 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval); 5447 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value); 5448 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset); 5449 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp); 5450 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp); 5451 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset); 5452 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset); 5453 PIPE_CONF_CHECK_I(dsc.config.initial_offset); 5454 PIPE_CONF_CHECK_I(dsc.config.final_offset); 5455 PIPE_CONF_CHECK_I(dsc.config.rc_model_size); 5456 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0); 5457 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1); 5458 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size); 5459 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset); 5460 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); 5461 5462 PIPE_CONF_CHECK_BOOL(dsc.compression_enable); 5463 PIPE_CONF_CHECK_BOOL(dsc.dsc_split); 5464 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); 5465 5466 PIPE_CONF_CHECK_BOOL(splitter.enable); 5467 PIPE_CONF_CHECK_I(splitter.link_count); 5468 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5469 5470 if (!fastset) { 5471 PIPE_CONF_CHECK_BOOL(vrr.enable); 5472 PIPE_CONF_CHECK_I(vrr.vmin); 5473 PIPE_CONF_CHECK_I(vrr.vmax); 5474 PIPE_CONF_CHECK_I(vrr.flipline); 5475 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5476 PIPE_CONF_CHECK_I(vrr.guardband); 5477 PIPE_CONF_CHECK_I(vrr.vsync_start); 5478 PIPE_CONF_CHECK_I(vrr.vsync_end); 5479 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); 5480 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); 5481 PIPE_CONF_CHECK_BOOL(cmrr.enable); 5482 } 5483 5484 #undef PIPE_CONF_CHECK_X 5485 #undef PIPE_CONF_CHECK_I 5486 #undef PIPE_CONF_CHECK_LLI 5487 #undef PIPE_CONF_CHECK_BOOL 5488 #undef PIPE_CONF_CHECK_P 5489 #undef PIPE_CONF_CHECK_FLAGS 5490 #undef PIPE_CONF_CHECK_COLOR_LUT 5491 #undef PIPE_CONF_CHECK_TIMINGS 5492 #undef PIPE_CONF_CHECK_RECT 5493 #undef PIPE_CONF_QUIRK 5494 5495 return ret; 5496 } 5497 5498 static void 5499 intel_verify_planes(struct intel_atomic_state *state) 5500 { 5501 struct intel_plane *plane; 5502 const struct intel_plane_state *plane_state; 5503 int i; 5504 5505 for_each_new_intel_plane_in_state(state, plane, 5506 plane_state, i) 5507 assert_plane(plane, plane_state->planar_slave || 5508 plane_state->uapi.visible); 5509 } 5510 5511 static int intel_modeset_pipe(struct intel_atomic_state *state, 5512 struct intel_crtc_state *crtc_state, 5513 const char *reason) 5514 { 5515 struct drm_i915_private *i915 = to_i915(state->base.dev); 5516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5517 int ret; 5518 5519 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5520 crtc->base.base.id, crtc->base.name, reason); 5521 5522 ret = drm_atomic_add_affected_connectors(&state->base, 5523 &crtc->base); 5524 if (ret) 5525 return ret; 5526 5527 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc); 5528 if (ret) 5529 return ret; 5530 5531 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5532 if (ret) 5533 return ret; 5534 5535 ret = intel_atomic_add_affected_planes(state, crtc); 5536 if (ret) 5537 return ret; 5538 5539 crtc_state->uapi.mode_changed = true; 5540 5541 return 0; 5542 } 5543 5544 /** 5545 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes 5546 * @state: intel atomic state 5547 * @reason: the reason for the full modeset 5548 * @mask: mask of pipes to modeset 5549 * 5550 * Add pipes in @mask to @state and force a full modeset on the enabled ones 5551 * due to the description in @reason. 5552 * This function can be called only before new plane states are computed. 5553 * 5554 * Returns 0 in case of success, negative error code otherwise. 5555 */ 5556 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 5557 const char *reason, u8 mask) 5558 { 5559 struct drm_i915_private *i915 = to_i915(state->base.dev); 5560 struct intel_crtc *crtc; 5561 5562 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) { 5563 struct intel_crtc_state *crtc_state; 5564 int ret; 5565 5566 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5567 if (IS_ERR(crtc_state)) 5568 return PTR_ERR(crtc_state); 5569 5570 if (!crtc_state->hw.enable || 5571 intel_crtc_needs_modeset(crtc_state)) 5572 continue; 5573 5574 ret = intel_modeset_pipe(state, crtc_state, reason); 5575 if (ret) 5576 return ret; 5577 } 5578 5579 return 0; 5580 } 5581 5582 static void 5583 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) 5584 { 5585 crtc_state->uapi.mode_changed = true; 5586 5587 crtc_state->update_pipe = false; 5588 crtc_state->update_m_n = false; 5589 crtc_state->update_lrr = false; 5590 } 5591 5592 /** 5593 * intel_modeset_all_pipes_late - force a full modeset on all pipes 5594 * @state: intel atomic state 5595 * @reason: the reason for the full modeset 5596 * 5597 * Add all pipes to @state and force a full modeset on the active ones due to 5598 * the description in @reason. 5599 * This function can be called only after new plane states are computed already. 5600 * 5601 * Returns 0 in case of success, negative error code otherwise. 5602 */ 5603 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 5604 const char *reason) 5605 { 5606 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5607 struct intel_crtc *crtc; 5608 5609 for_each_intel_crtc(&dev_priv->drm, crtc) { 5610 struct intel_crtc_state *crtc_state; 5611 int ret; 5612 5613 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5614 if (IS_ERR(crtc_state)) 5615 return PTR_ERR(crtc_state); 5616 5617 if (!crtc_state->hw.active || 5618 intel_crtc_needs_modeset(crtc_state)) 5619 continue; 5620 5621 ret = intel_modeset_pipe(state, crtc_state, reason); 5622 if (ret) 5623 return ret; 5624 5625 intel_crtc_flag_modeset(crtc_state); 5626 5627 crtc_state->update_planes |= crtc_state->active_planes; 5628 crtc_state->async_flip_planes = 0; 5629 crtc_state->do_async_flip = false; 5630 } 5631 5632 return 0; 5633 } 5634 5635 int intel_modeset_commit_pipes(struct drm_i915_private *i915, 5636 u8 pipe_mask, 5637 struct drm_modeset_acquire_ctx *ctx) 5638 { 5639 struct drm_atomic_state *state; 5640 struct intel_crtc *crtc; 5641 int ret; 5642 5643 state = drm_atomic_state_alloc(&i915->drm); 5644 if (!state) 5645 return -ENOMEM; 5646 5647 state->acquire_ctx = ctx; 5648 to_intel_atomic_state(state)->internal = true; 5649 5650 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { 5651 struct intel_crtc_state *crtc_state = 5652 intel_atomic_get_crtc_state(state, crtc); 5653 5654 if (IS_ERR(crtc_state)) { 5655 ret = PTR_ERR(crtc_state); 5656 goto out; 5657 } 5658 5659 crtc_state->uapi.connectors_changed = true; 5660 } 5661 5662 ret = drm_atomic_commit(state); 5663 out: 5664 drm_atomic_state_put(state); 5665 5666 return ret; 5667 } 5668 5669 /* 5670 * This implements the workaround described in the "notes" section of the mode 5671 * set sequence documentation. When going from no pipes or single pipe to 5672 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5673 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5674 */ 5675 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5676 { 5677 struct intel_crtc_state *crtc_state; 5678 struct intel_crtc *crtc; 5679 struct intel_crtc_state *first_crtc_state = NULL; 5680 struct intel_crtc_state *other_crtc_state = NULL; 5681 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5682 int i; 5683 5684 /* look at all crtc's that are going to be enabled in during modeset */ 5685 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5686 if (!crtc_state->hw.active || 5687 !intel_crtc_needs_modeset(crtc_state)) 5688 continue; 5689 5690 if (first_crtc_state) { 5691 other_crtc_state = crtc_state; 5692 break; 5693 } else { 5694 first_crtc_state = crtc_state; 5695 first_pipe = crtc->pipe; 5696 } 5697 } 5698 5699 /* No workaround needed? */ 5700 if (!first_crtc_state) 5701 return 0; 5702 5703 /* w/a possibly needed, check how many crtc's are already enabled. */ 5704 for_each_intel_crtc(state->base.dev, crtc) { 5705 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5706 if (IS_ERR(crtc_state)) 5707 return PTR_ERR(crtc_state); 5708 5709 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5710 5711 if (!crtc_state->hw.active || 5712 intel_crtc_needs_modeset(crtc_state)) 5713 continue; 5714 5715 /* 2 or more enabled crtcs means no need for w/a */ 5716 if (enabled_pipe != INVALID_PIPE) 5717 return 0; 5718 5719 enabled_pipe = crtc->pipe; 5720 } 5721 5722 if (enabled_pipe != INVALID_PIPE) 5723 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5724 else if (other_crtc_state) 5725 other_crtc_state->hsw_workaround_pipe = first_pipe; 5726 5727 return 0; 5728 } 5729 5730 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5731 u8 active_pipes) 5732 { 5733 const struct intel_crtc_state *crtc_state; 5734 struct intel_crtc *crtc; 5735 int i; 5736 5737 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5738 if (crtc_state->hw.active) 5739 active_pipes |= BIT(crtc->pipe); 5740 else 5741 active_pipes &= ~BIT(crtc->pipe); 5742 } 5743 5744 return active_pipes; 5745 } 5746 5747 static int intel_modeset_checks(struct intel_atomic_state *state) 5748 { 5749 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5750 5751 state->modeset = true; 5752 5753 if (IS_HASWELL(dev_priv)) 5754 return hsw_mode_set_planes_workaround(state); 5755 5756 return 0; 5757 } 5758 5759 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5760 struct intel_crtc_state *new_crtc_state) 5761 { 5762 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 5763 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5764 5765 /* only allow LRR when the timings stay within the VRR range */ 5766 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range) 5767 new_crtc_state->update_lrr = false; 5768 5769 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 5770 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", 5771 crtc->base.base.id, crtc->base.name); 5772 else 5773 new_crtc_state->uapi.mode_changed = false; 5774 5775 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, 5776 &new_crtc_state->dp_m_n)) 5777 new_crtc_state->update_m_n = false; 5778 5779 if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal && 5780 old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end)) 5781 new_crtc_state->update_lrr = false; 5782 5783 if (intel_crtc_needs_modeset(new_crtc_state)) 5784 intel_crtc_flag_modeset(new_crtc_state); 5785 else 5786 new_crtc_state->update_pipe = true; 5787 } 5788 5789 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5790 struct intel_crtc *crtc, 5791 u8 plane_ids_mask) 5792 { 5793 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5794 struct intel_plane *plane; 5795 5796 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5797 struct intel_plane_state *plane_state; 5798 5799 if ((plane_ids_mask & BIT(plane->id)) == 0) 5800 continue; 5801 5802 plane_state = intel_atomic_get_plane_state(state, plane); 5803 if (IS_ERR(plane_state)) 5804 return PTR_ERR(plane_state); 5805 } 5806 5807 return 0; 5808 } 5809 5810 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5811 struct intel_crtc *crtc) 5812 { 5813 const struct intel_crtc_state *old_crtc_state = 5814 intel_atomic_get_old_crtc_state(state, crtc); 5815 const struct intel_crtc_state *new_crtc_state = 5816 intel_atomic_get_new_crtc_state(state, crtc); 5817 5818 return intel_crtc_add_planes_to_state(state, crtc, 5819 old_crtc_state->enabled_planes | 5820 new_crtc_state->enabled_planes); 5821 } 5822 5823 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5824 { 5825 /* See {hsw,vlv,ivb}_plane_ratio() */ 5826 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5827 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5828 IS_IVYBRIDGE(dev_priv); 5829 } 5830 5831 static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state, 5832 struct intel_crtc *crtc, 5833 struct intel_crtc *other) 5834 { 5835 const struct intel_plane_state __maybe_unused *plane_state; 5836 struct intel_plane *plane; 5837 u8 plane_ids = 0; 5838 int i; 5839 5840 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5841 if (plane->pipe == crtc->pipe) 5842 plane_ids |= BIT(plane->id); 5843 } 5844 5845 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5846 } 5847 5848 static int intel_joiner_add_affected_planes(struct intel_atomic_state *state) 5849 { 5850 struct drm_i915_private *i915 = to_i915(state->base.dev); 5851 const struct intel_crtc_state *crtc_state; 5852 struct intel_crtc *crtc; 5853 int i; 5854 5855 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5856 struct intel_crtc *other; 5857 5858 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5859 crtc_state->joiner_pipes) { 5860 int ret; 5861 5862 if (crtc == other) 5863 continue; 5864 5865 ret = intel_crtc_add_joiner_planes(state, crtc, other); 5866 if (ret) 5867 return ret; 5868 } 5869 } 5870 5871 return 0; 5872 } 5873 5874 static int intel_atomic_check_planes(struct intel_atomic_state *state) 5875 { 5876 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5877 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5878 struct intel_plane_state __maybe_unused *plane_state; 5879 struct intel_plane *plane; 5880 struct intel_crtc *crtc; 5881 int i, ret; 5882 5883 ret = icl_add_linked_planes(state); 5884 if (ret) 5885 return ret; 5886 5887 ret = intel_joiner_add_affected_planes(state); 5888 if (ret) 5889 return ret; 5890 5891 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5892 ret = intel_plane_atomic_check(state, plane); 5893 if (ret) { 5894 drm_dbg_atomic(&dev_priv->drm, 5895 "[PLANE:%d:%s] atomic driver check failed\n", 5896 plane->base.base.id, plane->base.name); 5897 return ret; 5898 } 5899 } 5900 5901 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5902 new_crtc_state, i) { 5903 u8 old_active_planes, new_active_planes; 5904 5905 ret = icl_check_nv12_planes(state, crtc); 5906 if (ret) 5907 return ret; 5908 5909 /* 5910 * On some platforms the number of active planes affects 5911 * the planes' minimum cdclk calculation. Add such planes 5912 * to the state before we compute the minimum cdclk. 5913 */ 5914 if (!active_planes_affects_min_cdclk(dev_priv)) 5915 continue; 5916 5917 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5918 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5919 5920 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5921 continue; 5922 5923 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5924 if (ret) 5925 return ret; 5926 } 5927 5928 return 0; 5929 } 5930 5931 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5932 { 5933 struct intel_crtc_state __maybe_unused *crtc_state; 5934 struct intel_crtc *crtc; 5935 int i; 5936 5937 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5938 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5939 int ret; 5940 5941 ret = intel_crtc_atomic_check(state, crtc); 5942 if (ret) { 5943 drm_dbg_atomic(&i915->drm, 5944 "[CRTC:%d:%s] atomic driver check failed\n", 5945 crtc->base.base.id, crtc->base.name); 5946 return ret; 5947 } 5948 } 5949 5950 return 0; 5951 } 5952 5953 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5954 u8 transcoders) 5955 { 5956 const struct intel_crtc_state *new_crtc_state; 5957 struct intel_crtc *crtc; 5958 int i; 5959 5960 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5961 if (new_crtc_state->hw.enable && 5962 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5963 intel_crtc_needs_modeset(new_crtc_state)) 5964 return true; 5965 } 5966 5967 return false; 5968 } 5969 5970 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5971 u8 pipes) 5972 { 5973 const struct intel_crtc_state *new_crtc_state; 5974 struct intel_crtc *crtc; 5975 int i; 5976 5977 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5978 if (new_crtc_state->hw.enable && 5979 pipes & BIT(crtc->pipe) && 5980 intel_crtc_needs_modeset(new_crtc_state)) 5981 return true; 5982 } 5983 5984 return false; 5985 } 5986 5987 static int intel_atomic_check_joiner(struct intel_atomic_state *state, 5988 struct intel_crtc *primary_crtc) 5989 { 5990 struct drm_i915_private *i915 = to_i915(state->base.dev); 5991 struct intel_crtc_state *primary_crtc_state = 5992 intel_atomic_get_new_crtc_state(state, primary_crtc); 5993 struct intel_crtc *secondary_crtc; 5994 5995 if (!primary_crtc_state->joiner_pipes) 5996 return 0; 5997 5998 /* sanity check */ 5999 if (drm_WARN_ON(&i915->drm, 6000 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) 6001 return -EINVAL; 6002 6003 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) { 6004 drm_dbg_kms(&i915->drm, 6005 "[CRTC:%d:%s] Cannot act as joiner primary " 6006 "(need 0x%x as pipes, only 0x%x possible)\n", 6007 primary_crtc->base.base.id, primary_crtc->base.name, 6008 primary_crtc_state->joiner_pipes, joiner_pipes(i915)); 6009 return -EINVAL; 6010 } 6011 6012 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, 6013 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 6014 struct intel_crtc_state *secondary_crtc_state; 6015 int ret; 6016 6017 secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc); 6018 if (IS_ERR(secondary_crtc_state)) 6019 return PTR_ERR(secondary_crtc_state); 6020 6021 /* primary being enabled, secondary was already configured? */ 6022 if (secondary_crtc_state->uapi.enable) { 6023 drm_dbg_kms(&i915->drm, 6024 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " 6025 "[CRTC:%d:%s] claiming this CRTC for joiner.\n", 6026 secondary_crtc->base.base.id, secondary_crtc->base.name, 6027 primary_crtc->base.base.id, primary_crtc->base.name); 6028 return -EINVAL; 6029 } 6030 6031 /* 6032 * The state copy logic assumes the primary crtc gets processed 6033 * before the secondary crtc during the main compute_config loop. 6034 * This works because the crtcs are created in pipe order, 6035 * and the hardware requires primary pipe < secondary pipe as well. 6036 * Should that change we need to rethink the logic. 6037 */ 6038 if (WARN_ON(drm_crtc_index(&primary_crtc->base) > 6039 drm_crtc_index(&secondary_crtc->base))) 6040 return -EINVAL; 6041 6042 drm_dbg_kms(&i915->drm, 6043 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", 6044 secondary_crtc->base.base.id, secondary_crtc->base.name, 6045 primary_crtc->base.base.id, primary_crtc->base.name); 6046 6047 secondary_crtc_state->joiner_pipes = 6048 primary_crtc_state->joiner_pipes; 6049 6050 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc); 6051 if (ret) 6052 return ret; 6053 } 6054 6055 return 0; 6056 } 6057 6058 static void kill_joiner_secondaries(struct intel_atomic_state *state, 6059 struct intel_crtc *primary_crtc) 6060 { 6061 struct drm_i915_private *i915 = to_i915(state->base.dev); 6062 struct intel_crtc_state *primary_crtc_state = 6063 intel_atomic_get_new_crtc_state(state, primary_crtc); 6064 struct intel_crtc *secondary_crtc; 6065 6066 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, 6067 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 6068 struct intel_crtc_state *secondary_crtc_state = 6069 intel_atomic_get_new_crtc_state(state, secondary_crtc); 6070 6071 secondary_crtc_state->joiner_pipes = 0; 6072 6073 intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc); 6074 } 6075 6076 primary_crtc_state->joiner_pipes = 0; 6077 } 6078 6079 /** 6080 * DOC: asynchronous flip implementation 6081 * 6082 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6083 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6084 * Correspondingly, support is currently added for primary plane only. 6085 * 6086 * Async flip can only change the plane surface address, so anything else 6087 * changing is rejected from the intel_async_flip_check_hw() function. 6088 * Once this check is cleared, flip done interrupt is enabled using 6089 * the intel_crtc_enable_flip_done() function. 6090 * 6091 * As soon as the surface address register is written, flip done interrupt is 6092 * generated and the requested events are sent to the usersapce in the interrupt 6093 * handler itself. The timestamp and sequence sent during the flip done event 6094 * correspond to the last vblank and have no relation to the actual time when 6095 * the flip done event was sent. 6096 */ 6097 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6098 struct intel_crtc *crtc) 6099 { 6100 struct drm_i915_private *i915 = to_i915(state->base.dev); 6101 const struct intel_crtc_state *new_crtc_state = 6102 intel_atomic_get_new_crtc_state(state, crtc); 6103 const struct intel_plane_state *old_plane_state; 6104 struct intel_plane_state *new_plane_state; 6105 struct intel_plane *plane; 6106 int i; 6107 6108 if (!new_crtc_state->uapi.async_flip) 6109 return 0; 6110 6111 if (!new_crtc_state->uapi.active) { 6112 drm_dbg_kms(&i915->drm, 6113 "[CRTC:%d:%s] not active\n", 6114 crtc->base.base.id, crtc->base.name); 6115 return -EINVAL; 6116 } 6117 6118 if (intel_crtc_needs_modeset(new_crtc_state)) { 6119 drm_dbg_kms(&i915->drm, 6120 "[CRTC:%d:%s] modeset required\n", 6121 crtc->base.base.id, crtc->base.name); 6122 return -EINVAL; 6123 } 6124 6125 /* 6126 * FIXME: joiner+async flip is busted currently. 6127 * Remove this check once the issues are fixed. 6128 */ 6129 if (new_crtc_state->joiner_pipes) { 6130 drm_dbg_kms(&i915->drm, 6131 "[CRTC:%d:%s] async flip disallowed with joiner\n", 6132 crtc->base.base.id, crtc->base.name); 6133 return -EINVAL; 6134 } 6135 6136 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6137 new_plane_state, i) { 6138 if (plane->pipe != crtc->pipe) 6139 continue; 6140 6141 /* 6142 * TODO: Async flip is only supported through the page flip IOCTL 6143 * as of now. So support currently added for primary plane only. 6144 * Support for other planes on platforms on which supports 6145 * this(vlv/chv and icl+) should be added when async flip is 6146 * enabled in the atomic IOCTL path. 6147 */ 6148 if (!plane->async_flip) { 6149 drm_dbg_kms(&i915->drm, 6150 "[PLANE:%d:%s] async flip not supported\n", 6151 plane->base.base.id, plane->base.name); 6152 return -EINVAL; 6153 } 6154 6155 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6156 drm_dbg_kms(&i915->drm, 6157 "[PLANE:%d:%s] no old or new framebuffer\n", 6158 plane->base.base.id, plane->base.name); 6159 return -EINVAL; 6160 } 6161 } 6162 6163 return 0; 6164 } 6165 6166 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6167 { 6168 struct drm_i915_private *i915 = to_i915(state->base.dev); 6169 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6170 const struct intel_plane_state *new_plane_state, *old_plane_state; 6171 struct intel_plane *plane; 6172 int i; 6173 6174 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6175 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6176 6177 if (!new_crtc_state->uapi.async_flip) 6178 return 0; 6179 6180 if (!new_crtc_state->hw.active) { 6181 drm_dbg_kms(&i915->drm, 6182 "[CRTC:%d:%s] not active\n", 6183 crtc->base.base.id, crtc->base.name); 6184 return -EINVAL; 6185 } 6186 6187 if (intel_crtc_needs_modeset(new_crtc_state)) { 6188 drm_dbg_kms(&i915->drm, 6189 "[CRTC:%d:%s] modeset required\n", 6190 crtc->base.base.id, crtc->base.name); 6191 return -EINVAL; 6192 } 6193 6194 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6195 drm_dbg_kms(&i915->drm, 6196 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6197 crtc->base.base.id, crtc->base.name); 6198 return -EINVAL; 6199 } 6200 6201 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6202 new_plane_state, i) { 6203 if (plane->pipe != crtc->pipe) 6204 continue; 6205 6206 /* 6207 * Only async flip capable planes should be in the state 6208 * if we're really about to ask the hardware to perform 6209 * an async flip. We should never get this far otherwise. 6210 */ 6211 if (drm_WARN_ON(&i915->drm, 6212 new_crtc_state->do_async_flip && !plane->async_flip)) 6213 return -EINVAL; 6214 6215 /* 6216 * Only check async flip capable planes other planes 6217 * may be involved in the initial commit due to 6218 * the wm0/ddb optimization. 6219 * 6220 * TODO maybe should track which planes actually 6221 * were requested to do the async flip... 6222 */ 6223 if (!plane->async_flip) 6224 continue; 6225 6226 /* 6227 * FIXME: This check is kept generic for all platforms. 6228 * Need to verify this for all gen9 platforms to enable 6229 * this selectively if required. 6230 */ 6231 switch (new_plane_state->hw.fb->modifier) { 6232 case DRM_FORMAT_MOD_LINEAR: 6233 /* 6234 * FIXME: Async on Linear buffer is supported on ICL as 6235 * but with additional alignment and fbc restrictions 6236 * need to be taken care of. These aren't applicable for 6237 * gen12+. 6238 */ 6239 if (DISPLAY_VER(i915) < 12) { 6240 drm_dbg_kms(&i915->drm, 6241 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", 6242 plane->base.base.id, plane->base.name, 6243 new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); 6244 return -EINVAL; 6245 } 6246 break; 6247 6248 case I915_FORMAT_MOD_X_TILED: 6249 case I915_FORMAT_MOD_Y_TILED: 6250 case I915_FORMAT_MOD_Yf_TILED: 6251 case I915_FORMAT_MOD_4_TILED: 6252 break; 6253 default: 6254 drm_dbg_kms(&i915->drm, 6255 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", 6256 plane->base.base.id, plane->base.name, 6257 new_plane_state->hw.fb->modifier); 6258 return -EINVAL; 6259 } 6260 6261 if (new_plane_state->hw.fb->format->num_planes > 1) { 6262 drm_dbg_kms(&i915->drm, 6263 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6264 plane->base.base.id, plane->base.name); 6265 return -EINVAL; 6266 } 6267 6268 /* 6269 * We turn the first async flip request into a sync flip 6270 * so that we can reconfigure the plane (eg. change modifier). 6271 */ 6272 if (!new_crtc_state->do_async_flip) 6273 continue; 6274 6275 if (old_plane_state->view.color_plane[0].mapping_stride != 6276 new_plane_state->view.color_plane[0].mapping_stride) { 6277 drm_dbg_kms(&i915->drm, 6278 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6279 plane->base.base.id, plane->base.name); 6280 return -EINVAL; 6281 } 6282 6283 if (old_plane_state->hw.fb->modifier != 6284 new_plane_state->hw.fb->modifier) { 6285 drm_dbg_kms(&i915->drm, 6286 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6287 plane->base.base.id, plane->base.name); 6288 return -EINVAL; 6289 } 6290 6291 if (old_plane_state->hw.fb->format != 6292 new_plane_state->hw.fb->format) { 6293 drm_dbg_kms(&i915->drm, 6294 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6295 plane->base.base.id, plane->base.name); 6296 return -EINVAL; 6297 } 6298 6299 if (old_plane_state->hw.rotation != 6300 new_plane_state->hw.rotation) { 6301 drm_dbg_kms(&i915->drm, 6302 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6303 plane->base.base.id, plane->base.name); 6304 return -EINVAL; 6305 } 6306 6307 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6308 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6309 drm_dbg_kms(&i915->drm, 6310 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6311 plane->base.base.id, plane->base.name); 6312 return -EINVAL; 6313 } 6314 6315 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6316 drm_dbg_kms(&i915->drm, 6317 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6318 plane->base.base.id, plane->base.name); 6319 return -EINVAL; 6320 } 6321 6322 if (old_plane_state->hw.pixel_blend_mode != 6323 new_plane_state->hw.pixel_blend_mode) { 6324 drm_dbg_kms(&i915->drm, 6325 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6326 plane->base.base.id, plane->base.name); 6327 return -EINVAL; 6328 } 6329 6330 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6331 drm_dbg_kms(&i915->drm, 6332 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6333 plane->base.base.id, plane->base.name); 6334 return -EINVAL; 6335 } 6336 6337 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6338 drm_dbg_kms(&i915->drm, 6339 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6340 plane->base.base.id, plane->base.name); 6341 return -EINVAL; 6342 } 6343 6344 /* plane decryption is allow to change only in synchronous flips */ 6345 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6346 drm_dbg_kms(&i915->drm, 6347 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6348 plane->base.base.id, plane->base.name); 6349 return -EINVAL; 6350 } 6351 } 6352 6353 return 0; 6354 } 6355 6356 static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) 6357 { 6358 struct drm_i915_private *i915 = to_i915(state->base.dev); 6359 struct intel_crtc_state *crtc_state; 6360 struct intel_crtc *crtc; 6361 u8 affected_pipes = 0; 6362 u8 modeset_pipes = 0; 6363 int i; 6364 6365 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6366 affected_pipes |= crtc_state->joiner_pipes; 6367 if (intel_crtc_needs_modeset(crtc_state)) 6368 modeset_pipes |= crtc_state->joiner_pipes; 6369 } 6370 6371 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6372 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6373 if (IS_ERR(crtc_state)) 6374 return PTR_ERR(crtc_state); 6375 } 6376 6377 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6378 int ret; 6379 6380 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6381 6382 crtc_state->uapi.mode_changed = true; 6383 6384 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6385 if (ret) 6386 return ret; 6387 6388 ret = intel_atomic_add_affected_planes(state, crtc); 6389 if (ret) 6390 return ret; 6391 } 6392 6393 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6394 /* Kill old joiner link, we may re-establish afterwards */ 6395 if (intel_crtc_needs_modeset(crtc_state) && 6396 intel_crtc_is_joiner_primary(crtc_state)) 6397 kill_joiner_secondaries(state, crtc); 6398 } 6399 6400 return 0; 6401 } 6402 6403 static int intel_atomic_check_config(struct intel_atomic_state *state, 6404 struct intel_link_bw_limits *limits, 6405 enum pipe *failed_pipe) 6406 { 6407 struct drm_i915_private *i915 = to_i915(state->base.dev); 6408 struct intel_crtc_state *new_crtc_state; 6409 struct intel_crtc *crtc; 6410 int ret; 6411 int i; 6412 6413 *failed_pipe = INVALID_PIPE; 6414 6415 ret = intel_joiner_add_affected_crtcs(state); 6416 if (ret) 6417 return ret; 6418 6419 ret = intel_fdi_add_affected_crtcs(state); 6420 if (ret) 6421 return ret; 6422 6423 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6424 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6425 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6426 copy_joiner_crtc_state_nomodeset(state, crtc); 6427 else 6428 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6429 continue; 6430 } 6431 6432 if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6433 continue; 6434 6435 ret = intel_crtc_prepare_cleared_state(state, crtc); 6436 if (ret) 6437 goto fail; 6438 6439 if (!new_crtc_state->hw.enable) 6440 continue; 6441 6442 ret = intel_modeset_pipe_config(state, crtc, limits); 6443 if (ret) 6444 goto fail; 6445 } 6446 6447 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6448 if (!intel_crtc_needs_modeset(new_crtc_state)) 6449 continue; 6450 6451 if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6452 continue; 6453 6454 if (!new_crtc_state->hw.enable) 6455 continue; 6456 6457 ret = intel_modeset_pipe_config_late(state, crtc); 6458 if (ret) 6459 goto fail; 6460 } 6461 6462 fail: 6463 if (ret) 6464 *failed_pipe = crtc->pipe; 6465 6466 return ret; 6467 } 6468 6469 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) 6470 { 6471 struct intel_link_bw_limits new_limits; 6472 struct intel_link_bw_limits old_limits; 6473 int ret; 6474 6475 intel_link_bw_init_limits(state, &new_limits); 6476 old_limits = new_limits; 6477 6478 while (true) { 6479 enum pipe failed_pipe; 6480 6481 ret = intel_atomic_check_config(state, &new_limits, 6482 &failed_pipe); 6483 if (ret) { 6484 /* 6485 * The bpp limit for a pipe is below the minimum it supports, set the 6486 * limit to the minimum and recalculate the config. 6487 */ 6488 if (ret == -EINVAL && 6489 intel_link_bw_set_bpp_limit_for_pipe(state, 6490 &old_limits, 6491 &new_limits, 6492 failed_pipe)) 6493 continue; 6494 6495 break; 6496 } 6497 6498 old_limits = new_limits; 6499 6500 ret = intel_link_bw_atomic_check(state, &new_limits); 6501 if (ret != -EAGAIN) 6502 break; 6503 } 6504 6505 return ret; 6506 } 6507 /** 6508 * intel_atomic_check - validate state object 6509 * @dev: drm device 6510 * @_state: state to validate 6511 */ 6512 int intel_atomic_check(struct drm_device *dev, 6513 struct drm_atomic_state *_state) 6514 { 6515 struct drm_i915_private *dev_priv = to_i915(dev); 6516 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6517 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6518 struct intel_crtc *crtc; 6519 int ret, i; 6520 bool any_ms = false; 6521 6522 if (!intel_display_driver_check_access(dev_priv)) 6523 return -ENODEV; 6524 6525 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6526 new_crtc_state, i) { 6527 /* 6528 * crtc's state no longer considered to be inherited 6529 * after the first userspace/client initiated commit. 6530 */ 6531 if (!state->internal) 6532 new_crtc_state->inherited = false; 6533 6534 if (new_crtc_state->inherited != old_crtc_state->inherited) 6535 new_crtc_state->uapi.mode_changed = true; 6536 6537 if (new_crtc_state->uapi.scaling_filter != 6538 old_crtc_state->uapi.scaling_filter) 6539 new_crtc_state->uapi.mode_changed = true; 6540 } 6541 6542 intel_vrr_check_modeset(state); 6543 6544 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6545 if (ret) 6546 goto fail; 6547 6548 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6549 ret = intel_async_flip_check_uapi(state, crtc); 6550 if (ret) 6551 return ret; 6552 } 6553 6554 ret = intel_atomic_check_config_and_link(state); 6555 if (ret) 6556 goto fail; 6557 6558 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6559 if (!intel_crtc_needs_modeset(new_crtc_state)) 6560 continue; 6561 6562 if (intel_crtc_is_joiner_secondary(new_crtc_state)) { 6563 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6564 continue; 6565 } 6566 6567 ret = intel_atomic_check_joiner(state, crtc); 6568 if (ret) 6569 goto fail; 6570 } 6571 6572 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6573 new_crtc_state, i) { 6574 if (!intel_crtc_needs_modeset(new_crtc_state)) 6575 continue; 6576 6577 intel_joiner_adjust_pipe_src(new_crtc_state); 6578 6579 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6580 } 6581 6582 /** 6583 * Check if fastset is allowed by external dependencies like other 6584 * pipes and transcoders. 6585 * 6586 * Right now it only forces a fullmodeset when the MST master 6587 * transcoder did not changed but the pipe of the master transcoder 6588 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6589 * in case of port synced crtcs, if one of the synced crtcs 6590 * needs a full modeset, all other synced crtcs should be 6591 * forced a full modeset. 6592 */ 6593 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6594 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6595 continue; 6596 6597 if (intel_dp_mst_crtc_needs_modeset(state, crtc)) 6598 intel_crtc_flag_modeset(new_crtc_state); 6599 6600 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6601 enum transcoder master = new_crtc_state->mst_master_transcoder; 6602 6603 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) 6604 intel_crtc_flag_modeset(new_crtc_state); 6605 } 6606 6607 if (is_trans_port_sync_mode(new_crtc_state)) { 6608 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6609 6610 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6611 trans |= BIT(new_crtc_state->master_transcoder); 6612 6613 if (intel_cpu_transcoders_need_modeset(state, trans)) 6614 intel_crtc_flag_modeset(new_crtc_state); 6615 } 6616 6617 if (new_crtc_state->joiner_pipes) { 6618 if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes)) 6619 intel_crtc_flag_modeset(new_crtc_state); 6620 } 6621 } 6622 6623 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6624 new_crtc_state, i) { 6625 if (!intel_crtc_needs_modeset(new_crtc_state)) 6626 continue; 6627 6628 any_ms = true; 6629 6630 intel_release_shared_dplls(state, crtc); 6631 } 6632 6633 if (any_ms && !check_digital_port_conflicts(state)) { 6634 drm_dbg_kms(&dev_priv->drm, 6635 "rejecting conflicting digital port configuration\n"); 6636 ret = -EINVAL; 6637 goto fail; 6638 } 6639 6640 ret = intel_atomic_check_planes(state); 6641 if (ret) 6642 goto fail; 6643 6644 ret = intel_compute_global_watermarks(state); 6645 if (ret) 6646 goto fail; 6647 6648 ret = intel_bw_atomic_check(state); 6649 if (ret) 6650 goto fail; 6651 6652 ret = intel_cdclk_atomic_check(state, &any_ms); 6653 if (ret) 6654 goto fail; 6655 6656 if (intel_any_crtc_needs_modeset(state)) 6657 any_ms = true; 6658 6659 if (any_ms) { 6660 ret = intel_modeset_checks(state); 6661 if (ret) 6662 goto fail; 6663 6664 ret = intel_modeset_calc_cdclk(state); 6665 if (ret) 6666 return ret; 6667 } 6668 6669 ret = intel_pmdemand_atomic_check(state); 6670 if (ret) 6671 goto fail; 6672 6673 ret = intel_atomic_check_crtcs(state); 6674 if (ret) 6675 goto fail; 6676 6677 ret = intel_fbc_atomic_check(state); 6678 if (ret) 6679 goto fail; 6680 6681 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6682 new_crtc_state, i) { 6683 intel_color_assert_luts(new_crtc_state); 6684 6685 ret = intel_async_flip_check_hw(state, crtc); 6686 if (ret) 6687 goto fail; 6688 6689 /* Either full modeset or fastset (or neither), never both */ 6690 drm_WARN_ON(&dev_priv->drm, 6691 intel_crtc_needs_modeset(new_crtc_state) && 6692 intel_crtc_needs_fastset(new_crtc_state)); 6693 6694 if (!intel_crtc_needs_modeset(new_crtc_state) && 6695 !intel_crtc_needs_fastset(new_crtc_state)) 6696 continue; 6697 6698 intel_crtc_state_dump(new_crtc_state, state, 6699 intel_crtc_needs_modeset(new_crtc_state) ? 6700 "modeset" : "fastset"); 6701 } 6702 6703 return 0; 6704 6705 fail: 6706 if (ret == -EDEADLK) 6707 return ret; 6708 6709 /* 6710 * FIXME would probably be nice to know which crtc specifically 6711 * caused the failure, in cases where we can pinpoint it. 6712 */ 6713 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6714 new_crtc_state, i) 6715 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6716 6717 return ret; 6718 } 6719 6720 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6721 { 6722 struct intel_crtc_state __maybe_unused *crtc_state; 6723 struct intel_crtc *crtc; 6724 int i, ret; 6725 6726 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6727 if (ret < 0) 6728 return ret; 6729 6730 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 6731 intel_color_prepare_commit(state, crtc); 6732 6733 return 0; 6734 } 6735 6736 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6737 struct intel_crtc_state *crtc_state) 6738 { 6739 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6740 6741 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6742 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6743 6744 if (crtc_state->has_pch_encoder) { 6745 enum pipe pch_transcoder = 6746 intel_crtc_pch_transcoder(crtc); 6747 6748 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6749 } 6750 } 6751 6752 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6753 const struct intel_crtc_state *new_crtc_state) 6754 { 6755 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6757 6758 /* 6759 * Update pipe size and adjust fitter if needed: the reason for this is 6760 * that in compute_mode_changes we check the native mode (not the pfit 6761 * mode) to see if we can flip rather than do a full mode set. In the 6762 * fastboot case, we'll flip, but if we don't update the pipesrc and 6763 * pfit state, we'll end up with a big fb scanned out into the wrong 6764 * sized surface. 6765 */ 6766 intel_set_pipe_src_size(new_crtc_state); 6767 6768 /* on skylake this is done by detaching scalers */ 6769 if (DISPLAY_VER(dev_priv) >= 9) { 6770 if (new_crtc_state->pch_pfit.enabled) 6771 skl_pfit_enable(new_crtc_state); 6772 } else if (HAS_PCH_SPLIT(dev_priv)) { 6773 if (new_crtc_state->pch_pfit.enabled) 6774 ilk_pfit_enable(new_crtc_state); 6775 else if (old_crtc_state->pch_pfit.enabled) 6776 ilk_pfit_disable(old_crtc_state); 6777 } 6778 6779 /* 6780 * The register is supposedly single buffered so perhaps 6781 * not 100% correct to do this here. But SKL+ calculate 6782 * this based on the adjust pixel rate so pfit changes do 6783 * affect it and so it must be updated for fastsets. 6784 * HSW/BDW only really need this here for fastboot, after 6785 * that the value should not change without a full modeset. 6786 */ 6787 if (DISPLAY_VER(dev_priv) >= 9 || 6788 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6789 hsw_set_linetime_wm(new_crtc_state); 6790 6791 if (new_crtc_state->update_m_n) 6792 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6793 &new_crtc_state->dp_m_n); 6794 6795 if (new_crtc_state->update_lrr) 6796 intel_set_transcoder_timings_lrr(new_crtc_state); 6797 } 6798 6799 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6800 struct intel_crtc *crtc) 6801 { 6802 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6803 const struct intel_crtc_state *old_crtc_state = 6804 intel_atomic_get_old_crtc_state(state, crtc); 6805 const struct intel_crtc_state *new_crtc_state = 6806 intel_atomic_get_new_crtc_state(state, crtc); 6807 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6808 6809 /* 6810 * During modesets pipe configuration was programmed as the 6811 * CRTC was enabled. 6812 */ 6813 if (!modeset) { 6814 if (intel_crtc_needs_color_update(new_crtc_state)) 6815 intel_color_commit_arm(new_crtc_state); 6816 6817 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6818 bdw_set_pipe_misc(new_crtc_state); 6819 6820 if (intel_crtc_needs_fastset(new_crtc_state)) 6821 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6822 } 6823 6824 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6825 6826 intel_atomic_update_watermarks(state, crtc); 6827 } 6828 6829 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6830 struct intel_crtc *crtc) 6831 { 6832 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6833 const struct intel_crtc_state *old_crtc_state = 6834 intel_atomic_get_old_crtc_state(state, crtc); 6835 const struct intel_crtc_state *new_crtc_state = 6836 intel_atomic_get_new_crtc_state(state, crtc); 6837 6838 /* 6839 * Disable the scaler(s) after the plane(s) so that we don't 6840 * get a catastrophic underrun even if the two operations 6841 * end up happening in two different frames. 6842 */ 6843 if (DISPLAY_VER(dev_priv) >= 9 && 6844 !intel_crtc_needs_modeset(new_crtc_state)) 6845 skl_detach_scalers(new_crtc_state); 6846 6847 if (vrr_enabling(old_crtc_state, new_crtc_state)) 6848 intel_vrr_enable(new_crtc_state); 6849 } 6850 6851 static void intel_enable_crtc(struct intel_atomic_state *state, 6852 struct intel_crtc *crtc) 6853 { 6854 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6855 const struct intel_crtc_state *new_crtc_state = 6856 intel_atomic_get_new_crtc_state(state, crtc); 6857 struct intel_crtc *pipe_crtc; 6858 6859 if (!intel_crtc_needs_modeset(new_crtc_state)) 6860 return; 6861 6862 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, 6863 intel_crtc_joined_pipe_mask(new_crtc_state)) { 6864 const struct intel_crtc_state *pipe_crtc_state = 6865 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6866 6867 /* VRR will be enable later, if required */ 6868 intel_crtc_update_active_timings(pipe_crtc_state, false); 6869 } 6870 6871 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6872 6873 /* vblanks work again, re-enable pipe CRC. */ 6874 intel_crtc_enable_pipe_crc(crtc); 6875 } 6876 6877 static void intel_pre_update_crtc(struct intel_atomic_state *state, 6878 struct intel_crtc *crtc) 6879 { 6880 struct drm_i915_private *i915 = to_i915(state->base.dev); 6881 const struct intel_crtc_state *old_crtc_state = 6882 intel_atomic_get_old_crtc_state(state, crtc); 6883 struct intel_crtc_state *new_crtc_state = 6884 intel_atomic_get_new_crtc_state(state, crtc); 6885 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6886 6887 if (old_crtc_state->inherited || 6888 intel_crtc_needs_modeset(new_crtc_state)) { 6889 if (HAS_DPT(i915)) 6890 intel_dpt_configure(crtc); 6891 } 6892 6893 if (!modeset) { 6894 if (new_crtc_state->preload_luts && 6895 intel_crtc_needs_color_update(new_crtc_state)) 6896 intel_color_load_luts(new_crtc_state); 6897 6898 intel_pre_plane_update(state, crtc); 6899 6900 if (intel_crtc_needs_fastset(new_crtc_state)) 6901 intel_encoders_update_pipe(state, crtc); 6902 6903 if (DISPLAY_VER(i915) >= 11 && 6904 intel_crtc_needs_fastset(new_crtc_state)) 6905 icl_set_pipe_chicken(new_crtc_state); 6906 6907 if (vrr_params_changed(old_crtc_state, new_crtc_state) || 6908 cmrr_params_changed(old_crtc_state, new_crtc_state)) 6909 intel_vrr_set_transcoder_timings(new_crtc_state); 6910 } 6911 6912 intel_fbc_update(state, crtc); 6913 6914 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6915 6916 if (!modeset && 6917 intel_crtc_needs_color_update(new_crtc_state)) 6918 intel_color_commit_noarm(new_crtc_state); 6919 6920 intel_crtc_planes_update_noarm(state, crtc); 6921 } 6922 6923 static void intel_update_crtc(struct intel_atomic_state *state, 6924 struct intel_crtc *crtc) 6925 { 6926 const struct intel_crtc_state *old_crtc_state = 6927 intel_atomic_get_old_crtc_state(state, crtc); 6928 struct intel_crtc_state *new_crtc_state = 6929 intel_atomic_get_new_crtc_state(state, crtc); 6930 6931 /* Perform vblank evasion around commit operation */ 6932 intel_pipe_update_start(state, crtc); 6933 6934 commit_pipe_pre_planes(state, crtc); 6935 6936 intel_crtc_planes_update_arm(state, crtc); 6937 6938 commit_pipe_post_planes(state, crtc); 6939 6940 intel_pipe_update_end(state, crtc); 6941 6942 /* 6943 * VRR/Seamless M/N update may need to update frame timings. 6944 * 6945 * FIXME Should be synchronized with the start of vblank somehow... 6946 */ 6947 if (vrr_enabling(old_crtc_state, new_crtc_state) || 6948 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 6949 intel_crtc_update_active_timings(new_crtc_state, 6950 new_crtc_state->vrr.enable); 6951 6952 /* 6953 * We usually enable FIFO underrun interrupts as part of the 6954 * CRTC enable sequence during modesets. But when we inherit a 6955 * valid pipe configuration from the BIOS we need to take care 6956 * of enabling them on the CRTC's first fastset. 6957 */ 6958 if (intel_crtc_needs_fastset(new_crtc_state) && 6959 old_crtc_state->inherited) 6960 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6961 } 6962 6963 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6964 struct intel_crtc *crtc) 6965 { 6966 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6967 const struct intel_crtc_state *old_crtc_state = 6968 intel_atomic_get_old_crtc_state(state, crtc); 6969 struct intel_crtc *pipe_crtc; 6970 6971 /* 6972 * We need to disable pipe CRC before disabling the pipe, 6973 * or we race against vblank off. 6974 */ 6975 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 6976 intel_crtc_joined_pipe_mask(old_crtc_state)) 6977 intel_crtc_disable_pipe_crc(pipe_crtc); 6978 6979 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6980 6981 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 6982 intel_crtc_joined_pipe_mask(old_crtc_state)) { 6983 const struct intel_crtc_state *new_pipe_crtc_state = 6984 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6985 6986 pipe_crtc->active = false; 6987 intel_fbc_disable(pipe_crtc); 6988 6989 if (!new_pipe_crtc_state->hw.active) 6990 intel_initial_watermarks(state, pipe_crtc); 6991 } 6992 } 6993 6994 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6995 { 6996 struct drm_i915_private *i915 = to_i915(state->base.dev); 6997 const struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6998 struct intel_crtc *crtc; 6999 u8 disable_pipes = 0; 7000 int i; 7001 7002 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7003 new_crtc_state, i) { 7004 if (!intel_crtc_needs_modeset(new_crtc_state)) 7005 continue; 7006 7007 /* 7008 * Needs to be done even for pipes 7009 * that weren't enabled previously. 7010 */ 7011 intel_pre_plane_update(state, crtc); 7012 7013 if (!old_crtc_state->hw.active) 7014 continue; 7015 7016 disable_pipes |= BIT(crtc->pipe); 7017 } 7018 7019 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 7020 if ((disable_pipes & BIT(crtc->pipe)) == 0) 7021 continue; 7022 7023 intel_crtc_disable_planes(state, crtc); 7024 7025 drm_vblank_work_flush_all(&crtc->base); 7026 } 7027 7028 /* Only disable port sync and MST slaves */ 7029 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 7030 if ((disable_pipes & BIT(crtc->pipe)) == 0) 7031 continue; 7032 7033 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 7034 continue; 7035 7036 /* In case of Transcoder port Sync master slave CRTCs can be 7037 * assigned in any order and we need to make sure that 7038 * slave CRTCs are disabled first and then master CRTC since 7039 * Slave vblanks are masked till Master Vblanks. 7040 */ 7041 if (!is_trans_port_sync_slave(old_crtc_state) && 7042 !intel_dp_mst_is_slave_trans(old_crtc_state)) 7043 continue; 7044 7045 intel_old_crtc_state_disables(state, crtc); 7046 7047 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 7048 } 7049 7050 /* Disable everything else left on */ 7051 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 7052 if ((disable_pipes & BIT(crtc->pipe)) == 0) 7053 continue; 7054 7055 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 7056 continue; 7057 7058 intel_old_crtc_state_disables(state, crtc); 7059 7060 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 7061 } 7062 7063 drm_WARN_ON(&i915->drm, disable_pipes); 7064 } 7065 7066 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7067 { 7068 struct intel_crtc_state *new_crtc_state; 7069 struct intel_crtc *crtc; 7070 int i; 7071 7072 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7073 if (!new_crtc_state->hw.active) 7074 continue; 7075 7076 intel_enable_crtc(state, crtc); 7077 intel_pre_update_crtc(state, crtc); 7078 } 7079 7080 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7081 if (!new_crtc_state->hw.active) 7082 continue; 7083 7084 intel_update_crtc(state, crtc); 7085 } 7086 } 7087 7088 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7089 { 7090 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7091 struct intel_crtc *crtc; 7092 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7093 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7094 u8 update_pipes = 0, modeset_pipes = 0; 7095 int i; 7096 7097 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7098 enum pipe pipe = crtc->pipe; 7099 7100 if (!new_crtc_state->hw.active) 7101 continue; 7102 7103 /* ignore allocations for crtc's that have been turned off. */ 7104 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7105 entries[pipe] = old_crtc_state->wm.skl.ddb; 7106 update_pipes |= BIT(pipe); 7107 } else { 7108 modeset_pipes |= BIT(pipe); 7109 } 7110 } 7111 7112 /* 7113 * Whenever the number of active pipes changes, we need to make sure we 7114 * update the pipes in the right order so that their ddb allocations 7115 * never overlap with each other between CRTC updates. Otherwise we'll 7116 * cause pipe underruns and other bad stuff. 7117 * 7118 * So first lets enable all pipes that do not need a fullmodeset as 7119 * those don't have any external dependency. 7120 */ 7121 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7122 enum pipe pipe = crtc->pipe; 7123 7124 if ((update_pipes & BIT(pipe)) == 0) 7125 continue; 7126 7127 intel_pre_update_crtc(state, crtc); 7128 } 7129 7130 intel_dbuf_mbus_pre_ddb_update(state); 7131 7132 while (update_pipes) { 7133 /* 7134 * Commit in reverse order to make joiner primary 7135 * send the uapi events after secondaries are done. 7136 */ 7137 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, 7138 new_crtc_state, i) { 7139 enum pipe pipe = crtc->pipe; 7140 7141 if ((update_pipes & BIT(pipe)) == 0) 7142 continue; 7143 7144 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7145 entries, I915_MAX_PIPES, pipe)) 7146 continue; 7147 7148 entries[pipe] = new_crtc_state->wm.skl.ddb; 7149 update_pipes &= ~BIT(pipe); 7150 7151 intel_update_crtc(state, crtc); 7152 7153 /* 7154 * If this is an already active pipe, it's DDB changed, 7155 * and this isn't the last pipe that needs updating 7156 * then we need to wait for a vblank to pass for the 7157 * new ddb allocation to take effect. 7158 */ 7159 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7160 &old_crtc_state->wm.skl.ddb) && 7161 (update_pipes | modeset_pipes)) 7162 intel_crtc_wait_for_next_vblank(crtc); 7163 } 7164 } 7165 7166 intel_dbuf_mbus_post_ddb_update(state); 7167 7168 update_pipes = modeset_pipes; 7169 7170 /* 7171 * Enable all pipes that needs a modeset and do not depends on other 7172 * pipes 7173 */ 7174 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7175 enum pipe pipe = crtc->pipe; 7176 7177 if ((modeset_pipes & BIT(pipe)) == 0) 7178 continue; 7179 7180 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7181 continue; 7182 7183 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7184 is_trans_port_sync_master(new_crtc_state)) 7185 continue; 7186 7187 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7188 7189 intel_enable_crtc(state, crtc); 7190 } 7191 7192 /* 7193 * Then we enable all remaining pipes that depend on other 7194 * pipes: MST slaves and port sync masters 7195 */ 7196 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7197 enum pipe pipe = crtc->pipe; 7198 7199 if ((modeset_pipes & BIT(pipe)) == 0) 7200 continue; 7201 7202 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7203 continue; 7204 7205 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7206 7207 intel_enable_crtc(state, crtc); 7208 } 7209 7210 /* 7211 * Finally we do the plane updates/etc. for all pipes that got enabled. 7212 */ 7213 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7214 enum pipe pipe = crtc->pipe; 7215 7216 if ((update_pipes & BIT(pipe)) == 0) 7217 continue; 7218 7219 intel_pre_update_crtc(state, crtc); 7220 } 7221 7222 /* 7223 * Commit in reverse order to make joiner primary 7224 * send the uapi events after secondaries are done. 7225 */ 7226 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) { 7227 enum pipe pipe = crtc->pipe; 7228 7229 if ((update_pipes & BIT(pipe)) == 0) 7230 continue; 7231 7232 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7233 entries, I915_MAX_PIPES, pipe)); 7234 7235 entries[pipe] = new_crtc_state->wm.skl.ddb; 7236 update_pipes &= ~BIT(pipe); 7237 7238 intel_update_crtc(state, crtc); 7239 } 7240 7241 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7242 drm_WARN_ON(&dev_priv->drm, update_pipes); 7243 } 7244 7245 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7246 { 7247 struct drm_i915_private *i915 = to_i915(intel_state->base.dev); 7248 struct drm_plane *plane; 7249 struct drm_plane_state *new_plane_state; 7250 int ret, i; 7251 7252 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) { 7253 if (new_plane_state->fence) { 7254 ret = dma_fence_wait_timeout(new_plane_state->fence, false, 7255 i915_fence_timeout(i915)); 7256 if (ret <= 0) 7257 break; 7258 7259 dma_fence_put(new_plane_state->fence); 7260 new_plane_state->fence = NULL; 7261 } 7262 } 7263 } 7264 7265 static void intel_atomic_cleanup_work(struct work_struct *work) 7266 { 7267 struct intel_atomic_state *state = 7268 container_of(work, struct intel_atomic_state, base.commit_work); 7269 struct drm_i915_private *i915 = to_i915(state->base.dev); 7270 struct intel_crtc_state *old_crtc_state; 7271 struct intel_crtc *crtc; 7272 int i; 7273 7274 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7275 intel_color_cleanup_commit(old_crtc_state); 7276 7277 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7278 drm_atomic_helper_commit_cleanup_done(&state->base); 7279 drm_atomic_state_put(&state->base); 7280 } 7281 7282 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7283 { 7284 struct drm_i915_private *i915 = to_i915(state->base.dev); 7285 struct intel_plane *plane; 7286 struct intel_plane_state *plane_state; 7287 int i; 7288 7289 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7290 struct drm_framebuffer *fb = plane_state->hw.fb; 7291 int cc_plane; 7292 int ret; 7293 7294 if (!fb) 7295 continue; 7296 7297 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7298 if (cc_plane < 0) 7299 continue; 7300 7301 /* 7302 * The layout of the fast clear color value expected by HW 7303 * (the DRM ABI requiring this value to be located in fb at 7304 * offset 0 of cc plane, plane #2 previous generations or 7305 * plane #1 for flat ccs): 7306 * - 4 x 4 bytes per-channel value 7307 * (in surface type specific float/int format provided by the fb user) 7308 * - 8 bytes native color value used by the display 7309 * (converted/written by GPU during a fast clear operation using the 7310 * above per-channel values) 7311 * 7312 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7313 * caller made sure that the object is synced wrt. the related color clear value 7314 * GPU write on it. 7315 */ 7316 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7317 fb->offsets[cc_plane] + 16, 7318 &plane_state->ccval, 7319 sizeof(plane_state->ccval)); 7320 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7321 drm_WARN_ON(&i915->drm, ret); 7322 } 7323 } 7324 7325 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7326 { 7327 struct drm_device *dev = state->base.dev; 7328 struct drm_i915_private *dev_priv = to_i915(dev); 7329 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7330 struct intel_crtc *crtc; 7331 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7332 intel_wakeref_t wakeref = 0; 7333 int i; 7334 7335 intel_atomic_commit_fence_wait(state); 7336 7337 intel_td_flush(dev_priv); 7338 7339 drm_atomic_helper_wait_for_dependencies(&state->base); 7340 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7341 intel_atomic_global_state_wait_for_dependencies(state); 7342 7343 /* 7344 * During full modesets we write a lot of registers, wait 7345 * for PLLs, etc. Doing that while DC states are enabled 7346 * is not a good idea. 7347 * 7348 * During fastsets and other updates we also need to 7349 * disable DC states due to the following scenario: 7350 * 1. DC5 exit and PSR exit happen 7351 * 2. Some or all _noarm() registers are written 7352 * 3. Due to some long delay PSR is re-entered 7353 * 4. DC5 entry -> DMC saves the already written new 7354 * _noarm() registers and the old not yet written 7355 * _arm() registers 7356 * 5. DC5 exit -> DMC restores a mixture of old and 7357 * new register values and arms the update 7358 * 6. PSR exit -> hardware latches a mixture of old and 7359 * new register values -> corrupted frame, or worse 7360 * 7. New _arm() registers are finally written 7361 * 8. Hardware finally latches a complete set of new 7362 * register values, and subsequent frames will be OK again 7363 * 7364 * Also note that due to the pipe CSC hardware issues on 7365 * SKL/GLK DC states must remain off until the pipe CSC 7366 * state readout has happened. Otherwise we risk corrupting 7367 * the CSC latched register values with the readout (see 7368 * skl_read_csc() and skl_color_commit_noarm()). 7369 */ 7370 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 7371 7372 intel_atomic_prepare_plane_clear_colors(state); 7373 7374 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7375 new_crtc_state, i) { 7376 if (intel_crtc_needs_modeset(new_crtc_state) || 7377 intel_crtc_needs_fastset(new_crtc_state)) 7378 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7379 } 7380 7381 intel_commit_modeset_disables(state); 7382 7383 intel_dp_tunnel_atomic_alloc_bw(state); 7384 7385 /* FIXME: Eventually get rid of our crtc->config pointer */ 7386 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7387 crtc->config = new_crtc_state; 7388 7389 /* 7390 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7391 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7392 * index, cdclk/ddiclk frequencies are supposed to be configured before 7393 * the cdclk config is set. 7394 */ 7395 intel_pmdemand_pre_plane_update(state); 7396 7397 if (state->modeset) { 7398 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7399 7400 intel_set_cdclk_pre_plane_update(state); 7401 7402 intel_modeset_verify_disabled(state); 7403 } 7404 7405 intel_sagv_pre_plane_update(state); 7406 7407 /* Complete the events for pipes that have now been disabled */ 7408 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7409 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7410 7411 /* Complete events for now disable pipes here. */ 7412 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7413 spin_lock_irq(&dev->event_lock); 7414 drm_crtc_send_vblank_event(&crtc->base, 7415 new_crtc_state->uapi.event); 7416 spin_unlock_irq(&dev->event_lock); 7417 7418 new_crtc_state->uapi.event = NULL; 7419 } 7420 } 7421 7422 intel_encoders_update_prepare(state); 7423 7424 intel_dbuf_pre_plane_update(state); 7425 7426 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7427 if (new_crtc_state->do_async_flip) 7428 intel_crtc_enable_flip_done(state, crtc); 7429 } 7430 7431 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7432 dev_priv->display.funcs.display->commit_modeset_enables(state); 7433 7434 if (state->modeset) 7435 intel_set_cdclk_post_plane_update(state); 7436 7437 intel_wait_for_vblank_workers(state); 7438 7439 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7440 * already, but still need the state for the delayed optimization. To 7441 * fix this: 7442 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7443 * - schedule that vblank worker _before_ calling hw_done 7444 * - at the start of commit_tail, cancel it _synchrously 7445 * - switch over to the vblank wait helper in the core after that since 7446 * we don't need out special handling any more. 7447 */ 7448 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7449 7450 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7451 if (new_crtc_state->do_async_flip) 7452 intel_crtc_disable_flip_done(state, crtc); 7453 7454 intel_color_wait_commit(new_crtc_state); 7455 } 7456 7457 /* 7458 * Now that the vblank has passed, we can go ahead and program the 7459 * optimal watermarks on platforms that need two-step watermark 7460 * programming. 7461 * 7462 * TODO: Move this (and other cleanup) to an async worker eventually. 7463 */ 7464 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7465 new_crtc_state, i) { 7466 /* 7467 * Gen2 reports pipe underruns whenever all planes are disabled. 7468 * So re-enable underrun reporting after some planes get enabled. 7469 * 7470 * We do this before .optimize_watermarks() so that we have a 7471 * chance of catching underruns with the intermediate watermarks 7472 * vs. the new plane configuration. 7473 */ 7474 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7475 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7476 7477 intel_optimize_watermarks(state, crtc); 7478 } 7479 7480 intel_dbuf_post_plane_update(state); 7481 7482 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7483 intel_post_plane_update(state, crtc); 7484 7485 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7486 7487 intel_modeset_verify_crtc(state, crtc); 7488 7489 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7490 hsw_ips_post_update(state, crtc); 7491 7492 /* 7493 * Activate DRRS after state readout to avoid 7494 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7495 */ 7496 intel_drrs_activate(new_crtc_state); 7497 7498 /* 7499 * DSB cleanup is done in cleanup_work aligning with framebuffer 7500 * cleanup. So copy and reset the dsb structure to sync with 7501 * commit_done and later do dsb cleanup in cleanup_work. 7502 * 7503 * FIXME get rid of this funny new->old swapping 7504 */ 7505 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7506 } 7507 7508 /* Underruns don't always raise interrupts, so check manually */ 7509 intel_check_cpu_fifo_underruns(dev_priv); 7510 intel_check_pch_fifo_underruns(dev_priv); 7511 7512 if (state->modeset) 7513 intel_verify_planes(state); 7514 7515 intel_sagv_post_plane_update(state); 7516 intel_pmdemand_post_plane_update(state); 7517 7518 drm_atomic_helper_commit_hw_done(&state->base); 7519 intel_atomic_global_state_commit_done(state); 7520 7521 if (state->modeset) { 7522 /* As one of the primary mmio accessors, KMS has a high 7523 * likelihood of triggering bugs in unclaimed access. After we 7524 * finish modesetting, see if an error has been flagged, and if 7525 * so enable debugging for the next modeset - and hope we catch 7526 * the culprit. 7527 */ 7528 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7529 } 7530 /* 7531 * Delay re-enabling DC states by 17 ms to avoid the off->on->off 7532 * toggling overhead at and above 60 FPS. 7533 */ 7534 intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17); 7535 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7536 7537 /* 7538 * Defer the cleanup of the old state to a separate worker to not 7539 * impede the current task (userspace for blocking modesets) that 7540 * are executed inline. For out-of-line asynchronous modesets/flips, 7541 * deferring to a new worker seems overkill, but we would place a 7542 * schedule point (cond_resched()) here anyway to keep latencies 7543 * down. 7544 */ 7545 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7546 queue_work(system_highpri_wq, &state->base.commit_work); 7547 } 7548 7549 static void intel_atomic_commit_work(struct work_struct *work) 7550 { 7551 struct intel_atomic_state *state = 7552 container_of(work, struct intel_atomic_state, base.commit_work); 7553 7554 intel_atomic_commit_tail(state); 7555 } 7556 7557 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7558 { 7559 struct intel_plane_state *old_plane_state, *new_plane_state; 7560 struct intel_plane *plane; 7561 int i; 7562 7563 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7564 new_plane_state, i) 7565 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7566 to_intel_frontbuffer(new_plane_state->hw.fb), 7567 plane->frontbuffer_bit); 7568 } 7569 7570 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock) 7571 { 7572 int ret; 7573 7574 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7575 if (ret) 7576 return ret; 7577 7578 ret = intel_atomic_global_state_setup_commit(state); 7579 if (ret) 7580 return ret; 7581 7582 return 0; 7583 } 7584 7585 static int intel_atomic_swap_state(struct intel_atomic_state *state) 7586 { 7587 int ret; 7588 7589 ret = drm_atomic_helper_swap_state(&state->base, true); 7590 if (ret) 7591 return ret; 7592 7593 intel_atomic_swap_global_state(state); 7594 7595 intel_shared_dpll_swap_state(state); 7596 7597 intel_atomic_track_fbs(state); 7598 7599 return 0; 7600 } 7601 7602 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7603 bool nonblock) 7604 { 7605 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7606 struct drm_i915_private *dev_priv = to_i915(dev); 7607 int ret = 0; 7608 7609 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7610 7611 /* 7612 * The intel_legacy_cursor_update() fast path takes care 7613 * of avoiding the vblank waits for simple cursor 7614 * movement and flips. For cursor on/off and size changes, 7615 * we want to perform the vblank waits so that watermark 7616 * updates happen during the correct frames. Gen9+ have 7617 * double buffered watermarks and so shouldn't need this. 7618 * 7619 * Unset state->legacy_cursor_update before the call to 7620 * drm_atomic_helper_setup_commit() because otherwise 7621 * drm_atomic_helper_wait_for_flip_done() is a noop and 7622 * we get FIFO underruns because we didn't wait 7623 * for vblank. 7624 * 7625 * FIXME doing watermarks and fb cleanup from a vblank worker 7626 * (assuming we had any) would solve these problems. 7627 */ 7628 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7629 struct intel_crtc_state *new_crtc_state; 7630 struct intel_crtc *crtc; 7631 int i; 7632 7633 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7634 if (new_crtc_state->wm.need_postvbl_update || 7635 new_crtc_state->update_wm_post) 7636 state->base.legacy_cursor_update = false; 7637 } 7638 7639 ret = intel_atomic_prepare_commit(state); 7640 if (ret) { 7641 drm_dbg_atomic(&dev_priv->drm, 7642 "Preparing state failed with %i\n", ret); 7643 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7644 return ret; 7645 } 7646 7647 ret = intel_atomic_setup_commit(state, nonblock); 7648 if (!ret) 7649 ret = intel_atomic_swap_state(state); 7650 7651 if (ret) { 7652 struct intel_crtc_state *new_crtc_state; 7653 struct intel_crtc *crtc; 7654 int i; 7655 7656 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7657 intel_color_cleanup_commit(new_crtc_state); 7658 7659 drm_atomic_helper_unprepare_planes(dev, &state->base); 7660 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7661 return ret; 7662 } 7663 7664 drm_atomic_state_get(&state->base); 7665 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7666 7667 if (nonblock && state->modeset) { 7668 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7669 } else if (nonblock) { 7670 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7671 } else { 7672 if (state->modeset) 7673 flush_workqueue(dev_priv->display.wq.modeset); 7674 intel_atomic_commit_tail(state); 7675 } 7676 7677 return 0; 7678 } 7679 7680 /** 7681 * intel_plane_destroy - destroy a plane 7682 * @plane: plane to destroy 7683 * 7684 * Common destruction function for all types of planes (primary, cursor, 7685 * sprite). 7686 */ 7687 void intel_plane_destroy(struct drm_plane *plane) 7688 { 7689 drm_plane_cleanup(plane); 7690 kfree(to_intel_plane(plane)); 7691 } 7692 7693 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7694 struct drm_file *file) 7695 { 7696 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7697 struct drm_crtc *drmmode_crtc; 7698 struct intel_crtc *crtc; 7699 7700 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7701 if (!drmmode_crtc) 7702 return -ENOENT; 7703 7704 crtc = to_intel_crtc(drmmode_crtc); 7705 pipe_from_crtc_id->pipe = crtc->pipe; 7706 7707 return 0; 7708 } 7709 7710 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7711 { 7712 struct drm_device *dev = encoder->base.dev; 7713 struct intel_encoder *source_encoder; 7714 u32 possible_clones = 0; 7715 7716 for_each_intel_encoder(dev, source_encoder) { 7717 if (encoders_cloneable(encoder, source_encoder)) 7718 possible_clones |= drm_encoder_mask(&source_encoder->base); 7719 } 7720 7721 return possible_clones; 7722 } 7723 7724 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7725 { 7726 struct drm_device *dev = encoder->base.dev; 7727 struct intel_crtc *crtc; 7728 u32 possible_crtcs = 0; 7729 7730 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7731 possible_crtcs |= drm_crtc_mask(&crtc->base); 7732 7733 return possible_crtcs; 7734 } 7735 7736 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7737 { 7738 if (!IS_MOBILE(dev_priv)) 7739 return false; 7740 7741 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7742 return false; 7743 7744 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7745 return false; 7746 7747 return true; 7748 } 7749 7750 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7751 { 7752 if (DISPLAY_VER(dev_priv) >= 9) 7753 return false; 7754 7755 if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)) 7756 return false; 7757 7758 if (HAS_PCH_LPT_H(dev_priv) && 7759 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7760 return false; 7761 7762 /* DDI E can't be used if DDI A requires 4 lanes */ 7763 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7764 return false; 7765 7766 if (!dev_priv->display.vbt.int_crt_support) 7767 return false; 7768 7769 return true; 7770 } 7771 7772 bool assert_port_valid(struct drm_i915_private *i915, enum port port) 7773 { 7774 return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)), 7775 "Platform does not support port %c\n", port_name(port)); 7776 } 7777 7778 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7779 { 7780 struct intel_encoder *encoder; 7781 bool dpd_is_edp = false; 7782 7783 intel_pps_unlock_regs_wa(dev_priv); 7784 7785 if (!HAS_DISPLAY(dev_priv)) 7786 return; 7787 7788 if (HAS_DDI(dev_priv)) { 7789 if (intel_ddi_crt_present(dev_priv)) 7790 intel_crt_init(dev_priv); 7791 7792 intel_bios_for_each_encoder(dev_priv, intel_ddi_init); 7793 7794 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 7795 vlv_dsi_init(dev_priv); 7796 } else if (HAS_PCH_SPLIT(dev_priv)) { 7797 int found; 7798 7799 /* 7800 * intel_edp_init_connector() depends on this completing first, 7801 * to prevent the registration of both eDP and LVDS and the 7802 * incorrect sharing of the PPS. 7803 */ 7804 intel_lvds_init(dev_priv); 7805 intel_crt_init(dev_priv); 7806 7807 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7808 7809 if (ilk_has_edp_a(dev_priv)) 7810 g4x_dp_init(dev_priv, DP_A, PORT_A); 7811 7812 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7813 /* PCH SDVOB multiplex with HDMIB */ 7814 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7815 if (!found) 7816 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7817 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7818 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7819 } 7820 7821 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7822 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7823 7824 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7825 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7826 7827 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7828 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7829 7830 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7831 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7832 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7833 bool has_edp, has_port; 7834 7835 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7836 intel_crt_init(dev_priv); 7837 7838 /* 7839 * The DP_DETECTED bit is the latched state of the DDC 7840 * SDA pin at boot. However since eDP doesn't require DDC 7841 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7842 * eDP ports may have been muxed to an alternate function. 7843 * Thus we can't rely on the DP_DETECTED bit alone to detect 7844 * eDP ports. Consult the VBT as well as DP_DETECTED to 7845 * detect eDP ports. 7846 * 7847 * Sadly the straps seem to be missing sometimes even for HDMI 7848 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7849 * and VBT for the presence of the port. Additionally we can't 7850 * trust the port type the VBT declares as we've seen at least 7851 * HDMI ports that the VBT claim are DP or eDP. 7852 */ 7853 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7854 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7855 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7856 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7857 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7858 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7859 7860 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7861 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7862 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7863 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7864 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7865 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7866 7867 if (IS_CHERRYVIEW(dev_priv)) { 7868 /* 7869 * eDP not supported on port D, 7870 * so no need to worry about it 7871 */ 7872 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7873 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7874 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7875 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7876 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7877 } 7878 7879 vlv_dsi_init(dev_priv); 7880 } else if (IS_PINEVIEW(dev_priv)) { 7881 intel_lvds_init(dev_priv); 7882 intel_crt_init(dev_priv); 7883 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7884 bool found = false; 7885 7886 if (IS_MOBILE(dev_priv)) 7887 intel_lvds_init(dev_priv); 7888 7889 intel_crt_init(dev_priv); 7890 7891 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7892 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7893 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7894 if (!found && IS_G4X(dev_priv)) { 7895 drm_dbg_kms(&dev_priv->drm, 7896 "probing HDMI on SDVOB\n"); 7897 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7898 } 7899 7900 if (!found && IS_G4X(dev_priv)) 7901 g4x_dp_init(dev_priv, DP_B, PORT_B); 7902 } 7903 7904 /* Before G4X SDVOC doesn't have its own detect register */ 7905 7906 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7907 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7908 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7909 } 7910 7911 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7912 7913 if (IS_G4X(dev_priv)) { 7914 drm_dbg_kms(&dev_priv->drm, 7915 "probing HDMI on SDVOC\n"); 7916 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7917 } 7918 if (IS_G4X(dev_priv)) 7919 g4x_dp_init(dev_priv, DP_C, PORT_C); 7920 } 7921 7922 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7923 g4x_dp_init(dev_priv, DP_D, PORT_D); 7924 7925 if (SUPPORTS_TV(dev_priv)) 7926 intel_tv_init(dev_priv); 7927 } else if (DISPLAY_VER(dev_priv) == 2) { 7928 if (IS_I85X(dev_priv)) 7929 intel_lvds_init(dev_priv); 7930 7931 intel_crt_init(dev_priv); 7932 intel_dvo_init(dev_priv); 7933 } 7934 7935 for_each_intel_encoder(&dev_priv->drm, encoder) { 7936 encoder->base.possible_crtcs = 7937 intel_encoder_possible_crtcs(encoder); 7938 encoder->base.possible_clones = 7939 intel_encoder_possible_clones(encoder); 7940 } 7941 7942 intel_init_pch_refclk(dev_priv); 7943 7944 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7945 } 7946 7947 static int max_dotclock(struct drm_i915_private *i915) 7948 { 7949 int max_dotclock = i915->display.cdclk.max_dotclk_freq; 7950 7951 /* icl+ might use joiner */ 7952 if (DISPLAY_VER(i915) >= 11) 7953 max_dotclock *= 2; 7954 7955 return max_dotclock; 7956 } 7957 7958 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7959 const struct drm_display_mode *mode) 7960 { 7961 struct drm_i915_private *dev_priv = to_i915(dev); 7962 int hdisplay_max, htotal_max; 7963 int vdisplay_max, vtotal_max; 7964 7965 /* 7966 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7967 * of DBLSCAN modes to the output's mode list when they detect 7968 * the scaling mode property on the connector. And they don't 7969 * ask the kernel to validate those modes in any way until 7970 * modeset time at which point the client gets a protocol error. 7971 * So in order to not upset those clients we silently ignore the 7972 * DBLSCAN flag on such connectors. For other connectors we will 7973 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7974 * And we always reject DBLSCAN modes in connector->mode_valid() 7975 * as we never want such modes on the connector's mode list. 7976 */ 7977 7978 if (mode->vscan > 1) 7979 return MODE_NO_VSCAN; 7980 7981 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7982 return MODE_H_ILLEGAL; 7983 7984 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7985 DRM_MODE_FLAG_NCSYNC | 7986 DRM_MODE_FLAG_PCSYNC)) 7987 return MODE_HSYNC; 7988 7989 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7990 DRM_MODE_FLAG_PIXMUX | 7991 DRM_MODE_FLAG_CLKDIV2)) 7992 return MODE_BAD; 7993 7994 /* 7995 * Reject clearly excessive dotclocks early to 7996 * avoid having to worry about huge integers later. 7997 */ 7998 if (mode->clock > max_dotclock(dev_priv)) 7999 return MODE_CLOCK_HIGH; 8000 8001 /* Transcoder timing limits */ 8002 if (DISPLAY_VER(dev_priv) >= 11) { 8003 hdisplay_max = 16384; 8004 vdisplay_max = 8192; 8005 htotal_max = 16384; 8006 vtotal_max = 8192; 8007 } else if (DISPLAY_VER(dev_priv) >= 9 || 8008 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8009 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8010 vdisplay_max = 4096; 8011 htotal_max = 8192; 8012 vtotal_max = 8192; 8013 } else if (DISPLAY_VER(dev_priv) >= 3) { 8014 hdisplay_max = 4096; 8015 vdisplay_max = 4096; 8016 htotal_max = 8192; 8017 vtotal_max = 8192; 8018 } else { 8019 hdisplay_max = 2048; 8020 vdisplay_max = 2048; 8021 htotal_max = 4096; 8022 vtotal_max = 4096; 8023 } 8024 8025 if (mode->hdisplay > hdisplay_max || 8026 mode->hsync_start > htotal_max || 8027 mode->hsync_end > htotal_max || 8028 mode->htotal > htotal_max) 8029 return MODE_H_ILLEGAL; 8030 8031 if (mode->vdisplay > vdisplay_max || 8032 mode->vsync_start > vtotal_max || 8033 mode->vsync_end > vtotal_max || 8034 mode->vtotal > vtotal_max) 8035 return MODE_V_ILLEGAL; 8036 8037 return MODE_OK; 8038 } 8039 8040 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, 8041 const struct drm_display_mode *mode) 8042 { 8043 /* 8044 * Additional transcoder timing limits, 8045 * excluding BXT/GLK DSI transcoders. 8046 */ 8047 if (DISPLAY_VER(dev_priv) >= 5) { 8048 if (mode->hdisplay < 64 || 8049 mode->htotal - mode->hdisplay < 32) 8050 return MODE_H_ILLEGAL; 8051 8052 if (mode->vtotal - mode->vdisplay < 5) 8053 return MODE_V_ILLEGAL; 8054 } else { 8055 if (mode->htotal - mode->hdisplay < 32) 8056 return MODE_H_ILLEGAL; 8057 8058 if (mode->vtotal - mode->vdisplay < 3) 8059 return MODE_V_ILLEGAL; 8060 } 8061 8062 /* 8063 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8064 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8065 */ 8066 if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) && 8067 mode->hsync_start == mode->hdisplay) 8068 return MODE_H_ILLEGAL; 8069 8070 return MODE_OK; 8071 } 8072 8073 enum drm_mode_status 8074 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8075 const struct drm_display_mode *mode, 8076 bool joiner) 8077 { 8078 int plane_width_max, plane_height_max; 8079 8080 /* 8081 * intel_mode_valid() should be 8082 * sufficient on older platforms. 8083 */ 8084 if (DISPLAY_VER(dev_priv) < 9) 8085 return MODE_OK; 8086 8087 /* 8088 * Most people will probably want a fullscreen 8089 * plane so let's not advertize modes that are 8090 * too big for that. 8091 */ 8092 if (DISPLAY_VER(dev_priv) >= 11) { 8093 plane_width_max = 5120 << joiner; 8094 plane_height_max = 4320; 8095 } else { 8096 plane_width_max = 5120; 8097 plane_height_max = 4096; 8098 } 8099 8100 if (mode->hdisplay > plane_width_max) 8101 return MODE_H_ILLEGAL; 8102 8103 if (mode->vdisplay > plane_height_max) 8104 return MODE_V_ILLEGAL; 8105 8106 return MODE_OK; 8107 } 8108 8109 static const struct intel_display_funcs skl_display_funcs = { 8110 .get_pipe_config = hsw_get_pipe_config, 8111 .crtc_enable = hsw_crtc_enable, 8112 .crtc_disable = hsw_crtc_disable, 8113 .commit_modeset_enables = skl_commit_modeset_enables, 8114 .get_initial_plane_config = skl_get_initial_plane_config, 8115 .fixup_initial_plane_config = skl_fixup_initial_plane_config, 8116 }; 8117 8118 static const struct intel_display_funcs ddi_display_funcs = { 8119 .get_pipe_config = hsw_get_pipe_config, 8120 .crtc_enable = hsw_crtc_enable, 8121 .crtc_disable = hsw_crtc_disable, 8122 .commit_modeset_enables = intel_commit_modeset_enables, 8123 .get_initial_plane_config = i9xx_get_initial_plane_config, 8124 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8125 }; 8126 8127 static const struct intel_display_funcs pch_split_display_funcs = { 8128 .get_pipe_config = ilk_get_pipe_config, 8129 .crtc_enable = ilk_crtc_enable, 8130 .crtc_disable = ilk_crtc_disable, 8131 .commit_modeset_enables = intel_commit_modeset_enables, 8132 .get_initial_plane_config = i9xx_get_initial_plane_config, 8133 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8134 }; 8135 8136 static const struct intel_display_funcs vlv_display_funcs = { 8137 .get_pipe_config = i9xx_get_pipe_config, 8138 .crtc_enable = valleyview_crtc_enable, 8139 .crtc_disable = i9xx_crtc_disable, 8140 .commit_modeset_enables = intel_commit_modeset_enables, 8141 .get_initial_plane_config = i9xx_get_initial_plane_config, 8142 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8143 }; 8144 8145 static const struct intel_display_funcs i9xx_display_funcs = { 8146 .get_pipe_config = i9xx_get_pipe_config, 8147 .crtc_enable = i9xx_crtc_enable, 8148 .crtc_disable = i9xx_crtc_disable, 8149 .commit_modeset_enables = intel_commit_modeset_enables, 8150 .get_initial_plane_config = i9xx_get_initial_plane_config, 8151 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8152 }; 8153 8154 /** 8155 * intel_init_display_hooks - initialize the display modesetting hooks 8156 * @dev_priv: device private 8157 */ 8158 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8159 { 8160 if (DISPLAY_VER(dev_priv) >= 9) { 8161 dev_priv->display.funcs.display = &skl_display_funcs; 8162 } else if (HAS_DDI(dev_priv)) { 8163 dev_priv->display.funcs.display = &ddi_display_funcs; 8164 } else if (HAS_PCH_SPLIT(dev_priv)) { 8165 dev_priv->display.funcs.display = &pch_split_display_funcs; 8166 } else if (IS_CHERRYVIEW(dev_priv) || 8167 IS_VALLEYVIEW(dev_priv)) { 8168 dev_priv->display.funcs.display = &vlv_display_funcs; 8169 } else { 8170 dev_priv->display.funcs.display = &i9xx_display_funcs; 8171 } 8172 } 8173 8174 int intel_initial_commit(struct drm_device *dev) 8175 { 8176 struct drm_atomic_state *state = NULL; 8177 struct drm_modeset_acquire_ctx ctx; 8178 struct intel_crtc *crtc; 8179 int ret = 0; 8180 8181 state = drm_atomic_state_alloc(dev); 8182 if (!state) 8183 return -ENOMEM; 8184 8185 drm_modeset_acquire_init(&ctx, 0); 8186 8187 state->acquire_ctx = &ctx; 8188 to_intel_atomic_state(state)->internal = true; 8189 8190 retry: 8191 for_each_intel_crtc(dev, crtc) { 8192 struct intel_crtc_state *crtc_state = 8193 intel_atomic_get_crtc_state(state, crtc); 8194 8195 if (IS_ERR(crtc_state)) { 8196 ret = PTR_ERR(crtc_state); 8197 goto out; 8198 } 8199 8200 if (crtc_state->hw.active) { 8201 struct intel_encoder *encoder; 8202 8203 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8204 if (ret) 8205 goto out; 8206 8207 /* 8208 * FIXME hack to force a LUT update to avoid the 8209 * plane update forcing the pipe gamma on without 8210 * having a proper LUT loaded. Remove once we 8211 * have readout for pipe gamma enable. 8212 */ 8213 crtc_state->uapi.color_mgmt_changed = true; 8214 8215 for_each_intel_encoder_mask(dev, encoder, 8216 crtc_state->uapi.encoder_mask) { 8217 if (encoder->initial_fastset_check && 8218 !encoder->initial_fastset_check(encoder, crtc_state)) { 8219 ret = drm_atomic_add_affected_connectors(state, 8220 &crtc->base); 8221 if (ret) 8222 goto out; 8223 } 8224 } 8225 } 8226 } 8227 8228 ret = drm_atomic_commit(state); 8229 8230 out: 8231 if (ret == -EDEADLK) { 8232 drm_atomic_state_clear(state); 8233 drm_modeset_backoff(&ctx); 8234 goto retry; 8235 } 8236 8237 drm_atomic_state_put(state); 8238 8239 drm_modeset_drop_locks(&ctx); 8240 drm_modeset_acquire_fini(&ctx); 8241 8242 return ret; 8243 } 8244 8245 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8246 { 8247 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8248 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8249 /* 640x480@60Hz, ~25175 kHz */ 8250 struct dpll clock = { 8251 .m1 = 18, 8252 .m2 = 7, 8253 .p1 = 13, 8254 .p2 = 4, 8255 .n = 2, 8256 }; 8257 u32 dpll, fp; 8258 int i; 8259 8260 drm_WARN_ON(&dev_priv->drm, 8261 i9xx_calc_dpll_params(48000, &clock) != 25154); 8262 8263 drm_dbg_kms(&dev_priv->drm, 8264 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8265 pipe_name(pipe), clock.vco, clock.dot); 8266 8267 fp = i9xx_dpll_compute_fp(&clock); 8268 dpll = DPLL_DVO_2X_MODE | 8269 DPLL_VGA_MODE_DIS | 8270 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8271 PLL_P2_DIVIDE_BY_4 | 8272 PLL_REF_INPUT_DREFCLK | 8273 DPLL_VCO_ENABLE; 8274 8275 intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), 8276 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8277 intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), 8278 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8279 intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), 8280 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8281 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), 8282 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8283 intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), 8284 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8285 intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), 8286 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8287 intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), 8288 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8289 8290 intel_de_write(dev_priv, FP0(pipe), fp); 8291 intel_de_write(dev_priv, FP1(pipe), fp); 8292 8293 /* 8294 * Apparently we need to have VGA mode enabled prior to changing 8295 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8296 * dividers, even though the register value does change. 8297 */ 8298 intel_de_write(dev_priv, DPLL(dev_priv, pipe), 8299 dpll & ~DPLL_VGA_MODE_DIS); 8300 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); 8301 8302 /* Wait for the clocks to stabilize. */ 8303 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); 8304 udelay(150); 8305 8306 /* The pixel multiplier can only be updated once the 8307 * DPLL is enabled and the clocks are stable. 8308 * 8309 * So write it again. 8310 */ 8311 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); 8312 8313 /* We do this three times for luck */ 8314 for (i = 0; i < 3 ; i++) { 8315 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); 8316 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); 8317 udelay(150); /* wait for warmup */ 8318 } 8319 8320 intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE); 8321 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); 8322 8323 intel_wait_for_pipe_scanline_moving(crtc); 8324 } 8325 8326 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8327 { 8328 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8329 8330 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 8331 pipe_name(pipe)); 8332 8333 drm_WARN_ON(&dev_priv->drm, 8334 intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE); 8335 drm_WARN_ON(&dev_priv->drm, 8336 intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE); 8337 drm_WARN_ON(&dev_priv->drm, 8338 intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE); 8339 drm_WARN_ON(&dev_priv->drm, 8340 intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK); 8341 drm_WARN_ON(&dev_priv->drm, 8342 intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK); 8343 8344 intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0); 8345 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); 8346 8347 intel_wait_for_pipe_scanline_stopped(crtc); 8348 8349 intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); 8350 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); 8351 } 8352 8353 void intel_hpd_poll_fini(struct drm_i915_private *i915) 8354 { 8355 struct intel_connector *connector; 8356 struct drm_connector_list_iter conn_iter; 8357 8358 /* Kill all the work that may have been queued by hpd. */ 8359 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8360 for_each_intel_connector_iter(connector, &conn_iter) { 8361 if (connector->modeset_retry_work.func && 8362 cancel_work_sync(&connector->modeset_retry_work)) 8363 drm_connector_put(&connector->base); 8364 if (connector->hdcp.shim) { 8365 cancel_delayed_work_sync(&connector->hdcp.check_work); 8366 cancel_work_sync(&connector->hdcp.prop_work); 8367 } 8368 } 8369 drm_connector_list_iter_end(&conn_iter); 8370 } 8371 8372 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8373 { 8374 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8375 } 8376