1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef MLX5_ABI_USER_H 36 #define MLX5_ABI_USER_H 37 38 #ifdef _KERNEL 39 #include <linux/types.h> 40 #else 41 #include <infiniband/types.h> 42 #endif 43 44 enum { 45 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 46 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 47 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 48 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 49 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 50 }; 51 52 enum { 53 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 54 }; 55 56 enum { 57 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 58 }; 59 60 /* Increment this value if any changes that break userspace ABI 61 * compatibility are made. 62 */ 63 #define MLX5_IB_UVERBS_ABI_VERSION 1 64 65 /* Make sure that all structs defined in this file remain laid out so 66 * that they pack the same way on 32-bit and 64-bit architectures (to 67 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 68 * In particular do not use pointer types -- pass pointers in __u64 69 * instead. 70 */ 71 72 struct mlx5_ib_alloc_ucontext_req { 73 __u32 total_num_bfregs; 74 __u32 num_low_latency_bfregs; 75 }; 76 77 enum mlx5_lib_caps { 78 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 79 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, 80 }; 81 82 enum mlx5_ib_alloc_uctx_v2_flags { 83 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 84 }; 85 struct mlx5_ib_alloc_ucontext_req_v2 { 86 __u32 total_num_bfregs; 87 __u32 num_low_latency_bfregs; 88 __u32 flags; 89 __u32 comp_mask; 90 __u8 max_cqe_version; 91 __u8 reserved0; 92 __u16 reserved1; 93 __u32 reserved2; 94 __aligned_u64 lib_caps; 95 }; 96 97 enum mlx5_ib_alloc_ucontext_resp_mask { 98 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 99 }; 100 101 enum mlx5_user_cmds_supp_uhw { 102 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 103 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 104 }; 105 106 struct mlx5_ib_alloc_ucontext_resp { 107 __u32 qp_tab_size; 108 __u32 bf_reg_size; 109 __u32 tot_bfregs; 110 __u32 cache_line_size; 111 __u16 max_sq_desc_sz; 112 __u16 max_rq_desc_sz; 113 __u32 max_send_wqebb; 114 __u32 max_recv_wr; 115 __u32 max_srq_recv_wr; 116 __u16 num_ports; 117 __u16 reserved1; 118 __u32 comp_mask; 119 __u32 response_length; 120 __u8 cqe_version; 121 __u8 cmds_supp_uhw; 122 __u16 reserved2; 123 __u64 hca_core_clock_offset; 124 __u32 log_uar_size; 125 __u32 num_uars_per_page; 126 __u32 num_dyn_bfregs; 127 }; 128 129 struct mlx5_ib_alloc_pd_resp { 130 __u32 pdn; 131 }; 132 133 struct mlx5_ib_tso_caps { 134 __u32 max_tso; /* Maximum tso payload size in bytes */ 135 136 /* Corresponding bit will be set if qp type from 137 * 'enum ib_qp_type' is supported, e.g. 138 * supported_qpts |= 1 << IB_QPT_UD 139 */ 140 __u32 supported_qpts; 141 }; 142 143 struct mlx5_ib_rss_caps { 144 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 145 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 146 __u8 reserved[7]; 147 }; 148 149 struct mlx5_packet_pacing_caps { 150 __u32 qp_rate_limit_min; 151 __u32 qp_rate_limit_max; /* In kpbs */ 152 153 /* Corresponding bit will be set if qp type from 154 * 'enum ib_qp_type' is supported, e.g. 155 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 156 */ 157 __u32 supported_qpts; 158 __u32 reserved; 159 }; 160 161 enum mlx5_ib_cqe_comp_res_format { 162 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 163 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 164 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 165 }; 166 167 struct mlx5_ib_cqe_comp_caps { 168 __u32 max_num; 169 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 170 }; 171 172 enum mlx5_ib_sw_parsing_offloads { 173 MLX5_IB_SW_PARSING = 1 << 0, 174 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 175 MLX5_IB_SW_PARSING_LSO = 1 << 2, 176 }; 177 178 struct mlx5_ib_sw_parsing_caps { 179 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 180 181 /* Corresponding bit will be set if qp type from 182 * 'enum ib_qp_type' is supported, e.g. 183 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 184 */ 185 __u32 supported_qpts; 186 }; 187 188 struct mlx5_ib_striding_rq_caps { 189 __u32 min_single_stride_log_num_of_bytes; 190 __u32 max_single_stride_log_num_of_bytes; 191 __u32 min_single_wqe_log_num_of_strides; 192 __u32 max_single_wqe_log_num_of_strides; 193 194 /* Corresponding bit will be set if qp type from 195 * 'enum ib_qp_type' is supported, e.g. 196 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 197 */ 198 __u32 supported_qpts; 199 __u32 reserved; 200 }; 201 202 enum mlx5_ib_tunnel_offloads { 203 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 204 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 205 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 206 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 207 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 208 }; 209 210 struct mlx5_ib_query_device_resp { 211 __u32 comp_mask; 212 __u32 response_length; 213 struct mlx5_ib_tso_caps tso_caps; 214 struct mlx5_ib_rss_caps rss_caps; 215 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 216 struct mlx5_packet_pacing_caps packet_pacing_caps; 217 __u32 mlx5_ib_support_multi_pkt_send_wqes; 218 __u32 reserved; 219 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 220 struct mlx5_ib_striding_rq_caps striding_rq_caps; 221 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 222 __u32 reserved3; 223 }; 224 225 enum mlx5_ib_create_cq_flags { 226 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 227 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 228 }; 229 230 struct mlx5_ib_create_cq { 231 __u64 buf_addr; 232 __u64 db_addr; 233 __u32 cqe_size; 234 __u16 flags; 235 __u16 uar_page_index; 236 __u8 cqe_comp_en; 237 __u8 cqe_comp_res_format; 238 __u16 reserved0; 239 __u32 reserved1; 240 }; 241 242 struct mlx5_ib_create_cq_resp { 243 __u32 cqn; 244 __u32 reserved; 245 }; 246 247 struct mlx5_ib_resize_cq { 248 __u64 buf_addr; 249 __u16 cqe_size; 250 __u16 reserved0; 251 __u32 reserved1; 252 }; 253 254 struct mlx5_ib_create_srq { 255 __u64 buf_addr; 256 __u64 db_addr; 257 __u32 flags; 258 __u32 reserved0; /* explicit padding (optional on i386) */ 259 __u32 uidx; 260 __u32 reserved1; 261 }; 262 263 struct mlx5_ib_create_srq_resp { 264 __u32 srqn; 265 __u32 reserved; 266 }; 267 268 struct mlx5_ib_create_qp { 269 __u64 buf_addr; 270 __u64 db_addr; 271 __u32 sq_wqe_count; 272 __u32 rq_wqe_count; 273 __u32 rq_wqe_shift; 274 __u32 flags; 275 __u32 uidx; 276 __u32 bfreg_index; 277 __u64 sq_buf_addr; 278 }; 279 280 /* RX Hash function flags */ 281 enum mlx5_rx_hash_function_flags { 282 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 283 }; 284 285 /* 286 * RX Hash flags, these flags allows to set which incoming packet's field should 287 * participates in RX Hash. Each flag represent certain packet's field, 288 * when the flag is set the field that is represented by the flag will 289 * participate in RX Hash calculation. 290 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 291 * and *TCP and *UDP flags can't be enabled together on the same QP. 292 */ 293 enum mlx5_rx_hash_fields { 294 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 295 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 296 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 297 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 298 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 299 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 300 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 301 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 302 /* Save bits for future fields */ 303 MLX5_RX_HASH_INNER = (1UL << 31), 304 }; 305 306 struct mlx5_ib_create_qp_rss { 307 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 308 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 309 __u8 rx_key_len; /* valid only for Toeplitz */ 310 __u8 reserved[6]; 311 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 312 __u32 comp_mask; 313 __u32 flags; 314 }; 315 316 struct mlx5_ib_create_qp_resp { 317 __u32 bfreg_index; 318 }; 319 320 struct mlx5_ib_alloc_mw { 321 __u32 comp_mask; 322 __u8 num_klms; 323 __u8 reserved1; 324 __u16 reserved2; 325 }; 326 327 enum mlx5_ib_create_wq_mask { 328 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 329 }; 330 331 struct mlx5_ib_create_wq { 332 __u64 buf_addr; 333 __u64 db_addr; 334 __u32 rq_wqe_count; 335 __u32 rq_wqe_shift; 336 __u32 user_index; 337 __u32 flags; 338 __u32 comp_mask; 339 __u32 single_stride_log_num_of_bytes; 340 __u32 single_wqe_log_num_of_strides; 341 __u32 two_byte_shift_en; 342 }; 343 344 struct mlx5_ib_create_ah_resp { 345 __u32 response_length; 346 __u8 dmac[ETH_ALEN]; 347 __u8 reserved[6]; 348 }; 349 350 struct mlx5_ib_create_wq_resp { 351 __u32 response_length; 352 __u32 reserved; 353 }; 354 355 struct mlx5_ib_create_rwq_ind_tbl_resp { 356 __u32 response_length; 357 __u32 reserved; 358 }; 359 360 struct mlx5_ib_modify_wq { 361 __u32 comp_mask; 362 __u32 reserved; 363 }; 364 365 enum mlx5_ib_mmap_cmd { 366 MLX5_IB_MMAP_REGULAR_PAGE = 0, 367 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 368 MLX5_IB_MMAP_WC_PAGE = 2, 369 MLX5_IB_MMAP_NC_PAGE = 3, 370 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 371 MLX5_IB_MMAP_CORE_CLOCK = 5, 372 MLX5_IB_MMAP_ALLOC_WC = 6, 373 MLX5_IB_MMAP_CLOCK_INFO = 7, 374 MLX5_IB_MMAP_DEVICE_MEM = 8, 375 }; 376 377 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 378 enum { 379 MLX5_IB_CLOCK_INFO_V1 = 0, 380 }; 381 382 struct mlx5_ib_flow_counters_desc { 383 __u32 description; 384 __u32 index; 385 }; 386 387 struct mlx5_ib_flow_counters_data { 388 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 389 __u32 ncounters; 390 __u32 reserved; 391 }; 392 393 struct mlx5_ib_create_flow { 394 __u32 ncounters_data; 395 __u32 reserved; 396 /* 397 * Following are counters data based on ncounters_data, each 398 * entry in the data[] should match a corresponding counter object 399 * that was pointed by a counters spec upon the flow creation 400 */ 401 struct mlx5_ib_flow_counters_data data[]; 402 }; 403 404 #endif /* MLX5_ABI_USER_H */ 405