1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/module.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/ata.h>
34 #include <sys/bus.h>
35 #include <sys/conf.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <vm/uma.h>
41 #include <machine/stdarg.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
44 #include <sys/rman.h>
45 #include <dev/pci/pcivar.h>
46 #include "mvs.h"
47
48 #include <cam/cam.h>
49 #include <cam/cam_ccb.h>
50 #include <cam/cam_sim.h>
51 #include <cam/cam_xpt_sim.h>
52 #include <cam/cam_debug.h>
53
54 /* local prototypes */
55 static int mvs_ch_init(device_t dev);
56 static int mvs_ch_deinit(device_t dev);
57 static int mvs_ch_suspend(device_t dev);
58 static int mvs_ch_resume(device_t dev);
59 static void mvs_dmainit(device_t dev);
60 static void mvs_dmasetupc_cb(void *xsc,
61 bus_dma_segment_t *segs, int nsegs, int error);
62 static void mvs_dmafini(device_t dev);
63 static void mvs_slotsalloc(device_t dev);
64 static void mvs_slotsfree(device_t dev);
65 static void mvs_setup_edma_queues(device_t dev);
66 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode);
67 static void mvs_ch_pm(void *arg);
68 static void mvs_ch_intr_locked(void *data);
69 static void mvs_ch_intr(void *data);
70 static void mvs_reset(device_t dev);
71 static void mvs_softreset(device_t dev, union ccb *ccb);
72
73 static int mvs_sata_connect(struct mvs_channel *ch);
74 static int mvs_sata_phy_reset(device_t dev);
75 static int mvs_wait(device_t dev, u_int s, u_int c, int t);
76 static void mvs_tfd_read(device_t dev, union ccb *ccb);
77 static void mvs_tfd_write(device_t dev, union ccb *ccb);
78 static void mvs_legacy_intr(device_t dev, int poll);
79 static void mvs_crbq_intr(device_t dev);
80 static void mvs_begin_transaction(device_t dev, union ccb *ccb);
81 static void mvs_legacy_execute_transaction(struct mvs_slot *slot);
82 static void mvs_timeout(void *arg);
83 static void mvs_dmasetprd(void *arg,
84 bus_dma_segment_t *segs, int nsegs, int error);
85 static void mvs_requeue_frozen(device_t dev);
86 static void mvs_execute_transaction(struct mvs_slot *slot);
87 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et);
88
89 static void mvs_issue_recovery(device_t dev);
90 static void mvs_process_read_log(device_t dev, union ccb *ccb);
91 static void mvs_process_request_sense(device_t dev, union ccb *ccb);
92
93 static void mvsaction(struct cam_sim *sim, union ccb *ccb);
94 static void mvspoll(struct cam_sim *sim);
95
96 static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers");
97
98 #define recovery_type spriv_field0
99 #define RECOVERY_NONE 0
100 #define RECOVERY_READ_LOG 1
101 #define RECOVERY_REQUEST_SENSE 2
102 #define recovery_slot spriv_field1
103
104 static int
mvs_ch_probe(device_t dev)105 mvs_ch_probe(device_t dev)
106 {
107
108 device_set_desc(dev, "Marvell SATA channel");
109 return (BUS_PROBE_DEFAULT);
110 }
111
112 static int
mvs_ch_attach(device_t dev)113 mvs_ch_attach(device_t dev)
114 {
115 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev));
116 struct mvs_channel *ch = device_get_softc(dev);
117 struct cam_devq *devq;
118 int rid, error, i, sata_rev = 0;
119
120 ch->dev = dev;
121 ch->unit = (intptr_t)device_get_ivars(dev);
122 ch->quirks = ctlr->quirks;
123 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF);
124 ch->pm_level = 0;
125 resource_int_value(device_get_name(dev),
126 device_get_unit(dev), "pm_level", &ch->pm_level);
127 if (ch->pm_level > 3)
128 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
129 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
130 resource_int_value(device_get_name(dev),
131 device_get_unit(dev), "sata_rev", &sata_rev);
132 for (i = 0; i < 16; i++) {
133 ch->user[i].revision = sata_rev;
134 ch->user[i].mode = 0;
135 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048;
136 ch->user[i].tags = MVS_MAX_SLOTS;
137 ch->curr[i] = ch->user[i];
138 if (ch->pm_level) {
139 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
140 CTS_SATA_CAPS_H_APST |
141 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
142 }
143 ch->user[i].caps |= CTS_SATA_CAPS_H_AN;
144 }
145 rid = ch->unit;
146 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
147 &rid, RF_ACTIVE)))
148 return (ENXIO);
149 mvs_dmainit(dev);
150 mvs_slotsalloc(dev);
151 mvs_ch_init(dev);
152 mtx_lock(&ch->mtx);
153 rid = ATA_IRQ_RID;
154 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
155 &rid, RF_SHAREABLE | RF_ACTIVE))) {
156 device_printf(dev, "Unable to map interrupt\n");
157 error = ENXIO;
158 goto err0;
159 }
160 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
161 mvs_ch_intr_locked, dev, &ch->ih))) {
162 device_printf(dev, "Unable to setup interrupt\n");
163 error = ENXIO;
164 goto err1;
165 }
166 /* Create the device queue for our SIM. */
167 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1);
168 if (devq == NULL) {
169 device_printf(dev, "Unable to allocate simq\n");
170 error = ENOMEM;
171 goto err1;
172 }
173 /* Construct SIM entry */
174 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch,
175 device_get_unit(dev), &ch->mtx,
176 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1,
177 devq);
178 if (ch->sim == NULL) {
179 cam_simq_free(devq);
180 device_printf(dev, "unable to allocate sim\n");
181 error = ENOMEM;
182 goto err1;
183 }
184 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
185 device_printf(dev, "unable to register xpt bus\n");
186 error = ENXIO;
187 goto err2;
188 }
189 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
190 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
191 device_printf(dev, "unable to create path\n");
192 error = ENXIO;
193 goto err3;
194 }
195 if (ch->pm_level > 3) {
196 callout_reset(&ch->pm_timer,
197 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
198 mvs_ch_pm, dev);
199 }
200 mtx_unlock(&ch->mtx);
201 return (0);
202
203 err3:
204 xpt_bus_deregister(cam_sim_path(ch->sim));
205 err2:
206 cam_sim_free(ch->sim, /*free_devq*/TRUE);
207 err1:
208 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
209 err0:
210 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
211 mtx_unlock(&ch->mtx);
212 mtx_destroy(&ch->mtx);
213 return (error);
214 }
215
216 static int
mvs_ch_detach(device_t dev)217 mvs_ch_detach(device_t dev)
218 {
219 struct mvs_channel *ch = device_get_softc(dev);
220
221 mtx_lock(&ch->mtx);
222 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
223 /* Forget about reset. */
224 if (ch->resetting) {
225 ch->resetting = 0;
226 xpt_release_simq(ch->sim, TRUE);
227 }
228 xpt_free_path(ch->path);
229 xpt_bus_deregister(cam_sim_path(ch->sim));
230 cam_sim_free(ch->sim, /*free_devq*/TRUE);
231 mtx_unlock(&ch->mtx);
232
233 if (ch->pm_level > 3)
234 callout_drain(&ch->pm_timer);
235 callout_drain(&ch->reset_timer);
236 bus_teardown_intr(dev, ch->r_irq, ch->ih);
237 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
238
239 mvs_ch_deinit(dev);
240 mvs_slotsfree(dev);
241 mvs_dmafini(dev);
242
243 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
244 mtx_destroy(&ch->mtx);
245 return (0);
246 }
247
248 static int
mvs_ch_init(device_t dev)249 mvs_ch_init(device_t dev)
250 {
251 struct mvs_channel *ch = device_get_softc(dev);
252 uint32_t reg;
253
254 /* Disable port interrupts */
255 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
256 /* Stop EDMA */
257 ch->curr_mode = MVS_EDMA_UNKNOWN;
258 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
259 /* Clear and configure FIS interrupts. */
260 ATA_OUTL(ch->r_mem, SATA_FISIC, 0);
261 reg = ATA_INL(ch->r_mem, SATA_FISC);
262 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
263 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
264 reg = ATA_INL(ch->r_mem, SATA_FISIM);
265 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
266 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
267 /* Clear SATA error register. */
268 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
269 /* Clear any outstanding error interrupts. */
270 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
271 /* Unmask all error interrupts */
272 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
273 return (0);
274 }
275
276 static int
mvs_ch_deinit(device_t dev)277 mvs_ch_deinit(device_t dev)
278 {
279 struct mvs_channel *ch = device_get_softc(dev);
280
281 /* Stop EDMA */
282 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
283 /* Disable port interrupts. */
284 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
285 return (0);
286 }
287
288 static int
mvs_ch_suspend(device_t dev)289 mvs_ch_suspend(device_t dev)
290 {
291 struct mvs_channel *ch = device_get_softc(dev);
292
293 mtx_lock(&ch->mtx);
294 xpt_freeze_simq(ch->sim, 1);
295 while (ch->oslots)
296 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100);
297 /* Forget about reset. */
298 if (ch->resetting) {
299 ch->resetting = 0;
300 callout_stop(&ch->reset_timer);
301 xpt_release_simq(ch->sim, TRUE);
302 }
303 mvs_ch_deinit(dev);
304 mtx_unlock(&ch->mtx);
305 return (0);
306 }
307
308 static int
mvs_ch_resume(device_t dev)309 mvs_ch_resume(device_t dev)
310 {
311 struct mvs_channel *ch = device_get_softc(dev);
312
313 mtx_lock(&ch->mtx);
314 mvs_ch_init(dev);
315 mvs_reset(dev);
316 xpt_release_simq(ch->sim, TRUE);
317 mtx_unlock(&ch->mtx);
318 return (0);
319 }
320
321 struct mvs_dc_cb_args {
322 bus_addr_t maddr;
323 int error;
324 };
325
326 static void
mvs_dmainit(device_t dev)327 mvs_dmainit(device_t dev)
328 {
329 struct mvs_channel *ch = device_get_softc(dev);
330 struct mvs_dc_cb_args dcba;
331
332 /* EDMA command request area. */
333 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
334 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
335 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE,
336 0, NULL, NULL, &ch->dma.workrq_tag))
337 goto error;
338 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0,
339 &ch->dma.workrq_map))
340 goto error;
341 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map,
342 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
343 dcba.error) {
344 bus_dmamem_free(ch->dma.workrq_tag,
345 ch->dma.workrq, ch->dma.workrq_map);
346 goto error;
347 }
348 ch->dma.workrq_bus = dcba.maddr;
349 /* EDMA command response area. */
350 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0,
351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
352 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE,
353 0, NULL, NULL, &ch->dma.workrp_tag))
354 goto error;
355 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0,
356 &ch->dma.workrp_map))
357 goto error;
358 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map,
359 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
360 dcba.error) {
361 bus_dmamem_free(ch->dma.workrp_tag,
362 ch->dma.workrp, ch->dma.workrp_map);
363 goto error;
364 }
365 ch->dma.workrp_bus = dcba.maddr;
366 /* Data area. */
367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX,
368 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
369 NULL, NULL,
370 MVS_SG_ENTRIES * PAGE_SIZE, MVS_SG_ENTRIES, MVS_EPRD_MAX,
371 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
372 goto error;
373 }
374 return;
375
376 error:
377 device_printf(dev, "WARNING - DMA initialization failed\n");
378 mvs_dmafini(dev);
379 }
380
381 static void
mvs_dmasetupc_cb(void * xsc,bus_dma_segment_t * segs,int nsegs,int error)382 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
383 {
384 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc;
385
386 if (!(dcba->error = error))
387 dcba->maddr = segs[0].ds_addr;
388 }
389
390 static void
mvs_dmafini(device_t dev)391 mvs_dmafini(device_t dev)
392 {
393 struct mvs_channel *ch = device_get_softc(dev);
394
395 if (ch->dma.data_tag) {
396 bus_dma_tag_destroy(ch->dma.data_tag);
397 ch->dma.data_tag = NULL;
398 }
399 if (ch->dma.workrp_bus) {
400 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map);
401 bus_dmamem_free(ch->dma.workrp_tag,
402 ch->dma.workrp, ch->dma.workrp_map);
403 ch->dma.workrp_bus = 0;
404 ch->dma.workrp = NULL;
405 }
406 if (ch->dma.workrp_tag) {
407 bus_dma_tag_destroy(ch->dma.workrp_tag);
408 ch->dma.workrp_tag = NULL;
409 }
410 if (ch->dma.workrq_bus) {
411 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map);
412 bus_dmamem_free(ch->dma.workrq_tag,
413 ch->dma.workrq, ch->dma.workrq_map);
414 ch->dma.workrq_bus = 0;
415 ch->dma.workrq = NULL;
416 }
417 if (ch->dma.workrq_tag) {
418 bus_dma_tag_destroy(ch->dma.workrq_tag);
419 ch->dma.workrq_tag = NULL;
420 }
421 }
422
423 static void
mvs_slotsalloc(device_t dev)424 mvs_slotsalloc(device_t dev)
425 {
426 struct mvs_channel *ch = device_get_softc(dev);
427 int i;
428
429 /* Alloc and setup command/dma slots */
430 bzero(ch->slot, sizeof(ch->slot));
431 for (i = 0; i < MVS_MAX_SLOTS; i++) {
432 struct mvs_slot *slot = &ch->slot[i];
433
434 slot->dev = dev;
435 slot->slot = i;
436 slot->state = MVS_SLOT_EMPTY;
437 slot->eprd_offset = MVS_EPRD_OFFSET + MVS_EPRD_SIZE * i;
438 slot->ccb = NULL;
439 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
440
441 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
442 device_printf(ch->dev, "FAILURE - create data_map\n");
443 }
444 }
445
446 static void
mvs_slotsfree(device_t dev)447 mvs_slotsfree(device_t dev)
448 {
449 struct mvs_channel *ch = device_get_softc(dev);
450 int i;
451
452 /* Free all dma slots */
453 for (i = 0; i < MVS_MAX_SLOTS; i++) {
454 struct mvs_slot *slot = &ch->slot[i];
455
456 callout_drain(&slot->timeout);
457 if (slot->dma.data_map) {
458 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
459 slot->dma.data_map = NULL;
460 }
461 }
462 }
463
464 static void
mvs_setup_edma_queues(device_t dev)465 mvs_setup_edma_queues(device_t dev)
466 {
467 struct mvs_channel *ch = device_get_softc(dev);
468 uint64_t work;
469
470 /* Requests queue. */
471 work = ch->dma.workrq_bus;
472 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32);
473 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff);
474 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff);
475 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
476 BUS_DMASYNC_PREWRITE);
477 /* Responses queue. */
478 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE);
479 work = ch->dma.workrp_bus;
480 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32);
481 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff);
482 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff);
483 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
484 BUS_DMASYNC_PREREAD);
485 ch->out_idx = 0;
486 ch->in_idx = 0;
487 }
488
489 static void
mvs_set_edma_mode(device_t dev,enum mvs_edma_mode mode)490 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode)
491 {
492 struct mvs_channel *ch = device_get_softc(dev);
493 int timeout;
494 uint32_t ecfg, fcfg, hc, ltm, unkn;
495
496 if (mode == ch->curr_mode)
497 return;
498 /* If we are running, we should stop first. */
499 if (ch->curr_mode != MVS_EDMA_OFF) {
500 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA);
501 timeout = 0;
502 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) {
503 DELAY(1000);
504 if (timeout++ > 1000) {
505 device_printf(dev, "stopping EDMA engine failed\n");
506 break;
507 }
508 }
509 }
510 ch->curr_mode = mode;
511 ch->fbs_enabled = 0;
512 ch->fake_busy = 0;
513 /* Report mode to controller. Needed for correct CCC operation. */
514 MVS_EDMA(device_get_parent(dev), dev, mode);
515 /* Configure new mode. */
516 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN;
517 if (ch->pm_present) {
518 ecfg |= EDMA_CFG_EMASKRXPM;
519 if (ch->quirks & MVS_Q_GENIIE) {
520 ecfg |= EDMA_CFG_EEDMAFBS;
521 ch->fbs_enabled = 1;
522 }
523 }
524 if (ch->quirks & MVS_Q_GENI)
525 ecfg |= EDMA_CFG_ERDBSZ;
526 else if (ch->quirks & MVS_Q_GENII)
527 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN;
528 if (ch->quirks & MVS_Q_CT)
529 ecfg |= EDMA_CFG_ECUTTHROUGHEN;
530 if (mode != MVS_EDMA_OFF)
531 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN;
532 if (mode == MVS_EDMA_QUEUED)
533 ecfg |= EDMA_CFG_EQUE;
534 else if (mode == MVS_EDMA_NCQ)
535 ecfg |= EDMA_CFG_ESATANATVCMDQUE;
536 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg);
537 mvs_setup_edma_queues(dev);
538 if (ch->quirks & MVS_Q_GENIIE) {
539 /* Configure FBS-related registers */
540 fcfg = ATA_INL(ch->r_mem, SATA_FISC);
541 ltm = ATA_INL(ch->r_mem, SATA_LTM);
542 hc = ATA_INL(ch->r_mem, EDMA_HC);
543 if (ch->fbs_enabled) {
544 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP;
545 if (mode == MVS_EDMA_NCQ) {
546 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
547 hc &= ~EDMA_IE_EDEVERR;
548 } else {
549 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0;
550 hc |= EDMA_IE_EDEVERR;
551 }
552 ltm |= (1 << 8);
553 } else {
554 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP;
555 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
556 hc |= EDMA_IE_EDEVERR;
557 ltm &= ~(1 << 8);
558 }
559 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg);
560 ATA_OUTL(ch->r_mem, SATA_LTM, ltm);
561 ATA_OUTL(ch->r_mem, EDMA_HC, hc);
562 /* This is some magic, required to handle several DRQs
563 * with basic DMA. */
564 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD);
565 if (mode == MVS_EDMA_OFF)
566 unkn |= 1;
567 else
568 unkn &= ~1;
569 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn);
570 }
571 /* Run EDMA. */
572 if (mode != MVS_EDMA_OFF)
573 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA);
574 }
575
576 static device_method_t mvsch_methods[] = {
577 DEVMETHOD(device_probe, mvs_ch_probe),
578 DEVMETHOD(device_attach, mvs_ch_attach),
579 DEVMETHOD(device_detach, mvs_ch_detach),
580 DEVMETHOD(device_suspend, mvs_ch_suspend),
581 DEVMETHOD(device_resume, mvs_ch_resume),
582 { 0, 0 }
583 };
584 static driver_t mvsch_driver = {
585 "mvsch",
586 mvsch_methods,
587 sizeof(struct mvs_channel)
588 };
589 DRIVER_MODULE(mvsch, mvs, mvsch_driver, 0, 0);
590 DRIVER_MODULE(mvsch, sata, mvsch_driver, 0, 0);
591
592 static void
mvs_phy_check_events(device_t dev,u_int32_t serr)593 mvs_phy_check_events(device_t dev, u_int32_t serr)
594 {
595 struct mvs_channel *ch = device_get_softc(dev);
596
597 if (ch->pm_level == 0) {
598 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS);
599 union ccb *ccb;
600
601 if (bootverbose) {
602 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
603 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
604 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) {
605 device_printf(dev, "CONNECT requested\n");
606 } else
607 device_printf(dev, "DISCONNECT requested\n");
608 }
609 mvs_reset(dev);
610 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
611 return;
612 if (xpt_create_path(&ccb->ccb_h.path, NULL,
613 cam_sim_path(ch->sim),
614 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
615 xpt_free_ccb(ccb);
616 return;
617 }
618 xpt_rescan(ccb);
619 }
620 }
621
622 static void
mvs_notify_events(device_t dev)623 mvs_notify_events(device_t dev)
624 {
625 struct mvs_channel *ch = device_get_softc(dev);
626 struct cam_path *dpath;
627 uint32_t fis;
628 int d;
629
630 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */
631 fis = ATA_INL(ch->r_mem, SATA_FISDW0);
632 if ((fis & 0x80ff) == 0x80a1)
633 d = (fis & 0x0f00) >> 8;
634 else
635 d = ch->pm_present ? 15 : 0;
636 if (bootverbose)
637 device_printf(dev, "SNTF %d\n", d);
638 if (xpt_create_path(&dpath, NULL,
639 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) {
640 xpt_async(AC_SCSI_AEN, dpath, NULL);
641 xpt_free_path(dpath);
642 }
643 }
644
645 static void
mvs_ch_intr_locked(void * data)646 mvs_ch_intr_locked(void *data)
647 {
648 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
649 device_t dev = (device_t)arg->arg;
650 struct mvs_channel *ch = device_get_softc(dev);
651
652 mtx_lock(&ch->mtx);
653 mvs_ch_intr(data);
654 mtx_unlock(&ch->mtx);
655 }
656
657 static void
mvs_ch_pm(void * arg)658 mvs_ch_pm(void *arg)
659 {
660 device_t dev = (device_t)arg;
661 struct mvs_channel *ch = device_get_softc(dev);
662 uint32_t work;
663
664 if (ch->numrslots != 0)
665 return;
666 /* If we are idle - request power state transition. */
667 work = ATA_INL(ch->r_mem, SATA_SC);
668 work &= ~SATA_SC_SPM_MASK;
669 if (ch->pm_level == 4)
670 work |= SATA_SC_SPM_PARTIAL;
671 else
672 work |= SATA_SC_SPM_SLUMBER;
673 ATA_OUTL(ch->r_mem, SATA_SC, work);
674 }
675
676 static void
mvs_ch_pm_wake(device_t dev)677 mvs_ch_pm_wake(device_t dev)
678 {
679 struct mvs_channel *ch = device_get_softc(dev);
680 uint32_t work;
681 int timeout = 0;
682
683 work = ATA_INL(ch->r_mem, SATA_SS);
684 if (work & SATA_SS_IPM_ACTIVE)
685 return;
686 /* If we are not in active state - request power state transition. */
687 work = ATA_INL(ch->r_mem, SATA_SC);
688 work &= ~SATA_SC_SPM_MASK;
689 work |= SATA_SC_SPM_ACTIVE;
690 ATA_OUTL(ch->r_mem, SATA_SC, work);
691 /* Wait for transition to happen. */
692 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 &&
693 timeout++ < 100) {
694 DELAY(100);
695 }
696 }
697
698 static void
mvs_ch_intr(void * data)699 mvs_ch_intr(void *data)
700 {
701 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
702 device_t dev = (device_t)arg->arg;
703 struct mvs_channel *ch = device_get_softc(dev);
704 uint32_t iec, serr = 0, fisic = 0;
705 enum mvs_err_type et;
706 int i, ccs, port = -1, selfdis = 0;
707 int edma = (ch->numtslots != 0 || ch->numdslots != 0);
708
709 /* New item in response queue. */
710 if ((arg->cause & 2) && edma)
711 mvs_crbq_intr(dev);
712 /* Some error or special event. */
713 if (arg->cause & 1) {
714 iec = ATA_INL(ch->r_mem, EDMA_IEC);
715 if (iec & EDMA_IE_SERRINT) {
716 serr = ATA_INL(ch->r_mem, SATA_SE);
717 ATA_OUTL(ch->r_mem, SATA_SE, serr);
718 }
719 /* EDMA self-disabled due to error. */
720 if (iec & EDMA_IE_ESELFDIS)
721 selfdis = 1;
722 /* Transport interrupt. */
723 if (iec & EDMA_IE_ETRANSINT) {
724 /* For Gen-I this bit means self-disable. */
725 if (ch->quirks & MVS_Q_GENI)
726 selfdis = 1;
727 /* For Gen-II this bit means SDB-N. */
728 else if (ch->quirks & MVS_Q_GENII)
729 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1;
730 else /* For Gen-IIe - read FIS interrupt cause. */
731 fisic = ATA_INL(ch->r_mem, SATA_FISIC);
732 }
733 if (selfdis)
734 ch->curr_mode = MVS_EDMA_UNKNOWN;
735 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec);
736 /* Interface errors or Device error. */
737 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) {
738 port = -1;
739 if (ch->numpslots != 0) {
740 ccs = 0;
741 } else {
742 if (ch->quirks & MVS_Q_GENIIE)
743 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S));
744 else
745 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S));
746 /* Check if error is one-PMP-port-specific, */
747 if (ch->fbs_enabled) {
748 /* Which ports were active. */
749 for (i = 0; i < 16; i++) {
750 if (ch->numrslotspd[i] == 0)
751 continue;
752 if (port == -1)
753 port = i;
754 else if (port != i) {
755 port = -2;
756 break;
757 }
758 }
759 /* If several ports were active and EDMA still enabled -
760 * other ports are probably unaffected and may continue.
761 */
762 if (port == -2 && !selfdis) {
763 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16;
764 port = ffs(p) - 1;
765 if (port != (fls(p) - 1))
766 port = -2;
767 }
768 }
769 }
770 mvs_requeue_frozen(dev);
771 for (i = 0; i < MVS_MAX_SLOTS; i++) {
772 /* XXX: requests in loading state. */
773 if (((ch->rslots >> i) & 1) == 0)
774 continue;
775 if (port >= 0 &&
776 ch->slot[i].ccb->ccb_h.target_id != port)
777 continue;
778 if (iec & EDMA_IE_EDEVERR) { /* Device error. */
779 if (port != -2) {
780 if (ch->numtslots == 0) {
781 /* Untagged operation. */
782 if (i == ccs)
783 et = MVS_ERR_TFE;
784 else
785 et = MVS_ERR_INNOCENT;
786 } else {
787 /* Tagged operation. */
788 et = MVS_ERR_NCQ;
789 }
790 } else {
791 et = MVS_ERR_TFE;
792 ch->fatalerr = 1;
793 }
794 } else if (iec & 0xfc1e9000) {
795 if (ch->numtslots == 0 &&
796 i != ccs && port != -2)
797 et = MVS_ERR_INNOCENT;
798 else
799 et = MVS_ERR_SATA;
800 } else
801 et = MVS_ERR_INVALID;
802 mvs_end_transaction(&ch->slot[i], et);
803 }
804 }
805 /* Process SDB-N. */
806 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1)
807 mvs_notify_events(dev);
808 if (fisic)
809 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic);
810 /* Process hot-plug. */
811 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) ||
812 (serr & SATA_SE_PHY_CHANGED))
813 mvs_phy_check_events(dev, serr);
814 }
815 /* Legacy mode device interrupt. */
816 if ((arg->cause & 2) && !edma)
817 mvs_legacy_intr(dev, arg->cause & 4);
818 }
819
820 static uint8_t
mvs_getstatus(device_t dev,int clear)821 mvs_getstatus(device_t dev, int clear)
822 {
823 struct mvs_channel *ch = device_get_softc(dev);
824 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT);
825
826 if (ch->fake_busy) {
827 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR))
828 ch->fake_busy = 0;
829 else
830 status |= ATA_S_BUSY;
831 }
832 return (status);
833 }
834
835 static void
mvs_legacy_intr(device_t dev,int poll)836 mvs_legacy_intr(device_t dev, int poll)
837 {
838 struct mvs_channel *ch = device_get_softc(dev);
839 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */
840 union ccb *ccb = slot->ccb;
841 enum mvs_err_type et = MVS_ERR_NONE;
842 u_int length, resid, size;
843 uint8_t buf[2];
844 uint8_t status, ireason;
845
846 /* Clear interrupt and get status. */
847 status = mvs_getstatus(dev, 1);
848 if (slot->state < MVS_SLOT_RUNNING)
849 return;
850 /* Wait a bit for late !BUSY status update. */
851 if (status & ATA_S_BUSY) {
852 if (poll)
853 return;
854 DELAY(100);
855 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) {
856 DELAY(1000);
857 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY)
858 return;
859 }
860 }
861 /* If we got an error, we are done. */
862 if (status & ATA_S_ERROR) {
863 et = MVS_ERR_TFE;
864 goto end_finished;
865 }
866 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */
867 ccb->ataio.res.status = status;
868 /* Are we moving data? */
869 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
870 /* If data read command - get them. */
871 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
872 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
873 device_printf(dev, "timeout waiting for read DRQ\n");
874 et = MVS_ERR_TIMEOUT;
875 xpt_freeze_simq(ch->sim, 1);
876 ch->toslots |= (1 << slot->slot);
877 goto end_finished;
878 }
879 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
880 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
881 ch->transfersize / 2);
882 }
883 /* Update how far we've gotten. */
884 ch->donecount += ch->transfersize;
885 /* Do we need more? */
886 if (ccb->ataio.dxfer_len > ch->donecount) {
887 /* Set this transfer size according to HW capabilities */
888 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount,
889 ch->transfersize);
890 /* If data write command - put them */
891 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
892 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
893 device_printf(dev,
894 "timeout waiting for write DRQ\n");
895 et = MVS_ERR_TIMEOUT;
896 xpt_freeze_simq(ch->sim, 1);
897 ch->toslots |= (1 << slot->slot);
898 goto end_finished;
899 }
900 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
901 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
902 ch->transfersize / 2);
903 return;
904 }
905 /* If data read command, return & wait for interrupt */
906 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
907 return;
908 }
909 }
910 } else if (ch->basic_dma) { /* ATAPI DMA */
911 if (status & ATA_S_DWF)
912 et = MVS_ERR_TFE;
913 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR)
914 et = MVS_ERR_TFE;
915 /* Stop basic DMA. */
916 ATA_OUTL(ch->r_mem, DMA_C, 0);
917 goto end_finished;
918 } else { /* ATAPI PIO */
919 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) |
920 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8);
921 size = min(ch->transfersize, length);
922 ireason = ATA_INB(ch->r_mem,ATA_IREASON);
923 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) |
924 (status & ATA_S_DRQ)) {
925 case ATAPI_P_CMDOUT:
926 device_printf(dev, "ATAPI CMDOUT\n");
927 /* Return wait for interrupt */
928 return;
929
930 case ATAPI_P_WRITE:
931 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
932 device_printf(dev, "trying to write on read buffer\n");
933 et = MVS_ERR_TFE;
934 goto end_finished;
935 break;
936 }
937 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
938 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
939 (size + 1) / 2);
940 for (resid = ch->transfersize + (size & 1);
941 resid < length; resid += sizeof(int16_t))
942 ATA_OUTW(ch->r_mem, ATA_DATA, 0);
943 ch->donecount += length;
944 /* Set next transfer size according to HW capabilities */
945 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
946 ch->curr[ccb->ccb_h.target_id].bytecount);
947 /* Return wait for interrupt */
948 return;
949
950 case ATAPI_P_READ:
951 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
952 device_printf(dev, "trying to read on write buffer\n");
953 et = MVS_ERR_TFE;
954 goto end_finished;
955 }
956 if (size >= 2) {
957 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
958 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
959 size / 2);
960 }
961 if (size & 1) {
962 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1);
963 ((uint8_t *)ccb->csio.data_ptr + ch->donecount +
964 (size & ~1))[0] = buf[0];
965 }
966 for (resid = ch->transfersize + (size & 1);
967 resid < length; resid += sizeof(int16_t))
968 ATA_INW(ch->r_mem, ATA_DATA);
969 ch->donecount += length;
970 /* Set next transfer size according to HW capabilities */
971 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
972 ch->curr[ccb->ccb_h.target_id].bytecount);
973 /* Return wait for interrupt */
974 return;
975
976 case ATAPI_P_DONEDRQ:
977 device_printf(dev,
978 "WARNING - DONEDRQ non conformant device\n");
979 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
980 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
981 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
982 length / 2);
983 ch->donecount += length;
984 }
985 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
986 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
987 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
988 length / 2);
989 ch->donecount += length;
990 }
991 else
992 et = MVS_ERR_TFE;
993 /* FALLTHROUGH */
994
995 case ATAPI_P_ABORT:
996 case ATAPI_P_DONE:
997 if (status & (ATA_S_ERROR | ATA_S_DWF))
998 et = MVS_ERR_TFE;
999 goto end_finished;
1000
1001 default:
1002 device_printf(dev, "unknown transfer phase"
1003 " (status %02x, ireason %02x)\n",
1004 status, ireason);
1005 et = MVS_ERR_TFE;
1006 }
1007 }
1008
1009 end_finished:
1010 mvs_end_transaction(slot, et);
1011 }
1012
1013 static void
mvs_crbq_intr(device_t dev)1014 mvs_crbq_intr(device_t dev)
1015 {
1016 struct mvs_channel *ch = device_get_softc(dev);
1017 struct mvs_crpb *crpb;
1018 union ccb *ccb;
1019 int in_idx, fin_idx, cin_idx, slot;
1020 uint32_t val;
1021 uint16_t flags;
1022
1023 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1024 if (val == 0)
1025 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1026 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >>
1027 EDMA_RESQP_ERPQP_SHIFT;
1028 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1029 BUS_DMASYNC_POSTREAD);
1030 fin_idx = cin_idx = ch->in_idx;
1031 ch->in_idx = in_idx;
1032 while (in_idx != cin_idx) {
1033 crpb = (struct mvs_crpb *)
1034 (ch->dma.workrp + MVS_CRPB_OFFSET +
1035 (MVS_CRPB_SIZE * cin_idx));
1036 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK;
1037 flags = le16toh(crpb->rspflg);
1038 /*
1039 * Handle only successful completions here.
1040 * Errors will be handled by main intr handler.
1041 */
1042 #if defined(__i386__) || defined(__amd64__)
1043 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) {
1044 device_printf(dev, "Unfilled CRPB "
1045 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1046 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots);
1047 } else
1048 #endif
1049 if (ch->numtslots != 0 ||
1050 (flags & EDMA_IE_EDEVERR) == 0) {
1051 #if defined(__i386__) || defined(__amd64__)
1052 crpb->id = 0xffff;
1053 crpb->rspflg = 0xffff;
1054 #endif
1055 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) {
1056 ccb = ch->slot[slot].ccb;
1057 ccb->ataio.res.status =
1058 (flags & MVS_CRPB_ATASTS_MASK) >>
1059 MVS_CRPB_ATASTS_SHIFT;
1060 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE);
1061 } else {
1062 device_printf(dev, "Unused tag in CRPB "
1063 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1064 cin_idx, fin_idx, in_idx, slot, flags,
1065 ch->rslots);
1066 }
1067 } else {
1068 device_printf(dev,
1069 "CRPB with error %d tag %d flags %04x\n",
1070 cin_idx, slot, flags);
1071 }
1072 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1);
1073 }
1074 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1075 BUS_DMASYNC_PREREAD);
1076 if (cin_idx == ch->in_idx) {
1077 ATA_OUTL(ch->r_mem, EDMA_RESQOP,
1078 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT));
1079 }
1080 }
1081
1082 /* Must be called with channel locked. */
1083 static int
mvs_check_collision(device_t dev,union ccb * ccb)1084 mvs_check_collision(device_t dev, union ccb *ccb)
1085 {
1086 struct mvs_channel *ch = device_get_softc(dev);
1087
1088 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1089 /* NCQ DMA */
1090 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1091 /* Can't mix NCQ and non-NCQ DMA commands. */
1092 if (ch->numdslots != 0)
1093 return (1);
1094 /* Can't mix NCQ and PIO commands. */
1095 if (ch->numpslots != 0)
1096 return (1);
1097 /* If we have no FBS */
1098 if (!ch->fbs_enabled) {
1099 /* Tagged command while tagged to other target is active. */
1100 if (ch->numtslots != 0 &&
1101 ch->taggedtarget != ccb->ccb_h.target_id)
1102 return (1);
1103 }
1104 /* Non-NCQ DMA */
1105 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1106 /* Can't mix non-NCQ DMA and NCQ commands. */
1107 if (ch->numtslots != 0)
1108 return (1);
1109 /* Can't mix non-NCQ DMA and PIO commands. */
1110 if (ch->numpslots != 0)
1111 return (1);
1112 /* PIO */
1113 } else {
1114 /* Can't mix PIO with anything. */
1115 if (ch->numrslots != 0)
1116 return (1);
1117 }
1118 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1119 /* Atomic command while anything active. */
1120 if (ch->numrslots != 0)
1121 return (1);
1122 }
1123 } else { /* ATAPI */
1124 /* ATAPI goes without EDMA, so can't mix it with anything. */
1125 if (ch->numrslots != 0)
1126 return (1);
1127 }
1128 /* We have some atomic command running. */
1129 if (ch->aslots != 0)
1130 return (1);
1131 return (0);
1132 }
1133
1134 static void
mvs_tfd_read(device_t dev,union ccb * ccb)1135 mvs_tfd_read(device_t dev, union ccb *ccb)
1136 {
1137 struct mvs_channel *ch = device_get_softc(dev);
1138 struct ata_res *res = &ccb->ataio.res;
1139
1140 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT);
1141 res->error = ATA_INB(ch->r_mem, ATA_ERROR);
1142 res->device = ATA_INB(ch->r_mem, ATA_DRIVE);
1143 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB);
1144 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT);
1145 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR);
1146 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1147 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1148 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
1149 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT);
1150 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR);
1151 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1152 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1153 }
1154
1155 static void
mvs_tfd_write(device_t dev,union ccb * ccb)1156 mvs_tfd_write(device_t dev, union ccb *ccb)
1157 {
1158 struct mvs_channel *ch = device_get_softc(dev);
1159 struct ata_cmd *cmd = &ccb->ataio.cmd;
1160
1161 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device);
1162 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control);
1163 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp);
1164 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features);
1165 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp);
1166 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count);
1167 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp);
1168 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low);
1169 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp);
1170 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid);
1171 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp);
1172 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high);
1173 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command);
1174 }
1175
1176 /* Must be called with channel locked. */
1177 static void
mvs_begin_transaction(device_t dev,union ccb * ccb)1178 mvs_begin_transaction(device_t dev, union ccb *ccb)
1179 {
1180 struct mvs_channel *ch = device_get_softc(dev);
1181 struct mvs_slot *slot;
1182 int slotn, tag;
1183
1184 if (ch->pm_level > 0)
1185 mvs_ch_pm_wake(dev);
1186 /* Softreset is a special case. */
1187 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1188 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1189 mvs_softreset(dev, ccb);
1190 return;
1191 }
1192 /* Choose empty slot. */
1193 slotn = ffs(~ch->oslots) - 1;
1194 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1195 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1196 if (ch->quirks & MVS_Q_GENIIE)
1197 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1;
1198 else
1199 tag = slotn;
1200 } else
1201 tag = 0;
1202 /* Occupy chosen slot. */
1203 slot = &ch->slot[slotn];
1204 slot->ccb = ccb;
1205 slot->tag = tag;
1206 /* Stop PM timer. */
1207 if (ch->numrslots == 0 && ch->pm_level > 3)
1208 callout_stop(&ch->pm_timer);
1209 /* Update channel stats. */
1210 ch->oslots |= (1 << slot->slot);
1211 ch->numrslots++;
1212 ch->numrslotspd[ccb->ccb_h.target_id]++;
1213 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1214 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1215 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag);
1216 ch->numtslots++;
1217 ch->numtslotspd[ccb->ccb_h.target_id]++;
1218 ch->taggedtarget = ccb->ccb_h.target_id;
1219 mvs_set_edma_mode(dev, MVS_EDMA_NCQ);
1220 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1221 ch->numdslots++;
1222 mvs_set_edma_mode(dev, MVS_EDMA_ON);
1223 } else {
1224 ch->numpslots++;
1225 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1226 }
1227 if (ccb->ataio.cmd.flags &
1228 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1229 ch->aslots |= (1 << slot->slot);
1230 }
1231 } else {
1232 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1233 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes;
1234 ch->numpslots++;
1235 /* Use ATAPI DMA only for commands without under-/overruns. */
1236 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1237 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA &&
1238 (ch->quirks & MVS_Q_SOC) == 0 &&
1239 (cdb[0] == 0x08 ||
1240 cdb[0] == 0x0a ||
1241 cdb[0] == 0x28 ||
1242 cdb[0] == 0x2a ||
1243 cdb[0] == 0x88 ||
1244 cdb[0] == 0x8a ||
1245 cdb[0] == 0xa8 ||
1246 cdb[0] == 0xaa ||
1247 cdb[0] == 0xbe)) {
1248 ch->basic_dma = 1;
1249 }
1250 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1251 }
1252 if (ch->numpslots == 0 || ch->basic_dma) {
1253 slot->state = MVS_SLOT_LOADING;
1254 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map,
1255 ccb, mvs_dmasetprd, slot, 0);
1256 } else
1257 mvs_legacy_execute_transaction(slot);
1258 }
1259
1260 /* Locked by busdma engine. */
1261 static void
mvs_dmasetprd(void * arg,bus_dma_segment_t * segs,int nsegs,int error)1262 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1263 {
1264 struct mvs_slot *slot = arg;
1265 struct mvs_channel *ch = device_get_softc(slot->dev);
1266 struct mvs_eprd *eprd;
1267 int i;
1268
1269 if (error) {
1270 device_printf(slot->dev, "DMA load error\n");
1271 mvs_end_transaction(slot, MVS_ERR_INVALID);
1272 return;
1273 }
1274 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n"));
1275 /* If there is only one segment - no need to use S/G table on Gen-IIe. */
1276 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) {
1277 slot->dma.addr = segs[0].ds_addr;
1278 slot->dma.len = segs[0].ds_len;
1279 } else {
1280 slot->dma.addr = 0;
1281 /* Get a piece of the workspace for this EPRD */
1282 eprd = (struct mvs_eprd *)(ch->dma.workrq + slot->eprd_offset);
1283 /* Fill S/G table */
1284 for (i = 0; i < nsegs; i++) {
1285 eprd[i].prdbal = htole32(segs[i].ds_addr);
1286 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK);
1287 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16);
1288 }
1289 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF);
1290 }
1291 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1292 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1293 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1294 if (ch->basic_dma)
1295 mvs_legacy_execute_transaction(slot);
1296 else
1297 mvs_execute_transaction(slot);
1298 }
1299
1300 static void
mvs_legacy_execute_transaction(struct mvs_slot * slot)1301 mvs_legacy_execute_transaction(struct mvs_slot *slot)
1302 {
1303 device_t dev = slot->dev;
1304 struct mvs_channel *ch = device_get_softc(dev);
1305 bus_addr_t eprd;
1306 union ccb *ccb = slot->ccb;
1307 int port = ccb->ccb_h.target_id & 0x0f;
1308 int timeout;
1309
1310 slot->state = MVS_SLOT_RUNNING;
1311 ch->rslots |= (1 << slot->slot);
1312 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
1313 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1314 mvs_tfd_write(dev, ccb);
1315 /* Device reset doesn't interrupt. */
1316 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) {
1317 int timeout = 1000000;
1318 do {
1319 DELAY(10);
1320 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS);
1321 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--);
1322 mvs_legacy_intr(dev, 1);
1323 return;
1324 }
1325 ch->donecount = 0;
1326 if (ccb->ataio.cmd.command == ATA_READ_MUL ||
1327 ccb->ataio.cmd.command == ATA_READ_MUL48 ||
1328 ccb->ataio.cmd.command == ATA_WRITE_MUL ||
1329 ccb->ataio.cmd.command == ATA_WRITE_MUL48) {
1330 ch->transfersize = min(ccb->ataio.dxfer_len,
1331 ch->curr[port].bytecount);
1332 } else
1333 ch->transfersize = min(ccb->ataio.dxfer_len, 512);
1334 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE)
1335 ch->fake_busy = 1;
1336 /* If data write command - output the data */
1337 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1338 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
1339 device_printf(dev,
1340 "timeout waiting for write DRQ\n");
1341 xpt_freeze_simq(ch->sim, 1);
1342 ch->toslots |= (1 << slot->slot);
1343 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1344 return;
1345 }
1346 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1347 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
1348 ch->transfersize / 2);
1349 }
1350 } else {
1351 ch->donecount = 0;
1352 ch->transfersize = min(ccb->csio.dxfer_len,
1353 ch->curr[port].bytecount);
1354 /* Write ATA PACKET command. */
1355 if (ch->basic_dma) {
1356 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA);
1357 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0);
1358 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0);
1359 } else {
1360 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0);
1361 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize);
1362 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8);
1363 }
1364 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD);
1365 ch->fake_busy = 1;
1366 /* Wait for ready to write ATAPI command block */
1367 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) {
1368 device_printf(dev, "timeout waiting for ATAPI !BUSY\n");
1369 xpt_freeze_simq(ch->sim, 1);
1370 ch->toslots |= (1 << slot->slot);
1371 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1372 return;
1373 }
1374 timeout = 5000;
1375 while (timeout--) {
1376 int reason = ATA_INB(ch->r_mem, ATA_IREASON);
1377 int status = ATA_INB(ch->r_mem, ATA_STATUS);
1378
1379 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
1380 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
1381 break;
1382 DELAY(20);
1383 }
1384 if (timeout <= 0) {
1385 device_printf(dev,
1386 "timeout waiting for ATAPI command ready\n");
1387 xpt_freeze_simq(ch->sim, 1);
1388 ch->toslots |= (1 << slot->slot);
1389 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1390 return;
1391 }
1392 /* Write ATAPI command. */
1393 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1394 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1395 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes),
1396 ch->curr[port].atapi / 2);
1397 DELAY(10);
1398 if (ch->basic_dma) {
1399 /* Start basic DMA. */
1400 eprd = ch->dma.workrq_bus + slot->eprd_offset;
1401 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd);
1402 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16);
1403 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START |
1404 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ?
1405 DMA_C_READ : 0));
1406 }
1407 }
1408 /* Start command execution timeout */
1409 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0,
1410 mvs_timeout, slot, 0);
1411 }
1412
1413 /* Must be called with channel locked. */
1414 static void
mvs_execute_transaction(struct mvs_slot * slot)1415 mvs_execute_transaction(struct mvs_slot *slot)
1416 {
1417 device_t dev = slot->dev;
1418 struct mvs_channel *ch = device_get_softc(dev);
1419 bus_addr_t eprd;
1420 struct mvs_crqb *crqb;
1421 struct mvs_crqb_gen2e *crqb2e;
1422 union ccb *ccb = slot->ccb;
1423 int port = ccb->ccb_h.target_id & 0x0f;
1424 int i;
1425
1426 /* Get address of the prepared EPRD */
1427 eprd = ch->dma.workrq_bus + slot->eprd_offset;
1428 /* Prepare CRQB. Gen IIe uses different CRQB format. */
1429 if (ch->quirks & MVS_Q_GENIIE) {
1430 crqb2e = (struct mvs_crqb_gen2e *)
1431 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1432 crqb2e->ctrlflg = htole32(
1433 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) |
1434 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) |
1435 (port << MVS_CRQB2E_PMP_SHIFT) |
1436 (slot->slot << MVS_CRQB2E_HTAG_SHIFT));
1437 /* If there is only one segment - no need to use S/G table. */
1438 if (slot->dma.addr != 0) {
1439 eprd = slot->dma.addr;
1440 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD);
1441 crqb2e->drbc = slot->dma.len;
1442 }
1443 crqb2e->cprdbl = htole32(eprd);
1444 crqb2e->cprdbh = htole32((eprd >> 16) >> 16);
1445 crqb2e->cmd[0] = 0;
1446 crqb2e->cmd[1] = 0;
1447 crqb2e->cmd[2] = ccb->ataio.cmd.command;
1448 crqb2e->cmd[3] = ccb->ataio.cmd.features;
1449 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low;
1450 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid;
1451 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high;
1452 crqb2e->cmd[7] = ccb->ataio.cmd.device;
1453 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp;
1454 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp;
1455 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp;
1456 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp;
1457 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1458 crqb2e->cmd[12] = slot->tag << 3;
1459 crqb2e->cmd[13] = 0;
1460 } else {
1461 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count;
1462 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp;
1463 }
1464 crqb2e->cmd[14] = 0;
1465 crqb2e->cmd[15] = 0;
1466 } else {
1467 crqb = (struct mvs_crqb *)
1468 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1469 crqb->cprdbl = htole32(eprd);
1470 crqb->cprdbh = htole32((eprd >> 16) >> 16);
1471 crqb->ctrlflg = htole16(
1472 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) |
1473 (slot->slot << MVS_CRQB_TAG_SHIFT) |
1474 (port << MVS_CRQB_PMP_SHIFT));
1475 i = 0;
1476 /*
1477 * Controller can handle only 11 of 12 ATA registers,
1478 * so we have to choose which one to skip.
1479 */
1480 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1481 crqb->cmd[i++] = ccb->ataio.cmd.features_exp;
1482 crqb->cmd[i++] = 0x11;
1483 }
1484 crqb->cmd[i++] = ccb->ataio.cmd.features;
1485 crqb->cmd[i++] = 0x11;
1486 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1487 crqb->cmd[i++] = (slot->tag << 3) |
1488 (ccb->ataio.cmd.sector_count & 0x07);
1489 crqb->cmd[i++] = 0x12;
1490 } else {
1491 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp;
1492 crqb->cmd[i++] = 0x12;
1493 crqb->cmd[i++] = ccb->ataio.cmd.sector_count;
1494 crqb->cmd[i++] = 0x12;
1495 }
1496 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp;
1497 crqb->cmd[i++] = 0x13;
1498 crqb->cmd[i++] = ccb->ataio.cmd.lba_low;
1499 crqb->cmd[i++] = 0x13;
1500 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp;
1501 crqb->cmd[i++] = 0x14;
1502 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid;
1503 crqb->cmd[i++] = 0x14;
1504 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp;
1505 crqb->cmd[i++] = 0x15;
1506 crqb->cmd[i++] = ccb->ataio.cmd.lba_high;
1507 crqb->cmd[i++] = 0x15;
1508 crqb->cmd[i++] = ccb->ataio.cmd.device;
1509 crqb->cmd[i++] = 0x16;
1510 crqb->cmd[i++] = ccb->ataio.cmd.command;
1511 crqb->cmd[i++] = 0x97;
1512 }
1513 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1514 BUS_DMASYNC_PREWRITE);
1515 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1516 BUS_DMASYNC_PREREAD);
1517 slot->state = MVS_SLOT_RUNNING;
1518 ch->rslots |= (1 << slot->slot);
1519 /* Issue command to the controller. */
1520 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1);
1521 ATA_OUTL(ch->r_mem, EDMA_REQQIP,
1522 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1523 /* Start command execution timeout */
1524 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0,
1525 mvs_timeout, slot, 0);
1526 return;
1527 }
1528
1529 /* Must be called with channel locked. */
1530 static void
mvs_process_timeout(device_t dev)1531 mvs_process_timeout(device_t dev)
1532 {
1533 struct mvs_channel *ch = device_get_softc(dev);
1534 int i;
1535
1536 mtx_assert(&ch->mtx, MA_OWNED);
1537 /* Handle the rest of commands. */
1538 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1539 /* Do we have a running request on slot? */
1540 if (ch->slot[i].state < MVS_SLOT_RUNNING)
1541 continue;
1542 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT);
1543 }
1544 }
1545
1546 /* Must be called with channel locked. */
1547 static void
mvs_rearm_timeout(device_t dev)1548 mvs_rearm_timeout(device_t dev)
1549 {
1550 struct mvs_channel *ch = device_get_softc(dev);
1551 int i;
1552
1553 mtx_assert(&ch->mtx, MA_OWNED);
1554 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1555 struct mvs_slot *slot = &ch->slot[i];
1556
1557 /* Do we have a running request on slot? */
1558 if (slot->state < MVS_SLOT_RUNNING)
1559 continue;
1560 if ((ch->toslots & (1 << i)) == 0)
1561 continue;
1562 callout_reset_sbt(&slot->timeout,
1563 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1564 mvs_timeout, slot, 0);
1565 }
1566 }
1567
1568 /* Locked by callout mechanism. */
1569 static void
mvs_timeout(void * arg)1570 mvs_timeout(void *arg)
1571 {
1572 struct mvs_slot *slot = arg;
1573 device_t dev = slot->dev;
1574 struct mvs_channel *ch = device_get_softc(dev);
1575
1576 /* Check for stale timeout. */
1577 if (slot->state < MVS_SLOT_RUNNING)
1578 return;
1579 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1580 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x "
1581 "dma_c %08x dma_s %08x rs %08x status %02x\n",
1582 ATA_INL(ch->r_mem, EDMA_IEC),
1583 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE),
1584 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C),
1585 ATA_INL(ch->r_mem, DMA_S), ch->rslots,
1586 ATA_INB(ch->r_mem, ATA_ALTSTAT));
1587 /* Handle frozen command. */
1588 mvs_requeue_frozen(dev);
1589 /* We wait for other commands timeout and pray. */
1590 if (ch->toslots == 0)
1591 xpt_freeze_simq(ch->sim, 1);
1592 ch->toslots |= (1 << slot->slot);
1593 if ((ch->rslots & ~ch->toslots) == 0)
1594 mvs_process_timeout(dev);
1595 else
1596 device_printf(dev, " ... waiting for slots %08x\n",
1597 ch->rslots & ~ch->toslots);
1598 }
1599
1600 /* Must be called with channel locked. */
1601 static void
mvs_end_transaction(struct mvs_slot * slot,enum mvs_err_type et)1602 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
1603 {
1604 device_t dev = slot->dev;
1605 struct mvs_channel *ch = device_get_softc(dev);
1606 union ccb *ccb = slot->ccb;
1607 int lastto;
1608
1609 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1610 BUS_DMASYNC_POSTWRITE);
1611 /* Read result registers to the result struct
1612 * May be incorrect if several commands finished same time,
1613 * so read only when sure or have to.
1614 */
1615 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1616 struct ata_res *res = &ccb->ataio.res;
1617
1618 if ((et == MVS_ERR_TFE) ||
1619 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1620 mvs_tfd_read(dev, ccb);
1621 } else
1622 bzero(res, sizeof(*res));
1623 } else {
1624 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1625 ch->basic_dma == 0)
1626 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount;
1627 }
1628 if (ch->numpslots == 0 || ch->basic_dma) {
1629 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1630 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1631 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1632 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1633 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1634 }
1635 }
1636 if (et != MVS_ERR_NONE)
1637 ch->eslots |= (1 << slot->slot);
1638 /* In case of error, freeze device for proper recovery. */
1639 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) &&
1640 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1641 xpt_freeze_devq(ccb->ccb_h.path, 1);
1642 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1643 }
1644 /* Set proper result status. */
1645 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1646 switch (et) {
1647 case MVS_ERR_NONE:
1648 ccb->ccb_h.status |= CAM_REQ_CMP;
1649 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1650 ccb->csio.scsi_status = SCSI_STATUS_OK;
1651 break;
1652 case MVS_ERR_INVALID:
1653 ch->fatalerr = 1;
1654 ccb->ccb_h.status |= CAM_REQ_INVALID;
1655 break;
1656 case MVS_ERR_INNOCENT:
1657 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1658 break;
1659 case MVS_ERR_TFE:
1660 case MVS_ERR_NCQ:
1661 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1662 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1663 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1664 } else {
1665 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1666 }
1667 break;
1668 case MVS_ERR_SATA:
1669 ch->fatalerr = 1;
1670 if (!ch->recoverycmd) {
1671 xpt_freeze_simq(ch->sim, 1);
1672 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1673 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1674 }
1675 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1676 break;
1677 case MVS_ERR_TIMEOUT:
1678 if (!ch->recoverycmd) {
1679 xpt_freeze_simq(ch->sim, 1);
1680 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1681 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1682 }
1683 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1684 break;
1685 default:
1686 ch->fatalerr = 1;
1687 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1688 }
1689 /* Free slot. */
1690 ch->oslots &= ~(1 << slot->slot);
1691 ch->rslots &= ~(1 << slot->slot);
1692 ch->aslots &= ~(1 << slot->slot);
1693 slot->state = MVS_SLOT_EMPTY;
1694 slot->ccb = NULL;
1695 /* Update channel stats. */
1696 ch->numrslots--;
1697 ch->numrslotspd[ccb->ccb_h.target_id]--;
1698 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1699 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1700 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag);
1701 ch->numtslots--;
1702 ch->numtslotspd[ccb->ccb_h.target_id]--;
1703 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1704 ch->numdslots--;
1705 } else {
1706 ch->numpslots--;
1707 }
1708 } else {
1709 ch->numpslots--;
1710 ch->basic_dma = 0;
1711 }
1712 /* Cancel timeout state if request completed normally. */
1713 if (et != MVS_ERR_TIMEOUT) {
1714 lastto = (ch->toslots == (1 << slot->slot));
1715 ch->toslots &= ~(1 << slot->slot);
1716 if (lastto)
1717 xpt_release_simq(ch->sim, TRUE);
1718 }
1719 /* If it was our READ LOG command - process it. */
1720 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1721 mvs_process_read_log(dev, ccb);
1722 /* If it was our REQUEST SENSE command - process it. */
1723 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1724 mvs_process_request_sense(dev, ccb);
1725 /* If it was NCQ or ATAPI command error, put result on hold. */
1726 } else if (et == MVS_ERR_NCQ ||
1727 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1728 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1729 ch->hold[slot->slot] = ccb;
1730 ch->holdtag[slot->slot] = slot->tag;
1731 ch->numhslots++;
1732 } else
1733 xpt_done(ccb);
1734 /* If we have no other active commands, ... */
1735 if (ch->rslots == 0) {
1736 /* if there was fatal error - reset port. */
1737 if (ch->toslots != 0 || ch->fatalerr) {
1738 mvs_reset(dev);
1739 } else {
1740 /* if we have slots in error, we can reinit port. */
1741 if (ch->eslots != 0) {
1742 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1743 ch->eslots = 0;
1744 }
1745 /* if there commands on hold, we can do READ LOG. */
1746 if (!ch->recoverycmd && ch->numhslots)
1747 mvs_issue_recovery(dev);
1748 }
1749 /* If all the rest of commands are in timeout - give them chance. */
1750 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1751 et != MVS_ERR_TIMEOUT)
1752 mvs_rearm_timeout(dev);
1753 /* Unfreeze frozen command. */
1754 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
1755 union ccb *fccb = ch->frozen;
1756 ch->frozen = NULL;
1757 mvs_begin_transaction(dev, fccb);
1758 xpt_release_simq(ch->sim, TRUE);
1759 }
1760 /* Start PM timer. */
1761 if (ch->numrslots == 0 && ch->pm_level > 3 &&
1762 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1763 callout_schedule(&ch->pm_timer,
1764 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1765 }
1766 }
1767
1768 static void
mvs_issue_recovery(device_t dev)1769 mvs_issue_recovery(device_t dev)
1770 {
1771 struct mvs_channel *ch = device_get_softc(dev);
1772 union ccb *ccb;
1773 struct ccb_ataio *ataio;
1774 struct ccb_scsiio *csio;
1775 int i;
1776
1777 /* Find some held command. */
1778 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1779 if (ch->hold[i])
1780 break;
1781 }
1782 ccb = xpt_alloc_ccb_nowait();
1783 if (ccb == NULL) {
1784 device_printf(dev, "Unable to allocate recovery command\n");
1785 completeall:
1786 /* We can't do anything -- complete held commands. */
1787 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1788 if (ch->hold[i] == NULL)
1789 continue;
1790 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1791 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
1792 xpt_done(ch->hold[i]);
1793 ch->hold[i] = NULL;
1794 ch->numhslots--;
1795 }
1796 mvs_reset(dev);
1797 return;
1798 }
1799 xpt_setup_ccb(&ccb->ccb_h, ch->hold[i]->ccb_h.path,
1800 ch->hold[i]->ccb_h.pinfo.priority);
1801 if (ch->hold[i]->ccb_h.func_code == XPT_ATA_IO) {
1802 /* READ LOG */
1803 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
1804 ccb->ccb_h.func_code = XPT_ATA_IO;
1805 ccb->ccb_h.flags = CAM_DIR_IN;
1806 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1807 ataio = &ccb->ataio;
1808 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT);
1809 if (ataio->data_ptr == NULL) {
1810 xpt_free_ccb(ccb);
1811 device_printf(dev,
1812 "Unable to allocate memory for READ LOG command\n");
1813 goto completeall;
1814 }
1815 ataio->dxfer_len = 512;
1816 bzero(&ataio->cmd, sizeof(ataio->cmd));
1817 ataio->cmd.flags = CAM_ATAIO_48BIT;
1818 ataio->cmd.command = 0x2F; /* READ LOG EXT */
1819 ataio->cmd.sector_count = 1;
1820 ataio->cmd.sector_count_exp = 0;
1821 ataio->cmd.lba_low = 0x10;
1822 ataio->cmd.lba_mid = 0;
1823 ataio->cmd.lba_mid_exp = 0;
1824 } else {
1825 /* REQUEST SENSE */
1826 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
1827 ccb->ccb_h.recovery_slot = i;
1828 ccb->ccb_h.func_code = XPT_SCSI_IO;
1829 ccb->ccb_h.flags = CAM_DIR_IN;
1830 ccb->ccb_h.status = 0;
1831 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1832 csio = &ccb->csio;
1833 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
1834 csio->dxfer_len = ch->hold[i]->csio.sense_len;
1835 csio->cdb_len = 6;
1836 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
1837 csio->cdb_io.cdb_bytes[0] = 0x03;
1838 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
1839 }
1840 /* Freeze SIM while doing recovery. */
1841 ch->recoverycmd = 1;
1842 xpt_freeze_simq(ch->sim, 1);
1843 mvs_begin_transaction(dev, ccb);
1844 }
1845
1846 static void
mvs_process_read_log(device_t dev,union ccb * ccb)1847 mvs_process_read_log(device_t dev, union ccb *ccb)
1848 {
1849 struct mvs_channel *ch = device_get_softc(dev);
1850 uint8_t *data;
1851 struct ata_res *res;
1852 int i;
1853
1854 ch->recoverycmd = 0;
1855
1856 data = ccb->ataio.data_ptr;
1857 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
1858 (data[0] & 0x80) == 0) {
1859 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1860 if (!ch->hold[i])
1861 continue;
1862 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1863 continue;
1864 if ((data[0] & 0x1F) == ch->holdtag[i]) {
1865 res = &ch->hold[i]->ataio.res;
1866 res->status = data[2];
1867 res->error = data[3];
1868 res->lba_low = data[4];
1869 res->lba_mid = data[5];
1870 res->lba_high = data[6];
1871 res->device = data[7];
1872 res->lba_low_exp = data[8];
1873 res->lba_mid_exp = data[9];
1874 res->lba_high_exp = data[10];
1875 res->sector_count = data[12];
1876 res->sector_count_exp = data[13];
1877 } else {
1878 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1879 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
1880 }
1881 xpt_done(ch->hold[i]);
1882 ch->hold[i] = NULL;
1883 ch->numhslots--;
1884 }
1885 } else {
1886 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
1887 device_printf(dev, "Error while READ LOG EXT\n");
1888 else if ((data[0] & 0x80) == 0) {
1889 device_printf(dev,
1890 "Non-queued command error in READ LOG EXT\n");
1891 }
1892 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1893 if (!ch->hold[i])
1894 continue;
1895 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1896 continue;
1897 xpt_done(ch->hold[i]);
1898 ch->hold[i] = NULL;
1899 ch->numhslots--;
1900 }
1901 }
1902 free(ccb->ataio.data_ptr, M_MVS);
1903 xpt_free_ccb(ccb);
1904 xpt_release_simq(ch->sim, TRUE);
1905 }
1906
1907 static void
mvs_process_request_sense(device_t dev,union ccb * ccb)1908 mvs_process_request_sense(device_t dev, union ccb *ccb)
1909 {
1910 struct mvs_channel *ch = device_get_softc(dev);
1911 int i;
1912
1913 ch->recoverycmd = 0;
1914
1915 i = ccb->ccb_h.recovery_slot;
1916 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
1917 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
1918 } else {
1919 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1920 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
1921 }
1922 xpt_done(ch->hold[i]);
1923 ch->hold[i] = NULL;
1924 ch->numhslots--;
1925 xpt_free_ccb(ccb);
1926 xpt_release_simq(ch->sim, TRUE);
1927 }
1928
1929 static int
mvs_wait(device_t dev,u_int s,u_int c,int t)1930 mvs_wait(device_t dev, u_int s, u_int c, int t)
1931 {
1932 int timeout = 0;
1933 uint8_t st;
1934
1935 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) {
1936 if (timeout >= t) {
1937 if (t != 0)
1938 device_printf(dev, "Wait status %02x\n", st);
1939 return (-1);
1940 }
1941 DELAY(1000);
1942 timeout++;
1943 }
1944 return (timeout);
1945 }
1946
1947 static void
mvs_requeue_frozen(device_t dev)1948 mvs_requeue_frozen(device_t dev)
1949 {
1950 struct mvs_channel *ch = device_get_softc(dev);
1951 union ccb *fccb = ch->frozen;
1952
1953 if (fccb) {
1954 ch->frozen = NULL;
1955 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1956 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1957 xpt_freeze_devq(fccb->ccb_h.path, 1);
1958 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1959 }
1960 xpt_done(fccb);
1961 }
1962 }
1963
1964 static void
mvs_reset_to(void * arg)1965 mvs_reset_to(void *arg)
1966 {
1967 device_t dev = arg;
1968 struct mvs_channel *ch = device_get_softc(dev);
1969 int t;
1970
1971 if (ch->resetting == 0)
1972 return;
1973 ch->resetting--;
1974 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) {
1975 if (bootverbose) {
1976 device_printf(dev,
1977 "MVS reset: device ready after %dms\n",
1978 (310 - ch->resetting) * 100);
1979 }
1980 ch->resetting = 0;
1981 xpt_release_simq(ch->sim, TRUE);
1982 return;
1983 }
1984 if (ch->resetting == 0) {
1985 device_printf(dev,
1986 "MVS reset: device not ready after 31000ms\n");
1987 xpt_release_simq(ch->sim, TRUE);
1988 return;
1989 }
1990 callout_schedule(&ch->reset_timer, hz / 10);
1991 }
1992
1993 static void
mvs_errata(device_t dev)1994 mvs_errata(device_t dev)
1995 {
1996 struct mvs_channel *ch = device_get_softc(dev);
1997 uint32_t val;
1998
1999 if (ch->quirks & MVS_Q_SOC65) {
2000 val = ATA_INL(ch->r_mem, SATA_PHYM3);
2001 val &= ~(0x3 << 27); /* SELMUPF = 1 */
2002 val |= (0x1 << 27);
2003 val &= ~(0x3 << 29); /* SELMUPI = 1 */
2004 val |= (0x1 << 29);
2005 ATA_OUTL(ch->r_mem, SATA_PHYM3, val);
2006
2007 val = ATA_INL(ch->r_mem, SATA_PHYM4);
2008 val &= ~0x1; /* SATU_OD8 = 0 */
2009 val |= (0x1 << 16); /* reserved bit 16 = 1 */
2010 ATA_OUTL(ch->r_mem, SATA_PHYM4, val);
2011
2012 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2);
2013 val &= ~0xf; /* TXAMP[3:0] = 8 */
2014 val |= 0x8;
2015 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2016 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val);
2017
2018 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1);
2019 val &= ~0xf; /* TXAMP[3:0] = 8 */
2020 val |= 0x8;
2021 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2022 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val);
2023 }
2024 }
2025
2026 static void
mvs_reset(device_t dev)2027 mvs_reset(device_t dev)
2028 {
2029 struct mvs_channel *ch = device_get_softc(dev);
2030 int i;
2031
2032 xpt_freeze_simq(ch->sim, 1);
2033 if (bootverbose)
2034 device_printf(dev, "MVS reset...\n");
2035 /* Forget about previous reset. */
2036 if (ch->resetting) {
2037 ch->resetting = 0;
2038 callout_stop(&ch->reset_timer);
2039 xpt_release_simq(ch->sim, TRUE);
2040 }
2041 /* Requeue freezed command. */
2042 mvs_requeue_frozen(dev);
2043 /* Kill the engine and requeue all running commands. */
2044 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2045 ATA_OUTL(ch->r_mem, DMA_C, 0);
2046 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2047 /* Do we have a running request on slot? */
2048 if (ch->slot[i].state < MVS_SLOT_RUNNING)
2049 continue;
2050 /* XXX; Commands in loading state. */
2051 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT);
2052 }
2053 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2054 if (!ch->hold[i])
2055 continue;
2056 xpt_done(ch->hold[i]);
2057 ch->hold[i] = NULL;
2058 ch->numhslots--;
2059 }
2060 if (ch->toslots != 0)
2061 xpt_release_simq(ch->sim, TRUE);
2062 ch->eslots = 0;
2063 ch->toslots = 0;
2064 ch->fatalerr = 0;
2065 ch->fake_busy = 0;
2066 /* Tell the XPT about the event */
2067 xpt_async(AC_BUS_RESET, ch->path, NULL);
2068 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
2069 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST);
2070 DELAY(25);
2071 ATA_OUTL(ch->r_mem, EDMA_CMD, 0);
2072 mvs_errata(dev);
2073 /* Reset and reconnect PHY, */
2074 if (!mvs_sata_phy_reset(dev)) {
2075 if (bootverbose)
2076 device_printf(dev, "MVS reset: device not found\n");
2077 ch->devices = 0;
2078 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2079 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2080 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2081 xpt_release_simq(ch->sim, TRUE);
2082 return;
2083 }
2084 if (bootverbose)
2085 device_printf(dev, "MVS reset: device found\n");
2086 /* Wait for clearing busy status. */
2087 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ,
2088 dumping ? 31000 : 0)) < 0) {
2089 if (dumping) {
2090 device_printf(dev,
2091 "MVS reset: device not ready after 31000ms\n");
2092 } else
2093 ch->resetting = 310;
2094 } else if (bootverbose)
2095 device_printf(dev, "MVS reset: device ready after %dms\n", i);
2096 ch->devices = 1;
2097 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2098 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2099 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2100 if (ch->resetting)
2101 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev);
2102 else
2103 xpt_release_simq(ch->sim, TRUE);
2104 }
2105
2106 static void
mvs_softreset(device_t dev,union ccb * ccb)2107 mvs_softreset(device_t dev, union ccb *ccb)
2108 {
2109 struct mvs_channel *ch = device_get_softc(dev);
2110 int port = ccb->ccb_h.target_id & 0x0f;
2111 int i, stuck;
2112 uint8_t status;
2113
2114 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2115 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
2116 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2117 DELAY(10000);
2118 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2119 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2120 /* Wait for clearing busy status. */
2121 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) {
2122 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2123 stuck = 1;
2124 } else {
2125 status = mvs_getstatus(dev, 0);
2126 if (status & ATA_S_ERROR)
2127 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2128 else
2129 ccb->ccb_h.status |= CAM_REQ_CMP;
2130 if (status & ATA_S_DRQ)
2131 stuck = 1;
2132 else
2133 stuck = 0;
2134 }
2135 mvs_tfd_read(dev, ccb);
2136
2137 /*
2138 * XXX: If some device on PMP failed to soft-reset,
2139 * try to recover by sending dummy soft-reset to PMP.
2140 */
2141 if (stuck && ch->pm_present && port != 15) {
2142 ATA_OUTB(ch->r_mem, SATA_SATAICTL,
2143 15 << SATA_SATAICTL_PMPTX_SHIFT);
2144 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2145 DELAY(10000);
2146 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2147 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout);
2148 }
2149
2150 xpt_done(ccb);
2151 }
2152
2153 static int
mvs_sata_connect(struct mvs_channel * ch)2154 mvs_sata_connect(struct mvs_channel *ch)
2155 {
2156 u_int32_t status;
2157 int timeout, found = 0;
2158
2159 /* Wait up to 100ms for "connect well" */
2160 for (timeout = 0; timeout < 1000 ; timeout++) {
2161 status = ATA_INL(ch->r_mem, SATA_SS);
2162 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE)
2163 found = 1;
2164 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
2165 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
2166 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE))
2167 break;
2168 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) {
2169 if (bootverbose) {
2170 device_printf(ch->dev, "SATA offline status=%08x\n",
2171 status);
2172 }
2173 return (0);
2174 }
2175 if (found == 0 && timeout >= 100)
2176 break;
2177 DELAY(100);
2178 }
2179 if (timeout >= 1000 || !found) {
2180 if (bootverbose) {
2181 device_printf(ch->dev,
2182 "SATA connect timeout time=%dus status=%08x\n",
2183 timeout * 100, status);
2184 }
2185 return (0);
2186 }
2187 if (bootverbose) {
2188 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2189 timeout * 100, status);
2190 }
2191 /* Clear SATA error register */
2192 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2193 return (1);
2194 }
2195
2196 static int
mvs_sata_phy_reset(device_t dev)2197 mvs_sata_phy_reset(device_t dev)
2198 {
2199 struct mvs_channel *ch = device_get_softc(dev);
2200 int sata_rev;
2201 uint32_t val;
2202
2203 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2204 if (sata_rev == 1)
2205 val = SATA_SC_SPD_SPEED_GEN1;
2206 else if (sata_rev == 2)
2207 val = SATA_SC_SPD_SPEED_GEN2;
2208 else if (sata_rev == 3)
2209 val = SATA_SC_SPD_SPEED_GEN3;
2210 else
2211 val = 0;
2212 ATA_OUTL(ch->r_mem, SATA_SC,
2213 SATA_SC_DET_RESET | val |
2214 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER);
2215 DELAY(1000);
2216 ATA_OUTL(ch->r_mem, SATA_SC,
2217 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2218 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER)));
2219 if (!mvs_sata_connect(ch)) {
2220 if (ch->pm_level > 0)
2221 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE);
2222 return (0);
2223 }
2224 return (1);
2225 }
2226
2227 static int
mvs_check_ids(device_t dev,union ccb * ccb)2228 mvs_check_ids(device_t dev, union ccb *ccb)
2229 {
2230 struct mvs_channel *ch = device_get_softc(dev);
2231
2232 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) {
2233 ccb->ccb_h.status = CAM_TID_INVALID;
2234 xpt_done(ccb);
2235 return (-1);
2236 }
2237 if (ccb->ccb_h.target_lun != 0) {
2238 ccb->ccb_h.status = CAM_LUN_INVALID;
2239 xpt_done(ccb);
2240 return (-1);
2241 }
2242 /*
2243 * It's a programming error to see AUXILIARY register requests.
2244 */
2245 KASSERT(ccb->ccb_h.func_code != XPT_ATA_IO ||
2246 ((ccb->ataio.ata_flags & ATA_FLAG_AUX) == 0),
2247 ("AUX register unsupported"));
2248 return (0);
2249 }
2250
2251 static void
mvsaction(struct cam_sim * sim,union ccb * ccb)2252 mvsaction(struct cam_sim *sim, union ccb *ccb)
2253 {
2254 device_t dev, parent;
2255 struct mvs_channel *ch;
2256
2257 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n",
2258 ccb->ccb_h.func_code));
2259
2260 ch = (struct mvs_channel *)cam_sim_softc(sim);
2261 dev = ch->dev;
2262 switch (ccb->ccb_h.func_code) {
2263 /* Common cases first */
2264 case XPT_ATA_IO: /* Execute the requested I/O operation */
2265 case XPT_SCSI_IO:
2266 if (mvs_check_ids(dev, ccb))
2267 return;
2268 if (ch->devices == 0 ||
2269 (ch->pm_present == 0 &&
2270 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2271 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2272 break;
2273 }
2274 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2275 /* Check for command collision. */
2276 if (mvs_check_collision(dev, ccb)) {
2277 /* Freeze command. */
2278 ch->frozen = ccb;
2279 /* We have only one frozen slot, so freeze simq also. */
2280 xpt_freeze_simq(ch->sim, 1);
2281 return;
2282 }
2283 mvs_begin_transaction(dev, ccb);
2284 return;
2285 case XPT_ABORT: /* Abort the specified CCB */
2286 /* XXX Implement */
2287 ccb->ccb_h.status = CAM_REQ_INVALID;
2288 break;
2289 case XPT_SET_TRAN_SETTINGS:
2290 {
2291 struct ccb_trans_settings *cts = &ccb->cts;
2292 struct mvs_device *d;
2293
2294 if (mvs_check_ids(dev, ccb))
2295 return;
2296 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2297 d = &ch->curr[ccb->ccb_h.target_id];
2298 else
2299 d = &ch->user[ccb->ccb_h.target_id];
2300 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2301 d->revision = cts->xport_specific.sata.revision;
2302 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2303 d->mode = cts->xport_specific.sata.mode;
2304 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) {
2305 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048,
2306 cts->xport_specific.sata.bytecount);
2307 }
2308 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2309 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags);
2310 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2311 ch->pm_present = cts->xport_specific.sata.pm_present;
2312 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2313 d->atapi = cts->xport_specific.sata.atapi;
2314 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2315 d->caps = cts->xport_specific.sata.caps;
2316 ccb->ccb_h.status = CAM_REQ_CMP;
2317 break;
2318 }
2319 case XPT_GET_TRAN_SETTINGS:
2320 /* Get default/user set transfer settings for the target */
2321 {
2322 struct ccb_trans_settings *cts = &ccb->cts;
2323 struct mvs_device *d;
2324 uint32_t status;
2325
2326 if (mvs_check_ids(dev, ccb))
2327 return;
2328 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2329 d = &ch->curr[ccb->ccb_h.target_id];
2330 else
2331 d = &ch->user[ccb->ccb_h.target_id];
2332 cts->protocol = PROTO_UNSPECIFIED;
2333 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2334 cts->transport = XPORT_SATA;
2335 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2336 cts->proto_specific.valid = 0;
2337 cts->xport_specific.sata.valid = 0;
2338 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2339 (ccb->ccb_h.target_id == 15 ||
2340 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2341 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK;
2342 if (status & 0x0f0) {
2343 cts->xport_specific.sata.revision =
2344 (status & 0x0f0) >> 4;
2345 cts->xport_specific.sata.valid |=
2346 CTS_SATA_VALID_REVISION;
2347 }
2348 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2349 // if (ch->pm_level)
2350 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2351 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2352 cts->xport_specific.sata.caps &=
2353 ch->user[ccb->ccb_h.target_id].caps;
2354 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2355 } else {
2356 cts->xport_specific.sata.revision = d->revision;
2357 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2358 cts->xport_specific.sata.caps = d->caps;
2359 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* &&
2360 (ch->quirks & MVS_Q_GENIIE) == 0*/)
2361 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN;
2362 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2363 }
2364 cts->xport_specific.sata.mode = d->mode;
2365 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2366 cts->xport_specific.sata.bytecount = d->bytecount;
2367 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2368 cts->xport_specific.sata.pm_present = ch->pm_present;
2369 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2370 cts->xport_specific.sata.tags = d->tags;
2371 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2372 cts->xport_specific.sata.atapi = d->atapi;
2373 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2374 ccb->ccb_h.status = CAM_REQ_CMP;
2375 break;
2376 }
2377 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2378 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2379 mvs_reset(dev);
2380 ccb->ccb_h.status = CAM_REQ_CMP;
2381 break;
2382 case XPT_TERM_IO: /* Terminate the I/O process */
2383 /* XXX Implement */
2384 ccb->ccb_h.status = CAM_REQ_INVALID;
2385 break;
2386 case XPT_PATH_INQ: /* Path routing inquiry */
2387 {
2388 struct ccb_pathinq *cpi = &ccb->cpi;
2389
2390 parent = device_get_parent(dev);
2391 cpi->version_num = 1; /* XXX??? */
2392 cpi->hba_inquiry = PI_SDTR_ABLE;
2393 if (!(ch->quirks & MVS_Q_GENI)) {
2394 cpi->hba_inquiry |= PI_SATAPM;
2395 /* Gen-II is extremely slow with NCQ on PMP. */
2396 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0)
2397 cpi->hba_inquiry |= PI_TAG_ABLE;
2398 }
2399 cpi->target_sprt = 0;
2400 cpi->hba_misc = PIM_SEQSCAN;
2401 cpi->hba_eng_cnt = 0;
2402 if (!(ch->quirks & MVS_Q_GENI))
2403 cpi->max_target = 15;
2404 else
2405 cpi->max_target = 0;
2406 cpi->max_lun = 0;
2407 cpi->initiator_id = 0;
2408 cpi->bus_id = cam_sim_bus(sim);
2409 cpi->base_transfer_speed = 150000;
2410 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2411 strlcpy(cpi->hba_vid, "Marvell", HBA_IDLEN);
2412 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2413 cpi->unit_number = cam_sim_unit(sim);
2414 cpi->transport = XPORT_SATA;
2415 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2416 cpi->protocol = PROTO_ATA;
2417 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2418 cpi->maxio = maxphys;
2419 if ((ch->quirks & MVS_Q_SOC) == 0) {
2420 cpi->hba_vendor = pci_get_vendor(parent);
2421 cpi->hba_device = pci_get_device(parent);
2422 cpi->hba_subvendor = pci_get_subvendor(parent);
2423 cpi->hba_subdevice = pci_get_subdevice(parent);
2424 }
2425 cpi->ccb_h.status = CAM_REQ_CMP;
2426 break;
2427 }
2428 default:
2429 ccb->ccb_h.status = CAM_REQ_INVALID;
2430 break;
2431 }
2432 xpt_done(ccb);
2433 }
2434
2435 static void
mvspoll(struct cam_sim * sim)2436 mvspoll(struct cam_sim *sim)
2437 {
2438 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim);
2439 struct mvs_intr_arg arg;
2440
2441 arg.arg = ch->dev;
2442 arg.cause = 2 | 4; /* XXX */
2443 mvs_ch_intr(&arg);
2444 if (ch->resetting != 0 &&
2445 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2446 ch->resetpolldiv = 1000;
2447 mvs_reset_to(ch->dev);
2448 }
2449 }
2450